target/linux/brcm63xx-2.6/files/arch/mips/bcm963xx/include/6345_intr.h

   1 /*
   2 <:copyright-gpl
   3  Copyright 2002 Broadcom Corp. All Rights Reserved.
   4
   5  This program is free software; you can distribute it and/or modify it
   6  under the terms of the GNU General Public License (Version 2) as
   7  published by the Free Software Foundation.
   8
   9  This program is distributed in the hope it will be useful, but WITHOUT
  10  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  for more details.
  13
  14  You should have received a copy of the GNU General Public License along
  15  with this program; if not, write to the Free Software Foundation, Inc.,
  16  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17 :>
  18 */
  19
  20 #ifndef __6345_INTR_H
  21 #define __6345_INTR_H
  22
  23
  24 /*=====================================================================*/
  25 /* BCM6345 External Interrupt Level Assignments                       */
  26 /*=====================================================================*/
  27 #define INTERRUPT_ID_EXTERNAL_0         3
  28 #define INTERRUPT_ID_EXTERNAL_1         4
  29 #define INTERRUPT_ID_EXTERNAL_2         5
  30 #define INTERRUPT_ID_EXTERNAL_3         6
  31
  32 /*=====================================================================*/
  33 /* BCM6345 Timer Interrupt Level Assignments                          */
  34 /*=====================================================================*/
  35 #define MIPS_TIMER_INT                  7
  36
  37 /*=====================================================================*/
  38 /* Peripheral ISR Table Offset                                              */
  39 /*=====================================================================*/
  40 #define INTERNAL_ISR_TABLE_OFFSET       8
  41 #define DMA_ISR_TABLE_OFFSET            (INTERNAL_ISR_TABLE_OFFSET + 13)
  42
  43 /*=====================================================================*/
  44 /* Logical Peripheral Interrupt IDs                                    */
  45 /*=====================================================================*/
  46
  47 /* Internal peripheral interrupt IDs */
  48 #define INTERRUPT_ID_TIMER              (INTERNAL_ISR_TABLE_OFFSET +  0)
  49 #define INTERRUPT_ID_UART               (INTERNAL_ISR_TABLE_OFFSET +  2)
  50 #define INTERRUPT_ID_ADSL               (INTERNAL_ISR_TABLE_OFFSET +  3)
  51 #define INTERRUPT_ID_ATM                (INTERNAL_ISR_TABLE_OFFSET +  4)
  52 #define INTERRUPT_ID_USB                (INTERNAL_ISR_TABLE_OFFSET +  5)
  53 #define INTERRUPT_ID_EMAC               (INTERNAL_ISR_TABLE_OFFSET +  8)
  54 #define INTERRUPT_ID_EPHY               (INTERNAL_ISR_TABLE_OFFSET +  12)
  55
  56 /* DMA channel interrupt IDs */
  57 #define INTERRUPT_ID_EMAC_RX_CHAN       (DMA_ISR_TABLE_OFFSET + EMAC_RX_CHAN)
  58 #define INTERRUPT_ID_EMAC_TX_CHAN       (DMA_ISR_TABLE_OFFSET + EMAC_TX_CHAN)
  59 #define INTERRUPT_ID_EBI_RX_CHAN        (DMA_ISR_TABLE_OFFSET + EBI_RX_CHAN)
  60 #define INTERRUPT_ID_EBI_TX_CHAN        (DMA_ISR_TABLE_OFFSET + EBI_TX_CHAN)
  61 #define INTERRUPT_ID_RESERVED_RX_CHAN   (DMA_ISR_TABLE_OFFSET + RESERVED_RX_CHAN)
  62 #define INTERRUPT_ID_RESERVED_TX_CHAN   (DMA_ISR_TABLE_OFFSET + RESERVED_TX_CHAN)
  63 #define INTERRUPT_ID_USB_BULK_RX_CHAN   (DMA_ISR_TABLE_OFFSET + USB_BULK_RX_CHAN)
  64 #define INTERRUPT_ID_USB_BULK_TX_CHAN   (DMA_ISR_TABLE_OFFSET + USB_BULK_TX_CHAN)
  65 #define INTERRUPT_ID_USB_CNTL_RX_CHAN   (DMA_ISR_TABLE_OFFSET + USB_CNTL_RX_CHAN)
  66 #define INTERRUPT_ID_USB_CNTL_TX_CHAN   (DMA_ISR_TABLE_OFFSET + USB_CNTL_TX_CHAN)
  67 #define INTERRUPT_ID_USB_ISO_RX_CHAN    (DMA_ISR_TABLE_OFFSET + USB_ISO_RX_CHAN)
  68 #define INTERRUPT_ID_USB_ISO_TX_CHAN    (DMA_ISR_TABLE_OFFSET + USB_ISO_TX_CHAN)
  69
  70
  71 #endif  /* __BCM6345_H */
  72