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New Broadcom BCM63xx codebase, huge thanks to Maxime ;)
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / patches-2.6.27 / 002-add_support_for_broadcom_63xx_cpus.patch
1 From 0713aadd2a4e543b69022aa40bdec3e1dc5bc1e5 Mon Sep 17 00:00:00 2001
2 From: Maxime Bizon <mbizon@freebox.fr>
3 Date: Mon, 18 Aug 2008 13:56:57 +0200
4 Subject: [PATCH] [MIPS] BCM63XX: Add support for Broadcom 63xx CPUs.
5
6 Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
7 ---
8 arch/mips/Kconfig | 16 +
9 arch/mips/Makefile | 7 +
10 arch/mips/bcm63xx/Kconfig | 9 +
11 arch/mips/bcm63xx/Makefile | 2 +
12 arch/mips/bcm63xx/clk.c | 220 ++++++
13 arch/mips/bcm63xx/cpu.c | 245 +++++++
14 arch/mips/bcm63xx/cs.c | 144 ++++
15 arch/mips/bcm63xx/early_printk.c | 30 +
16 arch/mips/bcm63xx/gpio.c | 98 +++
17 arch/mips/bcm63xx/irq.c | 253 +++++++
18 arch/mips/bcm63xx/prom.c | 43 ++
19 arch/mips/bcm63xx/setup.c | 108 +++
20 arch/mips/bcm63xx/timer.c | 205 ++++++
21 include/asm-mips/fixmap.h | 4 +
22 include/asm-mips/mach-bcm63xx/bcm63xx_clk.h | 11 +
23 include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h | 314 +++++++++
24 include/asm-mips/mach-bcm63xx/bcm63xx_cs.h | 10 +
25 include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h | 14 +
26 include/asm-mips/mach-bcm63xx/bcm63xx_io.h | 93 +++
27 include/asm-mips/mach-bcm63xx/bcm63xx_irq.h | 15 +
28 include/asm-mips/mach-bcm63xx/bcm63xx_regs.h | 728 ++++++++++++++++++++
29 include/asm-mips/mach-bcm63xx/bcm63xx_timer.h | 11 +
30 .../asm-mips/mach-bcm63xx/cpu-feature-overrides.h | 51 ++
31 include/asm-mips/mach-bcm63xx/gpio.h | 52 ++
32 include/asm-mips/mach-bcm63xx/war.h | 25 +
33 25 files changed, 2708 insertions(+), 0 deletions(-)
34 create mode 100644 arch/mips/bcm63xx/Kconfig
35 create mode 100644 arch/mips/bcm63xx/Makefile
36 create mode 100644 arch/mips/bcm63xx/clk.c
37 create mode 100644 arch/mips/bcm63xx/cpu.c
38 create mode 100644 arch/mips/bcm63xx/cs.c
39 create mode 100644 arch/mips/bcm63xx/early_printk.c
40 create mode 100644 arch/mips/bcm63xx/gpio.c
41 create mode 100644 arch/mips/bcm63xx/irq.c
42 create mode 100644 arch/mips/bcm63xx/prom.c
43 create mode 100644 arch/mips/bcm63xx/setup.c
44 create mode 100644 arch/mips/bcm63xx/timer.c
45 create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_clk.h
46 create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
47 create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_cs.h
48 create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h
49 create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_io.h
50 create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_irq.h
51 create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
52 create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_timer.h
53 create mode 100644 include/asm-mips/mach-bcm63xx/cpu-feature-overrides.h
54 create mode 100644 include/asm-mips/mach-bcm63xx/gpio.h
55 create mode 100644 include/asm-mips/mach-bcm63xx/war.h
56
57 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
58 index 1e06d23..88dfe21 100644
59 --- a/arch/mips/Kconfig
60 +++ b/arch/mips/Kconfig
61 @@ -59,6 +59,21 @@ config BCM47XX
62 help
63 Support for BCM47XX based boards
64
65 +config BCM63XX
66 + bool "Broadcom 63xx based boards"
67 + select CEVT_R4K
68 + select CSRC_R4K
69 + select DMA_NONCOHERENT
70 + select IRQ_CPU
71 + select SYS_HAS_CPU_MIPS32_R1
72 + select SYS_SUPPORTS_32BIT_KERNEL
73 + select SYS_SUPPORTS_BIG_ENDIAN
74 + select SYS_HAS_EARLY_PRINTK
75 + select SWAP_IO_SPACE
76 + select GENERIC_GPIO
77 + help
78 + Support for BCM63XX based boards
79 +
80 config MIPS_COBALT
81 bool "Cobalt Server"
82 select CEVT_R4K
83 @@ -600,6 +615,7 @@ endchoice
84
85 source "arch/mips/au1000/Kconfig"
86 source "arch/mips/basler/excite/Kconfig"
87 +source "arch/mips/bcm63xx/Kconfig"
88 source "arch/mips/jazz/Kconfig"
89 source "arch/mips/lasat/Kconfig"
90 source "arch/mips/pmc-sierra/Kconfig"
91 diff --git a/arch/mips/Makefile b/arch/mips/Makefile
92 index 9aab51c..a45652e 100644
93 --- a/arch/mips/Makefile
94 +++ b/arch/mips/Makefile
95 @@ -533,6 +533,13 @@ cflags-$(CONFIG_BCM47XX) += -Iinclude/asm-mips/mach-bcm47xx
96 load-$(CONFIG_BCM47XX) := 0xffffffff80001000
97
98 #
99 +# Broadcom BCM63XX boards
100 +#
101 +core-$(CONFIG_BCM63XX) += arch/mips/bcm63xx/
102 +cflags-$(CONFIG_BCM63XX) += -Iinclude/asm-mips/mach-bcm63xx/
103 +load-$(CONFIG_BCM63XX) := 0xffffffff80010000
104 +
105 +#
106 # SNI RM
107 #
108 core-$(CONFIG_SNI_RM) += arch/mips/sni/
109 diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
110 new file mode 100644
111 index 0000000..e6d2699
112 --- /dev/null
113 +++ b/arch/mips/bcm63xx/Kconfig
114 @@ -0,0 +1,9 @@
115 +menu "CPU support"
116 + depends on BCM63XX
117 +
118 +config BCM63XX_CPU_6348
119 + bool "support 6348 CPU"
120 +
121 +config BCM63XX_CPU_6358
122 + bool "support 6358 CPU"
123 +endmenu
124 diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
125 new file mode 100644
126 index 0000000..4fc0a1c
127 --- /dev/null
128 +++ b/arch/mips/bcm63xx/Makefile
129 @@ -0,0 +1,2 @@
130 +obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o
131 +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
132 diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
133 new file mode 100644
134 index 0000000..ae1f41f
135 --- /dev/null
136 +++ b/arch/mips/bcm63xx/clk.c
137 @@ -0,0 +1,220 @@
138 +/*
139 + * This file is subject to the terms and conditions of the GNU General Public
140 + * License. See the file "COPYING" in the main directory of this archive
141 + * for more details.
142 + *
143 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
144 + */
145 +
146 +#include <linux/module.h>
147 +#include <linux/mutex.h>
148 +#include <linux/err.h>
149 +#include <linux/clk.h>
150 +#include <bcm63xx_cpu.h>
151 +#include <bcm63xx_io.h>
152 +#include <bcm63xx_regs.h>
153 +#include <bcm63xx_clk.h>
154 +
155 +DEFINE_MUTEX(clocks_mutex);
156 +
157 +
158 +static void clk_enable_unlocked(struct clk *clk)
159 +{
160 + if (clk->set && (clk->usage++) == 0)
161 + clk->set(clk, 1);
162 +}
163 +
164 +static void clk_disable_unlocked(struct clk *clk)
165 +{
166 + if (clk->set && (--clk->usage) == 0)
167 + clk->set(clk, 0);
168 +}
169 +
170 +static void bcm_hwclock_set(u32 mask, int enable)
171 +{
172 + u32 reg;
173 +
174 + reg = bcm_perf_readl(PERF_CKCTL_REG);
175 + if (enable)
176 + reg |= mask;
177 + else
178 + reg &= ~mask;
179 + bcm_perf_writel(reg, PERF_CKCTL_REG);
180 +}
181 +
182 +/*
183 + * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
184 + */
185 +static void enet_misc_set(struct clk *clk, int enable)
186 +{
187 + u32 mask;
188 +
189 + if (BCMCPU_IS_6348())
190 + mask = CKCTL_6348_ENET_EN;
191 + else
192 + /* BCMCPU_IS_6358 */
193 + mask = CKCTL_6358_EMUSB_EN;
194 + bcm_hwclock_set(mask, enable);
195 +}
196 +
197 +static struct clk clk_enet_misc = {
198 + .set = enet_misc_set,
199 +};
200 +
201 +/*
202 + * Ethernet MAC clocks: only revelant on 6358, silently enable misc
203 + * clocks
204 + */
205 +static void enetx_set(struct clk *clk, int enable)
206 +{
207 + if (enable)
208 + clk_enable_unlocked(&clk_enet_misc);
209 + else
210 + clk_disable_unlocked(&clk_enet_misc);
211 +
212 + if (BCMCPU_IS_6358()) {
213 + u32 mask;
214 +
215 + if (clk->id == 0)
216 + mask = CKCTL_6358_ENET0_EN;
217 + else
218 + mask = CKCTL_6358_ENET1_EN;
219 + bcm_hwclock_set(mask, enable);
220 + }
221 +}
222 +
223 +static struct clk clk_enet0 = {
224 + .id = 0,
225 + .set = enetx_set,
226 +};
227 +
228 +static struct clk clk_enet1 = {
229 + .id = 1,
230 + .set = enetx_set,
231 +};
232 +
233 +/*
234 + * Ethernet PHY clock
235 + */
236 +static void ephy_set(struct clk *clk, int enable)
237 +{
238 + if (!BCMCPU_IS_6358())
239 + return;
240 + bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
241 +}
242 +
243 +
244 +static struct clk clk_ephy = {
245 + .set = ephy_set,
246 +};
247 +
248 +/*
249 + * PCM clock
250 + */
251 +static void pcm_set(struct clk *clk, int enable)
252 +{
253 + if (!BCMCPU_IS_6358())
254 + return;
255 + bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
256 +}
257 +
258 +static struct clk clk_pcm = {
259 + .set = pcm_set,
260 +};
261 +
262 +/*
263 + * USB host clock
264 + */
265 +static void usbh_set(struct clk *clk, int enable)
266 +{
267 + if (!BCMCPU_IS_6348())
268 + return;
269 + bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
270 +}
271 +
272 +static struct clk clk_usbh = {
273 + .set = usbh_set,
274 +};
275 +
276 +/*
277 + * SPI clock
278 + */
279 +static void spi_set(struct clk *clk, int enable)
280 +{
281 + u32 mask;
282 +
283 + if (BCMCPU_IS_6348())
284 + mask = CKCTL_6348_SPI_EN;
285 + else
286 + /* BCMCPU_IS_6358 */
287 + mask = CKCTL_6358_SPI_EN;
288 + bcm_hwclock_set(mask, enable);
289 +}
290 +
291 +static struct clk clk_spi = {
292 + .set = spi_set,
293 +};
294 +
295 +/*
296 + * Internal peripheral clock
297 + */
298 +static struct clk clk_periph = {
299 + .rate = (50 * 1000 * 1000),
300 +};
301 +
302 +
303 +/*
304 + * Linux clock API implementation
305 + */
306 +int clk_enable(struct clk *clk)
307 +{
308 + mutex_lock(&clocks_mutex);
309 + clk_enable_unlocked(clk);
310 + mutex_unlock(&clocks_mutex);
311 + return 0;
312 +}
313 +
314 +EXPORT_SYMBOL(clk_enable);
315 +
316 +void clk_disable(struct clk *clk)
317 +{
318 + mutex_lock(&clocks_mutex);
319 + clk_disable_unlocked(clk);
320 + mutex_unlock(&clocks_mutex);
321 +}
322 +
323 +EXPORT_SYMBOL(clk_disable);
324 +
325 +unsigned long clk_get_rate(struct clk *clk)
326 +{
327 + return clk->rate;
328 +}
329 +
330 +EXPORT_SYMBOL(clk_get_rate);
331 +
332 +struct clk *clk_get(struct device *dev, const char *id)
333 +{
334 + if (!strcmp(id, "enet0"))
335 + return &clk_enet0;
336 + if (!strcmp(id, "enet1"))
337 + return &clk_enet1;
338 + if (!strcmp(id, "ephy"))
339 + return &clk_ephy;
340 + if (!strcmp(id, "usbh"))
341 + return &clk_usbh;
342 + if (!strcmp(id, "spi"))
343 + return &clk_spi;
344 + if (!strcmp(id, "periph"))
345 + return &clk_periph;
346 + if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
347 + return &clk_pcm;
348 + return ERR_PTR(-ENOENT);
349 +}
350 +
351 +EXPORT_SYMBOL(clk_get);
352 +
353 +void clk_put(struct clk *clk)
354 +{
355 +}
356 +
357 +EXPORT_SYMBOL(clk_put);
358 diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
359 new file mode 100644
360 index 0000000..0a403dd
361 --- /dev/null
362 +++ b/arch/mips/bcm63xx/cpu.c
363 @@ -0,0 +1,245 @@
364 +/*
365 + * This file is subject to the terms and conditions of the GNU General Public
366 + * License. See the file "COPYING" in the main directory of this archive
367 + * for more details.
368 + *
369 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
370 + */
371 +
372 +#include <linux/kernel.h>
373 +#include <linux/module.h>
374 +#include <linux/cpu.h>
375 +#include <bcm63xx_cpu.h>
376 +#include <bcm63xx_regs.h>
377 +#include <bcm63xx_io.h>
378 +#include <bcm63xx_irq.h>
379 +
380 +const unsigned long *bcm63xx_regs_base;
381 +EXPORT_SYMBOL(bcm63xx_regs_base);
382 +
383 +const int *bcm63xx_irqs;
384 +EXPORT_SYMBOL(bcm63xx_irqs);
385 +
386 +static u16 bcm63xx_cpu_id;
387 +static u16 bcm63xx_cpu_rev;
388 +static unsigned int bcm63xx_cpu_freq;
389 +static unsigned int bcm63xx_memory_size;
390 +
391 +/*
392 + * 6348 register sets and irqs
393 + */
394 +static const unsigned long bcm96348_regs_base[] = {
395 + [RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE,
396 + [RSET_PERF] = BCM_6348_PERF_BASE,
397 + [RSET_TIMER] = BCM_6348_TIMER_BASE,
398 + [RSET_WDT] = BCM_6348_WDT_BASE,
399 + [RSET_UART0] = BCM_6348_UART0_BASE,
400 + [RSET_GPIO] = BCM_6348_GPIO_BASE,
401 + [RSET_SPI] = BCM_6348_SPI_BASE,
402 + [RSET_OHCI0] = BCM_6348_OHCI0_BASE,
403 + [RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE,
404 + [RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE,
405 + [RSET_MPI] = BCM_6348_MPI_BASE,
406 + [RSET_PCMCIA] = BCM_6348_PCMCIA_BASE,
407 + [RSET_SDRAM] = BCM_6348_SDRAM_BASE,
408 + [RSET_DSL] = BCM_6348_DSL_BASE,
409 + [RSET_ENET0] = BCM_6348_ENET0_BASE,
410 + [RSET_ENET1] = BCM_6348_ENET1_BASE,
411 + [RSET_ENETDMA] = BCM_6348_ENETDMA_BASE,
412 + [RSET_MEMC] = BCM_6348_MEMC_BASE,
413 + [RSET_DDR] = BCM_6348_DDR_BASE,
414 +};
415 +
416 +static const int bcm96348_irqs[] = {
417 + [IRQ_TIMER] = BCM_6348_TIMER_IRQ,
418 + [IRQ_UART0] = BCM_6348_UART0_IRQ,
419 + [IRQ_DSL] = BCM_6348_DSL_IRQ,
420 + [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
421 + [IRQ_ENET1] = BCM_6348_ENET1_IRQ,
422 + [IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ,
423 + [IRQ_OHCI0] = BCM_6348_OHCI0_IRQ,
424 + [IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ,
425 + [IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ,
426 + [IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ,
427 + [IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ,
428 + [IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ,
429 + [IRQ_PCI] = BCM_6348_PCI_IRQ,
430 +};
431 +
432 +/*
433 + * 6358 register sets and irqs
434 + */
435 +static const unsigned long bcm96358_regs_base[] = {
436 + [RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE,
437 + [RSET_PERF] = BCM_6358_PERF_BASE,
438 + [RSET_TIMER] = BCM_6358_TIMER_BASE,
439 + [RSET_WDT] = BCM_6358_WDT_BASE,
440 + [RSET_UART0] = BCM_6358_UART0_BASE,
441 + [RSET_GPIO] = BCM_6358_GPIO_BASE,
442 + [RSET_SPI] = BCM_6358_SPI_BASE,
443 + [RSET_OHCI0] = BCM_6358_OHCI0_BASE,
444 + [RSET_EHCI0] = BCM_6358_EHCI0_BASE,
445 + [RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE,
446 + [RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE,
447 + [RSET_MPI] = BCM_6358_MPI_BASE,
448 + [RSET_PCMCIA] = BCM_6358_PCMCIA_BASE,
449 + [RSET_SDRAM] = BCM_6358_SDRAM_BASE,
450 + [RSET_DSL] = BCM_6358_DSL_BASE,
451 + [RSET_ENET0] = BCM_6358_ENET0_BASE,
452 + [RSET_ENET1] = BCM_6358_ENET1_BASE,
453 + [RSET_ENETDMA] = BCM_6358_ENETDMA_BASE,
454 + [RSET_MEMC] = BCM_6358_MEMC_BASE,
455 + [RSET_DDR] = BCM_6358_DDR_BASE,
456 +};
457 +
458 +static const int bcm96358_irqs[] = {
459 + [IRQ_TIMER] = BCM_6358_TIMER_IRQ,
460 + [IRQ_UART0] = BCM_6358_UART0_IRQ,
461 + [IRQ_DSL] = BCM_6358_DSL_IRQ,
462 + [IRQ_ENET0] = BCM_6358_ENET0_IRQ,
463 + [IRQ_ENET1] = BCM_6358_ENET1_IRQ,
464 + [IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ,
465 + [IRQ_OHCI0] = BCM_6358_OHCI0_IRQ,
466 + [IRQ_EHCI0] = BCM_6358_EHCI0_IRQ,
467 + [IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ,
468 + [IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ,
469 + [IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ,
470 + [IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ,
471 + [IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ,
472 + [IRQ_PCI] = BCM_6358_PCI_IRQ,
473 +};
474 +
475 +u16 __bcm63xx_get_cpu_id(void)
476 +{
477 + return bcm63xx_cpu_id;
478 +}
479 +
480 +EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
481 +
482 +u16 bcm63xx_get_cpu_rev(void)
483 +{
484 + return bcm63xx_cpu_rev;
485 +}
486 +
487 +EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
488 +
489 +unsigned int bcm63xx_get_cpu_freq(void)
490 +{
491 + return bcm63xx_cpu_freq;
492 +}
493 +
494 +unsigned int bcm63xx_get_memory_size(void)
495 +{
496 + return bcm63xx_memory_size;
497 +}
498 +
499 +static unsigned int detect_cpu_clock(void)
500 +{
501 + unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
502 +
503 + /*
504 + * frequency depends on PLL configuration:
505 + */
506 + if (BCMCPU_IS_6348()) {
507 + /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
508 + tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
509 + n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
510 + n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
511 + m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
512 + n1 += 1;
513 + n2 += 2;
514 + m1 += 1;
515 + }
516 +
517 + if (BCMCPU_IS_6358()) {
518 + /* 16MHz * N1 * N2 / M1_CPU */
519 + tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
520 + n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
521 + n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
522 + m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
523 + }
524 +
525 + return (16 * 1000000 * n1 * n2) / m1;
526 +}
527 +
528 +/*
529 + * attempt to detect the amount of memory installed
530 + */
531 +static unsigned int detect_memory_size(void)
532 +{
533 + unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
534 + u32 val;
535 +
536 + if (BCMCPU_IS_6348()) {
537 + val = bcm_sdram_readl(SDRAM_CFG_REG);
538 + rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
539 + cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
540 + is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
541 + banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
542 + }
543 +
544 + if (BCMCPU_IS_6358()) {
545 + val = bcm_memc_readl(MEMC_CFG_REG);
546 + rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
547 + cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
548 + is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
549 + banks = 2;
550 + }
551 +
552 + /* 0 => 11 address bits ... 2 => 13 address bits */
553 + rows += 11;
554 +
555 + /* 0 => 8 address bits ... 2 => 10 address bits */
556 + cols += 8;
557 +
558 + return 1 << (cols + rows + (is_32bits + 1) + banks);
559 +}
560 +
561 +void __init bcm63xx_cpu_init(void)
562 +{
563 + unsigned int tmp, expected_cpu_id;
564 + struct cpuinfo_mips *c = &current_cpu_data;
565 +
566 + /* soc registers location depends on cpu type */
567 + expected_cpu_id = 0;
568 +
569 + switch (c->cputype) {
570 + case CPU_BCM6348:
571 + expected_cpu_id = BCM6348_CPU_ID;
572 + bcm63xx_regs_base = bcm96348_regs_base;
573 + bcm63xx_irqs = bcm96348_irqs;
574 + break;
575 + case CPU_BCM6358:
576 + expected_cpu_id = BCM6358_CPU_ID;
577 + bcm63xx_regs_base = bcm96358_regs_base;
578 + bcm63xx_irqs = bcm96358_irqs;
579 + break;
580 + }
581 +
582 + /* really early to panic, but delaying panic would not help
583 + * since we will never get any working console */
584 + if (!expected_cpu_id)
585 + panic("unsupported Broadcom CPU");
586 +
587 + /*
588 + * bcm63xx_regs_base is set, we can access soc registers
589 + */
590 +
591 + /* double check CPU type */
592 + tmp = bcm_perf_readl(PERF_REV_REG);
593 + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
594 + bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
595 +
596 + if (bcm63xx_cpu_id != expected_cpu_id)
597 + panic("bcm63xx CPU id mismatch");
598 +
599 + bcm63xx_cpu_freq = detect_cpu_clock();
600 + bcm63xx_memory_size = detect_memory_size();
601 +
602 + printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
603 + bcm63xx_cpu_id, bcm63xx_cpu_rev);
604 + printk(KERN_INFO "CPU frequency is %u MHz\n",
605 + bcm63xx_cpu_freq);
606 + printk(KERN_INFO "%uMB of RAM installed\n",
607 + bcm63xx_memory_size >> 20);
608 +}
609 diff --git a/arch/mips/bcm63xx/cs.c b/arch/mips/bcm63xx/cs.c
610 new file mode 100644
611 index 0000000..50d8190
612 --- /dev/null
613 +++ b/arch/mips/bcm63xx/cs.c
614 @@ -0,0 +1,144 @@
615 +/*
616 + * This file is subject to the terms and conditions of the GNU General Public
617 + * License. See the file "COPYING" in the main directory of this archive
618 + * for more details.
619 + *
620 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
621 + */
622 +
623 +#include <linux/kernel.h>
624 +#include <linux/module.h>
625 +#include <linux/spinlock.h>
626 +#include <linux/log2.h>
627 +#include <bcm63xx_cpu.h>
628 +#include <bcm63xx_io.h>
629 +#include <bcm63xx_regs.h>
630 +#include <bcm63xx_cs.h>
631 +
632 +static DEFINE_SPINLOCK(bcm63xx_cs_lock);
633 +
634 +/*
635 + * check if given chip select exists
636 + */
637 +static int is_valid_cs(unsigned int cs)
638 +{
639 + if (cs > 6)
640 + return 0;
641 + return 1;
642 +}
643 +
644 +/*
645 + * Configure chipselect base address and size (bytes).
646 + * Size must be a power of two between 8k and 256M.
647 + */
648 +int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size)
649 +{
650 + unsigned long flags;
651 + u32 val;
652 +
653 + if (!is_valid_cs(cs))
654 + return -EINVAL;
655 +
656 + /* sanity check on size */
657 + if (size != roundup_pow_of_two(size))
658 + return -EINVAL;
659 +
660 + if (size < 8 * 1024 || size > 256 * 1024 * 1024)
661 + return -EINVAL;
662 +
663 + val = (base & MPI_CSBASE_BASE_MASK);
664 + /* 8k => 0 - 256M => 15 */
665 + val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT;
666 +
667 + spin_lock_irqsave(&bcm63xx_cs_lock, flags);
668 + bcm_mpi_writel(val, MPI_CSBASE_REG(cs));
669 + spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
670 +
671 + return 0;
672 +}
673 +
674 +EXPORT_SYMBOL(bcm63xx_set_cs_base);
675 +
676 +/*
677 + * configure chipselect timing (ns)
678 + */
679 +int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
680 + unsigned int setup, unsigned int hold)
681 +{
682 + unsigned long flags;
683 + u32 val;
684 +
685 + if (!is_valid_cs(cs))
686 + return -EINVAL;
687 +
688 + spin_lock_irqsave(&bcm63xx_cs_lock, flags);
689 + val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
690 + val &= ~(MPI_CSCTL_WAIT_MASK);
691 + val &= ~(MPI_CSCTL_SETUP_MASK);
692 + val &= ~(MPI_CSCTL_HOLD_MASK);
693 + val |= wait << MPI_CSCTL_WAIT_SHIFT;
694 + val |= setup << MPI_CSCTL_SETUP_SHIFT;
695 + val |= hold << MPI_CSCTL_HOLD_SHIFT;
696 + bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
697 + spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
698 +
699 + return 0;
700 +}
701 +
702 +EXPORT_SYMBOL(bcm63xx_set_cs_timing);
703 +
704 +/*
705 + * configure other chipselect parameter (data bus size, ...)
706 + */
707 +int bcm63xx_set_cs_param(unsigned int cs, u32 params)
708 +{
709 + unsigned long flags;
710 + u32 val;
711 +
712 + if (!is_valid_cs(cs))
713 + return -EINVAL;
714 +
715 + /* none of this fields apply to pcmcia */
716 + if (cs == MPI_CS_PCMCIA_COMMON ||
717 + cs == MPI_CS_PCMCIA_ATTR ||
718 + cs == MPI_CS_PCMCIA_IO)
719 + return -EINVAL;
720 +
721 + spin_lock_irqsave(&bcm63xx_cs_lock, flags);
722 + val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
723 + val &= ~(MPI_CSCTL_DATA16_MASK);
724 + val &= ~(MPI_CSCTL_SYNCMODE_MASK);
725 + val &= ~(MPI_CSCTL_TSIZE_MASK);
726 + val &= ~(MPI_CSCTL_ENDIANSWAP_MASK);
727 + val |= params;
728 + bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
729 + spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
730 +
731 + return 0;
732 +}
733 +
734 +EXPORT_SYMBOL(bcm63xx_set_cs_param);
735 +
736 +/*
737 + * set cs status (enable/disable)
738 + */
739 +int bcm63xx_set_cs_status(unsigned int cs, int enable)
740 +{
741 + unsigned long flags;
742 + u32 val;
743 +
744 + if (!is_valid_cs(cs))
745 + return -EINVAL;
746 +
747 + spin_lock_irqsave(&bcm63xx_cs_lock, flags);
748 + val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
749 + if (enable)
750 + val |= MPI_CSCTL_ENABLE_MASK;
751 + else
752 + val &= ~MPI_CSCTL_ENABLE_MASK;
753 + bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
754 + spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
755 + return 0;
756 +}
757 +
758 +EXPORT_SYMBOL(bcm63xx_set_cs_status);
759 diff --git a/arch/mips/bcm63xx/early_printk.c b/arch/mips/bcm63xx/early_printk.c
760 new file mode 100644
761 index 0000000..bf353c9
762 --- /dev/null
763 +++ b/arch/mips/bcm63xx/early_printk.c
764 @@ -0,0 +1,30 @@
765 +/*
766 + * This file is subject to the terms and conditions of the GNU General Public
767 + * License. See the file "COPYING" in the main directory of this archive
768 + * for more details.
769 + *
770 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
771 + */
772 +
773 +#include <linux/init.h>
774 +#include <bcm63xx_io.h>
775 +#include <bcm63xx_regs.h>
776 +
777 +static void __init wait_xfered(void)
778 +{
779 + unsigned int val;
780 +
781 + /* wait for any previous char to be transmitted */
782 + do {
783 + val = bcm_uart0_readl(UART_IR_REG);
784 + if (val & UART_IR_STAT(UART_IR_TXEMPTY))
785 + break;
786 + } while (1);
787 +}
788 +
789 +void __init prom_putchar(char c)
790 +{
791 + wait_xfered();
792 + bcm_uart0_writel(c, UART_FIFO_REG);
793 + wait_xfered();
794 +}
795 diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c
796 new file mode 100644
797 index 0000000..2c203a6
798 --- /dev/null
799 +++ b/arch/mips/bcm63xx/gpio.c
800 @@ -0,0 +1,98 @@
801 +/*
802 + * This file is subject to the terms and conditions of the GNU General Public
803 + * License. See the file "COPYING" in the main directory of this archive
804 + * for more details.
805 + *
806 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
807 + */
808 +
809 +#include <linux/kernel.h>
810 +#include <linux/module.h>
811 +#include <linux/spinlock.h>
812 +#include <bcm63xx_cpu.h>
813 +#include <bcm63xx_gpio.h>
814 +#include <bcm63xx_io.h>
815 +#include <bcm63xx_regs.h>
816 +
817 +static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
818 +
819 +void bcm63xx_gpio_set_dataout(int gpio, int val)
820 +{
821 + u32 reg;
822 + u32 mask;
823 + u32 tmp;
824 + unsigned long flags;
825 +
826 + if (gpio >= BCM63XX_GPIO_COUNT)
827 + BUG();
828 +
829 + if (gpio < 32) {
830 + reg = GPIO_DATA_LO_REG;
831 + mask = 1 << gpio;
832 + } else {
833 + reg = GPIO_DATA_HI_REG;
834 + mask = 1 << (gpio - 32);
835 + }
836 +
837 + spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
838 + tmp = bcm_gpio_readl(reg);
839 + if (val)
840 + tmp |= mask;
841 + else
842 + tmp &= ~mask;
843 + bcm_gpio_writel(tmp, reg);
844 + spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
845 +}
846 +
847 +EXPORT_SYMBOL(bcm63xx_gpio_set_dataout);
848 +
849 +int bcm63xx_gpio_get_datain(int gpio)
850 +{
851 + u32 reg;
852 + u32 mask;
853 +
854 + if (gpio >= BCM63XX_GPIO_COUNT)
855 + BUG();
856 +
857 + if (gpio < 32) {
858 + reg = GPIO_DATA_LO_REG;
859 + mask = 1 << gpio;
860 + } else {
861 + reg = GPIO_DATA_HI_REG;
862 + mask = 1 << (gpio - 32);
863 + }
864 +
865 + return !!(bcm_gpio_readl(reg) & mask);
866 +}
867 +
868 +EXPORT_SYMBOL(bcm63xx_gpio_get_datain);
869 +
870 +void bcm63xx_gpio_set_direction(int gpio, int dir)
871 +{
872 + u32 reg;
873 + u32 mask;
874 + u32 tmp;
875 + unsigned long flags;
876 +
877 + if (gpio >= BCM63XX_GPIO_COUNT)
878 + BUG();
879 +
880 + if (gpio < 32) {
881 + reg = GPIO_CTL_LO_REG;
882 + mask = 1 << gpio;
883 + } else {
884 + reg = GPIO_CTL_HI_REG;
885 + mask = 1 << (gpio - 32);
886 + }
887 +
888 + spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
889 + tmp = bcm_gpio_readl(reg);
890 + if (dir == GPIO_DIR_IN)
891 + tmp &= ~mask;
892 + else
893 + tmp |= mask;
894 + bcm_gpio_writel(tmp, reg);
895 + spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
896 +}
897 +
898 +EXPORT_SYMBOL(bcm63xx_gpio_set_direction);
899 diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
900 new file mode 100644
901 index 0000000..a0c5cd1
902 --- /dev/null
903 +++ b/arch/mips/bcm63xx/irq.c
904 @@ -0,0 +1,253 @@
905 +/*
906 + * This file is subject to the terms and conditions of the GNU General Public
907 + * License. See the file "COPYING" in the main directory of this archive
908 + * for more details.
909 + *
910 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
911 + * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
912 + */
913 +
914 +#include <linux/kernel.h>
915 +#include <linux/init.h>
916 +#include <linux/interrupt.h>
917 +#include <linux/module.h>
918 +#include <asm/irq_cpu.h>
919 +#include <asm/mipsregs.h>
920 +#include <bcm63xx_cpu.h>
921 +#include <bcm63xx_regs.h>
922 +#include <bcm63xx_io.h>
923 +#include <bcm63xx_irq.h>
924 +
925 +/*
926 + * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
927 + * prioritize any interrupt relatively to another. the static counter
928 + * will resume the loop where it ended the last time we left this
929 + * function.
930 + */
931 +static void bcm63xx_irq_dispatch_internal(void)
932 +{
933 + u32 pending;
934 + static int i;
935 +
936 + pending = bcm_perf_readl(PERF_IRQMASK_REG) &
937 + bcm_perf_readl(PERF_IRQSTAT_REG);
938 +
939 + if (!pending)
940 + return ;
941 +
942 + while (1) {
943 + int to_call = i;
944 +
945 + i = (i + 1) & 0x1f;
946 + if (pending & (1 << to_call)) {
947 + do_IRQ(to_call + IRQ_INTERNAL_BASE);
948 + break;
949 + }
950 + }
951 +}
952 +
953 +asmlinkage void plat_irq_dispatch(void)
954 +{
955 + u32 cause;
956 +
957 + do {
958 + cause = read_c0_cause() & read_c0_status() & ST0_IM;
959 +
960 + if (!cause)
961 + break;
962 +
963 + if (cause & CAUSEF_IP7)
964 + do_IRQ(7);
965 + if (cause & CAUSEF_IP2)
966 + bcm63xx_irq_dispatch_internal();
967 + if (cause & CAUSEF_IP3)
968 + do_IRQ(IRQ_EXT_0);
969 + if (cause & CAUSEF_IP4)
970 + do_IRQ(IRQ_EXT_1);
971 + if (cause & CAUSEF_IP5)
972 + do_IRQ(IRQ_EXT_2);
973 + if (cause & CAUSEF_IP6)
974 + do_IRQ(IRQ_EXT_3);
975 + } while (1);
976 +}
977 +
978 +/*
979 + * internal IRQs operations: only mask/unmask on PERF irq mask
980 + * register.
981 + */
982 +static inline void bcm63xx_internal_irq_mask(unsigned int irq)
983 +{
984 + u32 mask;
985 +
986 + irq -= IRQ_INTERNAL_BASE;
987 + mask = bcm_perf_readl(PERF_IRQMASK_REG);
988 + mask &= ~(1 << irq);
989 + bcm_perf_writel(mask, PERF_IRQMASK_REG);
990 +}
991 +
992 +static void bcm63xx_internal_irq_unmask(unsigned int irq)
993 +{
994 + u32 mask;
995 +
996 + irq -= IRQ_INTERNAL_BASE;
997 + mask = bcm_perf_readl(PERF_IRQMASK_REG);
998 + mask |= (1 << irq);
999 + bcm_perf_writel(mask, PERF_IRQMASK_REG);
1000 +}
1001 +
1002 +static unsigned int bcm63xx_internal_irq_startup(unsigned int irq)
1003 +{
1004 + bcm63xx_internal_irq_unmask(irq);
1005 + return 0;
1006 +}
1007 +
1008 +/*
1009 + * external IRQs operations: mask/unmask and clear on PERF external
1010 + * irq control register.
1011 + */
1012 +static void bcm63xx_external_irq_mask(unsigned int irq)
1013 +{
1014 + u32 reg;
1015 +
1016 + irq -= IRQ_EXT_BASE;
1017 + reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
1018 + reg &= ~EXTIRQ_CFG_MASK(irq);
1019 + bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
1020 +}
1021 +
1022 +static void bcm63xx_external_irq_unmask(unsigned int irq)
1023 +{
1024 + u32 reg;
1025 +
1026 + irq -= IRQ_EXT_BASE;
1027 + reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
1028 + reg |= EXTIRQ_CFG_MASK(irq);
1029 + bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
1030 +}
1031 +
1032 +static void bcm63xx_external_irq_clear(unsigned int irq)
1033 +{
1034 + u32 reg;
1035 +
1036 + irq -= IRQ_EXT_BASE;
1037 + reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
1038 + reg |= EXTIRQ_CFG_CLEAR(irq);
1039 + bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
1040 +}
1041 +
1042 +static unsigned int bcm63xx_external_irq_startup(unsigned int irq)
1043 +{
1044 + set_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
1045 + irq_enable_hazard();
1046 + bcm63xx_external_irq_unmask(irq);
1047 + return 0;
1048 +}
1049 +
1050 +static void bcm63xx_external_irq_shutdown(unsigned int irq)
1051 +{
1052 + bcm63xx_external_irq_mask(irq);
1053 + clear_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
1054 + irq_disable_hazard();
1055 +}
1056 +
1057 +static int bcm63xx_external_irq_set_type(unsigned int irq,
1058 + unsigned int flow_type)
1059 +{
1060 + u32 reg;
1061 + struct irq_desc *desc = irq_desc + irq;
1062 +
1063 + irq -= IRQ_EXT_BASE;
1064 +
1065 + flow_type &= IRQ_TYPE_SENSE_MASK;
1066 +
1067 + if (flow_type == IRQ_TYPE_NONE)
1068 + flow_type = IRQ_TYPE_LEVEL_LOW;
1069 +
1070 + reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
1071 + switch (flow_type) {
1072 + case IRQ_TYPE_EDGE_BOTH:
1073 + reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
1074 + reg |= EXTIRQ_CFG_BOTHEDGE(irq);
1075 + break;
1076 +
1077 + case IRQ_TYPE_EDGE_RISING:
1078 + reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
1079 + reg |= EXTIRQ_CFG_SENSE(irq);
1080 + reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
1081 + break;
1082 +
1083 + case IRQ_TYPE_EDGE_FALLING:
1084 + reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
1085 + reg &= ~EXTIRQ_CFG_SENSE(irq);
1086 + reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
1087 + break;
1088 +
1089 + case IRQ_TYPE_LEVEL_HIGH:
1090 + reg |= EXTIRQ_CFG_LEVELSENSE(irq);
1091 + reg |= EXTIRQ_CFG_SENSE(irq);
1092 + break;
1093 +
1094 + case IRQ_TYPE_LEVEL_LOW:
1095 + reg |= EXTIRQ_CFG_LEVELSENSE(irq);
1096 + reg &= ~EXTIRQ_CFG_SENSE(irq);
1097 + break;
1098 +
1099 + default:
1100 + printk(KERN_ERR "bogus flow type combination given !\n");
1101 + return -EINVAL;
1102 + }
1103 + bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
1104 +
1105 + if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
1106 + desc->status |= IRQ_LEVEL;
1107 + desc->handle_irq = handle_level_irq;
1108 + } else {
1109 + desc->handle_irq = handle_edge_irq;
1110 + }
1111 +
1112 + return 0;
1113 +}
1114 +
1115 +static struct irq_chip bcm63xx_internal_irq_chip = {
1116 + .name = "bcm63xx_ipic",
1117 + .startup = bcm63xx_internal_irq_startup,
1118 + .shutdown = bcm63xx_internal_irq_mask,
1119 +
1120 + .mask = bcm63xx_internal_irq_mask,
1121 + .mask_ack = bcm63xx_internal_irq_mask,
1122 + .unmask = bcm63xx_internal_irq_unmask,
1123 +};
1124 +
1125 +static struct irq_chip bcm63xx_external_irq_chip = {
1126 + .name = "bcm63xx_epic",
1127 + .startup = bcm63xx_external_irq_startup,
1128 + .shutdown = bcm63xx_external_irq_shutdown,
1129 +
1130 + .ack = bcm63xx_external_irq_clear,
1131 +
1132 + .mask = bcm63xx_external_irq_mask,
1133 + .unmask = bcm63xx_external_irq_unmask,
1134 +
1135 + .set_type = bcm63xx_external_irq_set_type,
1136 +};
1137 +
1138 +static struct irqaction cpu_ip2_cascade_action = {
1139 + .handler = no_action,
1140 + .name = "cascade_ip2",
1141 +};
1142 +
1143 +void __init arch_init_irq(void)
1144 +{
1145 + int i;
1146 +
1147 + mips_cpu_irq_init();
1148 + for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
1149 + set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip,
1150 + handle_level_irq);
1151 +
1152 + for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
1153 + set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip,
1154 + handle_edge_irq);
1155 +
1156 + setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
1157 +}
1158 diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
1159 new file mode 100644
1160 index 0000000..f0b49e8
1161 --- /dev/null
1162 +++ b/arch/mips/bcm63xx/prom.c
1163 @@ -0,0 +1,43 @@
1164 +/*
1165 + * This file is subject to the terms and conditions of the GNU General Public
1166 + * License. See the file "COPYING" in the main directory of this archive
1167 + * for more details.
1168 + *
1169 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
1170 + */
1171 +
1172 +#include <linux/init.h>
1173 +#include <linux/bootmem.h>
1174 +#include <asm/bootinfo.h>
1175 +#include <bcm63xx_cpu.h>
1176 +#include <bcm63xx_io.h>
1177 +#include <bcm63xx_regs.h>
1178 +
1179 +void __init prom_init(void)
1180 +{
1181 + u32 reg, mask;
1182 +
1183 + bcm63xx_cpu_init();
1184 +
1185 + /* stop any running watchdog */
1186 + bcm_wdt_writel(WDT_STOP_1, WDT_CTL_REG);
1187 + bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
1188 +
1189 + /* disable all hardware blocks clock for now */
1190 + if (BCMCPU_IS_6348())
1191 + mask = CKCTL_6348_ALL_SAFE_EN;
1192 + else
1193 + /* BCMCPU_IS_6358() */
1194 + mask = CKCTL_6358_ALL_SAFE_EN;
1195 +
1196 + reg = bcm_perf_readl(PERF_CKCTL_REG);
1197 + reg &= ~mask;
1198 + bcm_perf_writel(reg, PERF_CKCTL_REG);
1199 +
1200 + /* assign command line from kernel config */
1201 + strcpy(arcs_cmdline, CONFIG_CMDLINE);
1202 +}
1203 +
1204 +void __init prom_free_prom_memory(void)
1205 +{
1206 +}
1207 diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
1208 new file mode 100644
1209 index 0000000..55c51a9
1210 --- /dev/null
1211 +++ b/arch/mips/bcm63xx/setup.c
1212 @@ -0,0 +1,108 @@
1213 +/*
1214 + * This file is subject to the terms and conditions of the GNU General Public
1215 + * License. See the file "COPYING" in the main directory of this archive
1216 + * for more details.
1217 + *
1218 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
1219 + */
1220 +
1221 +#include <linux/init.h>
1222 +#include <linux/kernel.h>
1223 +#include <linux/delay.h>
1224 +#include <linux/bootmem.h>
1225 +#include <linux/ioport.h>
1226 +#include <linux/pm.h>
1227 +#include <asm/bootinfo.h>
1228 +#include <asm/time.h>
1229 +#include <asm/reboot.h>
1230 +#include <asm/cacheflush.h>
1231 +#include <bcm63xx_cpu.h>
1232 +#include <bcm63xx_regs.h>
1233 +#include <bcm63xx_io.h>
1234 +
1235 +void bcm63xx_machine_halt(void)
1236 +{
1237 + printk(KERN_INFO "System halted\n");
1238 + while (1);
1239 +}
1240 +
1241 +static void bcm6348_a1_reboot(void)
1242 +{
1243 + u32 reg;
1244 +
1245 + /* soft reset all blocks */
1246 + printk(KERN_INFO "soft-reseting all blocks ...\n");
1247 + reg = bcm_perf_readl(PERF_SOFTRESET_REG);
1248 + reg &= ~SOFTRESET_6348_ALL;
1249 + bcm_perf_writel(reg, PERF_SOFTRESET_REG);
1250 + mdelay(10);
1251 +
1252 + reg = bcm_perf_readl(PERF_SOFTRESET_REG);
1253 + reg |= SOFTRESET_6348_ALL;
1254 + bcm_perf_writel(reg, PERF_SOFTRESET_REG);
1255 + mdelay(10);
1256 +
1257 + /* Jump to the power on address. */
1258 + printk(KERN_INFO "jumping to reset vector.\n");
1259 + /* set high vectors (base at 0xbfc00000 */
1260 + set_c0_status(ST0_BEV | ST0_ERL);
1261 + /* run uncached in kseg0 */
1262 + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
1263 + __flush_cache_all();
1264 + /* remove all wired TLB entries */
1265 + write_c0_wired(0);
1266 + __asm__ __volatile__(
1267 + "jr\t%0"
1268 + :
1269 + : "r" (0xbfc00000));
1270 + while (1);
1271 +}
1272 +
1273 +void bcm63xx_machine_reboot(void)
1274 +{
1275 + u32 reg;
1276 +
1277 + /* mask and clear all external irq */
1278 + reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
1279 + reg &= ~EXTIRQ_CFG_MASK_ALL;
1280 + reg |= EXTIRQ_CFG_CLEAR_ALL;
1281 + bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
1282 +
1283 + if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
1284 + bcm6348_a1_reboot();
1285 +
1286 + printk(KERN_INFO "triggering watchdog soft-reset...\n");
1287 + bcm_perf_writel(SYS_PLL_SOFT_RESET, PERF_SYS_PLL_CTL_REG);
1288 + while (1);
1289 +}
1290 +
1291 +static void __bcm63xx_machine_reboot(char *p)
1292 +{
1293 + bcm63xx_machine_reboot();
1294 +}
1295 +
1296 +/*
1297 + * return system type in /proc/cpuinfo
1298 + */
1299 +const char *get_system_type(void)
1300 +{
1301 + static char buf[128];
1302 + sprintf(buf, "bcm963xx (0x%04x/0x%04X)",
1303 + bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev());
1304 + return buf;
1305 +}
1306 +
1307 +void __init plat_time_init(void)
1308 +{
1309 + mips_hpt_frequency = bcm63xx_get_cpu_freq() / 2;
1310 +}
1311 +void __init plat_mem_setup(void)
1312 +{
1313 + add_memory_region(0, bcm63xx_get_memory_size(), BOOT_MEM_RAM);
1314 +
1315 + _machine_halt = bcm63xx_machine_halt;
1316 + _machine_restart = __bcm63xx_machine_reboot;
1317 + pm_power_off = bcm63xx_machine_halt;
1318 +
1319 + set_io_port_base(0);
1320 +}
1321 diff --git a/arch/mips/bcm63xx/timer.c b/arch/mips/bcm63xx/timer.c
1322 new file mode 100644
1323 index 0000000..ba522bd
1324 --- /dev/null
1325 +++ b/arch/mips/bcm63xx/timer.c
1326 @@ -0,0 +1,205 @@
1327 +/*
1328 + * This file is subject to the terms and conditions of the GNU General Public
1329 + * License. See the file "COPYING" in the main directory of this archive
1330 + * for more details.
1331 + *
1332 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
1333 + */
1334 +
1335 +#include <linux/kernel.h>
1336 +#include <linux/err.h>
1337 +#include <linux/module.h>
1338 +#include <linux/spinlock.h>
1339 +#include <linux/interrupt.h>
1340 +#include <linux/clk.h>
1341 +#include <bcm63xx_cpu.h>
1342 +#include <bcm63xx_io.h>
1343 +#include <bcm63xx_timer.h>
1344 +#include <bcm63xx_regs.h>
1345 +
1346 +static DEFINE_SPINLOCK(timer_reg_lock);
1347 +static DEFINE_SPINLOCK(timer_data_lock);
1348 +static struct clk *periph_clk;
1349 +
1350 +static struct timer_data {
1351 + void (*cb)(void *);
1352 + void *data;
1353 +} timer_data[BCM63XX_TIMER_COUNT];
1354 +
1355 +static irqreturn_t timer_interrupt(int irq, void *dev_id)
1356 +{
1357 + u32 stat;
1358 + int i;
1359 +
1360 + spin_lock(&timer_reg_lock);
1361 + stat = bcm_timer_readl(TIMER_IRQSTAT_REG);
1362 + bcm_timer_writel(stat, TIMER_IRQSTAT_REG);
1363 + spin_unlock(&timer_reg_lock);
1364 +
1365 + for (i = 0; i < BCM63XX_TIMER_COUNT; i++) {
1366 + if (!(stat & TIMER_IRQSTAT_TIMER_CAUSE(i)))
1367 + continue;
1368 +
1369 + spin_lock(&timer_data_lock);
1370 + if (!timer_data[i].cb) {
1371 + spin_unlock(&timer_data_lock);
1372 + continue;
1373 + }
1374 +
1375 + timer_data[i].cb(timer_data[i].data);
1376 + spin_unlock(&timer_data_lock);
1377 + }
1378 +
1379 + return IRQ_HANDLED;
1380 +}
1381 +
1382 +int bcm63xx_timer_enable(int id)
1383 +{
1384 + u32 reg;
1385 + unsigned long flags;
1386 +
1387 + if (id >= BCM63XX_TIMER_COUNT)
1388 + return -EINVAL;
1389 +
1390 + spin_lock_irqsave(&timer_reg_lock, flags);
1391 +
1392 + reg = bcm_timer_readl(TIMER_CTLx_REG(id));
1393 + reg |= TIMER_CTL_ENABLE_MASK;
1394 + bcm_timer_writel(reg, TIMER_CTLx_REG(id));
1395 +
1396 + reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
1397 + reg |= TIMER_IRQSTAT_TIMER_IR_EN(id);
1398 + bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
1399 +
1400 + spin_unlock_irqrestore(&timer_reg_lock, flags);
1401 + return 0;
1402 +}
1403 +
1404 +EXPORT_SYMBOL(bcm63xx_timer_enable);
1405 +
1406 +int bcm63xx_timer_disable(int id)
1407 +{
1408 + u32 reg;
1409 + unsigned long flags;
1410 +
1411 + if (id >= BCM63XX_TIMER_COUNT)
1412 + return -EINVAL;
1413 +
1414 + spin_lock_irqsave(&timer_reg_lock, flags);
1415 +
1416 + reg = bcm_timer_readl(TIMER_CTLx_REG(id));
1417 + reg &= ~TIMER_CTL_ENABLE_MASK;
1418 + bcm_timer_writel(reg, TIMER_CTLx_REG(id));
1419 +
1420 + reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
1421 + reg &= ~TIMER_IRQSTAT_TIMER_IR_EN(id);
1422 + bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
1423 +
1424 + spin_unlock_irqrestore(&timer_reg_lock, flags);
1425 + return 0;
1426 +}
1427 +
1428 +EXPORT_SYMBOL(bcm63xx_timer_disable);
1429 +
1430 +int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data)
1431 +{
1432 + unsigned long flags;
1433 + int ret;
1434 +
1435 + if (id >= BCM63XX_TIMER_COUNT || !callback)
1436 + return -EINVAL;
1437 +
1438 + ret = 0;
1439 + spin_lock_irqsave(&timer_data_lock, flags);
1440 + if (timer_data[id].cb) {
1441 + ret = -EBUSY;
1442 + goto out;
1443 + }
1444 +
1445 + timer_data[id].cb = callback;
1446 + timer_data[id].data = data;
1447 +
1448 +out:
1449 + spin_unlock_irqrestore(&timer_data_lock, flags);
1450 + return ret;
1451 +}
1452 +
1453 +EXPORT_SYMBOL(bcm63xx_timer_register);
1454 +
1455 +void bcm63xx_timer_unregister(int id)
1456 +{
1457 + unsigned long flags;
1458 +
1459 + if (id >= BCM63XX_TIMER_COUNT)
1460 + return;
1461 +
1462 + spin_lock_irqsave(&timer_data_lock, flags);
1463 + timer_data[id].cb = NULL;
1464 + spin_unlock_irqrestore(&timer_data_lock, flags);
1465 +}
1466 +
1467 +EXPORT_SYMBOL(bcm63xx_timer_unregister);
1468 +
1469 +unsigned int bcm63xx_timer_countdown(unsigned int countdown_us)
1470 +{
1471 + return (clk_get_rate(periph_clk) / (1000 * 1000)) * countdown_us;
1472 +}
1473 +
1474 +EXPORT_SYMBOL(bcm63xx_timer_countdown);
1475 +
1476 +int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us)
1477 +{
1478 + u32 reg, countdown;
1479 + unsigned long flags;
1480 +
1481 + if (id >= BCM63XX_TIMER_COUNT)
1482 + return -EINVAL;
1483 +
1484 + countdown = bcm63xx_timer_countdown(countdown_us);
1485 + if (countdown & ~TIMER_CTL_COUNTDOWN_MASK)
1486 + return -EINVAL;
1487 +
1488 + spin_lock_irqsave(&timer_reg_lock, flags);
1489 + reg = bcm_timer_readl(TIMER_CTLx_REG(id));
1490 +
1491 + if (monotonic)
1492 + reg &= ~TIMER_CTL_MONOTONIC_MASK;
1493 + else
1494 + reg |= TIMER_CTL_MONOTONIC_MASK;
1495 +
1496 + reg &= ~TIMER_CTL_COUNTDOWN_MASK;
1497 + reg |= countdown;
1498 + bcm_timer_writel(reg, TIMER_CTLx_REG(id));
1499 +
1500 + spin_unlock_irqrestore(&timer_reg_lock, flags);
1501 + return 0;
1502 +}
1503 +
1504 +EXPORT_SYMBOL(bcm63xx_timer_set);
1505 +
1506 +int bcm63xx_timer_init(void)
1507 +{
1508 + int ret, irq;
1509 + u32 reg;
1510 +
1511 + reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
1512 + reg &= ~TIMER_IRQSTAT_TIMER0_IR_EN;
1513 + reg &= ~TIMER_IRQSTAT_TIMER1_IR_EN;
1514 + reg &= ~TIMER_IRQSTAT_TIMER2_IR_EN;
1515 + bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
1516 +
1517 + periph_clk = clk_get(NULL, "periph");
1518 + if (IS_ERR(periph_clk))
1519 + return -ENODEV;
1520 +
1521 + irq = bcm63xx_get_irq_number(IRQ_TIMER);
1522 + ret = request_irq(irq, timer_interrupt, 0, "bcm63xx_timer", NULL);
1523 + if (ret) {
1524 + printk(KERN_ERR "bcm63xx_timer: failed to register irq\n");
1525 + return ret;
1526 + }
1527 +
1528 + return 0;
1529 +}
1530 +
1531 +arch_initcall(bcm63xx_timer_init);
1532 diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h
1533 index 9cc8522..884c7a9 100644
1534 --- a/include/asm-mips/fixmap.h
1535 +++ b/include/asm-mips/fixmap.h
1536 @@ -67,11 +67,15 @@ enum fixed_addresses {
1537 * the start of the fixmap, and leave one page empty
1538 * at the top of mem..
1539 */
1540 +#ifdef CONFIG_BCM63XX
1541 +#define FIXADDR_TOP ((unsigned long)(long)(int)0xff000000)
1542 +#else
1543 #if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX)
1544 #define FIXADDR_TOP ((unsigned long)(long)(int)(0xff000000 - 0x20000))
1545 #else
1546 #define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
1547 #endif
1548 +#endif
1549 #define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
1550 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
1551
1552 diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_clk.h b/include/asm-mips/mach-bcm63xx/bcm63xx_clk.h
1553 new file mode 100644
1554 index 0000000..8fcf8df
1555 --- /dev/null
1556 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_clk.h
1557 @@ -0,0 +1,11 @@
1558 +#ifndef BCM63XX_CLK_H_
1559 +#define BCM63XX_CLK_H_
1560 +
1561 +struct clk {
1562 + void (*set)(struct clk *, int);
1563 + unsigned int rate;
1564 + unsigned int usage;
1565 + int id;
1566 +};
1567 +
1568 +#endif /* ! BCM63XX_CLK_H_ */
1569 diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h b/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
1570 new file mode 100644
1571 index 0000000..29b61fd
1572 --- /dev/null
1573 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
1574 @@ -0,0 +1,314 @@
1575 +#ifndef BCM63XX_CPU_H_
1576 +#define BCM63XX_CPU_H_
1577 +
1578 +#include <linux/types.h>
1579 +#include <linux/init.h>
1580 +
1581 +/*
1582 + * Macro to fetch bcm63xx cpu id and revision, should be optimized at
1583 + * compile time if only one CPU support is enabled (idea stolen from
1584 + * arm mach-types)
1585 + */
1586 +#define BCM6348_CPU_ID 0x6348
1587 +#define BCM6358_CPU_ID 0x6358
1588 +
1589 +void __init bcm63xx_cpu_init(void);
1590 +u16 __bcm63xx_get_cpu_id(void);
1591 +u16 bcm63xx_get_cpu_rev(void);
1592 +unsigned int bcm63xx_get_cpu_freq(void);
1593 +
1594 +#ifdef CONFIG_BCM63XX_CPU_6348
1595 +# ifdef bcm63xx_get_cpu_id
1596 +# undef bcm63xx_get_cpu_id
1597 +# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
1598 +# define BCMCPU_RUNTIME_DETECT
1599 +# else
1600 +# define bcm63xx_get_cpu_id() BCM6348_CPU_ID
1601 +# endif
1602 +# define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
1603 +#else
1604 +# define BCMCPU_IS_6348() (0)
1605 +#endif
1606 +
1607 +#ifdef CONFIG_BCM63XX_CPU_6358
1608 +# ifdef bcm63xx_get_cpu_id
1609 +# undef bcm63xx_get_cpu_id
1610 +# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
1611 +# define BCMCPU_RUNTIME_DETECT
1612 +# else
1613 +# define bcm63xx_get_cpu_id() BCM6358_CPU_ID
1614 +# endif
1615 +# define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
1616 +#else
1617 +# define BCMCPU_IS_6358() (0)
1618 +#endif
1619 +
1620 +#ifndef bcm63xx_get_cpu_id
1621 +#error "No CPU support configured"
1622 +#endif
1623 +
1624 +/*
1625 + * While registers sets are (mostly) the same across 63xx CPU, base
1626 + * address of these sets do change.
1627 + */
1628 +enum bcm63xx_regs_set {
1629 + RSET_DSL_LMEM = 0,
1630 + RSET_PERF,
1631 + RSET_TIMER,
1632 + RSET_WDT,
1633 + RSET_UART0,
1634 + RSET_GPIO,
1635 + RSET_SPI,
1636 + RSET_UDC0,
1637 + RSET_OHCI0,
1638 + RSET_OHCI_PRIV,
1639 + RSET_USBH_PRIV,
1640 + RSET_MPI,
1641 + RSET_PCMCIA,
1642 + RSET_DSL,
1643 + RSET_ENET0,
1644 + RSET_ENET1,
1645 + RSET_ENETDMA,
1646 + RSET_EHCI0,
1647 + RSET_SDRAM,
1648 + RSET_MEMC,
1649 + RSET_DDR,
1650 +};
1651 +
1652 +#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
1653 +#define RSET_DSL_SIZE 4096
1654 +#define RSET_WDT_SIZE 12
1655 +#define RSET_ENET_SIZE 2048
1656 +#define RSET_ENETDMA_SIZE 2048
1657 +#define RSET_UART_SIZE 24
1658 +#define RSET_UDC_SIZE 256
1659 +#define RSET_OHCI_SIZE 256
1660 +#define RSET_EHCI_SIZE 256
1661 +#define RSET_PCMCIA_SIZE 12
1662 +
1663 +/*
1664 + * 6348 register sets base address
1665 + */
1666 +#define BCM_6348_DSL_LMEM_BASE (0xfff00000)
1667 +#define BCM_6348_PERF_BASE (0xfffe0000)
1668 +#define BCM_6348_TIMER_BASE (0xfffe0200)
1669 +#define BCM_6348_WDT_BASE (0xfffe021c)
1670 +#define BCM_6348_UART0_BASE (0xfffe0300)
1671 +#define BCM_6348_GPIO_BASE (0xfffe0400)
1672 +#define BCM_6348_SPI_BASE (0xfffe0c00)
1673 +#define BCM_6348_UDC0_BASE (0xfffe1000)
1674 +#define BCM_6348_OHCI0_BASE (0xfffe1b00)
1675 +#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
1676 +#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
1677 +#define BCM_6348_MPI_BASE (0xfffe2000)
1678 +#define BCM_6348_PCMCIA_BASE (0xfffe2054)
1679 +#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
1680 +#define BCM_6348_DSL_BASE (0xfffe3000)
1681 +#define BCM_6348_ENET0_BASE (0xfffe6000)
1682 +#define BCM_6348_ENET1_BASE (0xfffe6800)
1683 +#define BCM_6348_ENETDMA_BASE (0xfffe7000)
1684 +#define BCM_6348_EHCI0_BASE (0xdeadbeef)
1685 +#define BCM_6348_SDRAM_BASE (0xfffe2300)
1686 +#define BCM_6348_MEMC_BASE (0xdeadbeef)
1687 +#define BCM_6348_DDR_BASE (0xdeadbeef)
1688 +
1689 +/*
1690 + * 6358 register sets base address
1691 + */
1692 +#define BCM_6358_DSL_LMEM_BASE (0xfff00000)
1693 +#define BCM_6358_PERF_BASE (0xfffe0000)
1694 +#define BCM_6358_TIMER_BASE (0xfffe0040)
1695 +#define BCM_6358_WDT_BASE (0xfffe005c)
1696 +#define BCM_6358_UART0_BASE (0xfffe0100)
1697 +#define BCM_6358_GPIO_BASE (0xfffe0080)
1698 +#define BCM_6358_SPI_BASE (0xdeadbeef)
1699 +#define BCM_6358_UDC0_BASE (0xfffe0800)
1700 +#define BCM_6358_OHCI0_BASE (0xfffe1400)
1701 +#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
1702 +#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
1703 +#define BCM_6358_MPI_BASE (0xfffe1000)
1704 +#define BCM_6358_PCMCIA_BASE (0xfffe1054)
1705 +#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
1706 +#define BCM_6358_DSL_BASE (0xfffe3000)
1707 +#define BCM_6358_ENET0_BASE (0xfffe4000)
1708 +#define BCM_6358_ENET1_BASE (0xfffe4800)
1709 +#define BCM_6358_ENETDMA_BASE (0xfffe5000)
1710 +#define BCM_6358_EHCI0_BASE (0xfffe1300)
1711 +#define BCM_6358_SDRAM_BASE (0xdeadbeef)
1712 +#define BCM_6358_MEMC_BASE (0xfffe1200)
1713 +#define BCM_6358_DDR_BASE (0xfffe12a0)
1714 +
1715 +
1716 +extern const unsigned long *bcm63xx_regs_base;
1717 +
1718 +static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
1719 +{
1720 +#ifdef BCMCPU_RUNTIME_DETECT
1721 + return bcm63xx_regs_base[set];
1722 +#else
1723 +#ifdef CONFIG_BCM63XX_CPU_6348
1724 + switch (set) {
1725 + case RSET_DSL_LMEM:
1726 + return BCM_6348_DSL_LMEM_BASE;
1727 + case RSET_PERF:
1728 + return BCM_6348_PERF_BASE;
1729 + case RSET_TIMER:
1730 + return BCM_6348_TIMER_BASE;
1731 + case RSET_WDT:
1732 + return BCM_6348_WDT_BASE;
1733 + case RSET_UART0:
1734 + return BCM_6348_UART0_BASE;
1735 + case RSET_GPIO:
1736 + return BCM_6348_GPIO_BASE;
1737 + case RSET_SPI:
1738 + return BCM_6348_SPI_BASE;
1739 + case RSET_UDC0:
1740 + return BCM_6348_UDC0_BASE;
1741 + case RSET_OHCI0:
1742 + return BCM_6348_OHCI0_BASE;
1743 + case RSET_OHCI_PRIV:
1744 + return BCM_6348_OHCI_PRIV_BASE;
1745 + case RSET_USBH_PRIV:
1746 + return BCM_6348_USBH_PRIV_BASE;
1747 + case RSET_MPI:
1748 + return BCM_6348_MPI_BASE;
1749 + case RSET_PCMCIA:
1750 + return BCM_6348_PCMCIA_BASE;
1751 + case RSET_DSL:
1752 + return BCM_6348_DSL_BASE;
1753 + case RSET_ENET0:
1754 + return BCM_6348_ENET0_BASE;
1755 + case RSET_ENET1:
1756 + return BCM_6348_ENET1_BASE;
1757 + case RSET_ENETDMA:
1758 + return BCM_6348_ENETDMA_BASE;
1759 + case RSET_EHCI0:
1760 + return BCM_6348_EHCI0_BASE;
1761 + case RSET_SDRAM:
1762 + return BCM_6348_SDRAM_BASE;
1763 + case RSET_MEMC:
1764 + return BCM_6348_MEMC_BASE;
1765 + case RSET_DDR:
1766 + return BCM_6348_DDR_BASE;
1767 + }
1768 +#endif
1769 +#ifdef CONFIG_BCM63XX_CPU_6358
1770 + switch (set) {
1771 + case RSET_DSL_LMEM:
1772 + return BCM_6358_DSL_LMEM_BASE;
1773 + case RSET_PERF:
1774 + return BCM_6358_PERF_BASE;
1775 + case RSET_TIMER:
1776 + return BCM_6358_TIMER_BASE;
1777 + case RSET_WDT:
1778 + return BCM_6358_WDT_BASE;
1779 + case RSET_UART0:
1780 + return BCM_6358_UART0_BASE;
1781 + case RSET_GPIO:
1782 + return BCM_6358_GPIO_BASE;
1783 + case RSET_SPI:
1784 + return BCM_6358_SPI_BASE;
1785 + case RSET_UDC0:
1786 + return BCM_6358_UDC0_BASE;
1787 + case RSET_OHCI0:
1788 + return BCM_6358_OHCI0_BASE;
1789 + case RSET_OHCI_PRIV:
1790 + return BCM_6358_OHCI_PRIV_BASE;
1791 + case RSET_USBH_PRIV:
1792 + return BCM_6358_USBH_PRIV_BASE;
1793 + case RSET_MPI:
1794 + return BCM_6358_MPI_BASE;
1795 + case RSET_PCMCIA:
1796 + return BCM_6358_PCMCIA_BASE;
1797 + case RSET_ENET0:
1798 + return BCM_6358_ENET0_BASE;
1799 + case RSET_ENET1:
1800 + return BCM_6358_ENET1_BASE;
1801 + case RSET_ENETDMA:
1802 + return BCM_6358_ENETDMA_BASE;
1803 + case RSET_DSL:
1804 + return BCM_6358_DSL_BASE;
1805 + case RSET_EHCI0:
1806 + return BCM_6358_EHCI0_BASE;
1807 + case RSET_SDRAM:
1808 + return BCM_6358_SDRAM_BASE;
1809 + case RSET_MEMC:
1810 + return BCM_6358_MEMC_BASE;
1811 + case RSET_DDR:
1812 + return BCM_6358_DDR_BASE;
1813 + }
1814 +#endif
1815 +#endif
1816 + /* unreached */
1817 + return 0;
1818 +}
1819 +
1820 +/*
1821 + * IRQ number changes across CPU too
1822 + */
1823 +enum bcm63xx_irq {
1824 + IRQ_TIMER = 0,
1825 + IRQ_UART0,
1826 + IRQ_DSL,
1827 + IRQ_ENET0,
1828 + IRQ_ENET1,
1829 + IRQ_ENET_PHY,
1830 + IRQ_OHCI0,
1831 + IRQ_EHCI0,
1832 + IRQ_PCMCIA0,
1833 + IRQ_ENET0_RXDMA,
1834 + IRQ_ENET0_TXDMA,
1835 + IRQ_ENET1_RXDMA,
1836 + IRQ_ENET1_TXDMA,
1837 + IRQ_PCI,
1838 + IRQ_PCMCIA,
1839 +};
1840 +
1841 +/*
1842 + * 6348 irqs
1843 + */
1844 +#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
1845 +#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
1846 +#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
1847 +#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
1848 +#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
1849 +#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
1850 +#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
1851 +#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
1852 +#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
1853 +#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
1854 +#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
1855 +#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
1856 +#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
1857 +
1858 +/*
1859 + * 6358 irqs
1860 + */
1861 +#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
1862 +#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
1863 +#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
1864 +#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
1865 +#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
1866 +#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
1867 +#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
1868 +#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
1869 +#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
1870 +#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
1871 +#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
1872 +#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
1873 +#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
1874 +#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
1875 +
1876 +extern const int *bcm63xx_irqs;
1877 +
1878 +static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
1879 +{
1880 + return bcm63xx_irqs[irq];
1881 +}
1882 +
1883 +/*
1884 + * return installed memory size
1885 + */
1886 +unsigned int bcm63xx_get_memory_size(void);
1887 +
1888 +#endif /* !BCM63XX_CPU_H_ */
1889 diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_cs.h b/include/asm-mips/mach-bcm63xx/bcm63xx_cs.h
1890 new file mode 100644
1891 index 0000000..b1821c8
1892 --- /dev/null
1893 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_cs.h
1894 @@ -0,0 +1,10 @@
1895 +#ifndef BCM63XX_CS_H
1896 +#define BCM63XX_CS_H
1897 +
1898 +int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size);
1899 +int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
1900 + unsigned int setup, unsigned int hold);
1901 +int bcm63xx_set_cs_param(unsigned int cs, u32 flags);
1902 +int bcm63xx_set_cs_status(unsigned int cs, int enable);
1903 +
1904 +#endif /* !BCM63XX_CS_H */
1905 diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h b/include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h
1906 new file mode 100644
1907 index 0000000..31145df
1908 --- /dev/null
1909 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h
1910 @@ -0,0 +1,14 @@
1911 +#ifndef BCM63XX_GPIO_H
1912 +#define BCM63XX_GPIO_H
1913 +
1914 +/* all helpers will BUG() if gpio count is >= 37. */
1915 +#define BCM63XX_GPIO_COUNT 37
1916 +
1917 +void bcm63xx_gpio_set_dataout(int gpio, int val);
1918 +int bcm63xx_gpio_get_datain(int gpio);
1919 +void bcm63xx_gpio_set_direction(int gpio, int dir);
1920 +
1921 +#define GPIO_DIR_OUT 0x0
1922 +#define GPIO_DIR_IN 0x1
1923 +
1924 +#endif /* !BCM63XX_GPIO_H */
1925 diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_io.h b/include/asm-mips/mach-bcm63xx/bcm63xx_io.h
1926 new file mode 100644
1927 index 0000000..1aef06f
1928 --- /dev/null
1929 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_io.h
1930 @@ -0,0 +1,93 @@
1931 +#ifndef BCM63XX_IO_H_
1932 +#define BCM63XX_IO_H_
1933 +
1934 +#include "bcm63xx_cpu.h"
1935 +
1936 +/*
1937 + * Physical memory map, RAM is mapped at 0x0.
1938 + *
1939 + * Note that size MUST be a power of two.
1940 + */
1941 +#define BCM_PCMCIA_COMMON_BASE_PA (0x20000000)
1942 +#define BCM_PCMCIA_COMMON_SIZE (16 * 1024 * 1024)
1943 +#define BCM_PCMCIA_COMMON_END_PA (BCM_PCMCIA_COMMON_BASE_PA + \
1944 + BCM_PCMCIA_COMMON_SIZE - 1)
1945 +
1946 +#define BCM_PCMCIA_ATTR_BASE_PA (0x21000000)
1947 +#define BCM_PCMCIA_ATTR_SIZE (16 * 1024 * 1024)
1948 +#define BCM_PCMCIA_ATTR_END_PA (BCM_PCMCIA_ATTR_BASE_PA + \
1949 + BCM_PCMCIA_ATTR_SIZE - 1)
1950 +
1951 +#define BCM_PCMCIA_IO_BASE_PA (0x22000000)
1952 +#define BCM_PCMCIA_IO_SIZE (64 * 1024)
1953 +#define BCM_PCMCIA_IO_END_PA (BCM_PCMCIA_IO_BASE_PA + \
1954 + BCM_PCMCIA_IO_SIZE - 1)
1955 +
1956 +#define BCM_PCI_MEM_BASE_PA (0x30000000)
1957 +#define BCM_PCI_MEM_SIZE (128 * 1024 * 1024)
1958 +#define BCM_PCI_MEM_END_PA (BCM_PCI_MEM_BASE_PA + \
1959 + BCM_PCI_MEM_SIZE - 1)
1960 +
1961 +#define BCM_PCI_IO_BASE_PA (0x08000000)
1962 +#define BCM_PCI_IO_SIZE (64 * 1024)
1963 +#define BCM_PCI_IO_END_PA (BCM_PCI_IO_BASE_PA + \
1964 + BCM_PCI_IO_SIZE - 1)
1965 +#define BCM_PCI_IO_HALF_PA (BCM_PCI_IO_BASE_PA + \
1966 + (BCM_PCI_IO_SIZE / 2) - 1)
1967 +
1968 +#define BCM_CB_MEM_BASE_PA (0x38000000)
1969 +#define BCM_CB_MEM_SIZE (128 * 1024 * 1024)
1970 +#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
1971 + BCM_CB_MEM_SIZE - 1)
1972 +
1973 +
1974 +/*
1975 + * Internal registers are accessed through KSEG3
1976 + */
1977 +#define BCM_REGS_VA(x) ((void __iomem *)(x))
1978 +
1979 +#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a))
1980 +#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a))
1981 +#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a))
1982 +#define bcm_writeb(v,a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
1983 +#define bcm_writew(v,a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
1984 +#define bcm_writel(v,a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
1985 +
1986 +/*
1987 + * IO helpers to access register set for current CPU
1988 + */
1989 +#define bcm_rset_readb(s,o) bcm_readb(bcm63xx_regset_address(s) + (o))
1990 +#define bcm_rset_readw(s,o) bcm_readw(bcm63xx_regset_address(s) + (o))
1991 +#define bcm_rset_readl(s,o) bcm_readl(bcm63xx_regset_address(s) + (o))
1992 +#define bcm_rset_writeb(s,v,o) bcm_writeb((v), \
1993 + bcm63xx_regset_address(s) + (o))
1994 +#define bcm_rset_writew(s,v,o) bcm_writew((v), \
1995 + bcm63xx_regset_address(s) + (o))
1996 +#define bcm_rset_writel(s,v,o) bcm_writel((v), \
1997 + bcm63xx_regset_address(s) + (o))
1998 +
1999 +/*
2000 + * helpers for frequently used register sets
2001 + */
2002 +#define bcm_perf_readl(o) bcm_rset_readl(RSET_PERF, (o))
2003 +#define bcm_perf_writel(v,o) bcm_rset_writel(RSET_PERF, (v), (o))
2004 +#define bcm_timer_readl(o) bcm_rset_readl(RSET_TIMER, (o))
2005 +#define bcm_timer_writel(v,o) bcm_rset_writel(RSET_TIMER, (v), (o))
2006 +#define bcm_wdt_readl(o) bcm_rset_readl(RSET_WDT, (o))
2007 +#define bcm_wdt_writel(v,o) bcm_rset_writel(RSET_WDT, (v), (o))
2008 +#define bcm_gpio_readl(o) bcm_rset_readl(RSET_GPIO, (o))
2009 +#define bcm_gpio_writel(v,o) bcm_rset_writel(RSET_GPIO, (v), (o))
2010 +#define bcm_uart0_readl(o) bcm_rset_readl(RSET_UART0, (o))
2011 +#define bcm_uart0_writel(v,o) bcm_rset_writel(RSET_UART0, (v), (o))
2012 +#define bcm_mpi_readl(o) bcm_rset_readl(RSET_MPI, (o))
2013 +#define bcm_mpi_writel(v,o) bcm_rset_writel(RSET_MPI, (v), (o))
2014 +#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o))
2015 +#define bcm_pcmcia_writel(v,o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
2016 +#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o))
2017 +#define bcm_sdram_writel(v,o) bcm_rset_writel(RSET_SDRAM, (v), (o))
2018 +#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o))
2019 +#define bcm_memc_writel(v,o) bcm_rset_writel(RSET_MEMC, (v), (o))
2020 +#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
2021 +#define bcm_ddr_writel(v,o) bcm_rset_writel(RSET_DDR, (v), (o))
2022 +
2023 +#endif /* ! BCM63XX_IO_H_ */
2024 diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_irq.h b/include/asm-mips/mach-bcm63xx/bcm63xx_irq.h
2025 new file mode 100644
2026 index 0000000..5f95577
2027 --- /dev/null
2028 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_irq.h
2029 @@ -0,0 +1,15 @@
2030 +#ifndef BCM63XX_IRQ_H_
2031 +#define BCM63XX_IRQ_H_
2032 +
2033 +#include <bcm63xx_cpu.h>
2034 +
2035 +#define IRQ_MIPS_BASE 0
2036 +#define IRQ_INTERNAL_BASE 8
2037 +
2038 +#define IRQ_EXT_BASE (IRQ_MIPS_BASE + 3)
2039 +#define IRQ_EXT_0 (IRQ_EXT_BASE + 0)
2040 +#define IRQ_EXT_1 (IRQ_EXT_BASE + 1)
2041 +#define IRQ_EXT_2 (IRQ_EXT_BASE + 2)
2042 +#define IRQ_EXT_3 (IRQ_EXT_BASE + 3)
2043 +
2044 +#endif /* ! BCM63XX_IRQ_H_ */
2045 diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h b/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
2046 new file mode 100644
2047 index 0000000..b5562b1
2048 --- /dev/null
2049 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
2050 @@ -0,0 +1,728 @@
2051 +#ifndef BCM63XX_REGS_H_
2052 +#define BCM63XX_REGS_H_
2053 +
2054 +/*************************************************************************
2055 + * _REG relative to RSET_PERF
2056 + *************************************************************************/
2057 +
2058 +/* Chip Identifier / Revision register */
2059 +#define PERF_REV_REG 0x0
2060 +#define REV_CHIPID_SHIFT 16
2061 +#define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
2062 +#define REV_REVID_SHIFT 0
2063 +#define REV_REVID_MASK (0xffff << REV_REVID_SHIFT)
2064 +
2065 +/* Clock Control register */
2066 +#define PERF_CKCTL_REG 0x4
2067 +
2068 +#define CKCTL_6348_ADSLPHY_EN (1 << 0)
2069 +#define CKCTL_6348_MPI_EN (1 << 1)
2070 +#define CKCTL_6348_SDRAM_EN (1 << 2)
2071 +#define CKCTL_6348_M2M_EN (1 << 3)
2072 +#define CKCTL_6348_ENET_EN (1 << 4)
2073 +#define CKCTL_6348_SAR_EN (1 << 5)
2074 +#define CKCTL_6348_USBS_EN (1 << 6)
2075 +#define CKCTL_6348_USBH_EN (1 << 8)
2076 +#define CKCTL_6348_SPI_EN (1 << 9)
2077 +
2078 +#define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \
2079 + CKCTL_6348_M2M_EN | \
2080 + CKCTL_6348_ENET_EN | \
2081 + CKCTL_6348_SAR_EN | \
2082 + CKCTL_6348_USBS_EN | \
2083 + CKCTL_6348_USBH_EN | \
2084 + CKCTL_6348_SPI_EN)
2085 +
2086 +#define CKCTL_6358_ENET_EN (1 << 4)
2087 +#define CKCTL_6358_ADSLPHY_EN (1 << 5)
2088 +#define CKCTL_6358_PCM_EN (1 << 8)
2089 +#define CKCTL_6358_SPI_EN (1 << 9)
2090 +#define CKCTL_6358_USBS_EN (1 << 10)
2091 +#define CKCTL_6358_SAR_EN (1 << 11)
2092 +#define CKCTL_6358_EMUSB_EN (1 << 17)
2093 +#define CKCTL_6358_ENET0_EN (1 << 18)
2094 +#define CKCTL_6358_ENET1_EN (1 << 19)
2095 +#define CKCTL_6358_USBSU_EN (1 << 20)
2096 +#define CKCTL_6358_EPHY_EN (1 << 21)
2097 +
2098 +#define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \
2099 + CKCTL_6358_ADSLPHY_EN | \
2100 + CKCTL_6358_PCM_EN | \
2101 + CKCTL_6358_SPI_EN | \
2102 + CKCTL_6358_USBS_EN | \
2103 + CKCTL_6358_SAR_EN | \
2104 + CKCTL_6358_EMUSB_EN | \
2105 + CKCTL_6358_ENET0_EN | \
2106 + CKCTL_6358_ENET1_EN | \
2107 + CKCTL_6358_USBSU_EN | \
2108 + CKCTL_6358_EPHY_EN)
2109 +
2110 +/* System PLL Control register */
2111 +#define PERF_SYS_PLL_CTL_REG 0x8
2112 +#define SYS_PLL_SOFT_RESET 0x1
2113 +
2114 +/* Interrupt Mask register */
2115 +#define PERF_IRQMASK_REG 0xc
2116 +#define PERF_IRQSTAT_REG 0x10
2117 +
2118 +/* Interrupt Status register */
2119 +#define PERF_IRQSTAT_REG 0x10
2120 +
2121 +/* External Interrupt Configuration register */
2122 +#define PERF_EXTIRQ_CFG_REG 0x14
2123 +#define EXTIRQ_CFG_SENSE(x) (1 << (x))
2124 +#define EXTIRQ_CFG_STAT(x) (1 << (x + 5))
2125 +#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10))
2126 +#define EXTIRQ_CFG_MASK(x) (1 << (x + 15))
2127 +#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20))
2128 +#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25))
2129 +
2130 +#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10)
2131 +#define EXTIRQ_CFG_MASK_ALL (0xf << 15)
2132 +
2133 +/* Soft Reset register */
2134 +#define PERF_SOFTRESET_REG 0x28
2135 +
2136 +#define SOFTRESET_6348_SPI_MASK (1 << 0)
2137 +#define SOFTRESET_6348_ENET_MASK (1 << 2)
2138 +#define SOFTRESET_6348_USBH_MASK (1 << 3)
2139 +#define SOFTRESET_6348_USBS_MASK (1 << 4)
2140 +#define SOFTRESET_6348_ADSL_MASK (1 << 5)
2141 +#define SOFTRESET_6348_DMAMEM_MASK (1 << 6)
2142 +#define SOFTRESET_6348_SAR_MASK (1 << 7)
2143 +#define SOFTRESET_6348_ACLC_MASK (1 << 8)
2144 +#define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
2145 +
2146 +#define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \
2147 + SOFTRESET_6348_ENET_MASK | \
2148 + SOFTRESET_6348_USBH_MASK | \
2149 + SOFTRESET_6348_USBS_MASK | \
2150 + SOFTRESET_6348_ADSL_MASK | \
2151 + SOFTRESET_6348_DMAMEM_MASK | \
2152 + SOFTRESET_6348_SAR_MASK | \
2153 + SOFTRESET_6348_ACLC_MASK | \
2154 + SOFTRESET_6348_ADSLMIPSPLL_MASK)
2155 +
2156 +/* MIPS PLL control register */
2157 +#define PERF_MIPSPLLCTL_REG 0x34
2158 +#define MIPSPLLCTL_N1_SHIFT 20
2159 +#define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
2160 +#define MIPSPLLCTL_N2_SHIFT 15
2161 +#define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
2162 +#define MIPSPLLCTL_M1REF_SHIFT 12
2163 +#define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
2164 +#define MIPSPLLCTL_M2REF_SHIFT 9
2165 +#define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
2166 +#define MIPSPLLCTL_M1CPU_SHIFT 6
2167 +#define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
2168 +#define MIPSPLLCTL_M1BUS_SHIFT 3
2169 +#define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
2170 +#define MIPSPLLCTL_M2BUS_SHIFT 0
2171 +#define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
2172 +
2173 +/* ADSL PHY PLL Control register */
2174 +#define PERF_ADSLPLLCTL_REG 0x38
2175 +#define ADSLPLLCTL_N1_SHIFT 20
2176 +#define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
2177 +#define ADSLPLLCTL_N2_SHIFT 15
2178 +#define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
2179 +#define ADSLPLLCTL_M1REF_SHIFT 12
2180 +#define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
2181 +#define ADSLPLLCTL_M2REF_SHIFT 9
2182 +#define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
2183 +#define ADSLPLLCTL_M1CPU_SHIFT 6
2184 +#define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
2185 +#define ADSLPLLCTL_M1BUS_SHIFT 3
2186 +#define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
2187 +#define ADSLPLLCTL_M2BUS_SHIFT 0
2188 +#define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
2189 +
2190 +#define ADSLPLLCTL_VAL(n1,n2,m1ref,m2ref,m1cpu,m1bus,m2bus) \
2191 + (((n1) << ADSLPLLCTL_N1_SHIFT) | \
2192 + ((n2) << ADSLPLLCTL_N2_SHIFT) | \
2193 + ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
2194 + ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
2195 + ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
2196 + ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
2197 + ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
2198 +
2199 +
2200 +/*************************************************************************
2201 + * _REG relative to RSET_TIMER
2202 + *************************************************************************/
2203 +
2204 +#define BCM63XX_TIMER_COUNT 4
2205 +#define TIMER_T0_ID 0
2206 +#define TIMER_T1_ID 1
2207 +#define TIMER_T2_ID 2
2208 +#define TIMER_WDT_ID 3
2209 +
2210 +/* Timer irqstat register */
2211 +#define TIMER_IRQSTAT_REG 0
2212 +#define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x))
2213 +#define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
2214 +#define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1)
2215 +#define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2)
2216 +#define TIMER_IRQSTAT_WDT_CAUSE (1 << 3)
2217 +#define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8))
2218 +#define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8)
2219 +#define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
2220 +#define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
2221 +
2222 +/* Timer control register */
2223 +#define TIMER_CTLx_REG(x) (0x4 + (x * 4))
2224 +#define TIMER_CTL0_REG 0x4
2225 +#define TIMER_CTL1_REG 0x8
2226 +#define TIMER_CTL2_REG 0xC
2227 +#define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
2228 +#define TIMER_CTL_MONOTONIC_MASK (1 << 30)
2229 +#define TIMER_CTL_ENABLE_MASK (1 << 31)
2230 +
2231 +
2232 +/*************************************************************************
2233 + * _REG relative to RSET_WDT
2234 + *************************************************************************/
2235 +
2236 +/* Watchdog default count register */
2237 +#define WDT_DEFVAL_REG 0x0
2238 +
2239 +/* Watchdog control register */
2240 +#define WDT_CTL_REG 0x4
2241 +
2242 +/* Watchdog control register constants */
2243 +#define WDT_START_1 (0xff00)
2244 +#define WDT_START_2 (0x00ff)
2245 +#define WDT_STOP_1 (0xee00)
2246 +#define WDT_STOP_2 (0x00ee)
2247 +
2248 +/* Watchdog reset length register */
2249 +#define WDT_RSTLEN_REG 0x8
2250 +
2251 +
2252 +/*************************************************************************
2253 + * _REG relative to RSET_UARTx
2254 + *************************************************************************/
2255 +
2256 +/* UART Control Register */
2257 +#define UART_CTL_REG 0x0
2258 +#define UART_CTL_RXTMOUTCNT_SHIFT 0
2259 +#define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
2260 +#define UART_CTL_RSTTXDN_SHIFT 5
2261 +#define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
2262 +#define UART_CTL_RSTRXFIFO_SHIFT 6
2263 +#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
2264 +#define UART_CTL_RSTTXFIFO_SHIFT 7
2265 +#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
2266 +#define UART_CTL_STOPBITS_SHIFT 8
2267 +#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
2268 +#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
2269 +#define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
2270 +#define UART_CTL_BITSPERSYM_SHIFT 12
2271 +#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
2272 +#define UART_CTL_XMITBRK_SHIFT 14
2273 +#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
2274 +#define UART_CTL_RSVD_SHIFT 15
2275 +#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
2276 +#define UART_CTL_RXPAREVEN_SHIFT 16
2277 +#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
2278 +#define UART_CTL_RXPAREN_SHIFT 17
2279 +#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
2280 +#define UART_CTL_TXPAREVEN_SHIFT 18
2281 +#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
2282 +#define UART_CTL_TXPAREN_SHIFT 18
2283 +#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
2284 +#define UART_CTL_LOOPBACK_SHIFT 20
2285 +#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
2286 +#define UART_CTL_RXEN_SHIFT 21
2287 +#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
2288 +#define UART_CTL_TXEN_SHIFT 22
2289 +#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
2290 +#define UART_CTL_BRGEN_SHIFT 23
2291 +#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
2292 +
2293 +/* UART Baudword register */
2294 +#define UART_BAUD_REG 0x4
2295 +
2296 +/* UART Misc Control register */
2297 +#define UART_MCTL_REG 0x8
2298 +#define UART_MCTL_DTR_SHIFT 0
2299 +#define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
2300 +#define UART_MCTL_RTS_SHIFT 1
2301 +#define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
2302 +#define UART_MCTL_RXFIFOTHRESH_SHIFT 8
2303 +#define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
2304 +#define UART_MCTL_TXFIFOTHRESH_SHIFT 12
2305 +#define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
2306 +#define UART_MCTL_RXFIFOFILL_SHIFT 16
2307 +#define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
2308 +#define UART_MCTL_TXFIFOFILL_SHIFT 24
2309 +#define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
2310 +
2311 +/* UART External Input Configuration register */
2312 +#define UART_EXTINP_REG 0xc
2313 +#define UART_EXTINP_RI_SHIFT 0
2314 +#define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
2315 +#define UART_EXTINP_CTS_SHIFT 1
2316 +#define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
2317 +#define UART_EXTINP_DCD_SHIFT 2
2318 +#define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
2319 +#define UART_EXTINP_DSR_SHIFT 3
2320 +#define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
2321 +#define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
2322 +#define UART_EXTINP_IRMASK(x) (1 << (x + 8))
2323 +#define UART_EXTINP_IR_RI 0
2324 +#define UART_EXTINP_IR_CTS 1
2325 +#define UART_EXTINP_IR_DCD 2
2326 +#define UART_EXTINP_IR_DSR 3
2327 +#define UART_EXTINP_RI_NOSENSE_SHIFT 16
2328 +#define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
2329 +#define UART_EXTINP_CTS_NOSENSE_SHIFT 17
2330 +#define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
2331 +#define UART_EXTINP_DCD_NOSENSE_SHIFT 18
2332 +#define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
2333 +#define UART_EXTINP_DSR_NOSENSE_SHIFT 19
2334 +#define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
2335 +
2336 +/* UART Interrupt register */
2337 +#define UART_IR_REG 0x10
2338 +#define UART_IR_MASK(x) (1 << (x + 16))
2339 +#define UART_IR_STAT(x) (1 << (x))
2340 +#define UART_IR_EXTIP 0
2341 +#define UART_IR_TXUNDER 1
2342 +#define UART_IR_TXOVER 2
2343 +#define UART_IR_TXTRESH 3
2344 +#define UART_IR_TXRDLATCH 4
2345 +#define UART_IR_TXEMPTY 5
2346 +#define UART_IR_RXUNDER 6
2347 +#define UART_IR_RXOVER 7
2348 +#define UART_IR_RXTIMEOUT 8
2349 +#define UART_IR_RXFULL 9
2350 +#define UART_IR_RXTHRESH 10
2351 +#define UART_IR_RXNOTEMPTY 11
2352 +#define UART_IR_RXFRAMEERR 12
2353 +#define UART_IR_RXPARERR 13
2354 +#define UART_IR_RXBRK 14
2355 +#define UART_IR_TXDONE 15
2356 +
2357 +/* UART Fifo register */
2358 +#define UART_FIFO_REG 0x14
2359 +#define UART_FIFO_VALID_SHIFT 0
2360 +#define UART_FIFO_VALID_MASK 0xff
2361 +#define UART_FIFO_FRAMEERR_SHIFT 8
2362 +#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
2363 +#define UART_FIFO_PARERR_SHIFT 9
2364 +#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
2365 +#define UART_FIFO_BRKDET_SHIFT 10
2366 +#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
2367 +#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
2368 + UART_FIFO_PARERR_MASK | \
2369 + UART_FIFO_BRKDET_MASK)
2370 +
2371 +
2372 +/*************************************************************************
2373 + * _REG relative to RSET_GPIO
2374 + *************************************************************************/
2375 +
2376 +/* GPIO registers */
2377 +#define GPIO_CTL_HI_REG 0x0
2378 +#define GPIO_CTL_LO_REG 0x4
2379 +#define GPIO_DATA_HI_REG 0x8
2380 +#define GPIO_DATA_LO_REG 0xC
2381 +
2382 +/* GPIO mux registers and constants */
2383 +#define GPIO_MODE_REG 0x18
2384 +
2385 +#define GPIO_MODE_6348_G4_DIAG 0x00090000
2386 +#define GPIO_MODE_6348_G4_UTOPIA 0x00080000
2387 +#define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
2388 +#define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
2389 +#define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
2390 +#define GPIO_MODE_6348_G3_DIAG 0x00009000
2391 +#define GPIO_MODE_6348_G3_UTOPIA 0x00008000
2392 +#define GPIO_MODE_6348_G3_EXT_MII 0x00007000
2393 +#define GPIO_MODE_6348_G2_DIAG 0x00000900
2394 +#define GPIO_MODE_6348_G2_PCI 0x00000500
2395 +#define GPIO_MODE_6348_G1_DIAG 0x00000090
2396 +#define GPIO_MODE_6348_G1_UTOPIA 0x00000080
2397 +#define GPIO_MODE_6348_G1_SPI_UART 0x00000060
2398 +#define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
2399 +#define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
2400 +#define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
2401 +#define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
2402 +#define GPIO_MODE_6348_G0_DIAG 0x00000009
2403 +#define GPIO_MODE_6348_G0_EXT_MII 0x00000007
2404 +
2405 +#define GPIO_MODE_6358_EXTRACS (1 << 5)
2406 +#define GPIO_MODE_6358_UART1 (1 << 6)
2407 +#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
2408 +#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
2409 +#define GPIO_MODE_6358_UTOPIA (1 << 12)
2410 +
2411 +
2412 +/*************************************************************************
2413 + * _REG relative to RSET_ENET
2414 + *************************************************************************/
2415 +
2416 +/* Receiver Configuration register */
2417 +#define ENET_RXCFG_REG 0x0
2418 +#define ENET_RXCFG_ALLMCAST_SHIFT 1
2419 +#define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT)
2420 +#define ENET_RXCFG_PROMISC_SHIFT 3
2421 +#define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT)
2422 +#define ENET_RXCFG_LOOPBACK_SHIFT 4
2423 +#define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT)
2424 +#define ENET_RXCFG_ENFLOW_SHIFT 5
2425 +#define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT)
2426 +
2427 +/* Receive Maximum Length register */
2428 +#define ENET_RXMAXLEN_REG 0x4
2429 +#define ENET_RXMAXLEN_SHIFT 0
2430 +#define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
2431 +
2432 +/* Transmit Maximum Length register */
2433 +#define ENET_TXMAXLEN_REG 0x8
2434 +#define ENET_TXMAXLEN_SHIFT 0
2435 +#define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
2436 +
2437 +/* MII Status/Control register */
2438 +#define ENET_MIISC_REG 0x10
2439 +#define ENET_MIISC_MDCFREQDIV_SHIFT 0
2440 +#define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
2441 +#define ENET_MIISC_PREAMBLEEN_SHIFT 7
2442 +#define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
2443 +
2444 +/* MII Data register */
2445 +#define ENET_MIIDATA_REG 0x14
2446 +#define ENET_MIIDATA_DATA_SHIFT 0
2447 +#define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
2448 +#define ENET_MIIDATA_TA_SHIFT 16
2449 +#define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
2450 +#define ENET_MIIDATA_REG_SHIFT 18
2451 +#define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
2452 +#define ENET_MIIDATA_PHYID_SHIFT 23
2453 +#define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
2454 +#define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
2455 +#define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
2456 +
2457 +/* Ethernet Interrupt Mask register */
2458 +#define ENET_IRMASK_REG 0x18
2459 +
2460 +/* Ethernet Interrupt register */
2461 +#define ENET_IR_REG 0x1c
2462 +#define ENET_IR_MII (1 << 0)
2463 +#define ENET_IR_MIB (1 << 1)
2464 +#define ENET_IR_FLOWC (1 << 2)
2465 +
2466 +/* Ethernet Control register */
2467 +#define ENET_CTL_REG 0x2c
2468 +#define ENET_CTL_ENABLE_SHIFT 0
2469 +#define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT)
2470 +#define ENET_CTL_DISABLE_SHIFT 1
2471 +#define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT)
2472 +#define ENET_CTL_SRESET_SHIFT 2
2473 +#define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT)
2474 +#define ENET_CTL_EPHYSEL_SHIFT 3
2475 +#define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT)
2476 +
2477 +/* Transmit Control register */
2478 +#define ENET_TXCTL_REG 0x30
2479 +#define ENET_TXCTL_FD_SHIFT 0
2480 +#define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT)
2481 +
2482 +/* Transmit Watermask register */
2483 +#define ENET_TXWMARK_REG 0x34
2484 +#define ENET_TXWMARK_WM_SHIFT 0
2485 +#define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
2486 +
2487 +/* MIB Control register */
2488 +#define ENET_MIBCTL_REG 0x38
2489 +#define ENET_MIBCTL_RDCLEAR_SHIFT 0
2490 +#define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
2491 +
2492 +/* Perfect Match Data Low register */
2493 +#define ENET_PML_REG(x) (0x58 + (x) * 8)
2494 +#define ENET_PMH_REG(x) (0x5c + (x) * 8)
2495 +#define ENET_PMH_DATAVALID_SHIFT 16
2496 +#define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT)
2497 +
2498 +/* MIB register */
2499 +#define ENET_MIB_REG(x) (0x200 + (x) * 4)
2500 +#define ENET_MIB_REG_COUNT 55
2501 +
2502 +
2503 +/*************************************************************************
2504 + * _REG relative to RSET_ENETDMA
2505 + *************************************************************************/
2506 +
2507 +/* Controller Configuration Register */
2508 +#define ENETDMA_CFG_REG (0x0)
2509 +#define ENETDMA_CFG_EN_SHIFT 0
2510 +#define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT)
2511 +#define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
2512 +
2513 +/* Flow Control Descriptor Low Threshold register */
2514 +#define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
2515 +
2516 +/* Flow Control Descriptor High Threshold register */
2517 +#define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
2518 +
2519 +/* Flow Control Descriptor Buffer Alloca Threshold register */
2520 +#define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
2521 +#define ENETDMA_BUFALLOC_FORCE_SHIFT 31
2522 +#define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
2523 +
2524 +/* Channel Configuration register */
2525 +#define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
2526 +#define ENETDMA_CHANCFG_EN_SHIFT 0
2527 +#define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
2528 +#define ENETDMA_CHANCFG_PKTHALT_SHIFT 1
2529 +#define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
2530 +
2531 +/* Interrupt Control/Status register */
2532 +#define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
2533 +#define ENETDMA_IR_BUFDONE_MASK (1 << 0)
2534 +#define ENETDMA_IR_PKTDONE_MASK (1 << 1)
2535 +#define ENETDMA_IR_NOTOWNER_MASK (1 << 2)
2536 +
2537 +/* Interrupt Mask register */
2538 +#define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
2539 +
2540 +/* Maximum Burst Length */
2541 +#define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
2542 +
2543 +/* Ring Start Address register */
2544 +#define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
2545 +
2546 +/* State Ram Word 2 */
2547 +#define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
2548 +
2549 +/* State Ram Word 3 */
2550 +#define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
2551 +
2552 +/* State Ram Word 4 */
2553 +#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
2554 +
2555 +
2556 +/*************************************************************************
2557 + * _REG relative to RSET_OHCI_PRIV
2558 + *************************************************************************/
2559 +
2560 +#define OHCI_PRIV_REG 0x0
2561 +#define OHCI_PRIV_PORT1_HOST_SHIFT 0
2562 +#define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
2563 +#define OHCI_PRIV_REG_SWAP_SHIFT 3
2564 +#define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT)
2565 +
2566 +
2567 +/*************************************************************************
2568 + * _REG relative to RSET_USBH_PRIV
2569 + *************************************************************************/
2570 +
2571 +#define USBH_PRIV_SWAP_REG 0x0
2572 +#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
2573 +#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
2574 +#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
2575 +#define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
2576 +#define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
2577 +#define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
2578 +#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
2579 +#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
2580 +
2581 +#define USBH_PRIV_TEST_REG 0x24
2582 +
2583 +
2584 +/*************************************************************************
2585 + * _REG relative to RSET_MPI
2586 + *************************************************************************/
2587 +
2588 +/* well known (hard wired) chip select */
2589 +#define MPI_CS_PCMCIA_COMMON 4
2590 +#define MPI_CS_PCMCIA_ATTR 5
2591 +#define MPI_CS_PCMCIA_IO 6
2592 +
2593 +/* Chip select base register */
2594 +#define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
2595 +#define MPI_CSBASE_BASE_SHIFT 13
2596 +#define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
2597 +#define MPI_CSBASE_SIZE_SHIFT 0
2598 +#define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
2599 +
2600 +#define MPI_CSBASE_SIZE_8K 0
2601 +#define MPI_CSBASE_SIZE_16K 1
2602 +#define MPI_CSBASE_SIZE_32K 2
2603 +#define MPI_CSBASE_SIZE_64K 3
2604 +#define MPI_CSBASE_SIZE_128K 4
2605 +#define MPI_CSBASE_SIZE_256K 5
2606 +#define MPI_CSBASE_SIZE_512K 6
2607 +#define MPI_CSBASE_SIZE_1M 7
2608 +#define MPI_CSBASE_SIZE_2M 8
2609 +#define MPI_CSBASE_SIZE_4M 9
2610 +#define MPI_CSBASE_SIZE_8M 10
2611 +#define MPI_CSBASE_SIZE_16M 11
2612 +#define MPI_CSBASE_SIZE_32M 12
2613 +#define MPI_CSBASE_SIZE_64M 13
2614 +#define MPI_CSBASE_SIZE_128M 14
2615 +#define MPI_CSBASE_SIZE_256M 15
2616 +
2617 +/* Chip select control register */
2618 +#define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
2619 +#define MPI_CSCTL_ENABLE_MASK (1 << 0)
2620 +#define MPI_CSCTL_WAIT_SHIFT 1
2621 +#define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
2622 +#define MPI_CSCTL_DATA16_MASK (1 << 4)
2623 +#define MPI_CSCTL_SYNCMODE_MASK (1 << 7)
2624 +#define MPI_CSCTL_TSIZE_MASK (1 << 8)
2625 +#define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10)
2626 +#define MPI_CSCTL_SETUP_SHIFT 16
2627 +#define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
2628 +#define MPI_CSCTL_HOLD_SHIFT 20
2629 +#define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
2630 +
2631 +/* PCI registers */
2632 +#define MPI_SP0_RANGE_REG 0x100
2633 +#define MPI_SP0_REMAP_REG 0x104
2634 +#define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
2635 +#define MPI_SP1_RANGE_REG 0x10C
2636 +#define MPI_SP1_REMAP_REG 0x110
2637 +#define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
2638 +
2639 +#define MPI_L2PCFG_REG 0x11C
2640 +#define MPI_L2PCFG_CFG_TYPE_SHIFT 0
2641 +#define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
2642 +#define MPI_L2PCFG_REG_SHIFT 2
2643 +#define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
2644 +#define MPI_L2PCFG_FUNC_SHIFT 8
2645 +#define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
2646 +#define MPI_L2PCFG_DEVNUM_SHIFT 11
2647 +#define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
2648 +#define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
2649 +#define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
2650 +
2651 +#define MPI_L2PMEMRANGE1_REG 0x120
2652 +#define MPI_L2PMEMBASE1_REG 0x124
2653 +#define MPI_L2PMEMREMAP1_REG 0x128
2654 +#define MPI_L2PMEMRANGE2_REG 0x12C
2655 +#define MPI_L2PMEMBASE2_REG 0x130
2656 +#define MPI_L2PMEMREMAP2_REG 0x134
2657 +#define MPI_L2PIORANGE_REG 0x138
2658 +#define MPI_L2PIOBASE_REG 0x13C
2659 +#define MPI_L2PIOREMAP_REG 0x140
2660 +#define MPI_L2P_BASE_MASK (0xffff8000)
2661 +#define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
2662 +#define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
2663 +
2664 +#define MPI_PCIMODESEL_REG 0x144
2665 +#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
2666 +#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
2667 +#define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
2668 +#define MPI_PCIMODESEL_PREFETCH_SHIFT 4
2669 +#define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
2670 +
2671 +#define MPI_LOCBUSCTL_REG 0x14C
2672 +#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
2673 +#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
2674 +
2675 +#define MPI_LOCINT_REG 0x150
2676 +#define MPI_LOCINT_MASK(x) (1 << (x + 16))
2677 +#define MPI_LOCINT_STAT(x) (1 << (x))
2678 +#define MPI_LOCINT_DIR_FAILED 6
2679 +#define MPI_LOCINT_EXT_PCI_INT 7
2680 +#define MPI_LOCINT_SERR 8
2681 +#define MPI_LOCINT_CSERR 9
2682 +
2683 +#define MPI_PCICFGCTL_REG 0x178
2684 +#define MPI_PCICFGCTL_CFGADDR_SHIFT 2
2685 +#define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
2686 +#define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
2687 +
2688 +#define MPI_PCICFGDATA_REG 0x17C
2689 +
2690 +/* PCI host bridge custom register */
2691 +#define BCMPCI_REG_TIMERS 0x40
2692 +#define REG_TIMER_TRDY_SHIFT 0
2693 +#define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
2694 +#define REG_TIMER_RETRY_SHIFT 8
2695 +#define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
2696 +
2697 +
2698 +/*************************************************************************
2699 + * _REG relative to RSET_PCMCIA
2700 + *************************************************************************/
2701 +
2702 +#define PCMCIA_C1_REG 0x0
2703 +#define PCMCIA_C1_CD1_MASK (1 << 0)
2704 +#define PCMCIA_C1_CD2_MASK (1 << 1)
2705 +#define PCMCIA_C1_VS1_MASK (1 << 2)
2706 +#define PCMCIA_C1_VS2_MASK (1 << 3)
2707 +#define PCMCIA_C1_VS1OE_MASK (1 << 6)
2708 +#define PCMCIA_C1_VS2OE_MASK (1 << 7)
2709 +#define PCMCIA_C1_CBIDSEL_SHIFT (8)
2710 +#define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
2711 +#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
2712 +#define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
2713 +#define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
2714 +#define PCMCIA_C1_RESET_MASK (1 << 18)
2715 +
2716 +#define PCMCIA_C2_REG 0x8
2717 +#define PCMCIA_C2_DATA16_MASK (1 << 0)
2718 +#define PCMCIA_C2_BYTESWAP_MASK (1 << 1)
2719 +#define PCMCIA_C2_RWCOUNT_SHIFT 2
2720 +#define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
2721 +#define PCMCIA_C2_INACTIVE_SHIFT 8
2722 +#define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
2723 +#define PCMCIA_C2_SETUP_SHIFT 16
2724 +#define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
2725 +#define PCMCIA_C2_HOLD_SHIFT 24
2726 +#define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
2727 +
2728 +
2729 +/*************************************************************************
2730 + * _REG relative to RSET_SDRAM
2731 + *************************************************************************/
2732 +
2733 +#define SDRAM_CFG_REG 0x0
2734 +#define SDRAM_CFG_ROW_SHIFT 4
2735 +#define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
2736 +#define SDRAM_CFG_COL_SHIFT 6
2737 +#define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
2738 +#define SDRAM_CFG_32B_SHIFT 10
2739 +#define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
2740 +#define SDRAM_CFG_BANK_SHIFT 13
2741 +#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
2742 +
2743 +#define SDRAM_PRIO_REG 0x2C
2744 +#define SDRAM_PRIO_MIPS_SHIFT 29
2745 +#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
2746 +#define SDRAM_PRIO_ADSL_SHIFT 30
2747 +#define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT)
2748 +#define SDRAM_PRIO_EN_SHIFT 31
2749 +#define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT)
2750 +
2751 +
2752 +/*************************************************************************
2753 + * _REG relative to RSET_MEMC
2754 + *************************************************************************/
2755 +
2756 +#define MEMC_CFG_REG 0x4
2757 +#define MEMC_CFG_32B_SHIFT 1
2758 +#define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
2759 +#define MEMC_CFG_COL_SHIFT 3
2760 +#define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
2761 +#define MEMC_CFG_ROW_SHIFT 6
2762 +#define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
2763 +
2764 +
2765 +/*************************************************************************
2766 + * _REG relative to RSET_DDR
2767 + *************************************************************************/
2768 +
2769 +#define DDR_DMIPSPLLCFG_REG 0x18
2770 +#define DMIPSPLLCFG_M1_SHIFT 0
2771 +#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
2772 +#define DMIPSPLLCFG_N1_SHIFT 23
2773 +#define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
2774 +#define DMIPSPLLCFG_N2_SHIFT 29
2775 +#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
2776 +
2777 +#endif /* BCM63XX_REGS_H_ */
2778 +
2779 diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_timer.h b/include/asm-mips/mach-bcm63xx/bcm63xx_timer.h
2780 new file mode 100644
2781 index 0000000..c0fce83
2782 --- /dev/null
2783 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_timer.h
2784 @@ -0,0 +1,11 @@
2785 +#ifndef BCM63XX_TIMER_H_
2786 +#define BCM63XX_TIMER_H_
2787 +
2788 +int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data);
2789 +void bcm63xx_timer_unregister(int id);
2790 +int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us);
2791 +int bcm63xx_timer_enable(int id);
2792 +int bcm63xx_timer_disable(int id);
2793 +unsigned int bcm63xx_timer_countdown(unsigned int countdown_us);
2794 +
2795 +#endif /* !BCM63XX_TIMER_H_ */
2796 diff --git a/include/asm-mips/mach-bcm63xx/cpu-feature-overrides.h b/include/asm-mips/mach-bcm63xx/cpu-feature-overrides.h
2797 new file mode 100644
2798 index 0000000..1a5c4b1
2799 --- /dev/null
2800 +++ b/include/asm-mips/mach-bcm63xx/cpu-feature-overrides.h
2801 @@ -0,0 +1,51 @@
2802 +#ifndef __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
2803 +#define __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
2804 +
2805 +#include <bcm63xx_cpu.h>
2806 +
2807 +#define cpu_has_tlb 1
2808 +#define cpu_has_4kex 1
2809 +#define cpu_has_4k_cache 1
2810 +#define cpu_has_fpu 0
2811 +#define cpu_has_32fpr 0
2812 +#define cpu_has_counter 1
2813 +#define cpu_has_watch 0
2814 +#define cpu_has_divec 1
2815 +#define cpu_has_vce 0
2816 +#define cpu_has_cache_cdex_p 0
2817 +#define cpu_has_cache_cdex_s 0
2818 +#define cpu_has_prefetch 1
2819 +#define cpu_has_mcheck 1
2820 +#define cpu_has_ejtag 1
2821 +#define cpu_has_llsc 1
2822 +#define cpu_has_mips16 0
2823 +#define cpu_has_mdmx 0
2824 +#define cpu_has_mips3d 0
2825 +#define cpu_has_smartmips 0
2826 +#define cpu_has_vtag_icache 0
2827 +
2828 +#if !defined(BCMCPU_RUNTIME_DETECT) && defined(CONFIG_BCMCPU_IS_6348)
2829 +#define cpu_has_dc_aliases 0
2830 +#endif
2831 +
2832 +#define cpu_has_ic_fills_f_dc 0
2833 +#define cpu_has_pindexed_dcache 0
2834 +
2835 +#define cpu_has_mips32r1 1
2836 +#define cpu_has_mips32r2 0
2837 +#define cpu_has_mips64r1 0
2838 +#define cpu_has_mips64r2 0
2839 +
2840 +#define cpu_has_dsp 0
2841 +#define cpu_has_mipsmt 0
2842 +#define cpu_has_userlocal 0
2843 +
2844 +#define cpu_has_nofpuex 0
2845 +#define cpu_has_64bits 0
2846 +#define cpu_has_64bit_zero_reg 0
2847 +
2848 +#define cpu_dcache_line_size() 16
2849 +#define cpu_icache_line_size() 16
2850 +#define cpu_scache_line_size() 0
2851 +
2852 +#endif /* __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H */
2853 diff --git a/include/asm-mips/mach-bcm63xx/gpio.h b/include/asm-mips/mach-bcm63xx/gpio.h
2854 new file mode 100644
2855 index 0000000..dd2c0f3
2856 --- /dev/null
2857 +++ b/include/asm-mips/mach-bcm63xx/gpio.h
2858 @@ -0,0 +1,52 @@
2859 +#ifndef __ASM_MIPS_MACH_BCM63XX_GPIO_H
2860 +#define __ASM_MIPS_MACH_BCM63XX_GPIO_H
2861 +
2862 +#include <bcm63xx_gpio.h>
2863 +
2864 +static inline int gpio_is_valid(int number)
2865 +{
2866 + return (number >= BCM63XX_GPIO_COUNT) ? 0 : 1;
2867 +}
2868 +
2869 +static inline int gpio_request(unsigned gpio, const char *label)
2870 +{
2871 + return 0;
2872 +}
2873 +
2874 +static inline void gpio_free(unsigned gpio)
2875 +{
2876 +}
2877 +
2878 +static inline int gpio_direction_input(unsigned gpio)
2879 +{
2880 + bcm63xx_gpio_set_direction(gpio, GPIO_DIR_IN);
2881 + return 0;
2882 +}
2883 +
2884 +static inline int gpio_direction_output(unsigned gpio, int value)
2885 +{
2886 + bcm63xx_gpio_set_direction(gpio, GPIO_DIR_OUT);
2887 + return 0;
2888 +}
2889 +
2890 +static inline int gpio_get_value(unsigned gpio)
2891 +{
2892 + return bcm63xx_gpio_get_datain(gpio);
2893 +}
2894 +
2895 +static inline void gpio_set_value(unsigned gpio, int value)
2896 +{
2897 + bcm63xx_gpio_set_dataout(gpio, value);
2898 +}
2899 +
2900 +static inline int gpio_to_irq(unsigned gpio)
2901 +{
2902 + return gpio;
2903 +}
2904 +
2905 +static inline int irq_to_gpio(unsigned irq)
2906 +{
2907 + return irq;
2908 +}
2909 +
2910 +#endif /* __ASM_MIPS_MACH_BCM63XX_GPIO_H */
2911 diff --git a/include/asm-mips/mach-bcm63xx/war.h b/include/asm-mips/mach-bcm63xx/war.h
2912 new file mode 100644
2913 index 0000000..8e3f3fd
2914 --- /dev/null
2915 +++ b/include/asm-mips/mach-bcm63xx/war.h
2916 @@ -0,0 +1,25 @@
2917 +/*
2918 + * This file is subject to the terms and conditions of the GNU General Public
2919 + * License. See the file "COPYING" in the main directory of this archive
2920 + * for more details.
2921 + *
2922 + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
2923 + */
2924 +#ifndef __ASM_MIPS_MACH_BCM63XX_WAR_H
2925 +#define __ASM_MIPS_MACH_BCM63XX_WAR_H
2926 +
2927 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
2928 +#define R4600_V1_HIT_CACHEOP_WAR 0
2929 +#define R4600_V2_HIT_CACHEOP_WAR 0
2930 +#define R5432_CP0_INTERRUPT_WAR 0
2931 +#define BCM1250_M3_WAR 0
2932 +#define SIBYTE_1956_WAR 0
2933 +#define MIPS4K_ICACHE_REFILL_WAR 0
2934 +#define MIPS_CACHE_SYNC_WAR 0
2935 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
2936 +#define RM9000_CDEX_SMP_WAR 0
2937 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
2938 +#define R10000_LLSC_WAR 0
2939 +#define MIPS34K_MISSED_ITLB_WAR 0
2940 +
2941 +#endif /* __ASM_MIPS_MACH_BCM63XX_WAR_H */
2942 --
2943 1.5.4.3
2944
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