target/linux/brcm63xx/patches-2.6.27/004_add_pci_support.patch

   1 From 2a7fa2dbbf68650644f807a50cc2d84ca30835c1 Mon Sep 17 00:00:00 2001
   2 From: Maxime Bizon <mbizon@freebox.fr>
   3 Date: Sun, 21 Sep 2008 04:47:13 +0200
   4 Subject: [PATCH] [MIPS] BCM63XX: Add PCI support.
   5
   6 Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
   7 ---
   8  arch/mips/bcm63xx/Kconfig                       |    2 +
   9  arch/mips/bcm63xx/setup.c                       |    2 +
  10  arch/mips/pci/Makefile                          |    2 +
  11  arch/mips/pci/fixup-bcm63xx.c                   |   21 +++
  12  arch/mips/pci/ops-bcm63xx.c                     |  179 +++++++++++++++++++++++
  13  arch/mips/pci/pci-bcm63xx.c                     |  178 ++++++++++++++++++++++
  14  arch/mips/pci/pci-bcm63xx.h                     |   27 ++++
  15  include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h |    6 +
  16  8 files changed, 417 insertions(+), 0 deletions(-)
  17  create mode 100644 arch/mips/pci/fixup-bcm63xx.c
  18  create mode 100644 arch/mips/pci/ops-bcm63xx.c
  19  create mode 100644 arch/mips/pci/pci-bcm63xx.c
  20  create mode 100644 arch/mips/pci/pci-bcm63xx.h
  21  create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h
  22
  23 diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
  24 index e6d2699..7ca370a 100644
  25 --- a/arch/mips/bcm63xx/Kconfig
  26 +++ b/arch/mips/bcm63xx/Kconfig
  27 @@ -3,7 +3,9 @@ menu "CPU support"
  28
  29  config BCM63XX_CPU_6348
  30         bool "support 6348 CPU"
  31 +       select HW_HAS_PCI
  32
  33  config BCM63XX_CPU_6358
  34         bool "support 6358 CPU"
  35 +       select HW_HAS_PCI
  36  endmenu
  37 diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
  38 index 55c51a9..4d8b127 100644
  39 --- a/arch/mips/bcm63xx/setup.c
  40 +++ b/arch/mips/bcm63xx/setup.c
  41 @@ -105,4 +105,6 @@ void __init plat_mem_setup(void)
  42         pm_power_off = bcm63xx_machine_halt;
  43
  44         set_io_port_base(0);
  45 +       ioport_resource.start = 0;
  46 +       ioport_resource.end = ~0;
  47  }
  48 diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
  49 index c8c32f4..0b688a8 100644
  50 --- a/arch/mips/pci/Makefile
  51 +++ b/arch/mips/pci/Makefile
  52 @@ -16,6 +16,8 @@ obj-$(CONFIG_PCI_VR41XX)      += ops-vr41xx.o pci-vr41xx.o
  53  obj-$(CONFIG_MARKEINS)         += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
  54  obj-$(CONFIG_PCI_TX4927)       += ops-tx4927.o
  55  obj-$(CONFIG_BCM47XX)          += pci-bcm47xx.o
  56 +obj-$(CONFIG_BCM63XX)          += pci-bcm63xx.o fixup-bcm63xx.o \
  57 +                                       ops-bcm63xx.o
  58
  59  #
  60  # These are still pretty much in the old state, watch, go blind.
  61 diff --git a/arch/mips/pci/fixup-bcm63xx.c b/arch/mips/pci/fixup-bcm63xx.c
  62 new file mode 100644
  63 index 0000000..3408630
  64 --- /dev/null
  65 +++ b/arch/mips/pci/fixup-bcm63xx.c
  66 @@ -0,0 +1,21 @@
  67 +/*
  68 + * This file is subject to the terms and conditions of the GNU General Public
  69 + * License.  See the file "COPYING" in the main directory of this archive
  70 + * for more details.
  71 + *
  72 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  73 + */
  74 +
  75 +#include <linux/types.h>
  76 +#include <linux/pci.h>
  77 +#include <bcm63xx_cpu.h>
  78 +
  79 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  80 +{
  81 +       return bcm63xx_get_irq_number(IRQ_PCI);
  82 +}
  83 +
  84 +int pcibios_plat_dev_init(struct pci_dev *dev)
  85 +{
  86 +       return 0;
  87 +}
  88 diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
  89 new file mode 100644
  90 index 0000000..f8dce9d
  91 --- /dev/null
  92 +++ b/arch/mips/pci/ops-bcm63xx.c
  93 @@ -0,0 +1,179 @@
  94 +/*
  95 + * This file is subject to the terms and conditions of the GNU General Public
  96 + * License.  See the file "COPYING" in the main directory of this archive
  97 + * for more details.
  98 + *
  99 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
 100 + */
 101 +
 102 +#include <linux/types.h>
 103 +#include <linux/pci.h>
 104 +#include <linux/kernel.h>
 105 +#include <linux/init.h>
 106 +#include <linux/delay.h>
 107 +#include <linux/io.h>
 108 +
 109 +#include "pci-bcm63xx.h"
 110 +
 111 +/*
 112 + * swizzle 32bits data to return only the needed part
 113 + */
 114 +static int postprocess_read(u32 data, int where, unsigned int size)
 115 +{
 116 +       u32 ret;
 117 +
 118 +       ret = 0;
 119 +       switch (size) {
 120 +       case 1:
 121 +               ret = (data >> ((where & 3) << 3)) & 0xff;
 122 +               break;
 123 +       case 2:
 124 +               ret = (data >> ((where & 3) << 3)) & 0xffff;
 125 +               break;
 126 +       case 4:
 127 +               ret = data;
 128 +               break;
 129 +       }
 130 +       return ret;
 131 +}
 132 +
 133 +static int preprocess_write(u32 orig_data, u32 val, int where,
 134 +                           unsigned int size)
 135 +{
 136 +       u32 ret;
 137 +
 138 +       ret = 0;
 139 +       switch (size) {
 140 +       case 1:
 141 +               ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
 142 +                       (val << ((where & 3) << 3));
 143 +               break;
 144 +       case 2:
 145 +               ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
 146 +                       (val << ((where & 3) << 3));
 147 +               break;
 148 +       case 4:
 149 +               ret = val;
 150 +               break;
 151 +       }
 152 +       return ret;
 153 +}
 154 +
 155 +/*
 156 + * setup hardware for a configuration cycle with given parameters
 157 + */
 158 +static int bcm63xx_setup_cfg_access(int type, unsigned int busn,
 159 +                                   unsigned int devfn, int where)
 160 +{
 161 +       unsigned int slot, func, reg;
 162 +       u32 val;
 163 +
 164 +       slot = PCI_SLOT(devfn);
 165 +       func = PCI_FUNC(devfn);
 166 +       reg = where >> 2;
 167 +
 168 +       /* sanity check */
 169 +       if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
 170 +               return 1;
 171 +
 172 +       if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
 173 +               return 1;
 174 +
 175 +       if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
 176 +               return 1;
 177 +
 178 +       /* ok, setup config access */
 179 +       val = (reg << MPI_L2PCFG_REG_SHIFT);
 180 +       val |= (func << MPI_L2PCFG_FUNC_SHIFT);
 181 +       val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
 182 +       val |= MPI_L2PCFG_CFG_USEREG_MASK;
 183 +       val |= MPI_L2PCFG_CFG_SEL_MASK;
 184 +       /* type 0 cycle for local bus, type 1 cycle for anything else */
 185 +       if (type != 0) {
 186 +               /* FIXME: how to specify bus ??? */
 187 +               val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
 188 +       }
 189 +       bcm_mpi_writel(val, MPI_L2PCFG_REG);
 190 +
 191 +       return 0;
 192 +}
 193 +
 194 +static int bcm63xx_do_cfg_read(int type, unsigned int busn,
 195 +                               unsigned int devfn, int where, int size,
 196 +                               u32 *val)
 197 +{
 198 +       u32 data;
 199 +
 200 +       /* two phase cycle, first we write address, then read data at
 201 +        * another location, caller already has a spinlock so no need
 202 +        * to add one here  */
 203 +       if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
 204 +               return PCIBIOS_DEVICE_NOT_FOUND;
 205 +       iob();
 206 +       data = le32_to_cpu(__raw_readl(pci_iospace_start));
 207 +       /* restore IO space normal behaviour */
 208 +       bcm_mpi_writel(0, MPI_L2PCFG_REG);
 209 +
 210 +       *val = postprocess_read(data, where, size);
 211 +
 212 +       return PCIBIOS_SUCCESSFUL;
 213 +}
 214 +
 215 +static int bcm63xx_do_cfg_write(int type, unsigned int busn,
 216 +                                unsigned int devfn, int where, int size,
 217 +                                u32 val)
 218 +{
 219 +       u32 data;
 220 +
 221 +       /* two phase cycle, first we write address, then write data to
 222 +        * another location, caller already has a spinlock so no need
 223 +        * to add one here  */
 224 +       if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
 225 +               return PCIBIOS_DEVICE_NOT_FOUND;
 226 +       iob();
 227 +
 228 +       data = le32_to_cpu(__raw_readl(pci_iospace_start));
 229 +       data = preprocess_write(data, val, where, size);
 230 +
 231 +       __raw_writel(cpu_to_le32(data), pci_iospace_start);
 232 +       wmb();
 233 +       /* no way to know the access is done, we have to wait */
 234 +       udelay(500);
 235 +       /* restore IO space normal behaviour */
 236 +       bcm_mpi_writel(0, MPI_L2PCFG_REG);
 237 +
 238 +       return PCIBIOS_SUCCESSFUL;
 239 +}
 240 +
 241 +static int bcm63xx_pci_read(struct pci_bus *bus, unsigned int devfn,
 242 +                            int where, int size, u32 *val)
 243 +{
 244 +       int type;
 245 +
 246 +       type = bus->parent ? 1 : 0;
 247 +
 248 +       if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
 249 +               return PCIBIOS_DEVICE_NOT_FOUND;
 250 +
 251 +       return bcm63xx_do_cfg_read(type, bus->number, devfn,
 252 +                                   where, size, val);
 253 +}
 254 +
 255 +static int bcm63xx_pci_write(struct pci_bus *bus, unsigned int devfn,
 256 +                             int where, int size, u32 val)
 257 +{
 258 +       int type;
 259 +
 260 +       type = bus->parent ? 1 : 0;
 261 +
 262 +       if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
 263 +               return PCIBIOS_DEVICE_NOT_FOUND;
 264 +
 265 +       return bcm63xx_do_cfg_write(type, bus->number, devfn,
 266 +                                    where, size, val);
 267 +}
 268 +
 269 +struct pci_ops bcm63xx_pci_ops = {
 270 +       .read   = bcm63xx_pci_read,
 271 +       .write  = bcm63xx_pci_write
 272 +};
 273 diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
 274 new file mode 100644
 275 index 0000000..52bac8e
 276 --- /dev/null
 277 +++ b/arch/mips/pci/pci-bcm63xx.c
 278 @@ -0,0 +1,178 @@
 279 +/*
 280 + * This file is subject to the terms and conditions of the GNU General Public
 281 + * License.  See the file "COPYING" in the main directory of this archive
 282 + * for more details.
 283 + *
 284 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
 285 + */
 286 +
 287 +#include <linux/types.h>
 288 +#include <linux/pci.h>
 289 +#include <linux/kernel.h>
 290 +#include <linux/init.h>
 291 +#include <asm/bootinfo.h>
 292 +
 293 +#include "pci-bcm63xx.h"
 294 +
 295 +/* allow PCI to be disabled at runtime depending on board nvram
 296 + * configuration */
 297 +int bcm63xx_pci_enabled = 0;
 298 +
 299 +static struct resource bcm_pci_mem_resource = {
 300 +       .name   = "bcm63xx PCI memory space",
 301 +       .start  = BCM_PCI_MEM_BASE_PA,
 302 +       .end    = BCM_PCI_MEM_END_PA,
 303 +       .flags  = IORESOURCE_MEM
 304 +};
 305 +
 306 +static struct resource bcm_pci_io_resource = {
 307 +       .name   = "bcm63xx PCI IO space",
 308 +       .start  = BCM_PCI_IO_BASE_PA,
 309 +       .end    = BCM_PCI_IO_END_PA,
 310 +       .flags  = IORESOURCE_IO
 311 +};
 312 +
 313 +struct pci_controller bcm63xx_controller = {
 314 +       .pci_ops        = &bcm63xx_pci_ops,
 315 +       .io_resource    = &bcm_pci_io_resource,
 316 +       .mem_resource   = &bcm_pci_mem_resource,
 317 +};
 318 +
 319 +static u32 bcm63xx_int_cfg_readl(u32 reg)
 320 +{
 321 +       u32 tmp;
 322 +
 323 +       tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
 324 +       tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
 325 +       bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
 326 +       iob();
 327 +       return bcm_mpi_readl(MPI_PCICFGDATA_REG);
 328 +}
 329 +
 330 +static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
 331 +{
 332 +       u32 tmp;
 333 +
 334 +       tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
 335 +       tmp |=  MPI_PCICFGCTL_WRITEEN_MASK;
 336 +       bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
 337 +       bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
 338 +}
 339 +
 340 +void __iomem *pci_iospace_start;
 341 +
 342 +static int __init bcm63xx_pci_init(void)
 343 +{
 344 +       unsigned int mem_size;
 345 +       u32 val;
 346 +
 347 +       if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
 348 +               return -ENODEV;
 349 +
 350 +       if (!bcm63xx_pci_enabled)
 351 +               return -ENODEV;
 352 +
 353 +       /*
 354 +        * configuration  access are  done through  IO space,  remap 4
 355 +        * first bytes to access it from CPU.
 356 +        *
 357 +        * this means that  no io access from CPU  should happen while
 358 +        * we do a configuration cycle,  but there's no way we can add
 359 +        * a spinlock for each io access, so this is currently kind of
 360 +        * broken on SMP.
 361 +        */
 362 +       pci_iospace_start = ioremap_nocache(BCM_PCI_IO_BASE_PA, 4);
 363 +       if (!pci_iospace_start)
 364 +               return -ENOMEM;
 365 +
 366 +       /* setup local bus to PCI access (PCI memory) */
 367 +       val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK;
 368 +       bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG);
 369 +       bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG);
 370 +       bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG);
 371 +
 372 +       /* set Cardbus IDSEL (type 0 cfg access on primary bus for
 373 +        * this IDSEL will be done on Cardbus instead) */
 374 +       val = bcm_pcmcia_readl(PCMCIA_C1_REG);
 375 +       val &= ~PCMCIA_C1_CBIDSEL_MASK;
 376 +       val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
 377 +       bcm_pcmcia_writel(val, PCMCIA_C1_REG);
 378 +
 379 +       /* disable second access windows */
 380 +       bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
 381 +
 382 +       /* setup local bus  to PCI access (IO memory),  we have only 1
 383 +        * IO window  for both PCI  and cardbus, but it  cannot handle
 384 +        * both  at the  same time,  assume standard  PCI for  now, if
 385 +        * cardbus card has  IO zone, PCI fixup will  change window to
 386 +        * cardbus */
 387 +       val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
 388 +       bcm_mpi_writel(val, MPI_L2PIOBASE_REG);
 389 +       bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG);
 390 +       bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG);
 391 +
 392 +       /* enable PCI related GPIO pins */
 393 +       bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG);
 394 +
 395 +       /* setup PCI to local bus access, used by PCI device to target
 396 +        * local RAM while bus mastering */
 397 +       bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
 398 +       if (BCMCPU_IS_6358())
 399 +               val = MPI_SP0_REMAP_ENABLE_MASK;
 400 +       else
 401 +               val = 0;
 402 +       bcm_mpi_writel(val, MPI_SP0_REMAP_REG);
 403 +
 404 +       bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4);
 405 +       bcm_mpi_writel(0, MPI_SP1_REMAP_REG);
 406 +
 407 +       mem_size = bcm63xx_get_memory_size();
 408 +
 409 +       /* 6348 before rev b0 exposes only 16 MB of RAM memory through
 410 +        * PCI, throw a warning if we have more memory */
 411 +       if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) {
 412 +               if (mem_size > (16 * 1024 * 1024))
 413 +                       printk(KERN_WARNING "bcm63xx: this CPU "
 414 +                              "revision cannot handle more than 16MB "
 415 +                              "of RAM for PCI bus mastering\n");
 416 +       } else {
 417 +               /* setup sp0 range to local RAM size */
 418 +               bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG);
 419 +               bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
 420 +       }
 421 +
 422 +       /* change  host bridge  retry  counter to  infinite number  of
 423 +        * retry,  needed for  some broadcom  wifi cards  with Silicon
 424 +        * Backplane bus where access to srom seems very slow  */
 425 +       val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
 426 +       val &= ~REG_TIMER_RETRY_MASK;
 427 +       bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS);
 428 +
 429 +       /* enable memory decoder and bus mastering */
 430 +       val = bcm63xx_int_cfg_readl(PCI_COMMAND);
 431 +       val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 432 +       bcm63xx_int_cfg_writel(val, PCI_COMMAND);
 433 +
 434 +       /* enable read prefetching & disable byte swapping for bus
 435 +        * mastering transfers */
 436 +       val = bcm_mpi_readl(MPI_PCIMODESEL_REG);
 437 +       val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
 438 +       val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
 439 +       val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
 440 +       val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
 441 +       bcm_mpi_writel(val, MPI_PCIMODESEL_REG);
 442 +
 443 +       /* enable pci interrupt */
 444 +       val = bcm_mpi_readl(MPI_LOCINT_REG);
 445 +       val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
 446 +       bcm_mpi_writel(val, MPI_LOCINT_REG);
 447 +
 448 +       register_pci_controller(&bcm63xx_controller);
 449 +
 450 +       /* mark memory space used for IO mapping as reserved */
 451 +       request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
 452 +                          "bcm63xx PCI IO space");
 453 +       return 0;
 454 +}
 455 +
 456 +arch_initcall(bcm63xx_pci_init);
 457 diff --git a/arch/mips/pci/pci-bcm63xx.h b/arch/mips/pci/pci-bcm63xx.h
 458 new file mode 100644
 459 index 0000000..a6e594e
 460 --- /dev/null
 461 +++ b/arch/mips/pci/pci-bcm63xx.h
 462 @@ -0,0 +1,27 @@
 463 +#ifndef PCI_BCM63XX_H_
 464 +#define PCI_BCM63XX_H_
 465 +
 466 +#include <bcm63xx_cpu.h>
 467 +#include <bcm63xx_io.h>
 468 +#include <bcm63xx_regs.h>
 469 +#include <bcm63xx_dev_pci.h>
 470 +
 471 +/*
 472 + * Cardbus shares  the PCI bus, but has  no IDSEL, so a  special id is
 473 + * reserved for it.  If you have a standard PCI device at this id, you
 474 + * need to change the following definition.
 475 + */
 476 +#define CARDBUS_PCI_IDSEL      0x8
 477 +
 478 +/*
 479 + * defined in ops-bcm63xx.c
 480 + */
 481 +extern struct pci_ops bcm63xx_pci_ops;
 482 +extern struct pci_ops bcm63xx_cb_ops;
 483 +
 484 +/*
 485 + * defined in pci-bcm63xx.c
 486 + */
 487 +extern void __iomem *pci_iospace_start;
 488 +
 489 +#endif /* ! PCI_BCM63XX_H_ */
 490 diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h
 491 new file mode 100644
 492 index 0000000..c549344
 493 --- /dev/null
 494 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h
 495 @@ -0,0 +1,6 @@
 496 +#ifndef BCM63XX_DEV_PCI_H_
 497 +#define BCM63XX_DEV_PCI_H_
 498 +
 499 +extern int bcm63xx_pci_enabled;
 500 +
 501 +#endif /* BCM63XX_DEV_PCI_H_ */
 502 --
 503 1.5.4.3
 504