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ab12a6f2b705a1571dac1195171bdf9ad11a6d92
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / patches-2.6.35 / 240-spi.patch
1 --- a/arch/mips/bcm63xx/cpu.c
2 +++ b/arch/mips/bcm63xx/cpu.c
3 @@ -56,6 +56,7 @@ static const unsigned long bcm96338_regs
4
5 static const int bcm96338_irqs[] = {
6 [IRQ_TIMER] = BCM_6338_TIMER_IRQ,
7 + [IRQ_SPI] = BCM_6338_SPI_IRQ,
8 [IRQ_UART0] = BCM_6338_UART0_IRQ,
9 [IRQ_DSL] = BCM_6338_DSL_IRQ,
10 [IRQ_ENET0] = BCM_6338_ENET0_IRQ,
11 @@ -130,6 +131,7 @@ static const unsigned long bcm96348_regs
12
13 static const int bcm96348_irqs[] = {
14 [IRQ_TIMER] = BCM_6348_TIMER_IRQ,
15 + [IRQ_SPI] = BCM_6348_SPI_IRQ,
16 [IRQ_UART0] = BCM_6348_UART0_IRQ,
17 [IRQ_DSL] = BCM_6348_DSL_IRQ,
18 [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
19 @@ -173,6 +175,7 @@ static const unsigned long bcm96358_regs
20
21 static const int bcm96358_irqs[] = {
22 [IRQ_TIMER] = BCM_6358_TIMER_IRQ,
23 + [IRQ_SPI] = BCM_6358_SPI_IRQ,
24 [IRQ_UART0] = BCM_6358_UART0_IRQ,
25 [IRQ_UART1] = BCM_6358_UART1_IRQ,
26 [IRQ_DSL] = BCM_6358_DSL_IRQ,
27 --- /dev/null
28 +++ b/arch/mips/bcm63xx/dev-spi.c
29 @@ -0,0 +1,127 @@
30 +/*
31 + * This file is subject to the terms and conditions of the GNU General Public
32 + * License. See the file "COPYING" in the main directory of this archive
33 + * for more details.
34 + *
35 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
36 + */
37 +
38 +#include <linux/init.h>
39 +#include <linux/kernel.h>
40 +#include <linux/platform_device.h>
41 +
42 +#include <bcm63xx_cpu.h>
43 +#include <bcm63xx_dev_spi.h>
44 +#include <bcm63xx_regs.h>
45 +
46 +#ifdef BCMCPU_RUNTIME_DETECT
47 +/*
48 + * register offsets
49 + */
50 +static const unsigned long bcm96338_regs_spi[] = {
51 + [SPI_CMD] = SPI_BCM_6338_SPI_CMD,
52 + [SPI_INT_STATUS] = SPI_BCM_6338_SPI_INT_STATUS,
53 + [SPI_INT_MASK_ST] = SPI_BCM_6338_SPI_MASK_INT_ST,
54 + [SPI_INT_MASK] = SPI_BCM_6338_SPI_INT_MASK,
55 + [SPI_ST] = SPI_BCM_6338_SPI_ST,
56 + [SPI_CLK_CFG] = SPI_BCM_6338_SPI_CLK_CFG,
57 + [SPI_FILL_BYTE] = SPI_BCM_6338_SPI_FILL_BYTE,
58 + [SPI_MSG_TAIL] = SPI_BCM_6338_SPI_MSG_TAIL,
59 + [SPI_RX_TAIL] = SPI_BCM_6338_SPI_RX_TAIL,
60 + [SPI_MSG_CTL] = SPI_BCM_6338_SPI_MSG_CTL,
61 + [SPI_MSG_DATA] = SPI_BCM_6338_SPI_MSG_DATA,
62 + [SPI_RX_DATA] = SPI_BCM_6338_SPI_RX_DATA,
63 +};
64 +
65 +static const unsigned long bcm96348_regs_spi[] = {
66 + [SPI_CMD] = SPI_BCM_6348_SPI_CMD,
67 + [SPI_INT_STATUS] = SPI_BCM_6348_SPI_INT_STATUS,
68 + [SPI_INT_MASK_ST] = SPI_BCM_6348_SPI_MASK_INT_ST,
69 + [SPI_INT_MASK] = SPI_BCM_6348_SPI_INT_MASK,
70 + [SPI_ST] = SPI_BCM_6348_SPI_ST,
71 + [SPI_CLK_CFG] = SPI_BCM_6348_SPI_CLK_CFG,
72 + [SPI_FILL_BYTE] = SPI_BCM_6348_SPI_FILL_BYTE,
73 + [SPI_MSG_TAIL] = SPI_BCM_6348_SPI_MSG_TAIL,
74 + [SPI_RX_TAIL] = SPI_BCM_6348_SPI_RX_TAIL,
75 + [SPI_MSG_CTL] = SPI_BCM_6348_SPI_MSG_CTL,
76 + [SPI_MSG_DATA] = SPI_BCM_6348_SPI_MSG_DATA,
77 + [SPI_RX_DATA] = SPI_BCM_6348_SPI_RX_DATA,
78 +};
79 +
80 +static const unsigned long bcm96358_regs_spi[] = {
81 + [SPI_CMD] = SPI_BCM_6358_SPI_CMD,
82 + [SPI_INT_STATUS] = SPI_BCM_6358_SPI_INT_STATUS,
83 + [SPI_INT_MASK_ST] = SPI_BCM_6358_SPI_MASK_INT_ST,
84 + [SPI_INT_MASK] = SPI_BCM_6358_SPI_INT_MASK,
85 + [SPI_ST] = SPI_BCM_6358_SPI_STATUS,
86 + [SPI_CLK_CFG] = SPI_BCM_6358_SPI_CLK_CFG,
87 + [SPI_FILL_BYTE] = SPI_BCM_6358_SPI_FILL_BYTE,
88 + [SPI_MSG_TAIL] = SPI_BCM_6358_SPI_MSG_TAIL,
89 + [SPI_RX_TAIL] = SPI_BCM_6358_SPI_RX_TAIL,
90 + [SPI_MSG_CTL] = SPI_BCM_6358_MSG_CTL,
91 + [SPI_MSG_DATA] = SPI_BCM_6358_SPI_MSG_DATA,
92 + [SPI_RX_DATA] = SPI_BCM_6358_SPI_RX_DATA,
93 +};
94 +
95 +const unsigned long *bcm63xx_regs_spi;
96 +EXPORT_SYMBOL(bcm63xx_regs_spi);
97 +
98 +static __init void bcm63xx_spi_regs_init(void)
99 +{
100 + if (BCMCPU_IS_6338())
101 + bcm63xx_regs_spi = bcm96338_regs_spi;
102 + if (BCMCPU_IS_6348())
103 + bcm63xx_regs_spi = bcm96348_regs_spi;
104 + if (BCMCPU_IS_6358())
105 + bcm63xx_regs_spi = bcm96358_regs_spi;
106 +}
107 +#else
108 +static __init void bcm63xx_spi_regs_init(void) { }
109 +#endif
110 +
111 +static struct resource spi_resources[] = {
112 + {
113 + .start = -1, /* filled at runtime */
114 + .end = -1, /* filled at runtime */
115 + .flags = IORESOURCE_MEM,
116 + },
117 + {
118 + .start = -1, /* filled at runtime */
119 + .flags = IORESOURCE_IRQ,
120 + },
121 +};
122 +
123 +static struct bcm63xx_spi_pdata spi_pdata = {
124 + .bus_num = 0,
125 + .num_chipselect = 8,
126 + .speed_hz = 50000000, /* Fclk */
127 +};
128 +
129 +static struct platform_device bcm63xx_spi_device = {
130 + .name = "bcm63xx-spi",
131 + .id = 0,
132 + .num_resources = ARRAY_SIZE(spi_resources),
133 + .resource = spi_resources,
134 + .dev = {
135 + .platform_data = &spi_pdata,
136 + },
137 +};
138 +
139 +int __init bcm63xx_spi_register(void)
140 +{
141 + spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
142 + spi_resources[0].end = spi_resources[0].start;
143 + spi_resources[0].end += RSET_SPI_SIZE - 1;
144 + spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
145 +
146 + /* Fill in platform data */
147 + if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
148 + spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
149 +
150 + if (BCMCPU_IS_6358())
151 + spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
152 +
153 + bcm63xx_spi_regs_init();
154 +
155 + return platform_device_register(&bcm63xx_spi_device);
156 +}
157 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
158 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
159 @@ -109,6 +109,7 @@ enum bcm63xx_regs_set {
160 #define RSET_WDT_SIZE 12
161 #define RSET_ENET_SIZE 2048
162 #define RSET_ENETDMA_SIZE 2048
163 +#define RSET_SPI_SIZE 256
164 #define RSET_UART_SIZE 24
165 #define RSET_UDC_SIZE 256
166 #define RSET_OHCI_SIZE 256
167 @@ -214,7 +215,7 @@ enum bcm63xx_regs_set {
168 #define BCM_6358_UART0_BASE (0xfffe0100)
169 #define BCM_6358_UART1_BASE (0xfffe0120)
170 #define BCM_6358_GPIO_BASE (0xfffe0080)
171 -#define BCM_6358_SPI_BASE (0xdeadbeef)
172 +#define BCM_6358_SPI_BASE (0xfffe0800)
173 #define BCM_6358_UDC0_BASE (0xfffe0400)
174 #define BCM_6358_OHCI0_BASE (0xfffe1400)
175 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
176 @@ -441,6 +442,7 @@ static inline unsigned long bcm63xx_regs
177 */
178 enum bcm63xx_irq {
179 IRQ_TIMER = 0,
180 + IRQ_SPI,
181 IRQ_UART0,
182 IRQ_UART1,
183 IRQ_DSL,
184 @@ -507,6 +509,7 @@ enum bcm63xx_irq {
185 * 6348 irqs
186 */
187 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
188 +#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
189 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
190 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
191 #define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6)
192 @@ -531,6 +534,7 @@ enum bcm63xx_irq {
193 * 6358 irqs
194 */
195 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
196 +#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
197 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
198 #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
199 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
200 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
201 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
202 @@ -769,4 +769,116 @@
203 #define DMIPSPLLCFG_N2_SHIFT 29
204 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
205
206 +/*************************************************************************
207 + * _REG relative to RSET_SPI
208 + *************************************************************************/
209 +
210 +/* BCM 6338 SPI core */
211 +#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */
212 +#define SPI_BCM_6338_SPI_INT_STATUS 0x02
213 +#define SPI_BCM_6338_SPI_MASK_INT_ST 0x03
214 +#define SPI_BCM_6338_SPI_INT_MASK 0x04
215 +#define SPI_BCM_6338_SPI_ST 0x05
216 +#define SPI_BCM_6338_SPI_CLK_CFG 0x06
217 +#define SPI_BCM_6338_SPI_FILL_BYTE 0x07
218 +#define SPI_BCM_6338_SPI_MSG_TAIL 0x09
219 +#define SPI_BCM_6338_SPI_RX_TAIL 0x0b
220 +#define SPI_BCM_6338_SPI_MSG_CTL 0x40
221 +#define SPI_BCM_6338_SPI_MSG_DATA 0x41
222 +#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
223 +#define SPI_BCM_6338_SPI_RX_DATA 0x80
224 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
225 +
226 +/* BCM 6348 SPI core */
227 +#define SPI_BCM_6348_SPI_MASK_INT_ST 0x00
228 +#define SPI_BCM_6348_SPI_INT_STATUS 0x01
229 +#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
230 +#define SPI_BCM_6348_SPI_FILL_BYTE 0x04
231 +#define SPI_BCM_6348_SPI_CLK_CFG 0x05
232 +#define SPI_BCM_6348_SPI_ST 0x06
233 +#define SPI_BCM_6348_SPI_INT_MASK 0x07
234 +#define SPI_BCM_6348_SPI_RX_TAIL 0x08
235 +#define SPI_BCM_6348_SPI_MSG_TAIL 0x10
236 +#define SPI_BCM_6348_SPI_MSG_DATA 0x40
237 +#define SPI_BCM_6348_SPI_MSG_CTL 0x42
238 +#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
239 +#define SPI_BCM_6348_SPI_RX_DATA 0x80
240 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
241 +
242 +/* BCM 6358 SPI core */
243 +#define SPI_BCM_6358_MSG_CTL 0x00 /* 16-bits register */
244 +
245 +#define SPI_BCM_6358_SPI_MSG_DATA 0x02
246 +#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
247 +
248 +#define SPI_BCM_6358_SPI_RX_DATA 0x400
249 +#define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
250 +
251 +#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
252 +
253 +#define SPI_BCM_6358_SPI_INT_STATUS 0x702
254 +#define SPI_BCM_6358_SPI_MASK_INT_ST 0x703
255 +
256 +#define SPI_BCM_6358_SPI_INT_MASK 0x704
257 +
258 +#define SPI_BCM_6358_SPI_STATUS 0x705
259 +
260 +#define SPI_BCM_6358_SPI_CLK_CFG 0x706
261 +
262 +#define SPI_BCM_6358_SPI_FILL_BYTE 0x707
263 +#define SPI_BCM_6358_SPI_MSG_TAIL 0x709
264 +#define SPI_BCM_6358_SPI_RX_TAIL 0x70B
265 +
266 +/* Shared SPI definitions */
267 +
268 +/* Message configuration */
269 +#define SPI_FD_RW 0x00
270 +#define SPI_HD_W 0x01
271 +#define SPI_HD_R 0x02
272 +#define SPI_BYTE_CNT_SHIFT 0
273 +#define SPI_MSG_TYPE_SHIFT 14
274 +
275 +/* Command */
276 +#define SPI_CMD_NOOP 0x01
277 +#define SPI_CMD_SOFT_RESET 0x02
278 +#define SPI_CMD_HARD_RESET 0x04
279 +#define SPI_CMD_START_IMMEDIATE 0x08
280 +#define SPI_CMD_COMMAND_SHIFT 0
281 +#define SPI_CMD_COMMAND_MASK 0x000f
282 +#define SPI_CMD_DEVICE_ID_SHIFT 4
283 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
284 +#define SPI_CMD_ONE_BYTE_SHIFT 11
285 +#define SPI_CMD_ONE_WIRE_SHIFT 12
286 +#define SPI_DEV_ID_0 0
287 +#define SPI_DEV_ID_1 1
288 +#define SPI_DEV_ID_2 2
289 +#define SPI_DEV_ID_3 3
290 +
291 +/* Interrupt mask */
292 +#define SPI_INTR_CMD_DONE 0x01
293 +#define SPI_INTR_RX_OVERFLOW 0x02
294 +#define SPI_INTR_TX_UNDERFLOW 0x04
295 +#define SPI_INTR_TX_OVERFLOW 0x08
296 +#define SPI_INTR_RX_UNDERFLOW 0x10
297 +#define SPI_INTR_CLEAR_ALL 0x1f
298 +
299 +/* Status */
300 +#define SPI_RX_EMPTY 0x02
301 +#define SPI_CMD_BUSY 0x04
302 +#define SPI_SERIAL_BUSY 0x08
303 +
304 +/* Clock configuration */
305 +#define SPI_CLK_20MHZ 0x00
306 +#define SPI_CLK_0_391MHZ 0x01
307 +#define SPI_CLK_0_781MHZ 0x02 /* default */
308 +#define SPI_CLK_1_563MHZ 0x03
309 +#define SPI_CLK_3_125MHZ 0x04
310 +#define SPI_CLK_6_250MHZ 0x05
311 +#define SPI_CLK_12_50MHZ 0x06
312 +#define SPI_CLK_25MHZ 0x07
313 +#define SPI_CLK_MASK 0x07
314 +#define SPI_SSOFFTIME_MASK 0x38
315 +#define SPI_SSOFFTIME_SHIFT 3
316 +#define SPI_BYTE_SWAP 0x80
317 +
318 #endif /* BCM63XX_REGS_H_ */
319 --- /dev/null
320 +++ b/drivers/spi/bcm63xx_spi.c
321 @@ -0,0 +1,501 @@
322 +/*
323 + * Broadcom BCM63xx SPI controller support
324 + *
325 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
326 + *
327 + * This program is free software; you can redistribute it and/or
328 + * modify it under the terms of the GNU General Public License
329 + * as published by the Free Software Foundation; either version 2
330 + * of the License, or (at your option) any later version.
331 + *
332 + * This program is distributed in the hope that it will be useful,
333 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
334 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
335 + * GNU General Public License for more details.
336 + *
337 + * You should have received a copy of the GNU General Public License
338 + * along with this program; if not, write to the
339 + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
340 + */
341 +
342 +#include <linux/kernel.h>
343 +#include <linux/init.h>
344 +#include <linux/clk.h>
345 +#include <linux/module.h>
346 +#include <linux/platform_device.h>
347 +#include <linux/delay.h>
348 +#include <linux/interrupt.h>
349 +#include <linux/spi/spi.h>
350 +#include <linux/completion.h>
351 +#include <linux/err.h>
352 +
353 +#include <bcm63xx_dev_spi.h>
354 +
355 +#define PFX KBUILD_MODNAME
356 +#define DRV_VER "0.1.2"
357 +
358 +struct bcm63xx_spi {
359 + spinlock_t lock;
360 + int stopping;
361 + struct completion done;
362 +
363 + void __iomem *regs;
364 + int irq;
365 +
366 + /* Platform data */
367 + u32 speed_hz;
368 + unsigned fifo_size;
369 +
370 + /* Data buffers */
371 + const unsigned char *tx_ptr;
372 + unsigned char *rx_ptr;
373 + int remaining_bytes;
374 +
375 + struct clk *clk;
376 + struct platform_device *pdev;
377 +};
378 +
379 +static inline u8 bcm_spi_readb(struct bcm63xx_hsspi *bs,
380 + unsigned int offset)
381 +{
382 + return bcm_readw(bs->regs + bcm63xx_spireg(offset));
383 +}
384 +
385 +static inline u16 bcm_spi_readw(struct bcm63xx_hsspi *bs,
386 + unsigned int offset)
387 +{
388 + return bcm_readw(bs->regs + bcm63xx_spireg(offset));
389 +}
390 +
391 +static inline void bcm_spi_writeb(struct bcm63xx_hsspi *bs,
392 + u8 value, unsigned int offset)
393 +{
394 + bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
395 +}
396 +
397 +static inline void bcm_spi_writew(struct bcm63xx_hsspi *bs,
398 + u16 value, unsigned int offset)
399 +{
400 + bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
401 +}
402 +
403 +static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
404 + struct spi_transfer *t)
405 +{
406 + u8 bits_per_word;
407 + u8 clk_cfg;
408 + u32 hz;
409 + unsigned int div;
410 +
411 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
412 +
413 + bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
414 + hz = (t) ? t->speed_hz : spi->max_speed_hz;
415 + if (bits_per_word != 8) {
416 + dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
417 + __func__, bits_per_word);
418 + return -EINVAL;
419 + }
420 +
421 + if (spi->chip_select > spi->master->num_chipselect) {
422 + dev_err(&spi->dev, "%s, unsupported slave %d\n",
423 + __func__, spi->chip_select);
424 + return -EINVAL;
425 + }
426 +
427 + /* Check clock setting */
428 + div = (bs->speed_hz / hz);
429 + switch (div) {
430 + case 2:
431 + clk_cfg = SPI_CLK_25MHZ;
432 + break;
433 + case 4:
434 + clk_cfg = SPI_CLK_12_50MHZ;
435 + break;
436 + case 8:
437 + clk_cfg = SPI_CLK_6_250MHZ;
438 + break;
439 + case 16:
440 + clk_cfg = SPI_CLK_3_125MHZ;
441 + break;
442 + case 32:
443 + clk_cfg = SPI_CLK_1_563MHZ;
444 + break;
445 + case 128:
446 + clk_cfg = SPI_CLK_0_781MHZ;
447 + break;
448 + case 64:
449 + default:
450 + /* Set to slowest mode for compatibility */
451 + clk_cfg = SPI_CLK_0_781MHZ;
452 + break;
453 + }
454 +
455 + bcm_spi_writeb(bs, clk_cfg, SPI_CLK_CFG);
456 + dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
457 + div, hz, clk_cfg);
458 +
459 + return 0;
460 +}
461 +
462 +/* the spi->mode bits understood by this driver: */
463 +#define MODEBITS (SPI_CPOL | SPI_CPHA)
464 +
465 +static int bcm63xx_spi_setup(struct spi_device *spi)
466 +{
467 + struct bcm63xx_spi *bs;
468 + int ret;
469 +
470 + bs = spi_master_get_devdata(spi->master);
471 +
472 + if (bs->stopping)
473 + return -ESHUTDOWN;
474 +
475 + if (!spi->bits_per_word)
476 + spi->bits_per_word = 8;
477 +
478 + if (spi->mode & ~MODEBITS) {
479 + dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
480 + __func__, spi->mode & ~MODEBITS);
481 + return -EINVAL;
482 + }
483 +
484 + ret = bcm63xx_spi_setup_transfer(spi, NULL);
485 + if (ret < 0) {
486 + dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
487 + spi->mode & ~MODEBITS);
488 + return ret;
489 + }
490 +
491 + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
492 + __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
493 +
494 + return 0;
495 +}
496 +
497 +/* Fill the TX FIFO with as many bytes as possible */
498 +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
499 +{
500 + u8 tail;
501 +
502 + /* Fill the Tx FIFO with as many bytes as possible */
503 + tail = bcm_spi_readb(bs, SPI_MSG_TAIL);
504 +
505 + while ((tail < bs->fifo_size) && (bs->remaining_bytes > 0)) {
506 + if (bs->tx_ptr)
507 + bcm_spi_writeb(bs, *bs->tx_ptr++, SPI_MSG_DATA);
508 + else
509 + bcm_spi_writeb(bs, 0, SPI_MSG_DATA);
510 +
511 + bs->remaining_bytes--;
512 + tail = bcm_spi_readb(bs, SPI_MSG_TAIL);
513 + }
514 +}
515 +
516 +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
517 +{
518 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
519 + u16 msg_ctl;
520 + u16 cmd;
521 +
522 + dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
523 + t->tx_buf, t->rx_buf, t->len);
524 +
525 + /* Transmitter is inhibited */
526 + bs->tx_ptr = t->tx_buf;
527 + bs->rx_ptr = t->rx_buf;
528 + init_completion(&bs->done);
529 +
530 + if (t->tx_buf) {
531 + bs->remaining_bytes = t->len;
532 + bcm63xx_spi_fill_tx_fifo(bs);
533 + }
534 +
535 + /* Enable the command done interrupt which
536 + * we use to determine completion of a command */
537 + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
538 +
539 + /* Fill in the Message control register */
540 + msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
541 +
542 + if (t->rx_buf && t->tx_buf)
543 + msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
544 + else if (t->rx_buf)
545 + msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
546 + else if (t->tx_buf)
547 + msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
548 +
549 + bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
550 +
551 + /* Issue the transfer */
552 + cmd = SPI_CMD_START_IMMEDIATE;
553 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
554 + bcm_spi_writew(bs, cmd, SPI_CMD);
555 + wait_for_completion(&bs->done);
556 +
557 + /* Disable the CMD_DONE interrupt */
558 + bcm_spi_writeb(bs, 0, SPI_INT_MASK);
559 +
560 + return t->len - bs->remaining_bytes;
561 +}
562 +
563 +static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m)
564 +{
565 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
566 + struct spi_transfer *t;
567 + int ret = 0;
568 +
569 + if (unlikely(list_empty(&m->transfers)))
570 + return -EINVAL;
571 +
572 + if (bs->stopping)
573 + return -ESHUTDOWN;
574 +
575 + list_for_each_entry(t, &m->transfers, transfer_list) {
576 + ret += bcm63xx_txrx_bufs(spi, t);
577 + }
578 +
579 + m->complete(m->context);
580 +
581 + return ret;
582 +}
583 +
584 +/* This driver supports single master mode only. Hence
585 + * CMD_DONE is the only interrupt we care about
586 + */
587 +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
588 +{
589 + struct spi_master *master = (struct spi_master *)dev_id;
590 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
591 + u8 intr;
592 + u16 cmd;
593 +
594 + /* Read interupts and clear them immediately */
595 + intr = bcm_spi_readb(bs, SPI_INT_STATUS);
596 + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
597 + bcm_spi_writeb(bs, 0, SPI_INT_MASK);
598 +
599 + /* A tansfer completed */
600 + if (intr & SPI_INTR_CMD_DONE) {
601 + u8 rx_tail;
602 +
603 + rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
604 +
605 + /* Read out all the data */
606 + if (rx_tail) {
607 + u8 data;
608 + u8 i = 0;
609 +
610 + for(i = 0; i < rx_tail; i++) {
611 + data = bcm_spi_readb(bs, SPI_RX_DATA);
612 + if (bs->rx_ptr)
613 + *bs->rx_ptr++ = data;
614 + }
615 + }
616 +
617 + /* See if there is more data to send */
618 + if (bs->remaining_bytes > 0) {
619 + bcm63xx_spi_fill_tx_fifo(bs);
620 +
621 + /* Start the transfer */
622 + bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT,
623 + SPI_MSG_CTL);
624 + cmd = bcm_spi_readw(bs, SPI_CMD);
625 + cmd |= SPI_CMD_START_IMMEDIATE;
626 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
627 + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
628 + bcm_spi_writew(bs, cmd, SPI_CMD);
629 + } else {
630 + complete(&bs->done);
631 + }
632 + }
633 +
634 + return IRQ_HANDLED;
635 +}
636 +
637 +
638 +static int __init bcm63xx_spi_probe(struct platform_device *pdev)
639 +{
640 + struct resource *r;
641 + struct device *dev = &pdev->dev;
642 + struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
643 + int irq;
644 + struct spi_master *master;
645 + struct clk *clk;
646 + struct bcm63xx_spi *bs;
647 + int ret;
648 +
649 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
650 + if (!r) {
651 + dev_err(dev, "no iomem\n");
652 + ret = -ENXIO;
653 + goto out;
654 + }
655 +
656 + irq = platform_get_irq(pdev, 0);
657 + if (irq < 0) {
658 + dev_err(dev, "no irq\n");
659 + ret = -ENXIO;
660 + goto out;
661 + }
662 +
663 + clk = clk_get(dev, "spi");
664 + if (IS_ERR(clk)) {
665 + dev_err(dev, "no clock for device\n");
666 + ret = -ENODEV;
667 + goto out;
668 + }
669 +
670 + master = spi_alloc_master(dev, sizeof(*bs));
671 + if (!master) {
672 + dev_err(dev, "out of memory\n");
673 + ret = -ENOMEM;
674 + goto out_free;
675 + }
676 +
677 + bs = spi_master_get_devdata(master);
678 + init_completion(&bs->done);
679 +
680 + platform_set_drvdata(pdev, master);
681 + bs->pdev = pdev;
682 +
683 + if (!request_mem_region(r->start, r->end - r->start, PFX)) {
684 + dev_err(dev, "iomem request failed\n");
685 + ret = -ENXIO;
686 + goto out_put_master;
687 + }
688 +
689 + bs->regs = ioremap_nocache(r->start, r->end - r->start);
690 + if (!bs->regs) {
691 + dev_err(dev, "unable to ioremap regs\n");
692 + ret = -ENOMEM;
693 + goto out_put_master;
694 + }
695 + bs->irq = irq;
696 + bs->clk = clk;
697 + bs->fifo_size = pdata->fifo_size;
698 +
699 + ret = request_irq(irq, bcm63xx_spi_interrupt, 0, pdev->name, master);
700 + if (ret) {
701 + dev_err(dev, "unable to request irq\n");
702 + goto out_unmap;
703 + }
704 +
705 + master->bus_num = pdata->bus_num;
706 + master->num_chipselect = pdata->num_chipselect;
707 + master->setup = bcm63xx_spi_setup;
708 + master->transfer = bcm63xx_transfer;
709 + bs->speed_hz = pdata->speed_hz;
710 + bs->stopping = 0;
711 + spin_lock_init(&bs->lock);
712 +
713 + /* Initialize hardware */
714 + clk_enable(bs->clk);
715 + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
716 +
717 + /* register and we are done */
718 + ret = spi_register_master(master);
719 + if (ret) {
720 + dev_err(dev, "spi register failed\n");
721 + goto out_reset_hw;
722 + }
723 +
724 + dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
725 + r->start, irq, bs->fifo_size, DRV_VER);
726 +
727 + return 0;
728 +
729 +out_reset_hw:
730 + clk_disable(clk);
731 + free_irq(irq, master);
732 +out_unmap:
733 + iounmap(bs->regs);
734 +out_put_master:
735 + spi_master_put(master);
736 +out_free:
737 + clk_put(clk);
738 +out:
739 + return ret;
740 +}
741 +
742 +static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
743 +{
744 + struct spi_master *master = platform_get_drvdata(pdev);
745 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
746 + struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
747 +
748 + /* reset spi block */
749 + bcm_spi_writeb(bs, 0, SPI_INT_MASK);
750 + spin_lock(&bs->lock);
751 + bs->stopping = 1;
752 +
753 + /* HW shutdown */
754 + clk_disable(bs->clk);
755 + clk_put(bs->clk);
756 +
757 + spin_unlock(&bs->lock);
758 +
759 + free_irq(bs->irq, master);
760 + iounmap(bs->regs);
761 + release_mem_region(r->start, r->end - r->start);
762 + platform_set_drvdata(pdev, 0);
763 + spi_unregister_master(master);
764 +
765 + return 0;
766 +}
767 +
768 +#ifdef CONFIG_PM
769 +static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
770 +{
771 + struct spi_master *master = platform_get_drvdata(pdev);
772 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
773 +
774 + clk_disable(bs->clk);
775 +
776 + return 0;
777 +}
778 +
779 +static int bcm63xx_spi_resume(struct platform_device *pdev)
780 +{
781 + struct spi_master *master = platform_get_drvdata(pdev);
782 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
783 +
784 + clk_enable(bs->clk);
785 +
786 + return 0;
787 +}
788 +#else
789 +#define bcm63xx_spi_suspend NULL
790 +#define bcm63xx_spi_resume NULL
791 +#endif
792 +
793 +static struct platform_driver bcm63xx_spi_driver = {
794 + .driver = {
795 + .name = "bcm63xx-spi",
796 + .owner = THIS_MODULE,
797 + },
798 + .probe = bcm63xx_spi_probe,
799 + .remove = bcm63xx_spi_remove,
800 + .suspend = bcm63xx_spi_suspend,
801 + .resume = bcm63xx_spi_resume,
802 +};
803 +
804 +
805 +static int __init bcm63xx_spi_init(void)
806 +{
807 + return platform_driver_register(&bcm63xx_spi_driver);
808 +}
809 +
810 +static void __exit bcm63xx_spi_exit(void)
811 +{
812 + platform_driver_unregister(&bcm63xx_spi_driver);
813 +}
814 +
815 +module_init(bcm63xx_spi_init);
816 +module_exit(bcm63xx_spi_exit);
817 +
818 +MODULE_ALIAS("platform:bcm63xx_spi");
819 +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
820 +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
821 +MODULE_LICENSE("GPL");
822 +MODULE_VERSION(DRV_VER);
823 --- a/drivers/spi/Kconfig
824 +++ b/drivers/spi/Kconfig
825 @@ -60,6 +60,12 @@ config SPI_ATMEL
826 This selects a driver for the Atmel SPI Controller, present on
827 many AT32 (AVR32) and AT91 (ARM) chips.
828
829 +config SPI_BCM63XX
830 + tristate "Broadcom BCM63xx SPI controller"
831 + depends on BCM63XX
832 + help
833 + This is the SPI controller master driver for Broadcom BCM63xx SoC.
834 +
835 config SPI_BFIN
836 tristate "SPI controller driver for ADI Blackfin5xx"
837 depends on BLACKFIN
838 --- a/drivers/spi/Makefile
839 +++ b/drivers/spi/Makefile
840 @@ -48,6 +48,7 @@ obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.
841 obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o
842 obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
843 obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o
844 +obj-$(CONFIG_SPI_BCM63XX) += bcm63xx_spi.o
845
846 # special build for s3c24xx spi driver with fiq support
847 spi_s3c24xx_hw-y := spi_s3c24xx.o
848 --- /dev/null
849 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
850 @@ -0,0 +1,126 @@
851 +#ifndef BCM63XX_DEV_SPI_H
852 +#define BCM63XX_DEV_SPI_H
853 +
854 +#include <linux/types.h>
855 +#include <bcm63xx_io.h>
856 +#include <bcm63xx_regs.h>
857 +
858 +int __init bcm63xx_spi_register(void);
859 +
860 +struct bcm63xx_spi_pdata {
861 + unsigned int fifo_size;
862 + int bus_num;
863 + int num_chipselect;
864 + u32 speed_hz;
865 +};
866 +
867 +enum bcm63xx_regs_spi {
868 + SPI_CMD,
869 + SPI_INT_STATUS,
870 + SPI_INT_MASK_ST,
871 + SPI_INT_MASK,
872 + SPI_ST,
873 + SPI_CLK_CFG,
874 + SPI_FILL_BYTE,
875 + SPI_MSG_TAIL,
876 + SPI_RX_TAIL,
877 + SPI_MSG_CTL,
878 + SPI_MSG_DATA,
879 + SPI_RX_DATA,
880 +};
881 +
882 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
883 +{
884 +#ifdef BCMCPU_RUNTIME_DETECT
885 + extern const unsigned long *bcm63xx_regs_spi;
886 + return bcm63xx_regs_spi[reg];
887 +#else
888 +#ifdef CONFIG_BCM63XX_CPU_6338
889 +switch (reg) {
890 + case SPI_CMD:
891 + return SPI_BCM_6338_SPI_CMD;
892 + case SPI_INT_STATUS:
893 + return SPI_BCM_6338_SPI_INT_STATUS;
894 + case SPI_INT_MASK_ST:
895 + return SPI_BCM_6338_SPI_MASK_INT_ST;
896 + case SPI_INT_MASK:
897 + return SPI_BCM_6338_SPI_INT_MASK;
898 + case SPI_ST:
899 + return SPI_BCM_6338_SPI_ST;
900 + case SPI_CLK_CFG:
901 + return SPI_BCM_6338_SPI_CLK_CFG;
902 + case SPI_FILL_BYTE:
903 + return SPI_BCM_6338_SPI_FILL_BYTE;
904 + case SPI_MSG_TAIL:
905 + return SPI_BCM_6338_SPI_MSG_TAIL;
906 + case SPI_RX_TAIL:
907 + return SPI_BCM_6338_SPI_RX_TAIL;
908 + case SPI_MSG_CTL:
909 + return SPI_BCM_6338_SPI_MSG_CTL;
910 + case SPI_MSG_DATA:
911 + return SPI_BCM_6338_SPI_MSG_DATA;
912 + case SPI_RX_DATA:
913 + return SPI_BCM_6338_SPI_RX_DATA;
914 +}
915 +#endif
916 +#ifdef CONFIG_BCM63XX_CPU_6348
917 +switch (reg) {
918 + case SPI_CMD:
919 + return SPI_BCM_6348_SPI_CMD;
920 + case SPI_INT_MASK_ST:
921 + return SPI_BCM_6348_SPI_MASK_INT_ST;
922 + case SPI_INT_MASK:
923 + return SPI_BCM_6348_SPI_INT_MASK;
924 + case SPI_INT_STATUS:
925 + return SPI_BCM_6348_SPI_INT_STATUS;
926 + case SPI_ST:
927 + return SPI_BCM_6348_SPI_ST;
928 + case SPI_CLK_CFG:
929 + return SPI_BCM_6348_SPI_CLK_CFG;
930 + case SPI_FILL_BYTE:
931 + return SPI_BCM_6348_SPI_FILL_BYTE;
932 + case SPI_MSG_TAIL:
933 + return SPI_BCM_6348_SPI_MSG_TAIL;
934 + case SPI_RX_TAIL:
935 + return SPI_BCM_6348_SPI_RX_TAIL;
936 + case SPI_MSG_CTL:
937 + return SPI_BCM_6348_SPI_MSG_CTL;
938 + case SPI_MSG_DATA:
939 + return SPI_BCM_6348_SPI_MSG_DATA;
940 + case SPI_RX_DATA:
941 + return SPI_BCM_6348_SPI_RX_DATA;
942 +}
943 +#endif
944 +#ifdef CONFIG_BCM63XX_CPU_6358
945 +switch (reg) {
946 + case SPI_CMD:
947 + return SPI_BCM_6358_SPI_CMD;
948 + case SPI_INT_STATUS:
949 + return SPI_BCM_6358_SPI_INT_STATUS;
950 + case SPI_INT_MASK_ST:
951 + return SPI_BCM_6358_SPI_MASK_INT_ST;
952 + case SPI_INT_MASK:
953 + return SPI_BCM_6358_SPI_INT_MASK;
954 + case SPI_ST:
955 + return SPI_BCM_6358_SPI_STATUS;
956 + case SPI_CLK_CFG:
957 + return SPI_BCM_6358_SPI_CLK_CFG;
958 + case SPI_FILL_BYTE:
959 + return SPI_BCM_6358_SPI_FILL_BYTE;
960 + case SPI_MSG_TAIL:
961 + return SPI_BCM_6358_SPI_MSG_TAIL;
962 + case SPI_RX_TAIL:
963 + return SPI_BCM_6358_SPI_RX_TAIL;
964 + case SPI_MSG_CTL:
965 + return SPI_BCM_6358_MSG_CTL;
966 + case SPI_MSG_DATA:
967 + return SPI_BCM_6358_SPI_MSG_DATA;
968 + case SPI_RX_DATA:
969 + return SPI_BCM_6358_SPI_RX_DATA;
970 +}
971 +#endif
972 +#endif
973 + return 0;
974 +}
975 +
976 +#endif /* BCM63XX_DEV_SPI_H */
977 --- a/arch/mips/bcm63xx/Makefile
978 +++ b/arch/mips/bcm63xx/Makefile
979 @@ -1,6 +1,6 @@
980 obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
981 dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o \
982 - dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o
983 + dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o dev-spi.o
984 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
985
986 obj-y += boards/
987 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
988 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
989 @@ -33,6 +33,7 @@
990 #include <bcm63xx_dev_usb_ohci.h>
991 #include <bcm63xx_dev_usb_ehci.h>
992 #include <bcm63xx_dev_usb_udc.h>
993 +#include <bcm63xx_dev_spi.h>
994 #include <board_bcm963xx.h>
995
996 #define PFX "board_bcm963xx: "
997 @@ -1587,6 +1588,9 @@ int __init board_register_devices(void)
998 if (board.num_spis)
999 spi_register_board_info(board.spis, board.num_spis);
1000
1001 + if (!BCMCPU_IS_6345())
1002 + bcm63xx_spi_register();
1003 +
1004 /* read base address of boot chip select (0) */
1005 if (BCMCPU_IS_6345())
1006 val = 0x1fc00000;
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