target/linux/brcm63xx/patches-3.14/324-MIPS-BCM63XX-protect-irq-register-accesses.patch

   1 From 5e86f3988854c62c0788e4820caf722fec7c791b Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Sun, 21 Apr 2013 15:38:56 +0200
   4 Subject: [PATCH 07/10] MIPS: BCM63XX: protect irq register accesses
   5
   6 Since we will have the chance of accessing the registers concurrently,
   7 protect any accesses through a spinlock.
   8
   9 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  10 ---
  11  arch/mips/bcm63xx/irq.c | 26 ++++++++++++++++++++++++++
  12  1 file changed, 26 insertions(+)
  13
  14 --- a/arch/mips/bcm63xx/irq.c
  15 +++ b/arch/mips/bcm63xx/irq.c
  16 @@ -12,6 +12,7 @@
  17  #include <linux/interrupt.h>
  18  #include <linux/module.h>
  19  #include <linux/irq.h>
  20 +#include <linux/spinlock.h>
  21  #include <asm/irq_cpu.h>
  22  #include <asm/mipsregs.h>
  23  #include <bcm63xx_cpu.h>
  24 @@ -20,6 +21,9 @@
  25  #include <bcm63xx_irq.h>
  26
  27
  28 +static DEFINE_SPINLOCK(ipic_lock);
  29 +static DEFINE_SPINLOCK(epic_lock);
  30 +
  31  static u32 irq_stat_addr[2];
  32  static u32 irq_mask_addr[2];
  33  static void (*dispatch_internal)(int cpu);
  34 @@ -62,8 +66,10 @@ void __dispatch_internal_##width(int cpu
  35         bool irqs_pending = false;                                      \
  36         static unsigned int i[2];                                       \
  37         unsigned int *next = &i[cpu];                                   \
  38 +       unsigned long flags;                                            \
  39                                                                         \
  40         /* read registers in reverse order */                           \
  41 +       spin_lock_irqsave(&ipic_lock, flags);                           \
  42         for (src = 0, tgt = (width / 32); src < (width / 32); src++) {  \
  43                 u32 val;                                                \
  44                                                                         \
  45 @@ -74,6 +80,7 @@ void __dispatch_internal_##width(int cpu
  46                 if (val)                                                \
  47                         irqs_pending = true;                            \
  48         }                                                               \
  49 +       spin_unlock_irqrestore(&ipic_lock, flags);                      \
  50                                                                         \
  51         if (!irqs_pending)                                              \
  52                 return;                                                 \
  53 @@ -94,10 +101,13 @@ static void __internal_irq_mask_##width(
  54         u32 val;                                                        \
  55         unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
  56         unsigned bit = irq & 0x1f;                                      \
  57 +       unsigned long flags;                                            \
  58                                                                         \
  59 +       spin_lock_irqsave(&ipic_lock, flags);                           \
  60         val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32));          \
  61         val &= ~(1 << bit);                                             \
  62         bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32));          \
  63 +       spin_unlock_irqrestore(&ipic_lock, flags);                      \
  64  }                                                                      \
  65                                                                         \
  66  static void __internal_irq_unmask_##width(unsigned int irq)            \
  67 @@ -105,10 +115,13 @@ static void __internal_irq_unmask_##widt
  68         u32 val;                                                        \
  69         unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
  70         unsigned bit = irq & 0x1f;                                      \
  71 +       unsigned long flags;                                            \
  72                                                                         \
  73 +       spin_lock_irqsave(&ipic_lock, flags);                           \
  74         val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32));          \
  75         val |= (1 << bit);                                              \
  76         bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32));          \
  77 +       spin_unlock_irqrestore(&ipic_lock, flags);                      \
  78  }
  79
  80  BUILD_IPIC_INTERNAL(32);
  81 @@ -167,8 +180,10 @@ static void bcm63xx_external_irq_mask(st
  82  {
  83         unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
  84         u32 reg, regaddr;
  85 +       unsigned long flags;
  86
  87         regaddr = get_ext_irq_perf_reg(irq);
  88 +       spin_lock_irqsave(&epic_lock, flags);
  89         reg = bcm_perf_readl(regaddr);
  90
  91         if (BCMCPU_IS_6348())
  92 @@ -177,6 +192,8 @@ static void bcm63xx_external_irq_mask(st
  93                 reg &= ~EXTIRQ_CFG_MASK(irq % 4);
  94
  95         bcm_perf_writel(reg, regaddr);
  96 +       spin_unlock_irqrestore(&epic_lock, flags);
  97 +
  98         if (is_ext_irq_cascaded)
  99                 internal_irq_mask(irq + ext_irq_start);
 100  }
 101 @@ -185,8 +202,10 @@ static void bcm63xx_external_irq_unmask(
 102  {
 103         unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
 104         u32 reg, regaddr;
 105 +       unsigned long flags;
 106
 107         regaddr = get_ext_irq_perf_reg(irq);
 108 +       spin_lock_irqsave(&epic_lock, flags);
 109         reg = bcm_perf_readl(regaddr);
 110
 111         if (BCMCPU_IS_6348())
 112 @@ -195,6 +214,7 @@ static void bcm63xx_external_irq_unmask(
 113                 reg |= EXTIRQ_CFG_MASK(irq % 4);
 114
 115         bcm_perf_writel(reg, regaddr);
 116 +       spin_unlock_irqrestore(&epic_lock, flags);
 117
 118         if (is_ext_irq_cascaded)
 119                 internal_irq_unmask(irq + ext_irq_start);
 120 @@ -204,8 +224,10 @@ static void bcm63xx_external_irq_clear(s
 121  {
 122         unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
 123         u32 reg, regaddr;
 124 +       unsigned long flags;
 125
 126         regaddr = get_ext_irq_perf_reg(irq);
 127 +       spin_lock_irqsave(&epic_lock, flags);
 128         reg = bcm_perf_readl(regaddr);
 129
 130         if (BCMCPU_IS_6348())
 131 @@ -214,6 +236,7 @@ static void bcm63xx_external_irq_clear(s
 132                 reg |= EXTIRQ_CFG_CLEAR(irq % 4);
 133
 134         bcm_perf_writel(reg, regaddr);
 135 +       spin_unlock_irqrestore(&epic_lock, flags);
 136  }
 137
 138  static int bcm63xx_external_irq_set_type(struct irq_data *d,
 139 @@ -222,6 +245,7 @@ static int bcm63xx_external_irq_set_type
 140         unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
 141         u32 reg, regaddr;
 142         int levelsense, sense, bothedge;
 143 +       unsigned long flags;
 144
 145         flow_type &= IRQ_TYPE_SENSE_MASK;
 146
 147 @@ -256,6 +280,7 @@ static int bcm63xx_external_irq_set_type
 148         }
 149
 150         regaddr = get_ext_irq_perf_reg(irq);
 151 +       spin_lock_irqsave(&epic_lock, flags);
 152         reg = bcm_perf_readl(regaddr);
 153         irq %= 4;
 154
 155 @@ -300,6 +325,7 @@ static int bcm63xx_external_irq_set_type
 156         }
 157
 158         bcm_perf_writel(reg, regaddr);
 159 +       spin_unlock_irqrestore(&epic_lock, flags);
 160
 161         irqd_set_trigger_type(d, flow_type);
 162         if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))