target/linux/brcm63xx/patches-3.3/030-MIPS-BCM63XX-Fix-BCM6345-clock-bits.patch

   1 [PATCH] MIPS: BCM63XX: fix BCM6345 clock bits shifting
   2
   3 BCM6345 has an intermediate 16-bits wide test control register between the
   4 peripheral identifier function, and its clock control register is only 16-bits
   5 wide contrary to other platforms where it is 32-bits wide. By shifting all
   6 clocks bits by 16-bits to the left we ensure they get written to the proper
   7 clock control register, without adding specific BCM6345 handling in the clock
   8 code.
   9
  10 Signed-off-by: Florian Fainelli <florian@openwrt.org>
  11 ---
  12 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  13 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  14 @@ -53,13 +53,13 @@
  15                                         CKCTL_6338_SAR_EN |             \
  16                                         CKCTL_6338_SPI_EN)
  17
  18 -#define CKCTL_6345_CPU_EN              (1 << 0)
  19 -#define CKCTL_6345_BUS_EN              (1 << 1)
  20 -#define CKCTL_6345_EBI_EN              (1 << 2)
  21 -#define CKCTL_6345_UART_EN             (1 << 3)
  22 -#define CKCTL_6345_ADSLPHY_EN          (1 << 4)
  23 -#define CKCTL_6345_ENET_EN             (1 << 7)
  24 -#define CKCTL_6345_USBH_EN             (1 << 8)
  25 +#define CKCTL_6345_CPU_EN              (1 << 16)
  26 +#define CKCTL_6345_BUS_EN              (1 << 17)
  27 +#define CKCTL_6345_EBI_EN              (1 << 18)
  28 +#define CKCTL_6345_UART_EN             (1 << 19)
  29 +#define CKCTL_6345_ADSLPHY_EN          (1 << 20)
  30 +#define CKCTL_6345_ENET_EN             (1 << 23)
  31 +#define CKCTL_6345_USBH_EN             (1 << 24)
  32
  33  #define CKCTL_6345_ALL_SAFE_EN         (CKCTL_6345_ENET_EN |   \
  34                                         CKCTL_6345_USBH_EN |    \