target/linux/brcm63xx/patches-3.8/419-MIPS-BCM63XX-enable-enet-for-BCM6345.patch

   1 From 1b0b5d325d0cc50cade62afd6a9416fb3cd1e658 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Mon, 7 Jan 2013 17:42:45 +0100
   4 Subject: [PATCH 69/72] 443-MIPS-BCM63XX-enable-enet-for-BCM6345.patch
   5
   6 ---
   7  arch/mips/bcm63xx/dev-enet.c                       |   63 ++++++-
   8  arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h   |    3 +-
   9  .../include/asm/mach-bcm63xx/bcm63xx_dev_enet.h    |   88 +++++++++
  10  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h  |   43 ++++-
  11  drivers/net/ethernet/broadcom/bcm63xx_enet.c       |  199 ++++++++++++--------
  12  drivers/net/ethernet/broadcom/bcm63xx_enet.h       |   15 ++
  13  6 files changed, 320 insertions(+), 91 deletions(-)
  14
  15 --- a/arch/mips/bcm63xx/dev-enet.c
  16 +++ b/arch/mips/bcm63xx/dev-enet.c
  17 @@ -9,10 +9,44 @@
  18  #include <linux/init.h>
  19  #include <linux/kernel.h>
  20  #include <linux/platform_device.h>
  21 +#include <linux/export.h>
  22  #include <bcm63xx_dev_enet.h>
  23  #include <bcm63xx_io.h>
  24  #include <bcm63xx_regs.h>
  25
  26 +#ifdef BCMCPU_RUNTIME_DETECT
  27 +static const unsigned long bcm6xxx_regs_enetdmac[] = {
  28 +       [ENETDMAC_CHANCFG]      = ENETDMAC_CHANCFG_REG,
  29 +       [ENETDMAC_IR]           = ENETDMAC_IR_REG,
  30 +       [ENETDMAC_IRMASK]       = ENETDMAC_IRMASK_REG,
  31 +       [ENETDMAC_MAXBURST]     = ENETDMAC_MAXBURST_REG,
  32 +};
  33 +
  34 +static const unsigned long bcm6345_regs_enetdmac[] = {
  35 +       [ENETDMAC_CHANCFG]      = ENETDMA_6345_CHANCFG_REG,
  36 +       [ENETDMAC_IR]           = ENETDMA_6345_IR_REG,
  37 +       [ENETDMAC_IRMASK]       = ENETDMA_6345_IRMASK_REG,
  38 +       [ENETDMAC_MAXBURST]     = ENETDMA_6345_MAXBURST_REG,
  39 +       [ENETDMAC_BUFALLOC]     = ENETDMA_6345_BUFALLOC_REG,
  40 +       [ENETDMAC_RSTART]       = ENETDMA_6345_RSTART_REG,
  41 +       [ENETDMAC_FC]           = ENETDMA_6345_FC_REG,
  42 +       [ENETDMAC_LEN]          = ENETDMA_6345_LEN_REG,
  43 +};
  44 +
  45 +const unsigned long *bcm63xx_regs_enetdmac;
  46 +EXPORT_SYMBOL(bcm63xx_regs_enetdmac);
  47 +
  48 +static __init void bcm63xx_enetdmac_regs_init(void)
  49 +{
  50 +       if (BCMCPU_IS_6345())
  51 +               bcm63xx_regs_enetdmac = bcm6345_regs_enetdmac;
  52 +       else
  53 +               bcm63xx_regs_enetdmac = bcm6xxx_regs_enetdmac;
  54 +}
  55 +#else
  56 +static __init void bcm63xx_enetdmac_regs_init(void) { }
  57 +#endif
  58 +
  59  static struct resource shared_res[] = {
  60         {
  61                 .start          = -1, /* filled at runtime */
  62 @@ -137,12 +171,19 @@ static int __init register_shared(void)
  63         if (shared_device_registered)
  64                 return 0;
  65
  66 +       bcm63xx_enetdmac_regs_init();
  67 +
  68         shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
  69         shared_res[0].end = shared_res[0].start;
  70 -       shared_res[0].end += (RSET_ENETDMA_SIZE)  - 1;
  71 +       if (BCMCPU_IS_6345())
  72 +               shared_res[0].end += (RSET_6345_ENETDMA_SIZE) - 1;
  73 +       else
  74 +               shared_res[0].end += (RSET_ENETDMA_SIZE)  - 1;
  75
  76         if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
  77                 chan_count = 32;
  78 +       else if (BCMCPU_IS_6345())
  79 +               chan_count = 8;
  80         else
  81                 chan_count = 16;
  82
  83 @@ -172,7 +213,7 @@ int __init bcm63xx_enet_register(int uni
  84         if (unit > 1)
  85                 return -ENODEV;
  86
  87 -       if (unit == 1 && BCMCPU_IS_6338())
  88 +       if (unit == 1 && (BCMCPU_IS_6338() || BCMCPU_IS_6345()))
  89                 return -ENODEV;
  90
  91         ret = register_shared();
  92 @@ -213,6 +254,20 @@ int __init bcm63xx_enet_register(int uni
  93                 dpd->phy_interrupt = bcm63xx_get_irq_number(IRQ_ENET_PHY);
  94         }
  95
  96 +       dpd->dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
  97 +       dpd->dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
  98 +       if (BCMCPU_IS_6345()) {
  99 +               dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_CHAINING_MASK;
 100 +               dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_WRAP_EN_MASK;
 101 +               dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_FLOWC_EN_MASK;
 102 +               dpd->dma_chan_int_mask |= ENETDMA_IR_BUFDONE_MASK;
 103 +               dpd->dma_chan_int_mask |= ENETDMA_IR_NOTOWNER_MASK;
 104 +               dpd->dma_chan_width = ENETDMA_6345_CHAN_WIDTH;
 105 +               dpd->dma_no_sram = 1;
 106 +               dpd->dma_desc_shift = ENETDMA_6345_DESC_SHIFT;
 107 +       } else
 108 +               dpd->dma_chan_width = ENETDMA_CHAN_WIDTH;
 109 +
 110         ret = platform_device_register(pdev);
 111         if (ret)
 112                 return ret;
 113 @@ -246,6 +301,10 @@ bcm63xx_enetsw_register(const struct bcm
 114         else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
 115                 enetsw_pd.num_ports = ENETSW_PORTS_6368;
 116
 117 +       enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH;
 118 +       enetsw_pd.dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
 119 +       enetsw_pd.dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
 120 +
 121         ret = platform_device_register(&bcm63xx_enetsw_device);
 122         if (ret)
 123                 return ret;
 124 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 125 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 126 @@ -175,6 +175,7 @@ enum bcm63xx_regs_set {
 127  #define BCM_6368_RSET_SPI_SIZE         1804
 128  #define RSET_ENET_SIZE                 2048
 129  #define RSET_ENETDMA_SIZE              256
 130 +#define RSET_6345_ENETDMA_SIZE         64
 131  #define RSET_ENETDMAC_SIZE(chans)      (16 * (chans))
 132  #define RSET_ENETDMAS_SIZE(chans)      (16 * (chans))
 133  #define RSET_ENETSW_SIZE               65536
 134 @@ -305,7 +306,7 @@ enum bcm63xx_regs_set {
 135  #define BCM_6345_USBDMA_BASE           (0xfffe2800)
 136  #define BCM_6345_ENET0_BASE            (0xfffe1800)
 137  #define BCM_6345_ENETDMA_BASE          (0xfffe2800)
 138 -#define BCM_6345_ENETDMAC_BASE         (0xfffe2900)
 139 +#define BCM_6345_ENETDMAC_BASE         (0xfffe2840)
 140  #define BCM_6345_ENETDMAS_BASE         (0xfffe2a00)
 141  #define BCM_6345_ENETSW_BASE           (0xdeadbeef)
 142  #define BCM_6345_PCMCIA_BASE           (0xfffe2028)
 143 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
 144 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
 145 @@ -4,6 +4,8 @@
 146  #include <linux/if_ether.h>
 147  #include <linux/init.h>
 148
 149 +#include <bcm63xx_regs.h>
 150 +
 151  /*
 152   * on board ethernet platform data
 153   */
 154 @@ -37,6 +39,21 @@ struct bcm63xx_enet_platform_data {
 155                                           int phy_id, int reg),
 156                           void (*mii_write)(struct net_device *dev,
 157                                             int phy_id, int reg, int val));
 158 +
 159 +       /* DMA channel enable mask */
 160 +       u32 dma_chan_en_mask;
 161 +
 162 +       /* DMA channel interrupt mask */
 163 +       u32 dma_chan_int_mask;
 164 +
 165 +       /* Set to one if DMA engine has *no* SRAM */
 166 +       unsigned int dma_no_sram;
 167 +
 168 +       /* DMA channel register width */
 169 +       unsigned int dma_chan_width;
 170 +
 171 +       /* DMA descriptor shift */
 172 +       unsigned int dma_desc_shift;
 173  };
 174
 175  /*
 176 @@ -63,6 +80,15 @@ struct bcm63xx_enetsw_platform_data {
 177         char mac_addr[ETH_ALEN];
 178         int num_ports;
 179         struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
 180 +
 181 +       /* DMA channel enable mask */
 182 +       u32 dma_chan_en_mask;
 183 +
 184 +       /* DMA channel interrupt mask */
 185 +       u32 dma_chan_int_mask;
 186 +
 187 +       /* DMA channel register width */
 188 +       unsigned int dma_chan_width;
 189  };
 190
 191  int __init bcm63xx_enet_register(int unit,
 192 @@ -70,4 +96,69 @@ int __init bcm63xx_enet_register(int uni
 193
 194  int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
 195
 196 +enum bcm63xx_regs_enetdmac {
 197 +       ENETDMAC_CHANCFG,
 198 +       ENETDMAC_IR,
 199 +       ENETDMAC_IRMASK,
 200 +       ENETDMAC_MAXBURST,
 201 +       ENETDMAC_BUFALLOC,
 202 +       ENETDMAC_RSTART,
 203 +       ENETDMAC_FC,
 204 +       ENETDMAC_LEN,
 205 +};
 206 +
 207 +static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
 208 +{
 209 +#ifdef BCMCPU_RUNTIME_DETECT
 210 +       extern const unsigned long *bcm63xx_regs_enetdmac;
 211 +
 212 +       return bcm63xx_regs_enetdmac[reg];
 213 +#else
 214 +#ifdef CONFIG_BCM63XX_CPU_6345
 215 +       switch (reg) {
 216 +       case ENETDMAC_CHANCFG:
 217 +               return ENETDMA_6345_CHANCFG_REG;
 218 +       case ENETDMAC_IR:
 219 +               return ENETDMA_6345_IR_REG;
 220 +       case ENETDMAC_IRMASK:
 221 +               return ENETDMA_6345_IRMASK_REG;
 222 +       case ENETDMAC_MAXBURST:
 223 +               return ENETDMA_6345_MAXBURST_REG;
 224 +       case ENETDMAC_BUFALLOC:
 225 +               return ENETDMA_6345_BUFALLOC_REG;
 226 +       case ENETDMAC_RSTART:
 227 +               return ENETDMA_6345_RSTART_REG;
 228 +       case ENETDMAC_FC:
 229 +               return ENETDMA_6345_FC_REG;
 230 +       case ENETDMAC_LEN:
 231 +               return ENETDMA_6345_LEN_REG;
 232 +       }
 233 +#endif
 234 +#if defined(CONFIG_BCM63XX_CPU_6328) || \
 235 +       defined(CONFIG_BCM63XX_CPU_6338) || \
 236 +       defined(CONFIG_BCM63XX_CPU_6348) || \
 237 +       defined(CONFIG_BCM63XX_CPU_6358) || \
 238 +       defined(CONFIG_BCM63XX_CPU_6362) || \
 239 +       defined(CONFIG_BCM63XX_CPU_6368)
 240 +       switch (reg) {
 241 +       case ENETDMAC_CHANCFG:
 242 +               return ENETDMAC_CHANCFG_REG;
 243 +       case ENETDMAC_IR:
 244 +               return ENETDMAC_IR_REG;
 245 +       case ENETDMAC_IRMASK:
 246 +               return ENETDMAC_IRMASK_REG;
 247 +       case ENETDMAC_MAXBURST:
 248 +               return ENETDMAC_MAXBURST_REG;
 249 +       case ENETDMAC_BUFALLOC:
 250 +       case ENETDMAC_RSTART:
 251 +       case ENETDMAC_FC:
 252 +       case ENETDMAC_LEN:
 253 +               return 0;
 254 +       }
 255 +#endif
 256 +#endif
 257 +       return 0;
 258 +}
 259 +
 260 +
 261  #endif /* ! BCM63XX_DEV_ENET_H_ */
 262 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 263 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 264 @@ -730,6 +730,8 @@
 265  /*************************************************************************
 266   * _REG relative to RSET_ENETDMA
 267   *************************************************************************/
 268 +#define ENETDMA_CHAN_WIDTH             0x10
 269 +#define ENETDMA_6345_CHAN_WIDTH                0x40
 270
 271  /* Controller Configuration Register */
 272  #define ENETDMA_CFG_REG                        (0x0)
 273 @@ -785,31 +787,56 @@
 274  /* State Ram Word 4 */
 275  #define ENETDMA_SRAM4_REG(x)           (0x20c + (x) * 0x10)
 276
 277 +/* Broadcom 6345 ENET DMA definitions */
 278 +#define ENETDMA_6345_CHANCFG_REG       (0x00)
 279 +
 280 +#define ENETDMA_6345_MAXBURST_REG      (0x40)
 281 +
 282 +#define ENETDMA_6345_RSTART_REG                (0x08)
 283 +
 284 +#define ENETDMA_6345_LEN_REG           (0x0C)
 285 +
 286 +#define ENETDMA_6345_IR_REG            (0x14)
 287 +
 288 +#define ENETDMA_6345_IRMASK_REG                (0x18)
 289 +
 290 +#define ENETDMA_6345_FC_REG            (0x1C)
 291 +
 292 +#define ENETDMA_6345_BUFALLOC_REG      (0x20)
 293 +
 294 +/* Shift down for EOP, SOP and WRAP bits */
 295 +#define ENETDMA_6345_DESC_SHIFT                (3)
 296
 297  /*************************************************************************
 298   * _REG relative to RSET_ENETDMAC
 299   *************************************************************************/
 300
 301  /* Channel Configuration register */
 302 -#define ENETDMAC_CHANCFG_REG(x)                ((x) * 0x10)
 303 +#define ENETDMAC_CHANCFG_REG           (0x0)
 304  #define ENETDMAC_CHANCFG_EN_SHIFT      0
 305  #define ENETDMAC_CHANCFG_EN_MASK       (1 << ENETDMAC_CHANCFG_EN_SHIFT)
 306  #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
 307  #define ENETDMAC_CHANCFG_PKTHALT_MASK  (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
 308  #define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
 309  #define ENETDMAC_CHANCFG_BUFHALT_MASK  (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
 310 +#define ENETDMAC_CHANCFG_CHAINING_SHIFT        2
 311 +#define ENETDMAC_CHANCFG_CHAINING_MASK (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
 312 +#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT 3
 313 +#define ENETDMAC_CHANCFG_WRAP_EN_MASK  (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
 314 +#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT        4
 315 +#define ENETDMAC_CHANCFG_FLOWC_EN_MASK (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
 316
 317  /* Interrupt Control/Status register */
 318 -#define ENETDMAC_IR_REG(x)             (0x4 + (x) * 0x10)
 319 +#define ENETDMAC_IR_REG                        (0x4)
 320  #define ENETDMAC_IR_BUFDONE_MASK       (1 << 0)
 321  #define ENETDMAC_IR_PKTDONE_MASK       (1 << 1)
 322  #define ENETDMAC_IR_NOTOWNER_MASK      (1 << 2)
 323
 324  /* Interrupt Mask register */
 325 -#define ENETDMAC_IRMASK_REG(x)         (0x8 + (x) * 0x10)
 326 +#define ENETDMAC_IRMASK_REG            (0x8)
 327
 328  /* Maximum Burst Length */
 329 -#define ENETDMAC_MAXBURST_REG(x)       (0xc + (x) * 0x10)
 330 +#define ENETDMAC_MAXBURST_REG          (0xc)
 331
 332
 333  /*************************************************************************
 334 @@ -817,16 +844,16 @@
 335   *************************************************************************/
 336
 337  /* Ring Start Address register */
 338 -#define ENETDMAS_RSTART_REG(x)         ((x) * 0x10)
 339 +#define ENETDMAS_RSTART_REG            (0x0)
 340
 341  /* State Ram Word 2 */
 342 -#define ENETDMAS_SRAM2_REG(x)          (0x4 + (x) * 0x10)
 343 +#define ENETDMAS_SRAM2_REG             (0x4)
 344
 345  /* State Ram Word 3 */
 346 -#define ENETDMAS_SRAM3_REG(x)          (0x8 + (x) * 0x10)
 347 +#define ENETDMAS_SRAM3_REG             (0x8)
 348
 349  /* State Ram Word 4 */
 350 -#define ENETDMAS_SRAM4_REG(x)          (0xc + (x) * 0x10)
 351 +#define ENETDMAS_SRAM4_REG             (0xc)
 352
 353
 354  /*************************************************************************
 355 --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
 356 +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
 357 @@ -115,26 +115,28 @@ static inline void enet_dma_writel(struc
 358         bcm_writel(val, bcm_enet_shared_base[0] + off);
 359  }
 360
 361 -static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off)
 362 +static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 363  {
 364 -       return bcm_readl(bcm_enet_shared_base[1] + off);
 365 +       return bcm_readl(bcm_enet_shared_base[1] +
 366 +               (bcm63xx_enetdmacreg(off) + (chan * priv->dma_chan_width)));
 367  }
 368
 369  static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
 370 -                                      u32 val, u32 off)
 371 +                                      u32 val, u32 off, int chan)
 372  {
 373 -       bcm_writel(val, bcm_enet_shared_base[1] + off);
 374 +       bcm_writel(val, bcm_enet_shared_base[1] +
 375 +               (bcm63xx_enetdmacreg(off) + (chan * priv->dma_chan_width)));
 376  }
 377
 378 -static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off)
 379 +static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 380  {
 381 -       return bcm_readl(bcm_enet_shared_base[2] + off);
 382 +       return bcm_readl(bcm_enet_shared_base[2] + (off + (chan * priv->dma_chan_width)));
 383  }
 384
 385  static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
 386 -                                      u32 val, u32 off)
 387 +                                      u32 val, u32 off, int chan)
 388  {
 389 -       bcm_writel(val, bcm_enet_shared_base[2] + off);
 390 +       bcm_writel(val, bcm_enet_shared_base[2] + (off + (chan * priv->dma_chan_width)));
 391  }
 392
 393  /*
 394 @@ -270,7 +272,7 @@ static int bcm_enet_refill_rx(struct net
 395                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 396                 len_stat |= DMADESC_OWNER_MASK;
 397                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 398 -                       len_stat |= DMADESC_WRAP_MASK;
 399 +                       len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 400                         priv->rx_dirty_desc = 0;
 401                 } else {
 402                         priv->rx_dirty_desc++;
 403 @@ -281,7 +283,10 @@ static int bcm_enet_refill_rx(struct net
 404                 priv->rx_desc_count++;
 405
 406                 /* tell dma engine we allocated one buffer */
 407 -               enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 408 +               if (!priv->dma_no_sram)
 409 +                       enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 410 +               else
 411 +                       enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
 412         }
 413
 414         /* If rx ring is still empty, set a timer to try allocating
 415 @@ -357,7 +362,8 @@ static int bcm_enet_receive_queue(struct
 416
 417                 /* if the packet does not have start of packet _and_
 418                  * end of packet flag set, then just recycle it */
 419 -               if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
 420 +               if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
 421 +                       (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
 422                         dev->stats.rx_dropped++;
 423                         continue;
 424                 }
 425 @@ -418,8 +424,8 @@ static int bcm_enet_receive_queue(struct
 426                 bcm_enet_refill_rx(dev);
 427
 428                 /* kick rx dma */
 429 -               enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
 430 -                                ENETDMAC_CHANCFG_REG(priv->rx_chan));
 431 +               enet_dmac_writel(priv, priv->dma_chan_en_mask,
 432 +                                        ENETDMAC_CHANCFG, priv->rx_chan);
 433         }
 434
 435         return processed;
 436 @@ -494,10 +500,10 @@ static int bcm_enet_poll(struct napi_str
 437         dev = priv->net_dev;
 438
 439         /* ack interrupts */
 440 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 441 -                        ENETDMAC_IR_REG(priv->rx_chan));
 442 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 443 -                        ENETDMAC_IR_REG(priv->tx_chan));
 444 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 445 +                        ENETDMAC_IR, priv->rx_chan);
 446 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 447 +                        ENETDMAC_IR, priv->tx_chan);
 448
 449         /* reclaim sent skb */
 450         tx_work_done = bcm_enet_tx_reclaim(dev, 0);
 451 @@ -516,10 +522,10 @@ static int bcm_enet_poll(struct napi_str
 452         napi_complete(napi);
 453
 454         /* restore rx/tx interrupt */
 455 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 456 -                        ENETDMAC_IRMASK_REG(priv->rx_chan));
 457 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 458 -                        ENETDMAC_IRMASK_REG(priv->tx_chan));
 459 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 460 +                        ENETDMAC_IRMASK, priv->rx_chan);
 461 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 462 +                        ENETDMAC_IRMASK, priv->tx_chan);
 463
 464         return rx_work_done;
 465  }
 466 @@ -562,8 +568,8 @@ static irqreturn_t bcm_enet_isr_dma(int
 467         priv = netdev_priv(dev);
 468
 469         /* mask rx/tx interrupts */
 470 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
 471 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
 472 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 473 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 474
 475         napi_schedule(&priv->napi);
 476
 477 @@ -624,14 +630,14 @@ static int bcm_enet_start_xmit(struct sk
 478                                        DMA_TO_DEVICE);
 479
 480         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 481 -       len_stat |= DMADESC_ESOP_MASK |
 482 +       len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
 483                 DMADESC_APPEND_CRC |
 484                 DMADESC_OWNER_MASK;
 485
 486         priv->tx_curr_desc++;
 487         if (priv->tx_curr_desc == priv->tx_ring_size) {
 488                 priv->tx_curr_desc = 0;
 489 -               len_stat |= DMADESC_WRAP_MASK;
 490 +               len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 491         }
 492         priv->tx_desc_count--;
 493
 494 @@ -642,8 +648,8 @@ static int bcm_enet_start_xmit(struct sk
 495         wmb();
 496
 497         /* kick tx dma */
 498 -       enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
 499 -                        ENETDMAC_CHANCFG_REG(priv->tx_chan));
 500 +       enet_dmac_writel(priv, priv->dma_chan_en_mask,
 501 +                                ENETDMAC_CHANCFG, priv->tx_chan);
 502
 503         /* stop queue if no more desc available */
 504         if (!priv->tx_desc_count)
 505 @@ -771,6 +777,9 @@ static void bcm_enet_set_flow(struct bcm
 506                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 507         enet_writel(priv, val, ENET_RXCFG_REG);
 508
 509 +       if (priv->dma_no_sram)
 510 +               return;
 511 +
 512         /* tx flow control (pause frame generation) */
 513         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 514         if (tx_en)
 515 @@ -886,8 +895,8 @@ static int bcm_enet_open(struct net_devi
 516
 517         /* mask all interrupts and request them */
 518         enet_writel(priv, 0, ENET_IRMASK_REG);
 519 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
 520 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
 521 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 522 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 523
 524         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 525         if (ret)
 526 @@ -966,8 +975,12 @@ static int bcm_enet_open(struct net_devi
 527         priv->rx_curr_desc = 0;
 528
 529         /* initialize flow control buffer allocation */
 530 -       enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 531 -                       ENETDMA_BUFALLOC_REG(priv->rx_chan));
 532 +       if (!priv->dma_no_sram)
 533 +               enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 534 +                               ENETDMA_BUFALLOC_REG(priv->rx_chan));
 535 +       else
 536 +               enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 537 +                               ENETDMAC_BUFALLOC, priv->rx_chan);
 538
 539         if (bcm_enet_refill_rx(dev)) {
 540                 dev_err(kdev, "cannot allocate rx skb queue\n");
 541 @@ -976,18 +989,30 @@ static int bcm_enet_open(struct net_devi
 542         }
 543
 544         /* write rx & tx ring addresses */
 545 -       enet_dmas_writel(priv, priv->rx_desc_dma,
 546 -                        ENETDMAS_RSTART_REG(priv->rx_chan));
 547 -       enet_dmas_writel(priv, priv->tx_desc_dma,
 548 -                        ENETDMAS_RSTART_REG(priv->tx_chan));
 549 +       if (!priv->dma_no_sram) {
 550 +               enet_dmas_writel(priv, priv->rx_desc_dma,
 551 +                                ENETDMAS_RSTART_REG, priv->rx_chan);
 552 +               enet_dmas_writel(priv, priv->tx_desc_dma,
 553 +                        ENETDMAS_RSTART_REG, priv->tx_chan);
 554 +       } else {
 555 +               enet_dmac_writel(priv, priv->rx_desc_dma,
 556 +                               ENETDMAC_RSTART, priv->rx_chan);
 557 +               enet_dmac_writel(priv, priv->tx_desc_dma,
 558 +                               ENETDMAC_RSTART, priv->tx_chan);
 559 +       }
 560
 561         /* clear remaining state ram for rx & tx channel */
 562 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
 563 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
 564 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
 565 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
 566 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
 567 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
 568 +       if (!priv->dma_no_sram) {
 569 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
 570 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
 571 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
 572 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
 573 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
 574 +               enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
 575 +       } else {
 576 +               enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
 577 +               enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
 578 +       }
 579
 580         /* set max rx/tx length */
 581         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
 582 @@ -995,18 +1020,24 @@ static int bcm_enet_open(struct net_devi
 583
 584         /* set dma maximum burst len */
 585         enet_dmac_writel(priv, priv->dma_maxburst,
 586 -                        ENETDMAC_MAXBURST_REG(priv->rx_chan));
 587 +                        ENETDMAC_MAXBURST, priv->rx_chan);
 588         enet_dmac_writel(priv, priv->dma_maxburst,
 589 -                        ENETDMAC_MAXBURST_REG(priv->tx_chan));
 590 +                        ENETDMAC_MAXBURST, priv->tx_chan);
 591
 592         /* set correct transmit fifo watermark */
 593         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
 594
 595         /* set flow control low/high threshold to 1/3 / 2/3 */
 596 -       val = priv->rx_ring_size / 3;
 597 -       enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
 598 -       val = (priv->rx_ring_size * 2) / 3;
 599 -       enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
 600 +       if (!priv->dma_no_sram) {
 601 +               val = priv->rx_ring_size / 3;
 602 +               enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
 603 +               val = (priv->rx_ring_size * 2) / 3;
 604 +               enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
 605 +       } else {
 606 +               enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
 607 +               enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
 608 +               enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
 609 +       }
 610
 611         /* all set, enable mac and interrupts, start dma engine and
 612          * kick rx dma channel */
 613 @@ -1015,26 +1046,26 @@ static int bcm_enet_open(struct net_devi
 614         val |= ENET_CTL_ENABLE_MASK;
 615         enet_writel(priv, val, ENET_CTL_REG);
 616         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
 617 -       enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
 618 -                        ENETDMAC_CHANCFG_REG(priv->rx_chan));
 619 +       enet_dmac_writel(priv, priv->dma_chan_en_mask,
 620 +                        ENETDMAC_CHANCFG, priv->rx_chan);
 621
 622         /* watch "mib counters about to overflow" interrupt */
 623         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 624         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
 625
 626         /* watch "packet transferred" interrupt in rx and tx */
 627 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 628 -                        ENETDMAC_IR_REG(priv->rx_chan));
 629 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 630 -                        ENETDMAC_IR_REG(priv->tx_chan));
 631 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 632 +                        ENETDMAC_IR, priv->rx_chan);
 633 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 634 +                        ENETDMAC_IR, priv->tx_chan);
 635
 636         /* make sure we enable napi before rx interrupt  */
 637         napi_enable(&priv->napi);
 638
 639 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 640 -                        ENETDMAC_IRMASK_REG(priv->rx_chan));
 641 -       enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 642 -                        ENETDMAC_IRMASK_REG(priv->tx_chan));
 643 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 644 +                        ENETDMAC_IRMASK, priv->rx_chan);
 645 +       enet_dmac_writel(priv, priv->dma_chan_int_mask,
 646 +                        ENETDMAC_IRMASK, priv->tx_chan);
 647
 648         if (priv->has_phy)
 649                 phy_start(priv->phydev);
 650 @@ -1111,13 +1142,13 @@ static void bcm_enet_disable_dma(struct
 651  {
 652         int limit;
 653
 654 -       enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG_REG(chan));
 655 +       enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
 656
 657         limit = 1000;
 658         do {
 659                 u32 val;
 660
 661 -               val = enet_dmac_readl(priv, ENETDMAC_CHANCFG_REG(chan));
 662 +               val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
 663                 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
 664                         break;
 665                 udelay(1);
 666 @@ -1144,8 +1175,8 @@ static int bcm_enet_stop(struct net_devi
 667
 668         /* mask all interrupts */
 669         enet_writel(priv, 0, ENET_IRMASK_REG);
 670 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
 671 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
 672 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 673 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 674
 675         /* make sure no mib update is scheduled */
 676         cancel_work_sync(&priv->mib_update_task);
 677 @@ -1752,6 +1783,11 @@ static int bcm_enet_probe(struct platfor
 678                 priv->pause_tx = pd->pause_tx;
 679                 priv->force_duplex_full = pd->force_duplex_full;
 680                 priv->force_speed_100 = pd->force_speed_100;
 681 +               priv->dma_chan_en_mask = pd->dma_chan_en_mask;
 682 +               priv->dma_chan_int_mask = pd->dma_chan_int_mask;
 683 +               priv->dma_chan_width = pd->dma_chan_width;
 684 +               priv->dma_no_sram = pd->dma_no_sram;
 685 +               priv->dma_desc_shift = pd->dma_desc_shift;
 686         }
 687
 688         if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
 689 @@ -2123,8 +2159,8 @@ static int bcm_enetsw_open(struct net_de
 690         kdev = &priv->pdev->dev;
 691
 692         /* mask all interrupts and request them */
 693 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
 694 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
 695 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 696 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 697
 698         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
 699                           IRQF_DISABLED, dev->name, dev);
 700 @@ -2248,23 +2284,23 @@ static int bcm_enetsw_open(struct net_de
 701
 702         /* write rx & tx ring addresses */
 703         enet_dmas_writel(priv, priv->rx_desc_dma,
 704 -                        ENETDMAS_RSTART_REG(priv->rx_chan));
 705 +                        ENETDMAS_RSTART_REG, priv->rx_chan);
 706         enet_dmas_writel(priv, priv->tx_desc_dma,
 707 -                        ENETDMAS_RSTART_REG(priv->tx_chan));
 708 +                        ENETDMAS_RSTART_REG, priv->tx_chan);
 709
 710         /* clear remaining state ram for rx & tx channel */
 711 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
 712 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
 713 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
 714 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
 715 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
 716 -       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
 717 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
 718 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
 719 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
 720 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
 721 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
 722 +       enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
 723
 724         /* set dma maximum burst len */
 725         enet_dmac_writel(priv, priv->dma_maxburst,
 726 -                        ENETDMAC_MAXBURST_REG(priv->rx_chan));
 727 +                        ENETDMAC_MAXBURST, priv->rx_chan);
 728         enet_dmac_writel(priv, priv->dma_maxburst,
 729 -                        ENETDMAC_MAXBURST_REG(priv->tx_chan));
 730 +                        ENETDMAC_MAXBURST, priv->tx_chan);
 731
 732         /* set flow control low/high threshold to 1/3 / 2/3 */
 733         val = priv->rx_ring_size / 3;
 734 @@ -2277,21 +2313,21 @@ static int bcm_enetsw_open(struct net_de
 735         wmb();
 736         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
 737         enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
 738 -                        ENETDMAC_CHANCFG_REG(priv->rx_chan));
 739 +                        ENETDMAC_CHANCFG, priv->rx_chan);
 740
 741         /* watch "packet transferred" interrupt in rx and tx */
 742         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 743 -                        ENETDMAC_IR_REG(priv->rx_chan));
 744 +                        ENETDMAC_IR, priv->rx_chan);
 745         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 746 -                        ENETDMAC_IR_REG(priv->tx_chan));
 747 +                        ENETDMAC_IR, priv->tx_chan);
 748
 749         /* make sure we enable napi before rx interrupt  */
 750         napi_enable(&priv->napi);
 751
 752         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 753 -                        ENETDMAC_IRMASK_REG(priv->rx_chan));
 754 +                        ENETDMAC_IRMASK, priv->rx_chan);
 755         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
 756 -                        ENETDMAC_IRMASK_REG(priv->tx_chan));
 757 +                        ENETDMAC_IRMASK, priv->tx_chan);
 758
 759         netif_carrier_on(dev);
 760         netif_start_queue(dev);
 761 @@ -2397,8 +2433,8 @@ static int bcm_enetsw_stop(struct net_de
 762         del_timer_sync(&priv->rx_timeout);
 763
 764         /* mask all interrupts */
 765 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
 766 -       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
 767 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 768 +       enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 769
 770         /* disable dma & mac */
 771         bcm_enet_disable_dma(priv, priv->tx_chan);
 772 @@ -2736,6 +2772,9 @@ static int bcm_enetsw_probe(struct platf
 773                 memcpy(priv->used_ports, pd->used_ports,
 774                        sizeof (pd->used_ports));
 775                 priv->num_ports = pd->num_ports;
 776 +               priv->dma_chan_en_mask = pd->dma_chan_en_mask;
 777 +               priv->dma_chan_int_mask = pd->dma_chan_int_mask;
 778 +               priv->dma_chan_width = pd->dma_chan_width;
 779         }
 780
 781         ret = compute_hw_mtu(priv, dev->mtu);
 782 --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
 783 +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
 784 @@ -339,6 +339,21 @@ struct bcm_enet_priv {
 785         /* used to poll switch port state */
 786         struct timer_list swphy_poll;
 787         spinlock_t enetsw_mdio_lock;
 788 +
 789 +       /* dma channel enable mask */
 790 +       u32 dma_chan_en_mask;
 791 +
 792 +       /* dma channel interrupt mask */
 793 +       u32 dma_chan_int_mask;
 794 +
 795 +       /* dma engine has *no* internal SRAM */
 796 +       unsigned int dma_no_sram;
 797 +
 798 +       /* dma channel width */
 799 +       unsigned int dma_chan_width;
 800 +
 801 +       /* dma descriptor shift value */
 802 +       unsigned int dma_desc_shift;
 803  };
 804
 805  static inline int bcm_enet_port_is_rgmii(int portid)