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[ramips] unbreak port mapping detection
[openwrt/svn-archive/archive.git] / target / linux / cns21xx / patches-3.3 / 100-cns21xx-core.patch
1 --- a/arch/arm/Kconfig
2 +++ b/arch/arm/Kconfig
3 @@ -190,6 +190,11 @@ config FIQ
4 config ARCH_MTD_XIP
5 bool
6
7 +config ARM_L1_CACHE_SHIFT_4
8 + bool
9 + help
10 + Setting ARM L1 cache line size to 16 bytes.
11 +
12 config VECTORS_BASE
13 hex
14 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
15 @@ -355,6 +360,15 @@ config ARCH_HIGHBANK
16 help
17 Support for the Calxeda Highbank SoC based boards.
18
19 +config ARCH_CNS21XX
20 + bool "Cavium Networks CNS21xx family"
21 + select CPU_FA526
22 + select PLAT_FA
23 + select PLAT_FA_TIME
24 + select ARM_L1_CACHE_SHIFT_4
25 + help
26 + Support for Cavium Networks CNS21xx family.
27 +
28 config ARCH_CLPS711X
29 bool "Cirrus Logic CLPS711x/EP721x-based"
30 select CPU_ARM720T
31 @@ -1003,6 +1017,8 @@ source "arch/arm/mach-davinci/Kconfig"
32
33 source "arch/arm/mach-dove/Kconfig"
34
35 +source "arch/arm/mach-cns21xx/Kconfig"
36 +
37 source "arch/arm/mach-ep93xx/Kconfig"
38
39 source "arch/arm/mach-footbridge/Kconfig"
40 --- /dev/null
41 +++ b/arch/arm/mach-cns21xx/Kconfig
42 @@ -0,0 +1,6 @@
43 +if ARCH_CNS21XX
44 +
45 +menu "Cavium Networks CNS21xx based machines"
46 +endmenu
47 +
48 +endif
49 --- /dev/null
50 +++ b/arch/arm/mach-cns21xx/Makefile
51 @@ -0,0 +1,10 @@
52 +#
53 +# Makefile for the linux kernel.
54 +#
55 +
56 +# Object file lists.
57 +
58 +obj-y := core.o irq.o mm.o time.o
59 +
60 +# machine specific files
61 +
62 --- /dev/null
63 +++ b/arch/arm/mach-cns21xx/Makefile.boot
64 @@ -0,0 +1,3 @@
65 + zreladdr-y += 0x00008000
66 +params_phys-y := 0x00000100
67 +initrd_phys-y := 0x00C00000
68 --- a/arch/arm/Makefile
69 +++ b/arch/arm/Makefile
70 @@ -136,6 +136,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x0020
71 # by CONFIG_* macro name.
72 machine-$(CONFIG_ARCH_AT91) := at91
73 machine-$(CONFIG_ARCH_BCMRING) := bcmring
74 +machine-$(CONFIG_ARCH_CNS21XX) := cns21xx
75 machine-$(CONFIG_ARCH_CLPS711X) := clps711x
76 machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx
77 machine-$(CONFIG_ARCH_DAVINCI) := davinci
78 --- /dev/null
79 +++ b/arch/arm/mach-cns21xx/common.h
80 @@ -0,0 +1,19 @@
81 +/*
82 + * Copyright (c) 2008 Cavium Networks
83 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
84 + *
85 + * This file is free software; you can redistribute it and/or modify
86 + * it under the terms of the GNU General Public License, Version 2, as
87 + * published by the Free Software Foundation.
88 + */
89 +
90 +#ifndef _MACH_CNS21XX_COMMON_H
91 +#define _MACH_CNS21XX_COMMON_H
92 +
93 +void cns21xx_restart(char mode, const char *cmd);
94 +void cns21xx_map_io(void);
95 +void cns21xx_init_irq(void);
96 +
97 +extern struct sys_timer cns21xx_timer;
98 +
99 +#endif /* _MACH_CNS21XX_COMMON_H */
100 --- /dev/null
101 +++ b/arch/arm/mach-cns21xx/mm.c
102 @@ -0,0 +1,170 @@
103 +/*
104 + * Copyright (c) 2008 Cavium Networks
105 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
106 + *
107 + * This file is free software; you can redistribute it and/or modify
108 + * it under the terms of the GNU General Public License, Version 2, as
109 + * published by the Free Software Foundation.
110 + */
111 +
112 +#include <linux/mm.h>
113 +#include <linux/init.h>
114 +
115 +#include <asm/mach/map.h>
116 +
117 +#include <mach/hardware.h>
118 +#include <mach/cns21xx.h>
119 +
120 +#include "common.h"
121 +
122 +/*
123 + * Standard IO mapping
124 + */
125 +static struct map_desc cns21xx_io_desc[] __initdata = {
126 + {
127 + .virtual = CNS21XX_FLASH_BANK0_BASE_VIRT,
128 + .pfn = __phys_to_pfn(CNS21XX_FLASH_BANK0_BASE),
129 + .length = SZ_256M,
130 + .type = MT_DEVICE
131 + }, {
132 + .virtual = CNS21XX_IDE_DEVICE_BASE_VIRT,
133 + .pfn = __phys_to_pfn(CNS21XX_IDE_DEVICE_BASE),
134 + .length = SZ_4K,
135 + .type = MT_DEVICE
136 + }, {
137 + .virtual = CNS21XX_GDMAC_BASE_VIRT,
138 + .pfn = __phys_to_pfn(CNS21XX_GDMAC_BASE),
139 + .length = SZ_4K,
140 + .type = MT_DEVICE
141 + }, {
142 + .virtual = CNS21XX_NIC_BASE_VIRT,
143 + .pfn = __phys_to_pfn(CNS21XX_NIC_BASE),
144 + .length = SZ_4K,
145 + .type = MT_DEVICE
146 + }, {
147 + .virtual = CNS21XX_SPI_BASE_VIRT,
148 + .pfn = __phys_to_pfn(CNS21XX_SPI_BASE),
149 + .length = SZ_4K,
150 + .type = MT_DEVICE
151 + }, {
152 + .virtual = CNS21XX_PCM_BASE_VIRT,
153 + .pfn = __phys_to_pfn(CNS21XX_PCM_BASE),
154 + .length = SZ_4K,
155 + .type = MT_DEVICE
156 + }, {
157 + .virtual = CNS21XX_I2C_BASE_VIRT,
158 + .pfn = __phys_to_pfn(CNS21XX_I2C_BASE),
159 + .length = SZ_4K,
160 + .type = MT_DEVICE
161 + }, {
162 + .virtual = CNS21XX_I2S_BASE_VIRT,
163 + .pfn = __phys_to_pfn(CNS21XX_I2S_BASE),
164 + .length = SZ_4K,
165 + .type = MT_DEVICE
166 + }, {
167 + .virtual = CNS21XX_DDRC_BASE_VIRT,
168 + .pfn = __phys_to_pfn(CNS21XX_DDRC_BASE),
169 + .length = SZ_4K,
170 + .type = MT_DEVICE
171 + }, {
172 + .virtual = CNS21XX_SMC_BASE_VIRT,
173 + .pfn = __phys_to_pfn(CNS21XX_SMC_BASE),
174 + .length = SZ_4K,
175 + .type = MT_DEVICE
176 + }, {
177 + .virtual = CNS21XX_IDE_CTRL_BASE_VIRT,
178 + .pfn = __phys_to_pfn(CNS21XX_IDE_CTRL_BASE),
179 + .length = SZ_4K,
180 + .type = MT_DEVICE
181 + }, {
182 + .virtual = CNS21XX_MISC_BASE_VIRT,
183 + .pfn = __phys_to_pfn(CNS21XX_MISC_BASE),
184 + .length = SZ_4K,
185 + .type = MT_DEVICE
186 + }, {
187 + .virtual = CNS21XX_CPM_BASE_VIRT,
188 + .pfn = __phys_to_pfn(CNS21XX_CPM_BASE),
189 + .length = SZ_4K,
190 + .type = MT_DEVICE
191 + }, {
192 + .virtual = CNS21XX_UART0_BASE_VIRT,
193 + .pfn = __phys_to_pfn(CNS21XX_UART0_BASE),
194 + .length = SZ_4K,
195 + .type = MT_DEVICE
196 + }, {
197 + .virtual = CNS21XX_UART1_BASE_VIRT,
198 + .pfn = __phys_to_pfn(CNS21XX_UART1_BASE),
199 + .length = SZ_4K,
200 + .type = MT_DEVICE
201 + }, {
202 + .virtual = CNS21XX_TIMER_BASE_VIRT,
203 + .pfn = __phys_to_pfn(CNS21XX_TIMER_BASE),
204 + .length = SZ_4K,
205 + .type = MT_DEVICE
206 + }, {
207 + .virtual = CNS21XX_WDT_BASE_VIRT,
208 + .pfn = __phys_to_pfn(CNS21XX_WDT_BASE),
209 + .length = SZ_4K,
210 + .type = MT_DEVICE
211 + }, {
212 + .virtual = CNS21XX_RTC_BASE_VIRT,
213 + .pfn = __phys_to_pfn(CNS21XX_RTC_BASE),
214 + .length = SZ_4K,
215 + .type = MT_DEVICE
216 + }, {
217 + .virtual = CNS21XX_GPIOA_BASE_VIRT,
218 + .pfn = __phys_to_pfn(CNS21XX_GPIOA_BASE),
219 + .length = SZ_4K,
220 + .type = MT_DEVICE
221 + }, {
222 + .virtual = CNS21XX_GPIOB_BASE_VIRT,
223 + .pfn = __phys_to_pfn(CNS21XX_GPIOB_BASE),
224 + .length = SZ_4K,
225 + .type = MT_DEVICE
226 + }, {
227 + .virtual = CNS21XX_PCI_CFGDATA_BASE_VIRT,
228 + .pfn = __phys_to_pfn(CNS21XX_PCI_CFGDATA_BASE),
229 + .length = SZ_4K,
230 + .type = MT_DEVICE
231 + }, {
232 + .virtual = CNS21XX_PCI_CFGADDR_BASE_VIRT,
233 + .pfn = __phys_to_pfn(CNS21XX_PCI_CFGADDR_BASE),
234 + .length = SZ_4K,
235 + .type = MT_DEVICE
236 + }, {
237 + .virtual = CNS21XX_OHCI_CONFIG_BASE_VIRT,
238 + .pfn = __phys_to_pfn(CNS21XX_OHCI_CONFIG_BASE),
239 + .length = SZ_4K,
240 + .type = MT_DEVICE
241 + }, {
242 + .virtual = CNS21XX_OHCI_CTRL_BASE_VIRT,
243 + .pfn = __phys_to_pfn(CNS21XX_OHCI_CTRL_BASE),
244 + .length = SZ_4K,
245 + .type = MT_DEVICE
246 + }, {
247 + .virtual = CNS21XX_EHCI_CONFIG_BASE_VIRT,
248 + .pfn = __phys_to_pfn(CNS21XX_EHCI_CONFIG_BASE),
249 + .length = SZ_4K,
250 + .type = MT_DEVICE
251 + }, {
252 + .virtual = CNS21XX_EHCI_CTRL_BASE_VIRT,
253 + .pfn = __phys_to_pfn(CNS21XX_EHCI_CTRL_BASE),
254 + .length = SZ_4K,
255 + .type = MT_DEVICE
256 + }, {
257 + .virtual = CNS21XX_USB_DEVICE_BASE_VIRT,
258 + .pfn = __phys_to_pfn(CNS21XX_USB_DEVICE_BASE),
259 + .length = SZ_4K,
260 + .type = MT_DEVICE
261 + }, {
262 + .virtual = CNS21XX_INTC_BASE_VIRT,
263 + .pfn = __phys_to_pfn(CNS21XX_INTC_BASE),
264 + .length = SZ_4K,
265 + .type = MT_DEVICE
266 + }
267 +};
268 +
269 +void __init cns21xx_map_io(void)
270 +{
271 + iotable_init(cns21xx_io_desc, ARRAY_SIZE(cns21xx_io_desc));
272 +}
273 --- /dev/null
274 +++ b/arch/arm/mach-cns21xx/include/mach/hardware.h
275 @@ -0,0 +1,20 @@
276 +/*
277 + * Copyright (c) 2008 Cavium Networks
278 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
279 + *
280 + * This file is free software; you can redistribute it and/or modify
281 + * it under the terms of the GNU General Public License, Version 2, as
282 + * published by the Free Software Foundation.
283 + */
284 +
285 +#ifndef _CNS21XX_HARDWARE_H
286 +#define _CNS21XX_HARDWARE_H
287 +
288 +#ifndef __ASSEMBLY__
289 +extern unsigned long cns21xx_get_pll_freq(void);
290 +extern unsigned long cns21xx_get_cpu_freq(void);
291 +extern unsigned long cns21xx_get_ahb_freq(void);
292 +extern unsigned long cns21xx_get_apb_freq(void);
293 +#endif
294 +
295 +#endif /* _CNS21XX_HARDWARE_H */
296 --- /dev/null
297 +++ b/arch/arm/mach-cns21xx/include/mach/debug-macro.S
298 @@ -0,0 +1,25 @@
299 +/*
300 + * Copyright (c) 2008 Cavium Networks
301 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
302 + *
303 + * This file is free software; you can redistribute it and/or modify
304 + * it under the terms of the GNU General Public License, Version 2, as
305 + * published by the Free Software Foundation.
306 + */
307 +
308 +#include <mach/cns21xx.h>
309 +
310 +/* TODO: make it configurable */
311 +#define CNS21XX_DEBUG_UART_BASE CNS21XX_UART0_BASE
312 +#define CNS21XX_DEBUG_UART_BASE_VIRT CNS21XX_UART0_BASE_VIRT
313 +
314 + .macro addruart, rp, rv
315 + mov \rp, #(CNS21XX_DEBUG_UART_BASE) @ physical
316 + mov \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0xff000000) @virtual
317 + orr \rv, \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0x00ff0000)
318 + orr \rv, \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0x0000ff00)
319 + orr \rv, \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0x000000ff)
320 + .endm
321 +
322 +#define UART_SHIFT 2
323 +#include <asm/hardware/debug-8250.S>
324 --- /dev/null
325 +++ b/arch/arm/mach-cns21xx/include/mach/entry-macro.S
326 @@ -0,0 +1,39 @@
327 +/*
328 + * Copyright (c) 2008 Cavium Networks
329 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
330 + *
331 + * This file is free software; you can redistribute it and/or modify
332 + * it under the terms of the GNU General Public License, Version 2, as
333 + * published by the Free Software Foundation.
334 + */
335 +
336 +#include <mach/cns21xx.h>
337 +#include <mach/irqs.h>
338 +
339 +#define INTC_IRQ_STATUS 0x1c
340 +
341 + .macro disable_fiq
342 + .endm
343 +
344 + .macro get_irqnr_preamble, base, tmp
345 + .endm
346 +
347 + .macro arch_ret_to_user, tmp1, tmp2
348 + .endm
349 +
350 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
351 + ldr \base, =(CNS21XX_INTC_BASE_VIRT + INTC_IRQ_STATUS)
352 + ldr \irqstat, [\base]
353 + mov \irqnr, #0
354 +9001:
355 + tst \irqstat, #1
356 + bne 9002f
357 + add \irqnr, \irqnr, #1
358 + mov \irqstat, \irqstat, lsr #1
359 + cmp \irqnr, #CNS21XX_NR_INTC_IRQS
360 + bcc 9001b
361 +9002:
362 + .endm
363 +
364 + .macro irq_prio_table
365 + .endm
366 --- /dev/null
367 +++ b/arch/arm/mach-cns21xx/include/mach/io.h
368 @@ -0,0 +1,18 @@
369 +/*
370 + * Copyright (c) 2008 Cavium Networks
371 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
372 + *
373 + * This file is free software; you can redistribute it and/or modify
374 + * it under the terms of the GNU General Public License, Version 2, as
375 + * published by the Free Software Foundation.
376 + */
377 +
378 +#ifndef _CNS21XX_IO_H
379 +#define _CNS21XX_IO_H
380 +
381 +#define IO_SPACE_LIMIT 0xffffffff
382 +
383 +#define __io(p) __typesafe_io(p)
384 +#define __mem_pci(a) (a)
385 +
386 +#endif /* _CNS21XX_IO_H */
387 --- /dev/null
388 +++ b/arch/arm/mach-cns21xx/include/mach/irqs.h
389 @@ -0,0 +1,53 @@
390 +/*
391 + * Copyright (c) 2008 Cavium Networks
392 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
393 + *
394 + * This file is free software; you can redistribute it and/or modify
395 + * it under the terms of the GNU General Public License, Version 2, as
396 + * published by the Free Software Foundation.
397 + */
398 +
399 +#ifndef _CNS21XX_IRQS_H
400 +#define _CNS21XX_IRQS_H
401 +
402 +#define CNS21XX_IRQ_TIMER1 0
403 +#define CNS21XX_IRQ_TIMER2 1
404 +#define CNS21XX_IRQ_CPM 2
405 +#define CNS21XX_IRQ_WDT 3
406 +#define CNS21XX_IRQ_GPIO 4
407 +#define CNS21XX_IRQ_PCI_INTA 5
408 +#define CNS21XX_IRQ_PCI_INTB 6
409 +#define CNS21XX_IRQ_PCI_BROKEN 7
410 +#define CNS21XX_IRQ_AHB2PCI 8
411 +#define CNS21XX_IRQ_UART0 9
412 +#define CNS21XX_IRQ_UART1 10
413 +#define CNS21XX_IRQ_GDMAC_TC 11
414 +#define CNS21XX_IRQ_GDMAC_ERR 12
415 +#define CNS21XX_IRQ_PCMCIA 13
416 +#define CNS21XX_IRQ_RTC 14
417 +#define CNS21XX_IRQ_PCM 15
418 +#define CNS21XX_IRQ_USB_DEVICE 16
419 +#define CNS21XX_IRQ_IDE 17
420 +#define CNS21XX_IRQ_NIC_STATUS 18
421 +#define CNS21XX_IRQ_NIC_TXTC 19
422 +#define CNS21XX_IRQ_NIC_RXRC 20
423 +#define CNS21XX_IRQ_NIC_TXQE 21
424 +#define CNS21XX_IRQ_NIC_RXQF 22
425 +#define CNS21XX_IRQ_OHCI 23
426 +#define CNS21XX_IRQ_EHCI 24
427 +#define CNS21XX_IRQ_I2S 25
428 +#define CNS21XX_IRQ_SPI 26
429 +#define CNS21XX_IRQ_I2C 27
430 +#define CNS21XX_IRQ_USB_VBUS 28
431 +#define CNS21XX_IRQ_EXT_29 29
432 +#define CNS21XX_IRQ_EXT_30 30
433 +#define CNS21XX_IRQ_HSDMAC 31
434 +
435 +#define CNS21XX_GPIO_IRQ_BASE 32
436 +
437 +#define CNS21XX_NR_INTC_IRQS 32
438 +#define CNS21XX_NR_GPIO_IRQS 64
439 +
440 +#define NR_IRQS 96
441 +
442 +#endif /* _CNS21XX_IRQS_H */
443 --- /dev/null
444 +++ b/arch/arm/mach-cns21xx/include/mach/timex.h
445 @@ -0,0 +1,15 @@
446 +/*
447 + * Copyright (c) 2008 Cavium Networks
448 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
449 + *
450 + * This file is free software; you can redistribute it and/or modify
451 + * it under the terms of the GNU General Public License, Version 2, as
452 + * published by the Free Software Foundation.
453 + */
454 +
455 +#ifndef _CNS21XX_TIMEX_H
456 +#define _CNS21XX_TIMEX_H
457 +
458 +#define CLOCK_TICK_RATE 43750000
459 +
460 +#endif /* _CNS21XX_TIMEX_H */
461 --- /dev/null
462 +++ b/arch/arm/mach-cns21xx/include/mach/uncompress.h
463 @@ -0,0 +1,40 @@
464 +/*
465 + * Copyright (c) 2008 Cavium Networks
466 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
467 + *
468 + * This file is free software; you can redistribute it and/or modify
469 + * it under the terms of the GNU General Public License, Version 2, as
470 + * published by the Free Software Foundation.
471 + */
472 +
473 +#ifndef _CNS21XX_UNCOMPRESS_H
474 +#define _CNS21XX_UNCOMPRESS_H
475 +
476 +#define UART_BASE 0x78000000
477 +
478 +#define UART_REG(offs) (*((volatile unsigned int *)(UART_BASE + offs)))
479 +
480 +#define UART_THR UART_REG(0x00)
481 +#define UART_LSR UART_REG(0x14)
482 +#define THR_EMPTY (1 << 5)
483 +
484 +#define UART_THR_EMPTY() (((UART_LSR) & THR_EMPTY) == (THR_EMPTY))
485 +
486 +static void putc(int c)
487 +{
488 + if (c != 0) {
489 + while (!UART_THR_EMPTY())
490 + barrier();
491 +
492 + UART_THR = (int)(c & 0xFF);
493 + }
494 +}
495 +
496 +static inline void flush(void)
497 +{
498 +}
499 +
500 +#define arch_decomp_setup()
501 +#define arch_decomp_wdog()
502 +
503 +#endif /* _CNS21XX_UNCOMPRESS_H */
504 --- /dev/null
505 +++ b/arch/arm/mach-cns21xx/include/mach/system.h
506 @@ -0,0 +1,30 @@
507 +/*
508 + * Copyright (c) 2008 Cavium Networks
509 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
510 + *
511 + * This file is free software; you can redistribute it and/or modify
512 + * it under the terms of the GNU General Public License, Version 2, as
513 + * published by the Free Software Foundation.
514 + */
515 +
516 +#ifndef _CNS21XX_SYSTEM_H
517 +#define _CNS21XX_SYSTEM_H
518 +
519 +#include <mach/cns21xx.h>
520 +#include <mach/cns21xx_powermgmt.h>
521 +
522 +static inline void arch_idle(void)
523 +{
524 + /*
525 + * Because of broken hardware we have to enable interrupts or the CPU
526 + * will never wakeup... Acctualy it is not very good to enable
527 + * interrupts here since scheduler can miss a tick, but there is
528 + * no other way around this. Platforms that needs it for power saving
529 + * should call enable_hlt() in init code, since by default it is
530 + * disabled.
531 + */
532 + local_irq_enable();
533 + cpu_do_idle();
534 +}
535 +
536 +#endif /* _CNS21XX_SYSTEM_H */
537 --- /dev/null
538 +++ b/arch/arm/mach-cns21xx/irq.c
539 @@ -0,0 +1,174 @@
540 +/*
541 + * Copyright (c) 2008 Cavium Networks
542 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
543 + *
544 + * This file is free software; you can redistribute it and/or modify
545 + * it under the terms of the GNU General Public License, Version 2, as
546 + * published by the Free Software Foundation.
547 + */
548 +
549 +#include <linux/init.h>
550 +#include <linux/interrupt.h>
551 +#include <linux/irq.h>
552 +#include <linux/io.h>
553 +#include <linux/ioport.h>
554 +
555 +#include <mach/cns21xx.h>
556 +
557 +#define INTC_INTERRUPT_RAW_STATUS_REG 0x000
558 +#define INTC_EDGE_INTERRUPT_SOURCE_CLEAR_REG 0x004
559 +#define INTC_INTERRUPT_MASK_REG 0x008
560 +#define INTC_INTERRUPT_MASK_CLEAR_REG 0x00c
561 +#define INTC_INTERRUPT_TRIGGER_MODE_REG 0x010
562 +#define INTC_INTERRUPT_TRIGGER_LEVEL_REG 0x014
563 +#define INTC_FIQ_SELECT_REG 0x018
564 +#define INTC_IRQ_STATUS_REG 0x01c
565 +#define INTC_FIQ_STATUS_REG 0x020
566 +#define INTC_SOFTWARE_INTERRUPT_REG 0x024
567 +#define INTC_SOFTWARE_INTERRUPT_CLEAR_REG 0x028
568 +#define INTC_SOFTWARE_PRIORITY_MASK_REG 0x02c
569 +#define INTC_POWER_MANAGEMENT_INTERRUPT_REG 0x034
570 +
571 +#define INTC_VECTOR_ADDRESS_REG(_x) ((_x) + 0x040)
572 +#define INTC_PRIORITY_REG(_x) ((_x) + 0x0c0)
573 +#define INTC_IRQ_VECTOR_ADDRESS_REG 0x140
574 +#define INTC_VECTOR_INTERRUPT_ENABLE_REG 0x144
575 +
576 +#define INTC_SIZE 0x148
577 +
578 +static unsigned int cns21xx_irq_types[CNS21XX_NR_INTC_IRQS] = {
579 + [CNS21XX_IRQ_TIMER1] = IRQ_TYPE_EDGE_RISING,
580 + [CNS21XX_IRQ_TIMER2] = IRQ_TYPE_EDGE_RISING,
581 + [CNS21XX_IRQ_CPM] = IRQ_TYPE_EDGE_FALLING,
582 + [CNS21XX_IRQ_WDT] = IRQ_TYPE_EDGE_RISING,
583 + [CNS21XX_IRQ_GPIO] = IRQ_TYPE_NONE,
584 + [CNS21XX_IRQ_PCI_INTA] = IRQ_TYPE_LEVEL_LOW,
585 + [CNS21XX_IRQ_PCI_INTB] = IRQ_TYPE_LEVEL_LOW,
586 + [CNS21XX_IRQ_PCI_BROKEN] = IRQ_TYPE_LEVEL_HIGH,
587 + [CNS21XX_IRQ_AHB2PCI] = IRQ_TYPE_LEVEL_HIGH,
588 + [CNS21XX_IRQ_UART0] = IRQ_TYPE_LEVEL_HIGH,
589 + [CNS21XX_IRQ_UART1] = IRQ_TYPE_LEVEL_HIGH,
590 + [CNS21XX_IRQ_GDMAC_TC] = IRQ_TYPE_LEVEL_HIGH,
591 + [CNS21XX_IRQ_GDMAC_ERR] = IRQ_TYPE_LEVEL_HIGH,
592 + [CNS21XX_IRQ_PCMCIA] = IRQ_TYPE_NONE,
593 + [CNS21XX_IRQ_RTC] = IRQ_TYPE_LEVEL_HIGH,
594 + [CNS21XX_IRQ_PCM] = IRQ_TYPE_LEVEL_LOW,
595 + [CNS21XX_IRQ_USB_DEVICE] = IRQ_TYPE_LEVEL_LOW,
596 + [CNS21XX_IRQ_IDE] = IRQ_TYPE_LEVEL_HIGH,
597 + [CNS21XX_IRQ_NIC_STATUS] = IRQ_TYPE_LEVEL_HIGH,
598 + [CNS21XX_IRQ_NIC_TXTC] = IRQ_TYPE_EDGE_RISING,
599 + [CNS21XX_IRQ_NIC_RXRC] = IRQ_TYPE_EDGE_RISING,
600 + [CNS21XX_IRQ_NIC_TXQE] = IRQ_TYPE_EDGE_RISING,
601 + [CNS21XX_IRQ_NIC_RXQF] = IRQ_TYPE_EDGE_RISING,
602 + [CNS21XX_IRQ_OHCI] = IRQ_TYPE_LEVEL_LOW,
603 + [CNS21XX_IRQ_EHCI] = IRQ_TYPE_LEVEL_LOW,
604 + [CNS21XX_IRQ_I2S] = IRQ_TYPE_LEVEL_LOW,
605 + [CNS21XX_IRQ_SPI] = IRQ_TYPE_LEVEL_LOW,
606 + [CNS21XX_IRQ_I2C] = IRQ_TYPE_LEVEL_LOW,
607 + [CNS21XX_IRQ_USB_VBUS] = IRQ_TYPE_EDGE_RISING,
608 + [CNS21XX_IRQ_EXT_29] = IRQ_TYPE_NONE,
609 + [CNS21XX_IRQ_EXT_30] = IRQ_TYPE_NONE,
610 + [CNS21XX_IRQ_HSDMAC] = IRQ_TYPE_EDGE_RISING,
611 +};
612 +
613 +static void __iomem *cns21xx_intc_base;
614 +
615 +static inline void cns21xx_intc_writel(u32 val, unsigned int reg)
616 +{
617 + __raw_writel(val, cns21xx_intc_base + reg);
618 +}
619 +
620 +static inline u32 cns21xx_intc_readl(unsigned int reg)
621 +{
622 + return __raw_readl(cns21xx_intc_base + reg);
623 +}
624 +
625 +static void cns21xx_irq_ack(struct irq_data *d)
626 +{
627 + cns21xx_intc_writel(1 << d->irq, INTC_EDGE_INTERRUPT_SOURCE_CLEAR_REG);
628 +}
629 +
630 +static void cns21xx_irq_mask(struct irq_data *d)
631 +{
632 + cns21xx_intc_writel(1 << d->irq, INTC_INTERRUPT_MASK_REG);
633 +}
634 +
635 +static void cns21xx_irq_unmask(struct irq_data *d)
636 +{
637 + cns21xx_intc_writel(1 << d->irq, INTC_INTERRUPT_MASK_CLEAR_REG);
638 +}
639 +
640 +static struct irq_chip cns21xx_irq_chip = {
641 + .name = "INTC",
642 + .irq_ack = cns21xx_irq_ack,
643 + .irq_mask = cns21xx_irq_mask,
644 + .irq_unmask = cns21xx_irq_unmask,
645 +};
646 +
647 +static struct resource cns21xx_intc_resource = {
648 + .name = "INTC",
649 + .flags = IORESOURCE_MEM,
650 + .start = CNS21XX_INTC_BASE,
651 + .end = CNS21XX_INTC_BASE + INTC_SIZE - 1,
652 +};
653 +
654 +void __init cns21xx_init_irq(void)
655 +{
656 + unsigned int mode = 0;
657 + unsigned int level = 0;
658 + int i;
659 +
660 + /*
661 + * Disable arch_idle() by default since it is buggy
662 + * For more info see arch/arm/mach-cns21xx/include/mach/system.h
663 + */
664 + disable_hlt();
665 +
666 + request_resource(&iomem_resource, &cns21xx_intc_resource);
667 + cns21xx_intc_base = ioremap(cns21xx_intc_resource.start, INTC_SIZE);
668 +
669 + cns21xx_intc_writel(0xffffffff, INTC_INTERRUPT_MASK_REG);
670 + cns21xx_intc_writel(0xffffffff, INTC_EDGE_INTERRUPT_SOURCE_CLEAR_REG);
671 + cns21xx_intc_writel(0xffffffff, INTC_SOFTWARE_INTERRUPT_CLEAR_REG);
672 + cns21xx_intc_writel(0, INTC_SOFTWARE_PRIORITY_MASK_REG);
673 + cns21xx_intc_writel(0, INTC_FIQ_SELECT_REG);
674 + cns21xx_intc_writel(0, INTC_VECTOR_INTERRUPT_ENABLE_REG);
675 +
676 + for (i = 0; i < ARRAY_SIZE(cns21xx_irq_types); i++) {
677 + irq_flow_handler_t handler;
678 +
679 + switch (cns21xx_irq_types[i]) {
680 + case IRQ_TYPE_EDGE_RISING:
681 + handler = handle_edge_irq;
682 + mode |= (1 << i);
683 + break;
684 +
685 + case IRQ_TYPE_EDGE_FALLING:
686 + handler = handle_edge_irq;
687 + mode |= (1 << i);
688 + level |= (1 << i);
689 + break;
690 +
691 + case IRQ_TYPE_LEVEL_LOW:
692 + handler = handle_level_irq;
693 + level |= (1 << i);
694 + break;
695 +
696 + case IRQ_TYPE_LEVEL_HIGH:
697 + case IRQ_TYPE_NONE:
698 + handler = handle_level_irq;
699 + break;
700 +
701 + default:
702 + BUG();
703 + break;
704 + }
705 +
706 + irq_set_chip(i, &cns21xx_irq_chip);
707 + irq_set_handler(i, handler);
708 + set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
709 + }
710 +
711 + cns21xx_intc_writel(mode, INTC_INTERRUPT_TRIGGER_MODE_REG);
712 + cns21xx_intc_writel(level, INTC_INTERRUPT_TRIGGER_LEVEL_REG);
713 +}
714 --- /dev/null
715 +++ b/arch/arm/mach-cns21xx/time.c
716 @@ -0,0 +1,28 @@
717 +/*
718 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
719 + *
720 + * This file is free software; you can redistribute it and/or modify
721 + * it under the terms of the GNU General Public License, Version 2, as
722 + * published by the Free Software Foundation.
723 + */
724 +
725 +#include <linux/init.h>
726 +#include <linux/irq.h>
727 +
728 +#include <asm/mach/time.h>
729 +
730 +#include <plat/time.h>
731 +#include <mach/hardware.h>
732 +#include <mach/cns21xx.h>
733 +
734 +#include "common.h"
735 +
736 +static void __init cns21xx_timer_init(void)
737 +{
738 + fa_timer_init(CNS21XX_TIMER_BASE, CNS21XX_IRQ_TIMER1, FA_TIMER1,
739 + cns21xx_get_apb_freq());
740 +}
741 +
742 +struct sys_timer cns21xx_timer = {
743 + .init = cns21xx_timer_init,
744 +};
745 --- /dev/null
746 +++ b/arch/arm/mach-cns21xx/include/mach/cns21xx_powermgmt.h
747 @@ -0,0 +1,591 @@
748 +/*
749 + * Copyright (c) 2008 Cavium Networks
750 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
751 + *
752 + * This file is free software; you can redistribute it and/or modify
753 + * it under the terms of the GNU General Public License, Version 2, as
754 + * published by the Free Software Foundation.
755 + */
756 +
757 +#ifndef _CNS21XX_POWERMGMT_H
758 +#define _CNS21XX_POWERMGMT_H
759 +
760 +#define PWRMGT_MEM_MAP_VALUE(reg_offset) \
761 + (*((u32 volatile *)(CNS21XX_CPM_BASE_VIRT + reg_offset)))
762 +
763 +/*
764 + * define access macros
765 + */
766 +#define PWRMGT_CLOCK_GATE_CONTROL0_REG PWRMGT_MEM_MAP_VALUE(0x00)
767 +#define PWRMGT_CLOCK_GATE_CONTROL1_REG PWRMGT_MEM_MAP_VALUE(0x04)
768 +#define PWRMGT_SOFTWARE_RESET_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x08)
769 +#define PWRMGT_SYSTEM_CLOCK_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x0C)
770 +#define PWRMGT_PLL_POWER_DOWN_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x10)
771 +#define PWRMGT_CPU_INITIALIZATION_REG PWRMGT_MEM_MAP_VALUE(0x14)
772 +#define PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x1C)
773 +#define PWRMGT_USB_DEVICE_POWERMGT_REG PWRMGT_MEM_MAP_VALUE(0x20)
774 +#define PWRMGT_REGULATOR_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x24)
775 +#define PWRMGT_RTC_XTAL_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x28)
776 +#define PWRMGT_PLL250_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x2C)
777 +
778 +
779 +/*
780 + * define constants macros
781 + */
782 +#define PWRMGT_GLOBAL_SOFTWARE_RESET_MASK_BIT_INDEX 0
783 +#define PWRMGT_PCMCIA_SOFTWARE_RESET_BIT_INDEX 1
784 +#define PWRMGT_IDE_SOFTWARE_RESET_BIT_INDEX 2
785 +#define PWRMGT_VIC_SOFTWARE_RESET_BIT_INDEX 3
786 +#define PWRMGT_DMA_SOFTWARE_RESET_BIT_INDEX 4
787 +#define PWRMGT_NIC_SOFTWARE_RESET_BIT_INDEX 5
788 +#define PWRMGT_USB_HOST_SOFTWARE_RESET_BIT_INDEX 6
789 +#define PWRMGT_PCI_BRIDGE_SOFTWARE_RESET_BIT_INDEX 7
790 +#define PWRMGT_P2S_SOFTWARE_RESET_BIT_INDEX 8
791 +#define PWRMGT_UART0_SOFTWARE_RESET_BIT_INDEX 9
792 +#define PWRMGT_UART1_SOFTWARE_RESET_BIT_INDEX 10
793 +#define PWRMGT_TIMER_SOFTWARE_RESET_BIT_INDEX 11
794 +#define PWRMGT_WDTIMER_SOFTWARE_RESET_BIT_INDEX 12
795 +#define PWRMGT_GPIO_SOFTWARE_RESET_BIT_INDEX 13
796 +#define PWRMGT_USB_DEVICE_SOFTWARE_RESET_BIT_INDEX 14
797 +#define PWRMGT_FAST_ETHERNET_PHY_SOFTWARE_RESET_BIT_INDEX 15
798 +#define PWRMGT_HSDMA_SOFTWARE_RESET_BIT_INDEX 16
799 +
800 +#define PWRMGT_PLL_FREQUENCY_175MHZ (0 << 0)
801 +#define PWRMGT_PLL_FREQUENCY_200MHZ (1 << 0)
802 +#define PWRMGT_PLL_FREQUENCY_225MHZ (2 << 0)
803 +#define PWRMGT_PLL_FREQUENCY_250MHZ (3 << 0)
804 +
805 +#define PWRMGT_CPUCLK_DIVIDER_BY_1 (0 << 2)
806 +#define PWRMGT_CPUCLK_DIVIDER_BY_2 (1 << 2)
807 +#define PWRMGT_CPUCLK_DIVIDER_BY_3 (2 << 2)
808 +#define PWRMGT_CPUCLK_DIVIDER_BY_4 (3 << 2)
809 +
810 +#define PWRMGT_HCLK_DIVIDER_BY_1 (0 << 4)
811 +#define PWRMGT_HCLK_DIVIDER_BY_2 (1 << 4)
812 +#define PWRMGT_HCLK_DIVIDER_BY_3 (2 << 4)
813 +#define PWRMGT_HCLK_DIVIDER_BY_4 (3 << 4)
814 +
815 +#define PWRMGT_HCLK_SOURCE_FCLK (0 << 6)
816 +#define PWRMGT_HCLK_SOURCE_125MHZ (1 << 6)
817 +
818 +#define PWRMGT_PCLK_DIVIDER_BY_1 (0 << 8)
819 +#define PWRMGT_PCLK_DIVIDER_BY_2 (1 << 8)
820 +#define PWRMGT_PCLK_DIVIDER_BY_3 (2 << 8)
821 +#define PWRMGT_PCLK_DIVIDER_BY_4 (3 << 8)
822 +
823 +#define PWRMGT_PCICLK_DIVIDER_BY_1 (0 << 10)
824 +#define PWRMGT_PCICLK_DIVIDER_BY_2 (1 << 10)
825 +#define PWRMGT_PCICLK_DIVIDER_BY_3 (2 << 10)
826 +#define PWRMGT_PCICLK_DIVIDER_BY_4 (3 << 10)
827 +
828 +
829 +#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_1 1
830 +#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_2 2
831 +#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_3 3
832 +#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_4 4
833 +
834 +#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_1 1
835 +#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_2 2
836 +#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_3 3
837 +#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_4 4
838 +
839 +#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_1 1
840 +#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_2 2
841 +#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_3 3
842 +#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_4 4
843 +
844 +/*
845 + * Macro defines for Clock Gate Control
846 + */
847 +#define HAL_PWRMGT_DISABLE_DRAMC_CLOCK() \
848 +{ \
849 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1); \
850 +}
851 +
852 +
853 +#define HAL_PWRMGT_ENABLE_NIC_CLOCK() \
854 +{ \
855 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 0); \
856 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x0F << 20); \
857 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 5); \
858 +}
859 +
860 +#define HAL_PWRMGT_DISABLE_NIC_CLOCK() \
861 +{ \
862 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x0F << 20); \
863 +}
864 +
865 +
866 +#define HAL_PWRMGT_ENABLE_PCI_BRIDGE_33M_CLOCK() \
867 +{ \
868 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 1); \
869 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 10); \
870 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 10); \
871 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 28) | (0x1 << 30); \
872 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 7); \
873 +}
874 +
875 +#define HAL_PWRMGT_ENABLE_PCI_BRIDGE_66M_CLOCK() \
876 +{ \
877 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 1); \
878 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 10); \
879 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x0 << 10); \
880 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 28) | (0x1 << 30); \
881 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 7); \
882 +}
883 +
884 +#define HAL_PWRMGT_DISABLE_PCI_CLOCK() \
885 +{ \
886 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 28) | (0x1 << 30)); \
887 +}
888 +
889 +
890 +#define HAL_PWRMGT_ENABLE_USB_CLOCK() \
891 +{ \
892 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0xF << 1); \
893 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 24); \
894 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 28); \
895 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 6) | (0x1 << 14); \
896 +}
897 +
898 +#define HAL_PWRMGT_DISABLE_USB_CLOCK() \
899 +{ \
900 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1 << 24); \
901 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 28); \
902 +}
903 +
904 +
905 +#define HAL_PWRMGT_ENABLE_DMA_CLOCK() \
906 +{ \
907 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 16); \
908 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 4); \
909 +}
910 +
911 +#define HAL_PWRMGT_DISABLE_DMA_CLOCK() \
912 +{ \
913 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1 << 16); \
914 +}
915 +
916 +
917 +#define HAL_PWRMGT_ENABLE_IDE_CLOCK() \
918 +{ \
919 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 8) | (0x1 << 9); \
920 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 2); \
921 +}
922 +
923 +#define HAL_PWRMGT_DISABLE_IDE_CLOCK() \
924 +{ \
925 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 8) | (0x1 << 9)); \
926 +}
927 +
928 +
929 +#define HAL_PWRMGT_ENABLE_UART0_CLOCK() \
930 +{ \
931 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~((0x1 << 1) | (0x1 << 2) | (0x1 << 5)); \
932 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 12); \
933 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 9); \
934 +}
935 +
936 +#define HAL_PWRMGT_DISABLE_UART0_CLOCK() \
937 +{ \
938 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 12); \
939 +}
940 +
941 +
942 +#define HAL_PWRMGT_ENABLE_UART1_CLOCK() \
943 +{ \
944 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~((0x1 << 1) | (0x1 << 2) | (0x1 << 5)); \
945 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 13); \
946 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 10); \
947 +}
948 +
949 +#define HAL_PWRMGT_DISABLE_UART1_CLOCK() \
950 +{ \
951 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 13); \
952 +}
953 +
954 +
955 +#define HAL_PWRMGT_ENABLE_PCMCIA_CLOCK() \
956 +{ \
957 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 4) | (0x1 << 5); \
958 +}
959 +
960 +#define HAL_PWRMGT_DISABLE_PCMCIA_CLOCK() \
961 +{ \
962 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 4) | (0x1 << 5)); \
963 +}
964 +
965 +
966 +#define HAL_PWRMGT_ENABLE_GPIO_CLOCK() \
967 +{ \
968 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 25); \
969 +}
970 +
971 +#define HAL_PWRMGT_DISABLE_GPIO_CLOCK() \
972 +{ \
973 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 25); \
974 +}
975 +
976 +
977 +#define HAL_PWRMGT_ENABLE_WDTIMER_CLOCK() \
978 +{ \
979 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 21) | (0x1 << 22); \
980 +}
981 +
982 +#define HAL_PWRMGT_DISABLE_WDTIMER_CLOCK() \
983 +{ \
984 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 21) | (0x1 << 22)); \
985 +}
986 +
987 +
988 +#define HAL_PWRMGT_ENABLE_RTC_CLOCK() \
989 +{ \
990 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 23); \
991 +}
992 +
993 +#define HAL_PWRMGT_DISABLE_RTC_CLOCK() \
994 +{ \
995 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 23); \
996 +}
997 +
998 +
999 +#define HAL_PWRMGT_ENABLE_TIMER_CLOCK() \
1000 +{ \
1001 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 17) | (0x1 << 18) | (0x1 << 19); \
1002 +}
1003 +
1004 +#define HAL_PWRMGT_DISABLE_TIMER_CLOCK() \
1005 +{ \
1006 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 17) | (0x1 << 18) | (0x1 << 19)); \
1007 +}
1008 +
1009 +
1010 +#define HAL_PWRMGT_ENABLE_I2C_CLOCK() \
1011 +{ \
1012 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 1); \
1013 +}
1014 +
1015 +#define HAL_PWRMGT_DISABLE_I2C_CLOCK() \
1016 +{ \
1017 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 1); \
1018 +}
1019 +
1020 +
1021 +#define HAL_PWRMGT_ENABLE_I2S_CLOCK() \
1022 +{ \
1023 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~((0x1 << 5) | (0x1 << 6)); \
1024 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 1) | (0x1 << 10); \
1025 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 8); \
1026 +}
1027 +
1028 +#define HAL_PWRMGT_DISABLE_I2S_CLOCK() \
1029 +{ \
1030 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 1) | (0x1 << 10)); \
1031 +}
1032 +
1033 +
1034 +#define HAL_PWRMGT_ENABLE_PCM_CLOCK() \
1035 +{ \
1036 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 5); \
1037 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 1) | (0x1 << 6); \
1038 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 8); \
1039 +}
1040 +
1041 +#define HAL_PWRMGT_DISABLE_PCM_CLOCK() \
1042 +{ \
1043 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 1) | (0x1 << 6)); \
1044 +}
1045 +
1046 +
1047 +#define HAL_PWRMGT_ENABLE_SPI_CLOCK() \
1048 +{ \
1049 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 0) | (0x1 << 1); \
1050 +}
1051 +
1052 +#define HAL_PWRMGT_DISABLE_SPI_CLOCK() \
1053 +{ \
1054 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 0) | (0x1 << 1)); \
1055 +}
1056 +
1057 +
1058 +#define HAL_PWRMGT_ENABLE_VIC_CLOCK() \
1059 +{ \
1060 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 12); \
1061 +}
1062 +
1063 +#define HAL_PWRMGT_DISABLE_VIC_CLOCK() \
1064 +{ \
1065 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1 << 12); \
1066 +}
1067 +
1068 +
1069 +#define HAL_PWRMGT_ENABLE_SMC_CLOCK() \
1070 +{ \
1071 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 4) | (0x1 << 5); \
1072 +}
1073 +
1074 +#define HAL_PWRMGT_DISABLE_SMC_CLOCK() \
1075 +{ \
1076 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 4) | (0x1 << 5)); \
1077 +}
1078 +
1079 +
1080 +#define HAL_PWRMGT_ENABLE_HSDMA_CLOCK() \
1081 +{ \
1082 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 29); \
1083 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 16); \
1084 +}
1085 +
1086 +#define HAL_PWRMGT_DISABLE_HSDMA_CLOCK() \
1087 +{ \
1088 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 29); \
1089 +}
1090 +
1091 +
1092 +
1093 +/*
1094 + * Macro defines for Reset Control
1095 + */
1096 +#define HAL_PWRMGT_GLOBAL_SOFTWARE_RESET() \
1097 +{ \
1098 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1); \
1099 + PWRMGT_SOFTWARE_RESET_CONTROL_REG &= ~(0x1); \
1100 +}
1101 +
1102 +
1103 +/*
1104 + * Macro defines for System Clock Control
1105 + */
1106 +#define HAL_PWRMGT_SET_PLL_FREQUENCY_175MHZ() \
1107 +{ \
1108 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1109 +}
1110 +
1111 +
1112 +#define HAL_PWRMGT_SET_PLL_FREQUENCY_200MHZ() \
1113 +{ \
1114 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1115 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= 0x1; \
1116 +}
1117 +
1118 +
1119 +#define HAL_PWRMGT_SET_PLL_FREQUENCY_225MHZ() \
1120 +{ \
1121 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1122 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= 0x2; \
1123 +}
1124 +
1125 +
1126 +#define HAL_PWRMGT_SET_PLL_FREQUENCY_250MHZ() \
1127 +{ \
1128 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1129 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= 0x3; \
1130 +}
1131 +
1132 +
1133 +#define HAL_PWRMGT_CONFIG_PLLCLK_TO_CPUCLK_RATIO(ratio) \
1134 +{ \
1135 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 2); \
1136 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (((ratio - 1) & 0x3) << 2); \
1137 +}
1138 +
1139 +
1140 +#define HAL_PWRMGT_CONFIG_CPUCLK_TO_HCLK_RATIO(ratio) \
1141 +{ \
1142 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 4); \
1143 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (((ratio - 1) & 0x3) << 4); \
1144 +}
1145 +
1146 +
1147 +#define HAL_PWRMGT_HCLK_SOURCE_FCLK() \
1148 +{ \
1149 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x1 << 6); \
1150 +}
1151 +
1152 +
1153 +#define HAL_PWRMGT_HCLK_SOURCE_125MHZ() \
1154 +{ \
1155 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 6); \
1156 +}
1157 +
1158 +
1159 +#define HAL_PWRMGT_GIGA_NIC_CLOCK_SOURCE_HCLK() \
1160 +{ \
1161 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x1 << 7); \
1162 +}
1163 +
1164 +
1165 +#define HAL_PWRMGT_GIGA_NIC_CLOCK_SOURCE_62_5MHZ() \
1166 +{ \
1167 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 7); \
1168 +}
1169 +
1170 +
1171 +#define HAL_PWRMGT_CONFIG_HCLK_TO_PCLK_RATIO(ratio) \
1172 +{ \
1173 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 8); \
1174 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (((ratio - 1) & 0x3) << 8); \
1175 +}
1176 +
1177 +
1178 +#define HAL_PWRMGT_I2S_CLOCK_SOURCE_8192000HZ() \
1179 +{ \
1180 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 12); \
1181 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x0 << 12); \
1182 +}
1183 +
1184 +
1185 +#define HAL_PWRMGT_I2S_CLOCK_SOURCE_11289600HZ() \
1186 +{ \
1187 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 12); \
1188 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 12); \
1189 +}
1190 +
1191 +
1192 +#define HAL_PWRMGT_I2S_CLOCK_SOURCE_12288000HZ() \
1193 +{ \
1194 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 12); \
1195 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x2 << 12); \
1196 +}
1197 +
1198 +
1199 +#define HAL_PWRMGT_CONFIGURE_MDC_CLOCK_DIVIDER(divided_value) \
1200 +{ \
1201 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 14); \
1202 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= ((divided_value & 0x3) << 14); \
1203 +}
1204 +
1205 +
1206 +#define HAL_PWRMGT_CONFIGURE_CLOCK_OUT_PIN(pin_source_select, divided_value) \
1207 +{ \
1208 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3F << 16); \
1209 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= ((pin_source_select & 0xF) << 16); \
1210 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= ((divided_value & 0x3) << 20); \
1211 +}
1212 +
1213 +
1214 +/*
1215 + * Macro defines for PLL Power Down Control
1216 + */
1217 +#define HAL_PWRMGT_POWER_DOWN_SYSTEM_XTAL_PAD() \
1218 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 7)
1219 +
1220 +#define HAL_PWRMGT_POWER_ON_SYSTEM_XTAL_PAD() \
1221 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 7)
1222 +
1223 +
1224 +#define HAL_PWRMGT_POWER_DOWN_PLL_X5() \
1225 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 0)
1226 +
1227 +#define HAL_PWRMGT_POWER_ON_PLL_X5() \
1228 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 0)
1229 +
1230 +
1231 +#define HAL_PWRMGT_POWER_DOWN_PLL_X8() \
1232 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 1)
1233 +
1234 +#define HAL_PWRMGT_POWER_ON_PLL_X8() \
1235 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 1)
1236 +
1237 +
1238 +#define HAL_PWRMGT_POWER_DOWN_PLL_X3() \
1239 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 2)
1240 +
1241 +#define HAL_PWRMGT_POWER_ON_PLL_X3() \
1242 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 2)
1243 +
1244 +
1245 +#define HAL_PWRMGT_POWER_DOWN_USBH_PHY_PLL() \
1246 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 3)
1247 +
1248 +#define HAL_PWRMGT_POWER_ON_USBH_PHY_PLL() \
1249 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 3)
1250 +
1251 +
1252 +#define HAL_PWRMGT_POWER_DOWN_USBD_PHY_PLL() \
1253 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 4)
1254 +
1255 +#define HAL_PWRMGT_POWER_ON_USBD_PHY_PLL() \
1256 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 4)
1257 +
1258 +
1259 +#define HAL_PWRMGT_POWER_DOWN_PLL_X2250() \
1260 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 5)
1261 +
1262 +#define HAL_PWRMGT_POWER_ON_PLL_X2250() \
1263 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 5)
1264 +
1265 +
1266 +#define HAL_PWRMGT_POWER_DOWN_PLL_X7() \
1267 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 6)
1268 +
1269 +#define HAL_PWRMGT_POWER_ON_PLL_X7() \
1270 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 6)
1271 +
1272 +
1273 +#define HAL_PWRMGT_POWER_DOWN_ALL_PLL() \
1274 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG = 0x7F;
1275 +
1276 +#define HAL_PWRMGT_POWER_ON_ALL_PLL() \
1277 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG = 0;
1278 +
1279 +
1280 +/*
1281 + * Macro defines for Pad Drive Strength Control
1282 + */
1283 +#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_PCMCIA_CARDBUS_MODE() \
1284 +{ \
1285 + PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x3 << 0); \
1286 +}
1287 +
1288 +#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_PCI_MODE() \
1289 +{ \
1290 + PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x3 << 0); \
1291 + PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG |= (0x1 << 0); \
1292 +}
1293 +
1294 +#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_MII_MODE() \
1295 +{ \
1296 + PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG |= (0x1 << 2); \
1297 +}
1298 +
1299 +#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_RGMII_MODE() \
1300 +{ \
1301 + PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x1 << 2); \
1302 +}
1303 +
1304 +#define HAL_PWRMGT_ENABLE_MII_PAD_SIGNAL_NOT_BOUNDED() \
1305 +{ \
1306 + PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG |= (0x1 << 3); \
1307 +}
1308 +
1309 +#define HAL_PWRMGT_DISABLE_MII_PAD_SIGNAL_NOT_BOUNDED() \
1310 +{ \
1311 + PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x1 << 3); \
1312 +}
1313 +
1314 +
1315 +/*
1316 + * Macro defines for USB Device Power Management
1317 + */
1318 +#define HAL_PWRMGT_REMOTE_WAKEUP_USB_HOST() \
1319 +{ \
1320 + PWRMGT_USB_DEVICE_POWERMGT_REG |= (0x1 << 4); \
1321 +}
1322 +
1323 +#define HAL_PWRMGT_USB_DEVICE_PHY_CLOCK_SOURCE_EXTERNAL_12MHZ() \
1324 +{ \
1325 + PWRMGT_USB_DEVICE_POWERMGT_REG &= ~(0x1 << 5); \
1326 +}
1327 +
1328 +#define HAL_PWRMGT_USB_DEVICE_PHY_CLOCK_SOURCE_INTERNAL_12MHZ() \
1329 +{ \
1330 + PWRMGT_USB_DEVICE_POWERMGT_REG |= (0x1 << 5); \
1331 +}
1332 +
1333 +
1334 +/*
1335 + * Macro defines for Regulator Control
1336 + */
1337 +
1338 +#endif /* _CNS21XX_POWERMGMT_H */
1339 --- /dev/null
1340 +++ b/arch/arm/mach-cns21xx/include/mach/cns21xx.h
1341 @@ -0,0 +1,88 @@
1342 +/*
1343 + * Copyright (c) 2008 Cavium Networks
1344 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
1345 + *
1346 + * This file is free software; you can redistribute it and/or modify
1347 + * it under the terms of the GNU General Public License, Version 2, as
1348 + * published by the Free Software Foundation.
1349 + */
1350 +
1351 +#ifndef _CNS21XX_H
1352 +#define _CNS21XX_H
1353 +
1354 +#define CNS21XX_FLASH_BANK0_BASE 0x10000000
1355 +#define CNS21XX_FLASH_BANK1_BASE 0x11000000
1356 +#define CNS21XX_FLASH_BANK2_BASE 0x12000000
1357 +#define CNS21XX_FLASH_BANK3_BASE 0x13000000
1358 +#define CNS21XX_PCMCIA_ATTR_BASE 0x14000000
1359 +#define CNS21XX_PCMCIA_MEM_BASE 0x15000000
1360 +#define CNS21XX_PCMCIA_IO_BASE 0x16000000
1361 +#define CNS21XX_IDE_DEVICE_BASE 0x18000000
1362 +#define CNS21XX_SDRAM_MEMORY_BASE 0x20000000
1363 +#define CNS21XX_GDMAC_BASE 0x60000000
1364 +#define CNS21XX_NIC_BASE 0x70000000
1365 +#define CNS21XX_SPI_BASE 0x71000000
1366 +#define CNS21XX_PCM_BASE 0x71000000
1367 +#define CNS21XX_I2C_BASE 0x71000000
1368 +#define CNS21XX_I2S_BASE 0x71000000
1369 +#define CNS21XX_DDRC_BASE 0x72000000
1370 +#define CNS21XX_SMC_BASE 0x73000000
1371 +#define CNS21XX_PCMCIA_CTRL_BASE 0x73000000
1372 +#define CNS21XX_IDE_CTRL_BASE 0x74000000
1373 +#define CNS21XX_MISC_BASE 0x76000000
1374 +#define CNS21XX_CPM_BASE 0x77000000
1375 +#define CNS21XX_UART0_BASE 0x78000000
1376 +#define CNS21XX_UART1_BASE 0x78800000
1377 +#define CNS21XX_TIMER_BASE 0x79000000
1378 +#define CNS21XX_WDT_BASE 0x7a000000
1379 +#define CNS21XX_RTC_BASE 0x7b000000
1380 +#define CNS21XX_GPIOA_BASE 0x7c000000
1381 +#define CNS21XX_GPIOB_BASE 0x7c800000
1382 +#define CNS21XX_PCI_CFGDATA_BASE 0xa0000000
1383 +#define CNS21XX_PCI_CFGADDR_BASE 0xa4000000
1384 +#define CNS21XX_PCI_IO_BASE 0xa8000000
1385 +#define CNS21XX_PCI_MEMORY_BASE 0xb0000000
1386 +#define CNS21XX_OHCI_CONFIG_BASE 0xc0000000
1387 +#define CNS21XX_OHCI_CTRL_BASE 0xc4000000
1388 +#define CNS21XX_EHCI_CONFIG_BASE 0xc8000000
1389 +#define CNS21XX_EHCI_CTRL_BASE 0xcc000000
1390 +#define CNS21XX_USB_DEVICE_BASE 0xd0000000
1391 +#define CNS21XX_INTC_BASE 0xfffff000
1392 +
1393 +#define CNS21XX_FLASH_BANK0_BASE_VIRT 0xe0000000
1394 +#define CNS21XX_FLASH_BANK1_BASE_VIRT 0xe2000000
1395 +#define CNS21XX_FLASH_BANK2_BASE_VIRT 0xe4000000
1396 +#define CNS21XX_FLASH_BANK3_BASE_VIRT 0xe8000000
1397 +#define CNS21XX_IDE_DEVICE_BASE_VIRT 0xfef00000
1398 +#define CNS21XX_GDMAC_BASE_VIRT 0xfef01000
1399 +#define CNS21XX_NIC_BASE_VIRT 0xfef02000
1400 +#define CNS21XX_SPI_BASE_VIRT 0xfef03000
1401 +#define CNS21XX_PCM_BASE_VIRT 0xfef04000
1402 +#define CNS21XX_I2C_BASE_VIRT 0xfef05000
1403 +#define CNS21XX_I2S_BASE_VIRT 0xfef06000
1404 +#define CNS21XX_DDRC_BASE_VIRT 0xfef07000
1405 +#define CNS21XX_SMC_BASE_VIRT 0xfef08000
1406 +#define CNS21XX_PCMCIA_CTRL_BASE_VIRT 0xfef09000
1407 +#define CNS21XX_IDE_CTRL_BASE_VIRT 0xfef0A000
1408 +#define CNS21XX_MISC_BASE_VIRT 0xfef0B000
1409 +#define CNS21XX_CPM_BASE_VIRT 0xfef0C000
1410 +#define CNS21XX_UART0_BASE_VIRT 0xfef0D000
1411 +#define CNS21XX_UART1_BASE_VIRT 0xfef0E000
1412 +#define CNS21XX_TIMER_BASE_VIRT 0xfef0F000
1413 +#define CNS21XX_WDT_BASE_VIRT 0xfef10000
1414 +#define CNS21XX_RTC_BASE_VIRT 0xfef11000
1415 +#define CNS21XX_GPIOA_BASE_VIRT 0xfef12000
1416 +#define CNS21XX_GPIOB_BASE_VIRT 0xfef13000
1417 +#define CNS21XX_PCI_CFGDATA_BASE_VIRT 0xfef14000
1418 +#define CNS21XX_PCI_CFGADDR_BASE_VIRT 0xfef15000
1419 +#define CNS21XX_OHCI_CONFIG_BASE_VIRT 0xfef16000
1420 +#define CNS21XX_OHCI_CTRL_BASE_VIRT 0xfef17000
1421 +#define CNS21XX_EHCI_CONFIG_BASE_VIRT 0xfef18000
1422 +#define CNS21XX_EHCI_CTRL_BASE_VIRT 0xfef19000
1423 +#define CNS21XX_USB_DEVICE_BASE_VIRT 0xfef1a000
1424 +#define CNS21XX_INTC_BASE_VIRT 0xfef1b000
1425 +
1426 +#define CNS21XX_PHYS_IO CNS21XX_UART0_BASE
1427 +#define CNS21XX_IO_PAGE_OFFSET ((CNS21XX_UART0_BASE_VIRT) >> 18) & 0xfffc
1428 +
1429 +#endif /* _CNS21XX_H */
1430 --- /dev/null
1431 +++ b/arch/arm/mach-cns21xx/core.c
1432 @@ -0,0 +1,85 @@
1433 +/*
1434 + * Copyright (c) 2008 Cavium Networks
1435 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
1436 + *
1437 + * This file is free software; you can redistribute it and/or modify
1438 + * it under the terms of the GNU General Public License, Version 2, as
1439 + * published by the Free Software Foundation.
1440 + */
1441 +
1442 +#include <linux/kernel.h>
1443 +
1444 +#include <mach/hardware.h>
1445 +#include <mach/cns21xx.h>
1446 +#include <mach/cns21xx_powermgmt.h>
1447 +
1448 +static unsigned long cns21xx_pll_freq;
1449 +static unsigned long cns21xx_cpu_freq;
1450 +static unsigned long cns21xx_ahb_freq;
1451 +static unsigned long cns21xx_apb_freq;
1452 +
1453 +static void cns21xx_init_freq(void)
1454 +{
1455 + static int freq_init_done;
1456 + unsigned int t;
1457 +
1458 + if (freq_init_done)
1459 + return;
1460 +
1461 + t = PWRMGT_SYSTEM_CLOCK_CONTROL_REG;
1462 + switch (t & 0x3) {
1463 + case 0x00:
1464 + cns21xx_pll_freq = 175000000;
1465 + break;
1466 +
1467 + case 0x01:
1468 + cns21xx_pll_freq = 200000000;
1469 + break;
1470 +
1471 + case 0x02:
1472 + cns21xx_pll_freq = 225000000;
1473 + break;
1474 +
1475 + case 0x03:
1476 + cns21xx_pll_freq = 250000000;
1477 + break;
1478 + }
1479 +
1480 + cns21xx_cpu_freq = cns21xx_pll_freq / (((t >> 2) & 0x3) + 1);
1481 + cns21xx_ahb_freq = cns21xx_cpu_freq / (((t >> 4) & 0x3) + 1);
1482 + cns21xx_apb_freq = cns21xx_ahb_freq / (((t >> 8) & 0x3) + 1);
1483 +
1484 + freq_init_done = 1;
1485 +}
1486 +
1487 +unsigned long cns21xx_get_pll_freq(void)
1488 +{
1489 + cns21xx_init_freq();
1490 + return cns21xx_pll_freq;
1491 +}
1492 +
1493 +unsigned long cns21xx_get_cpu_freq(void)
1494 +{
1495 + cns21xx_init_freq();
1496 + return cns21xx_cpu_freq;
1497 +}
1498 +
1499 +unsigned long cns21xx_get_ahb_freq(void)
1500 +{
1501 + cns21xx_init_freq();
1502 + return cns21xx_ahb_freq;
1503 +}
1504 +
1505 +unsigned long cns21xx_get_apb_freq(void)
1506 +{
1507 + cns21xx_init_freq();
1508 + return cns21xx_apb_freq;
1509 +}
1510 +
1511 +void cns21xx_restart(char mode, const char *cmd)
1512 +{
1513 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |=
1514 + (1UL << PWRMGT_GLOBAL_SOFTWARE_RESET_MASK_BIT_INDEX);
1515 + PWRMGT_SOFTWARE_RESET_CONTROL_REG &=
1516 + ~(1UL << PWRMGT_GLOBAL_SOFTWARE_RESET_MASK_BIT_INDEX);
1517 +}
1518 --- a/arch/arm/mm/Kconfig
1519 +++ b/arch/arm/mm/Kconfig
1520 @@ -890,6 +890,7 @@ config ARM_L1_CACHE_SHIFT_6
1521 config ARM_L1_CACHE_SHIFT
1522 int
1523 default 6 if ARM_L1_CACHE_SHIFT_6
1524 + default 4 if ARM_L1_CACHE_SHIFT_4
1525 default 5
1526
1527 config ARM_DMA_MEM_BUFFERABLE
1528 --- a/arch/arm/mm/cache-fa.S
1529 +++ b/arch/arm/mm/cache-fa.S
1530 @@ -28,7 +28,7 @@
1531 /*
1532 * The total size of the data cache.
1533 */
1534 -#ifdef CONFIG_ARCH_GEMINI
1535 +#if (defined(CONFIG_ARCH_GEMINI) || defined(CONFIG_ARCH_CNS21XX))
1536 #define CACHE_DSIZE 8192
1537 #else
1538 #define CACHE_DSIZE 16384
1539 --- /dev/null
1540 +++ b/arch/arm/mach-cns21xx/include/mach/cns21xx_misc.h
1541 @@ -0,0 +1,507 @@
1542 +/*******************************************************************************
1543 + *
1544 + * Copyright (c) 2008 Cavium Networks
1545 + *
1546 + * This file is free software; you can redistribute it and/or modify
1547 + * it under the terms of the GNU General Public License, Version 2, as
1548 + * published by the Free Software Foundation.
1549 + *
1550 + * This file is distributed in the hope that it will be useful,
1551 + * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
1552 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1553 + * NONINFRINGEMENT. See the GNU General Public License for more details.
1554 + *
1555 + * You should have received a copy of the GNU General Public License
1556 + * along with this file; if not, write to the Free Software
1557 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
1558 + * visit http://www.gnu.org/licenses/.
1559 + *
1560 + * This file may also be available under a different license from Cavium.
1561 + * Contact Cavium Networks for more information
1562 + *
1563 + ******************************************************************************/
1564 +
1565 +#ifndef _STAR_MISC_H_
1566 +#define _STAR_MISC_H_
1567 +
1568 +#include <mach/cns21xx.h>
1569 +
1570 +#define MISC_MEM_MAP_VALUE(reg_offset) \
1571 + (*((u32 volatile *)(CNS21XX_MISC_BASE_VIRT + reg_offset)))
1572 +
1573 +/*
1574 + * define access macros
1575 + */
1576 +#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00)
1577 +#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04)
1578 +#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08)
1579 +#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C)
1580 +#define MISC_PCI_CONTROL_BROKEN_MASK_REG MISC_MEM_MAP_VALUE(0x10)
1581 +#define MISC_PCI_BROKEN_STATUS_REG MISC_MEM_MAP_VALUE(0x14)
1582 +#define MISC_PCI_DEVICE_VENDOR_ID_REG MISC_MEM_MAP_VALUE(0x18)
1583 +#define MISC_USB_HOST_PHY_CONTROL_TEST_REG MISC_MEM_MAP_VALUE(0x1C)
1584 +#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x20)
1585 +#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x24)
1586 +#define MISC_GPIOA_RESISTOR_CONFIG_REG MISC_MEM_MAP_VALUE(0x28)
1587 +#define MISC_GPIOA_DRIVE_STRENGTH_CONFIG_REG MISC_MEM_MAP_VALUE(0x2C)
1588 +#define MISC_FAST_ETHERNET_PHY_CONFIG_REG MISC_MEM_MAP_VALUE(0x30)
1589 +#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x38)
1590 +#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x3C)
1591 +
1592 +#define MISC_E_FUSE_0_REG MISC_MEM_MAP_VALUE(0x60)
1593 +#define MISC_E_FUSE_1_REG MISC_MEM_MAP_VALUE(0x64)
1594 +
1595 +
1596 +/*
1597 + * define constants macros
1598 + */
1599 +#define MISC_PARALLEL_FLASH_BOOT 0
1600 +#define MISC_SPI_SERIAL_FLASH_BOOT 1
1601 +
1602 +#define MISC_LITTLE_ENDIAN 0
1603 +#define MISC_BIG_ENDIAN 1
1604 +
1605 +#define MISC_FARADAY_ICE 0
1606 +#define MISC_ARM_ICE 1
1607 +
1608 +#define MISC_EXT_INT29_PINS ((0x1 << 0))
1609 +#define MISC_EXT_INT30_PINS ((0x1 << 1))
1610 +#define MISC_EXT_INT31_PINS ((0x1 << 2))
1611 +#define MISC_I2C_PINS ((0x1 << 13) | (0x1 << 14))
1612 +#define MISC_I2S_PINS ((0x1 << 15) | (0x1 << 16) | (0x1 << 17))
1613 +#define MISC_I2SSD_PINS (1 << 15)
1614 +#define MISC_I2SWS_PINS (1 << 16)
1615 +#define MISC_I2SCLK_PINS (1 << 17)
1616 +#define MISC_PCM_PINS ((0x1 << 18) | (0x1 << 19) | (0x1 << 20) | (0x1 << 21))
1617 +#define MISC_PCMDR_PINS (1 << 18)
1618 +#define MISC_PCMDT_PINS (1 << 19)
1619 +#define MISC_PCMFS_PINS (1 << 20)
1620 +#define MISC_PCMCLK_PINS (1 << 21)
1621 +#define MISC_LED0_PINS ((0x1 << 22))
1622 +#define MISC_LED1_PINS ((0x1 << 23))
1623 +#define MISC_LED2_PINS ((0x1 << 24))
1624 +#define MISC_LED012_PINS ((0x1 << 22) | (0x1 << 23) | (0x1 << 24))
1625 +#define MISC_WDTIMER_RESET_PINS ((0x1 << 25))
1626 +#define MISC_SPIDR_PINS (0x1 << 26)
1627 +#define MISC_SPICLK_PINS (0x1 << 27)
1628 +#define MISC_SPICSN0_PINS (0x1 << 28)
1629 +#define MISC_SPICSN1_PINS (0x1 << 29)
1630 +#define MISC_SPICSN2_PINS (0x1 << 30)
1631 +#define MISC_SPICSN3_PINS (0x1 << 31)
1632 +#define MISC_SPI_PINS ((0x1 << 26) | (0x1 << 27) | (0x1 << 28) | (0x1 << 29) | (0x1 << 30) | (0x1 << 31))
1633 +#define MISC_MDC_MDIO_PINS ((0x1 << 0) | (0x1 << 1))
1634 +#define MISC_NIC_COL_PINS ((0x1 << 2))
1635 +#define MISC_IDE_PINS ((0xFF << 3))
1636 +#define MISC_SRAM_BANK1_PINS ((0x1 << 11) | (0x1 << 14))
1637 +#define MISC_SRAM_BANK2_PINS ((0x1 << 12) | (0x1 << 15))
1638 +#define MISC_SRAM_BANK3_PINS ((0x1 << 13) | (0x1 << 16))
1639 +#define MISC_PCMCIA_PINS ((0x1 << 17) | (0x1 << 18) | (0x1 << 19) | (0x1 << 20))
1640 +#define MISC_UART1_PINS ((0x1 << 21) | (0x1 << 22))
1641 +#define MISC_PCI_PINS (((u32)0x1FF << 23))
1642 +
1643 +#define MISC_UART0_ACT0_Pin (0x1 << 2)
1644 +#define MISC_UART1_ACT1_Pin (0x1 << 3)
1645 +
1646 +#define MISC_GPIOA_PIN_0 0
1647 +#define MISC_GPIOA_PIN_1 1
1648 +#define MISC_GPIOA_PIN_2 2
1649 +#define MISC_GPIOA_PIN_3 3
1650 +#define MISC_GPIOA_PIN_4 4
1651 +#define MISC_GPIOA_PIN_5 5
1652 +#define MISC_GPIOA_PIN_6 6
1653 +#define MISC_GPIOA_PIN_7 7
1654 +#define MISC_GPIOA_PIN_8 8
1655 +#define MISC_GPIOA_PIN_9 9
1656 +#define MISC_GPIOA_PIN_10 10
1657 +
1658 +#define MISC_GPIOA_75K_RESISTOR_PULL_DOWN 1
1659 +#define MISC_GPIOA_75K_RESISTOR_PULL_UP 2
1660 +#define MISC_GPIOA_75K_RESISTOR_PULL_KEEPER 3
1661 +
1662 +#define MISC_GPIOA_DRIVE_STRENGTH_4MA 0
1663 +#define MISC_GPIOA_DRIVE_STRENGTH_8MA 1
1664 +
1665 +
1666 +/*
1667 + * macro declarations
1668 + */
1669 +#define HAL_MISC_ENABLE_SPI_SERIAL_FLASH_BANK_ACCESS() \
1670 +{ \
1671 + (MISC_CHIP_CONFIG_REG) |= (0x1 << 4); \
1672 +}
1673 +
1674 +#define HAL_MISC_DISABLE_SPI_SERIAL_FLASH_BANK_ACCESS() \
1675 +{ \
1676 + (MISC_CHIP_CONFIG_REG) &= ~(0x1 << 4); \
1677 +}
1678 +
1679 +
1680 +/*
1681 + * Macro defines for GPIOA and GPIOB Pin Enable Register
1682 + */
1683 +#define HAL_MISC_ENABLE_EXT_INT29_PINS() \
1684 +{ \
1685 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_EXT_INT29_PINS); \
1686 +}
1687 +
1688 +#define HAL_MISC_DISABLE_EXT_INT29_PINS() \
1689 +{ \
1690 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_EXT_INT29_PINS); \
1691 +}
1692 +
1693 +#define HAL_MISC_ENABLE_EXT_INT30_PINS() \
1694 +{ \
1695 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_EXT_INT30_PINS); \
1696 +}
1697 +
1698 +#define HAL_MISC_DISABLE_EXT_INT30_PINS() \
1699 +{ \
1700 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_EXT_INT30_PINS); \
1701 +}
1702 +
1703 +#define HAL_MISC_ENABLE_I2C_PINS() \
1704 +{ \
1705 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_I2C_PINS); \
1706 +}
1707 +
1708 +#define HAL_MISC_DISABLE_I2C_PINS() \
1709 +{ \
1710 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2C_PINS); \
1711 +}
1712 +
1713 +#define HAL_MISC_ENABLE_I2S_PINS() \
1714 +{ \
1715 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_I2S_PINS); \
1716 +}
1717 +
1718 +#define HAL_MISC_DISABLE_I2S_PINS() \
1719 +{ \
1720 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2S_PINS); \
1721 +}
1722 +
1723 +#define HAL_MISC_DISABLE_I2SSD_PINS() \
1724 +{ \
1725 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2SSD_PINS); \
1726 +}
1727 +
1728 +#define HAL_MISC_DISABLE_I2SWS_PINS() \
1729 +{ \
1730 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2SWS_PINS); \
1731 +}
1732 +
1733 +#define HAL_MISC_DISABLE_I2SCLK_PINS() \
1734 +{ \
1735 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2SCLK_PINS); \
1736 +}
1737 +
1738 +#define HAL_MISC_ENABLE_PCM_PINS() \
1739 +{ \
1740 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_PCM_PINS); \
1741 +}
1742 +
1743 +#define HAL_MISC_DISABLE_PCM_PINS() \
1744 +{ \
1745 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCM_PINS); \
1746 +}
1747 +
1748 +#define HAL_MISC_DISABLE_PCMDR_PINS() \
1749 +{ \
1750 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMDR_PINS); \
1751 +}
1752 +
1753 +#define HAL_MISC_DISABLE_PCMDT_PINS() \
1754 +{ \
1755 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMDT_PINS); \
1756 +}
1757 +
1758 +#define HAL_MISC_DISABLE_PCMFS_PINS() \
1759 +{ \
1760 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMFS_PINS); \
1761 +}
1762 +
1763 +#define HAL_MISC_DISABLE_PCMCLK_PINS() \
1764 +{ \
1765 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMCLK_PINS); \
1766 +}
1767 +
1768 +#define HAL_MISC_ENABLE_LED0_PINS() \
1769 +{ \
1770 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED0_PINS); \
1771 +}
1772 +
1773 +#define HAL_MISC_DISABLE_LED0_PINS() \
1774 +{ \
1775 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED0_PINS); \
1776 +}
1777 +
1778 +#define HAL_MISC_ENABLE_LED1_PINS() \
1779 +{ \
1780 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED1_PINS); \
1781 +}
1782 +
1783 +#define HAL_MISC_DISABLE_LED1_PINS() \
1784 +{ \
1785 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED1_PINS); \
1786 +}
1787 +
1788 +#define HAL_MISC_ENABLE_LED2_PINS() \
1789 +{ \
1790 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED2_PINS); \
1791 +}
1792 +
1793 +#define HAL_MISC_DISABLE_LED2_PINS() \
1794 +{ \
1795 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED2_PINS); \
1796 +}
1797 +
1798 +#define HAL_MISC_ENABLE_LED012_PINS() \
1799 +{ \
1800 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED012_PINS); \
1801 +}
1802 +
1803 +#define HAL_MISC_DISABLE_LED012_PINS() \
1804 +{ \
1805 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED012_PINS); \
1806 +}
1807 +
1808 +#define HAL_MISC_ENABLE_WDTIMER_RESET_PINS() \
1809 +{ \
1810 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_WDTIMER_RESET_PINS); \
1811 +}
1812 +
1813 +#define HAL_MISC_DISABLE_WDTIMER_RESET_PINS() \
1814 +{ \
1815 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_WDTIMER_RESET_PINS); \
1816 +}
1817 +
1818 +#define HAL_MISC_ENABLE_SPI_PINS() \
1819 +{ \
1820 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPI_PINS); \
1821 +}
1822 +
1823 +#define HAL_MISC_ENABLE_SPIDR_PINS() \
1824 +{ \
1825 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPIDR_PINS); \
1826 +}
1827 +
1828 +#define HAL_MISC_ENABLE_SPICLK_PINS() \
1829 +{ \
1830 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICLK_PINS); \
1831 +}
1832 +
1833 +#define HAL_MISC_ENABLE_SPICSN0_PINS() \
1834 +{ \
1835 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN0_PINS); \
1836 +}
1837 +
1838 +#define HAL_MISC_ENABLE_SPICSN0_PINS() \
1839 +{ \
1840 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN0_PINS); \
1841 +}
1842 +
1843 +#define HAL_MISC_ENABLE_SPICSN1_PINS() \
1844 +{ \
1845 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN1_PINS); \
1846 +}
1847 +
1848 +#define HAL_MISC_ENABLE_SPICSN2_PINS() \
1849 +{ \
1850 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN2_PINS); \
1851 +}
1852 +
1853 +#define HAL_MISC_ENABLE_SPICSN3_PINS() \
1854 +{ \
1855 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN3_PINS); \
1856 +}
1857 +
1858 +#define HAL_MISC_DISABLE_SPI_PINS() \
1859 +{ \
1860 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPI_PINS); \
1861 +}
1862 +
1863 +#define HAL_MISC_DISABLE_SPIDR_PINS() \
1864 +{ \
1865 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPIDR_PINS); \
1866 +}
1867 +
1868 +#define HAL_MISC_DISABLE_SPICLK_PINS() \
1869 +{ \
1870 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICLK_PINS); \
1871 +}
1872 +
1873 +#define HAL_MISC_DISABLE_SPICSN0_PINS() \
1874 +{ \
1875 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN0_PINS); \
1876 +}
1877 +
1878 +#define HAL_MISC_DISABLE_SPICSN1_PINS() \
1879 +{ \
1880 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN1_PINS); \
1881 +}
1882 +
1883 +#define HAL_MISC_DISABLE_SPICSN2_PINS() \
1884 +{ \
1885 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN2_PINS); \
1886 +}
1887 +
1888 +#define HAL_MISC_DISABLE_SPICSN3_PINS() \
1889 +{ \
1890 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN3_PINS); \
1891 +}
1892 +
1893 +#define HAL_MISC_ENABLE_UART0_ACT0_PIN() \
1894 +{ \
1895 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_UART0_ACT0_Pin); \
1896 +}
1897 +
1898 +#define HAL_MISC_DISABLE_UART0_ACT0_PIN() \
1899 +{ \
1900 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_UART0_ACT0_Pin); \
1901 +}
1902 +
1903 +#define HAL_MISC_ENABLE_UART1_ACT1_PIN() \
1904 +{ \
1905 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_UART1_ACT1_Pin); \
1906 +}
1907 +
1908 +#define HAL_MISC_DISABLE_UART1_ACT1_PIN() \
1909 +{ \
1910 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_UART1_ACT1_Pin); \
1911 +}
1912 +
1913 +#define HAL_MISC_ENABLE_MDC_MDIO_PINS() \
1914 +{ \
1915 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_MDC_MDIO_PINS); \
1916 +}
1917 +
1918 +#define HAL_MISC_DISABLE_MDC_MDIO_PINS() \
1919 +{ \
1920 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_MDC_MDIO_PINS); \
1921 +}
1922 +
1923 +#define HAL_MISC_ENABLE_NIC_COL_PINS() \
1924 +{ \
1925 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_NIC_COL_PINS); \
1926 +}
1927 +
1928 +#define HAL_MISC_DISABLE_NIC_COL_PINS() \
1929 +{ \
1930 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_NIC_COL_PINS); \
1931 +}
1932 +
1933 +#define HAL_MISC_ENABLE_IDE_PINS() \
1934 +{ \
1935 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_IDE_PINS); \
1936 +}
1937 +
1938 +#define HAL_MISC_DISABLE_IDE_PINS() \
1939 +{ \
1940 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_IDE_PINS); \
1941 +}
1942 +
1943 +#define HAL_MISC_ENABLE_SRAM_BANK1_PINS() \
1944 +{ \
1945 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_SRAM_BANK1_PINS); \
1946 +}
1947 +
1948 +#define HAL_MISC_DISABLE_SRAM_BANK1_PINS() \
1949 +{ \
1950 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_SRAM_BANK1_PINS); \
1951 +}
1952 +
1953 +#define HAL_MISC_ENABLE_SRAM_BANK2_PINS() \
1954 +{ \
1955 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_SRAM_BANK2_PINS); \
1956 +}
1957 +
1958 +#define HAL_MISC_DISABLE_SRAM_BANK2_PINS() \
1959 +{ \
1960 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_SRAM_BANK2_PINS); \
1961 +}
1962 +
1963 +#define HAL_MISC_ENABLE_SRAM_BANK3_PINS() \
1964 +{ \
1965 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_SRAM_BANK3_PINS); \
1966 +}
1967 +
1968 +#define HAL_MISC_DISABLE_SRAM_BANK3_PINS() \
1969 +{ \
1970 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_SRAM_BANK3_PINS); \
1971 +}
1972 +
1973 +#define HAL_MISC_ENABLE_PCMCIA_PINS() \
1974 +{ \
1975 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_PCMCIA_PINS); \
1976 +}
1977 +
1978 +#define HAL_MISC_DISABLE_PCMCIA_PINS() \
1979 +{ \
1980 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_PCMCIA_PINS); \
1981 +}
1982 +
1983 +#define HAL_MISC_ENABLE_UART1_PINS() \
1984 +{ \
1985 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_UART1_PINS); \
1986 +}
1987 +
1988 +#define HAL_MISC_DISABLE_UART1_PINS() \
1989 +{ \
1990 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_UART1_PINS); \
1991 +}
1992 +
1993 +#define HAL_MISC_ENABLE_PCI_PINS() \
1994 +{ \
1995 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_PCI_PINS); \
1996 +}
1997 +
1998 +#define HAL_MISC_DISABLE_PCI_PINS() \
1999 +{ \
2000 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_PCI_PINS); \
2001 +}
2002 +
2003 +#define HAL_MISC_ENABLE_ALL_SHARED_GPIO_PINS() \
2004 +{ \
2005 + (MISC_GPIOA_PIN_ENABLE_REG) = (0x0); \
2006 + (MISC_GPIOB_PIN_ENABLE_REG) = (0x0); \
2007 +}
2008 +
2009 +#define HAL_MISC_DISABLE_ALL_SHARED_GPIO_PINS() \
2010 +{ \
2011 + (MISC_GPIOA_PIN_ENABLE_REG) = (0xFFFFFFFF); \
2012 + (MISC_GPIOB_PIN_ENABLE_REG) = (0xFFFFFFFF); \
2013 +}
2014 +
2015 +#define HAL_MISC_CONFIGURE_GPIOA_RESISTOR(pin_index, value) \
2016 +{ \
2017 + (MISC_GPIOA_RESISTOR_CONFIG_REG) &= ~(0x3 << (2 * pin_index)); \
2018 + (MISC_GPIOA_RESISTOR_CONFIG_REG) |= ((value & 0x3) << (2 * pin_index)); \
2019 +}
2020 +
2021 +#define HAL_MISC_CONFIGURE_GPIOA_DRIVE_STRENGTH(pin_index, value) \
2022 +{ \
2023 + (MISC_GPIOA_DRIVE_STRENGTH_CONFIG_REG) &= ~(0x1 << pin_index); \
2024 + (MISC_GPIOA_DRIVE_STRENGTH_CONFIG_REG) |= (value << pin_index); \
2025 +}
2026 +
2027 +#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE0() \
2028 +{ \
2029 + (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x0); \
2030 +}
2031 +
2032 +#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE1() \
2033 +{ \
2034 + (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x1); \
2035 +}
2036 +
2037 +#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE2() \
2038 +{ \
2039 + (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x2); \
2040 +}
2041 +
2042 +#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE3() \
2043 +{ \
2044 + (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x3); \
2045 +}
2046 +
2047 +
2048 +#endif // end of #ifndef _STAR_MISC_H_
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