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cns21xx: switch to 3.8
[openwrt/svn-archive/archive.git] / target / linux / cns21xx / patches-3.7 / 100-cns21xx-core.patch
1 --- a/arch/arm/Kconfig
2 +++ b/arch/arm/Kconfig
3 @@ -183,6 +183,11 @@ config NEED_RET_TO_USER
4 config ARCH_MTD_XIP
5 bool
6
7 +config ARM_L1_CACHE_SHIFT_4
8 + bool
9 + help
10 + Setting ARM L1 cache line size to 16 bytes.
11 +
12 config VECTORS_BASE
13 hex
14 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
15 @@ -362,6 +367,15 @@ config ARCH_CNS3XXX
16 help
17 Support for Cavium Networks CNS3XXX platform.
18
19 +config ARCH_CNS21XX
20 + bool "Cavium Networks CNS21xx family"
21 + select CPU_FA526
22 + select PLAT_FA
23 + select PLAT_FA_TIME
24 + select ARM_L1_CACHE_SHIFT_4
25 + help
26 + Support for Cavium Networks CNS21xx family.
27 +
28 config ARCH_CLPS711X
29 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
30 select ARCH_USES_GETTIMEOFFSET
31 @@ -1031,6 +1045,8 @@ source "arch/arm/mach-davinci/Kconfig"
32
33 source "arch/arm/mach-dove/Kconfig"
34
35 +source "arch/arm/mach-cns21xx/Kconfig"
36 +
37 source "arch/arm/mach-ep93xx/Kconfig"
38
39 source "arch/arm/mach-footbridge/Kconfig"
40 --- /dev/null
41 +++ b/arch/arm/mach-cns21xx/Kconfig
42 @@ -0,0 +1,6 @@
43 +if ARCH_CNS21XX
44 +
45 +menu "Cavium Networks CNS21xx based machines"
46 +endmenu
47 +
48 +endif
49 --- /dev/null
50 +++ b/arch/arm/mach-cns21xx/Makefile
51 @@ -0,0 +1,10 @@
52 +#
53 +# Makefile for the linux kernel.
54 +#
55 +
56 +# Object file lists.
57 +
58 +obj-y := core.o irq.o mm.o time.o
59 +
60 +# machine specific files
61 +
62 --- /dev/null
63 +++ b/arch/arm/mach-cns21xx/Makefile.boot
64 @@ -0,0 +1,3 @@
65 + zreladdr-y += 0x00008000
66 +params_phys-y := 0x00000100
67 +initrd_phys-y := 0x00C00000
68 --- a/arch/arm/Makefile
69 +++ b/arch/arm/Makefile
70 @@ -139,6 +139,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x0020
71 machine-$(CONFIG_ARCH_AT91) += at91
72 machine-$(CONFIG_ARCH_BCM2835) += bcm2835
73 machine-$(CONFIG_ARCH_CLPS711X) += clps711x
74 +machine-$(CONFIG_ARCH_CNS21XX) += cns21xx
75 machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
76 machine-$(CONFIG_ARCH_DAVINCI) += davinci
77 machine-$(CONFIG_ARCH_DOVE) += dove
78 --- /dev/null
79 +++ b/arch/arm/mach-cns21xx/common.h
80 @@ -0,0 +1,19 @@
81 +/*
82 + * Copyright (c) 2008 Cavium Networks
83 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
84 + *
85 + * This file is free software; you can redistribute it and/or modify
86 + * it under the terms of the GNU General Public License, Version 2, as
87 + * published by the Free Software Foundation.
88 + */
89 +
90 +#ifndef _MACH_CNS21XX_COMMON_H
91 +#define _MACH_CNS21XX_COMMON_H
92 +
93 +void cns21xx_restart(char mode, const char *cmd);
94 +void cns21xx_map_io(void);
95 +void cns21xx_init_irq(void);
96 +
97 +extern struct sys_timer cns21xx_timer;
98 +
99 +#endif /* _MACH_CNS21XX_COMMON_H */
100 --- /dev/null
101 +++ b/arch/arm/mach-cns21xx/mm.c
102 @@ -0,0 +1,170 @@
103 +/*
104 + * Copyright (c) 2008 Cavium Networks
105 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
106 + *
107 + * This file is free software; you can redistribute it and/or modify
108 + * it under the terms of the GNU General Public License, Version 2, as
109 + * published by the Free Software Foundation.
110 + */
111 +
112 +#include <linux/mm.h>
113 +#include <linux/init.h>
114 +
115 +#include <asm/mach/map.h>
116 +
117 +#include <mach/hardware.h>
118 +#include <mach/cns21xx.h>
119 +
120 +#include "common.h"
121 +
122 +/*
123 + * Standard IO mapping
124 + */
125 +static struct map_desc cns21xx_io_desc[] __initdata = {
126 + {
127 + .virtual = CNS21XX_FLASH_BANK0_BASE_VIRT,
128 + .pfn = __phys_to_pfn(CNS21XX_FLASH_BANK0_BASE),
129 + .length = SZ_256M,
130 + .type = MT_DEVICE
131 + }, {
132 + .virtual = CNS21XX_IDE_DEVICE_BASE_VIRT,
133 + .pfn = __phys_to_pfn(CNS21XX_IDE_DEVICE_BASE),
134 + .length = SZ_4K,
135 + .type = MT_DEVICE
136 + }, {
137 + .virtual = CNS21XX_GDMAC_BASE_VIRT,
138 + .pfn = __phys_to_pfn(CNS21XX_GDMAC_BASE),
139 + .length = SZ_4K,
140 + .type = MT_DEVICE
141 + }, {
142 + .virtual = CNS21XX_NIC_BASE_VIRT,
143 + .pfn = __phys_to_pfn(CNS21XX_NIC_BASE),
144 + .length = SZ_4K,
145 + .type = MT_DEVICE
146 + }, {
147 + .virtual = CNS21XX_SPI_BASE_VIRT,
148 + .pfn = __phys_to_pfn(CNS21XX_SPI_BASE),
149 + .length = SZ_4K,
150 + .type = MT_DEVICE
151 + }, {
152 + .virtual = CNS21XX_PCM_BASE_VIRT,
153 + .pfn = __phys_to_pfn(CNS21XX_PCM_BASE),
154 + .length = SZ_4K,
155 + .type = MT_DEVICE
156 + }, {
157 + .virtual = CNS21XX_I2C_BASE_VIRT,
158 + .pfn = __phys_to_pfn(CNS21XX_I2C_BASE),
159 + .length = SZ_4K,
160 + .type = MT_DEVICE
161 + }, {
162 + .virtual = CNS21XX_I2S_BASE_VIRT,
163 + .pfn = __phys_to_pfn(CNS21XX_I2S_BASE),
164 + .length = SZ_4K,
165 + .type = MT_DEVICE
166 + }, {
167 + .virtual = CNS21XX_DDRC_BASE_VIRT,
168 + .pfn = __phys_to_pfn(CNS21XX_DDRC_BASE),
169 + .length = SZ_4K,
170 + .type = MT_DEVICE
171 + }, {
172 + .virtual = CNS21XX_SMC_BASE_VIRT,
173 + .pfn = __phys_to_pfn(CNS21XX_SMC_BASE),
174 + .length = SZ_4K,
175 + .type = MT_DEVICE
176 + }, {
177 + .virtual = CNS21XX_IDE_CTRL_BASE_VIRT,
178 + .pfn = __phys_to_pfn(CNS21XX_IDE_CTRL_BASE),
179 + .length = SZ_4K,
180 + .type = MT_DEVICE
181 + }, {
182 + .virtual = CNS21XX_MISC_BASE_VIRT,
183 + .pfn = __phys_to_pfn(CNS21XX_MISC_BASE),
184 + .length = SZ_4K,
185 + .type = MT_DEVICE
186 + }, {
187 + .virtual = CNS21XX_CPM_BASE_VIRT,
188 + .pfn = __phys_to_pfn(CNS21XX_CPM_BASE),
189 + .length = SZ_4K,
190 + .type = MT_DEVICE
191 + }, {
192 + .virtual = CNS21XX_UART0_BASE_VIRT,
193 + .pfn = __phys_to_pfn(CNS21XX_UART0_BASE),
194 + .length = SZ_4K,
195 + .type = MT_DEVICE
196 + }, {
197 + .virtual = CNS21XX_UART1_BASE_VIRT,
198 + .pfn = __phys_to_pfn(CNS21XX_UART1_BASE),
199 + .length = SZ_4K,
200 + .type = MT_DEVICE
201 + }, {
202 + .virtual = CNS21XX_TIMER_BASE_VIRT,
203 + .pfn = __phys_to_pfn(CNS21XX_TIMER_BASE),
204 + .length = SZ_4K,
205 + .type = MT_DEVICE
206 + }, {
207 + .virtual = CNS21XX_WDT_BASE_VIRT,
208 + .pfn = __phys_to_pfn(CNS21XX_WDT_BASE),
209 + .length = SZ_4K,
210 + .type = MT_DEVICE
211 + }, {
212 + .virtual = CNS21XX_RTC_BASE_VIRT,
213 + .pfn = __phys_to_pfn(CNS21XX_RTC_BASE),
214 + .length = SZ_4K,
215 + .type = MT_DEVICE
216 + }, {
217 + .virtual = CNS21XX_GPIOA_BASE_VIRT,
218 + .pfn = __phys_to_pfn(CNS21XX_GPIOA_BASE),
219 + .length = SZ_4K,
220 + .type = MT_DEVICE
221 + }, {
222 + .virtual = CNS21XX_GPIOB_BASE_VIRT,
223 + .pfn = __phys_to_pfn(CNS21XX_GPIOB_BASE),
224 + .length = SZ_4K,
225 + .type = MT_DEVICE
226 + }, {
227 + .virtual = CNS21XX_PCI_CFGDATA_BASE_VIRT,
228 + .pfn = __phys_to_pfn(CNS21XX_PCI_CFGDATA_BASE),
229 + .length = SZ_4K,
230 + .type = MT_DEVICE
231 + }, {
232 + .virtual = CNS21XX_PCI_CFGADDR_BASE_VIRT,
233 + .pfn = __phys_to_pfn(CNS21XX_PCI_CFGADDR_BASE),
234 + .length = SZ_4K,
235 + .type = MT_DEVICE
236 + }, {
237 + .virtual = CNS21XX_OHCI_CONFIG_BASE_VIRT,
238 + .pfn = __phys_to_pfn(CNS21XX_OHCI_CONFIG_BASE),
239 + .length = SZ_4K,
240 + .type = MT_DEVICE
241 + }, {
242 + .virtual = CNS21XX_OHCI_CTRL_BASE_VIRT,
243 + .pfn = __phys_to_pfn(CNS21XX_OHCI_CTRL_BASE),
244 + .length = SZ_4K,
245 + .type = MT_DEVICE
246 + }, {
247 + .virtual = CNS21XX_EHCI_CONFIG_BASE_VIRT,
248 + .pfn = __phys_to_pfn(CNS21XX_EHCI_CONFIG_BASE),
249 + .length = SZ_4K,
250 + .type = MT_DEVICE
251 + }, {
252 + .virtual = CNS21XX_EHCI_CTRL_BASE_VIRT,
253 + .pfn = __phys_to_pfn(CNS21XX_EHCI_CTRL_BASE),
254 + .length = SZ_4K,
255 + .type = MT_DEVICE
256 + }, {
257 + .virtual = CNS21XX_USB_DEVICE_BASE_VIRT,
258 + .pfn = __phys_to_pfn(CNS21XX_USB_DEVICE_BASE),
259 + .length = SZ_4K,
260 + .type = MT_DEVICE
261 + }, {
262 + .virtual = CNS21XX_INTC_BASE_VIRT,
263 + .pfn = __phys_to_pfn(CNS21XX_INTC_BASE),
264 + .length = SZ_4K,
265 + .type = MT_DEVICE
266 + }
267 +};
268 +
269 +void __init cns21xx_map_io(void)
270 +{
271 + iotable_init(cns21xx_io_desc, ARRAY_SIZE(cns21xx_io_desc));
272 +}
273 --- /dev/null
274 +++ b/arch/arm/mach-cns21xx/include/mach/hardware.h
275 @@ -0,0 +1,20 @@
276 +/*
277 + * Copyright (c) 2008 Cavium Networks
278 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
279 + *
280 + * This file is free software; you can redistribute it and/or modify
281 + * it under the terms of the GNU General Public License, Version 2, as
282 + * published by the Free Software Foundation.
283 + */
284 +
285 +#ifndef _CNS21XX_HARDWARE_H
286 +#define _CNS21XX_HARDWARE_H
287 +
288 +#ifndef __ASSEMBLY__
289 +extern unsigned long cns21xx_get_pll_freq(void);
290 +extern unsigned long cns21xx_get_cpu_freq(void);
291 +extern unsigned long cns21xx_get_ahb_freq(void);
292 +extern unsigned long cns21xx_get_apb_freq(void);
293 +#endif
294 +
295 +#endif /* _CNS21XX_HARDWARE_H */
296 --- /dev/null
297 +++ b/arch/arm/mach-cns21xx/include/mach/debug-macro.S
298 @@ -0,0 +1,25 @@
299 +/*
300 + * Copyright (c) 2008 Cavium Networks
301 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
302 + *
303 + * This file is free software; you can redistribute it and/or modify
304 + * it under the terms of the GNU General Public License, Version 2, as
305 + * published by the Free Software Foundation.
306 + */
307 +
308 +#include <mach/cns21xx.h>
309 +
310 +/* TODO: make it configurable */
311 +#define CNS21XX_DEBUG_UART_BASE CNS21XX_UART0_BASE
312 +#define CNS21XX_DEBUG_UART_BASE_VIRT CNS21XX_UART0_BASE_VIRT
313 +
314 + .macro addruart, rp, rv
315 + mov \rp, #(CNS21XX_DEBUG_UART_BASE) @ physical
316 + mov \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0xff000000) @virtual
317 + orr \rv, \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0x00ff0000)
318 + orr \rv, \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0x0000ff00)
319 + orr \rv, \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0x000000ff)
320 + .endm
321 +
322 +#define UART_SHIFT 2
323 +#include <asm/hardware/debug-8250.S>
324 --- /dev/null
325 +++ b/arch/arm/mach-cns21xx/include/mach/entry-macro.S
326 @@ -0,0 +1,39 @@
327 +/*
328 + * Copyright (c) 2008 Cavium Networks
329 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
330 + *
331 + * This file is free software; you can redistribute it and/or modify
332 + * it under the terms of the GNU General Public License, Version 2, as
333 + * published by the Free Software Foundation.
334 + */
335 +
336 +#include <mach/cns21xx.h>
337 +#include <mach/irqs.h>
338 +
339 +#define INTC_IRQ_STATUS 0x1c
340 +
341 + .macro disable_fiq
342 + .endm
343 +
344 + .macro get_irqnr_preamble, base, tmp
345 + .endm
346 +
347 + .macro arch_ret_to_user, tmp1, tmp2
348 + .endm
349 +
350 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
351 + ldr \base, =(CNS21XX_INTC_BASE_VIRT + INTC_IRQ_STATUS)
352 + ldr \irqstat, [\base]
353 + mov \irqnr, #0
354 +9001:
355 + tst \irqstat, #1
356 + bne 9002f
357 + add \irqnr, \irqnr, #1
358 + mov \irqstat, \irqstat, lsr #1
359 + cmp \irqnr, #CNS21XX_NR_INTC_IRQS
360 + bcc 9001b
361 +9002:
362 + .endm
363 +
364 + .macro irq_prio_table
365 + .endm
366 --- /dev/null
367 +++ b/arch/arm/mach-cns21xx/include/mach/io.h
368 @@ -0,0 +1,18 @@
369 +/*
370 + * Copyright (c) 2008 Cavium Networks
371 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
372 + *
373 + * This file is free software; you can redistribute it and/or modify
374 + * it under the terms of the GNU General Public License, Version 2, as
375 + * published by the Free Software Foundation.
376 + */
377 +
378 +#ifndef _CNS21XX_IO_H
379 +#define _CNS21XX_IO_H
380 +
381 +#define IO_SPACE_LIMIT 0xffffffff
382 +
383 +#define __io(p) __typesafe_io(p)
384 +#define __mem_pci(a) (a)
385 +
386 +#endif /* _CNS21XX_IO_H */
387 --- /dev/null
388 +++ b/arch/arm/mach-cns21xx/include/mach/irqs.h
389 @@ -0,0 +1,53 @@
390 +/*
391 + * Copyright (c) 2008 Cavium Networks
392 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
393 + *
394 + * This file is free software; you can redistribute it and/or modify
395 + * it under the terms of the GNU General Public License, Version 2, as
396 + * published by the Free Software Foundation.
397 + */
398 +
399 +#ifndef _CNS21XX_IRQS_H
400 +#define _CNS21XX_IRQS_H
401 +
402 +#define CNS21XX_IRQ_TIMER1 0
403 +#define CNS21XX_IRQ_TIMER2 1
404 +#define CNS21XX_IRQ_CPM 2
405 +#define CNS21XX_IRQ_WDT 3
406 +#define CNS21XX_IRQ_GPIO 4
407 +#define CNS21XX_IRQ_PCI_INTA 5
408 +#define CNS21XX_IRQ_PCI_INTB 6
409 +#define CNS21XX_IRQ_PCI_BROKEN 7
410 +#define CNS21XX_IRQ_AHB2PCI 8
411 +#define CNS21XX_IRQ_UART0 9
412 +#define CNS21XX_IRQ_UART1 10
413 +#define CNS21XX_IRQ_GDMAC_TC 11
414 +#define CNS21XX_IRQ_GDMAC_ERR 12
415 +#define CNS21XX_IRQ_PCMCIA 13
416 +#define CNS21XX_IRQ_RTC 14
417 +#define CNS21XX_IRQ_PCM 15
418 +#define CNS21XX_IRQ_USB_DEVICE 16
419 +#define CNS21XX_IRQ_IDE 17
420 +#define CNS21XX_IRQ_NIC_STATUS 18
421 +#define CNS21XX_IRQ_NIC_TXTC 19
422 +#define CNS21XX_IRQ_NIC_RXRC 20
423 +#define CNS21XX_IRQ_NIC_TXQE 21
424 +#define CNS21XX_IRQ_NIC_RXQF 22
425 +#define CNS21XX_IRQ_OHCI 23
426 +#define CNS21XX_IRQ_EHCI 24
427 +#define CNS21XX_IRQ_I2S 25
428 +#define CNS21XX_IRQ_SPI 26
429 +#define CNS21XX_IRQ_I2C 27
430 +#define CNS21XX_IRQ_USB_VBUS 28
431 +#define CNS21XX_IRQ_EXT_29 29
432 +#define CNS21XX_IRQ_EXT_30 30
433 +#define CNS21XX_IRQ_HSDMAC 31
434 +
435 +#define CNS21XX_GPIO_IRQ_BASE 32
436 +
437 +#define CNS21XX_NR_INTC_IRQS 32
438 +#define CNS21XX_NR_GPIO_IRQS 64
439 +
440 +#define NR_IRQS 96
441 +
442 +#endif /* _CNS21XX_IRQS_H */
443 --- /dev/null
444 +++ b/arch/arm/mach-cns21xx/include/mach/timex.h
445 @@ -0,0 +1,15 @@
446 +/*
447 + * Copyright (c) 2008 Cavium Networks
448 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
449 + *
450 + * This file is free software; you can redistribute it and/or modify
451 + * it under the terms of the GNU General Public License, Version 2, as
452 + * published by the Free Software Foundation.
453 + */
454 +
455 +#ifndef _CNS21XX_TIMEX_H
456 +#define _CNS21XX_TIMEX_H
457 +
458 +#define CLOCK_TICK_RATE 43750000
459 +
460 +#endif /* _CNS21XX_TIMEX_H */
461 --- /dev/null
462 +++ b/arch/arm/mach-cns21xx/include/mach/uncompress.h
463 @@ -0,0 +1,40 @@
464 +/*
465 + * Copyright (c) 2008 Cavium Networks
466 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
467 + *
468 + * This file is free software; you can redistribute it and/or modify
469 + * it under the terms of the GNU General Public License, Version 2, as
470 + * published by the Free Software Foundation.
471 + */
472 +
473 +#ifndef _CNS21XX_UNCOMPRESS_H
474 +#define _CNS21XX_UNCOMPRESS_H
475 +
476 +#define UART_BASE 0x78000000
477 +
478 +#define UART_REG(offs) (*((volatile unsigned int *)(UART_BASE + offs)))
479 +
480 +#define UART_THR UART_REG(0x00)
481 +#define UART_LSR UART_REG(0x14)
482 +#define THR_EMPTY (1 << 5)
483 +
484 +#define UART_THR_EMPTY() (((UART_LSR) & THR_EMPTY) == (THR_EMPTY))
485 +
486 +static void putc(int c)
487 +{
488 + if (c != 0) {
489 + while (!UART_THR_EMPTY())
490 + barrier();
491 +
492 + UART_THR = (int)(c & 0xFF);
493 + }
494 +}
495 +
496 +static inline void flush(void)
497 +{
498 +}
499 +
500 +#define arch_decomp_setup()
501 +#define arch_decomp_wdog()
502 +
503 +#endif /* _CNS21XX_UNCOMPRESS_H */
504 --- /dev/null
505 +++ b/arch/arm/mach-cns21xx/include/mach/system.h
506 @@ -0,0 +1,30 @@
507 +/*
508 + * Copyright (c) 2008 Cavium Networks
509 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
510 + *
511 + * This file is free software; you can redistribute it and/or modify
512 + * it under the terms of the GNU General Public License, Version 2, as
513 + * published by the Free Software Foundation.
514 + */
515 +
516 +#ifndef _CNS21XX_SYSTEM_H
517 +#define _CNS21XX_SYSTEM_H
518 +
519 +#include <mach/cns21xx.h>
520 +#include <mach/cns21xx_powermgmt.h>
521 +
522 +static inline void arch_idle(void)
523 +{
524 + /*
525 + * Because of broken hardware we have to enable interrupts or the CPU
526 + * will never wakeup... Acctualy it is not very good to enable
527 + * interrupts here since scheduler can miss a tick, but there is
528 + * no other way around this. Platforms that needs it for power saving
529 + * should call enable_hlt() in init code, since by default it is
530 + * disabled.
531 + */
532 + local_irq_enable();
533 + cpu_do_idle();
534 +}
535 +
536 +#endif /* _CNS21XX_SYSTEM_H */
537 --- /dev/null
538 +++ b/arch/arm/mach-cns21xx/irq.c
539 @@ -0,0 +1,176 @@
540 +/*
541 + * Copyright (c) 2008 Cavium Networks
542 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
543 + *
544 + * This file is free software; you can redistribute it and/or modify
545 + * it under the terms of the GNU General Public License, Version 2, as
546 + * published by the Free Software Foundation.
547 + */
548 +
549 +#include <linux/init.h>
550 +#include <linux/interrupt.h>
551 +#include <linux/irq.h>
552 +#include <linux/io.h>
553 +#include <linux/ioport.h>
554 +
555 +#include <asm/system_misc.h>
556 +
557 +#include <mach/cns21xx.h>
558 +
559 +#define INTC_INTERRUPT_RAW_STATUS_REG 0x000
560 +#define INTC_EDGE_INTERRUPT_SOURCE_CLEAR_REG 0x004
561 +#define INTC_INTERRUPT_MASK_REG 0x008
562 +#define INTC_INTERRUPT_MASK_CLEAR_REG 0x00c
563 +#define INTC_INTERRUPT_TRIGGER_MODE_REG 0x010
564 +#define INTC_INTERRUPT_TRIGGER_LEVEL_REG 0x014
565 +#define INTC_FIQ_SELECT_REG 0x018
566 +#define INTC_IRQ_STATUS_REG 0x01c
567 +#define INTC_FIQ_STATUS_REG 0x020
568 +#define INTC_SOFTWARE_INTERRUPT_REG 0x024
569 +#define INTC_SOFTWARE_INTERRUPT_CLEAR_REG 0x028
570 +#define INTC_SOFTWARE_PRIORITY_MASK_REG 0x02c
571 +#define INTC_POWER_MANAGEMENT_INTERRUPT_REG 0x034
572 +
573 +#define INTC_VECTOR_ADDRESS_REG(_x) ((_x) + 0x040)
574 +#define INTC_PRIORITY_REG(_x) ((_x) + 0x0c0)
575 +#define INTC_IRQ_VECTOR_ADDRESS_REG 0x140
576 +#define INTC_VECTOR_INTERRUPT_ENABLE_REG 0x144
577 +
578 +#define INTC_SIZE 0x148
579 +
580 +static unsigned int cns21xx_irq_types[CNS21XX_NR_INTC_IRQS] = {
581 + [CNS21XX_IRQ_TIMER1] = IRQ_TYPE_EDGE_RISING,
582 + [CNS21XX_IRQ_TIMER2] = IRQ_TYPE_EDGE_RISING,
583 + [CNS21XX_IRQ_CPM] = IRQ_TYPE_EDGE_FALLING,
584 + [CNS21XX_IRQ_WDT] = IRQ_TYPE_EDGE_RISING,
585 + [CNS21XX_IRQ_GPIO] = IRQ_TYPE_NONE,
586 + [CNS21XX_IRQ_PCI_INTA] = IRQ_TYPE_LEVEL_LOW,
587 + [CNS21XX_IRQ_PCI_INTB] = IRQ_TYPE_LEVEL_LOW,
588 + [CNS21XX_IRQ_PCI_BROKEN] = IRQ_TYPE_LEVEL_HIGH,
589 + [CNS21XX_IRQ_AHB2PCI] = IRQ_TYPE_LEVEL_HIGH,
590 + [CNS21XX_IRQ_UART0] = IRQ_TYPE_LEVEL_HIGH,
591 + [CNS21XX_IRQ_UART1] = IRQ_TYPE_LEVEL_HIGH,
592 + [CNS21XX_IRQ_GDMAC_TC] = IRQ_TYPE_LEVEL_HIGH,
593 + [CNS21XX_IRQ_GDMAC_ERR] = IRQ_TYPE_LEVEL_HIGH,
594 + [CNS21XX_IRQ_PCMCIA] = IRQ_TYPE_NONE,
595 + [CNS21XX_IRQ_RTC] = IRQ_TYPE_LEVEL_HIGH,
596 + [CNS21XX_IRQ_PCM] = IRQ_TYPE_LEVEL_LOW,
597 + [CNS21XX_IRQ_USB_DEVICE] = IRQ_TYPE_LEVEL_LOW,
598 + [CNS21XX_IRQ_IDE] = IRQ_TYPE_LEVEL_HIGH,
599 + [CNS21XX_IRQ_NIC_STATUS] = IRQ_TYPE_LEVEL_HIGH,
600 + [CNS21XX_IRQ_NIC_TXTC] = IRQ_TYPE_EDGE_RISING,
601 + [CNS21XX_IRQ_NIC_RXRC] = IRQ_TYPE_EDGE_RISING,
602 + [CNS21XX_IRQ_NIC_TXQE] = IRQ_TYPE_EDGE_RISING,
603 + [CNS21XX_IRQ_NIC_RXQF] = IRQ_TYPE_EDGE_RISING,
604 + [CNS21XX_IRQ_OHCI] = IRQ_TYPE_LEVEL_LOW,
605 + [CNS21XX_IRQ_EHCI] = IRQ_TYPE_LEVEL_LOW,
606 + [CNS21XX_IRQ_I2S] = IRQ_TYPE_LEVEL_LOW,
607 + [CNS21XX_IRQ_SPI] = IRQ_TYPE_LEVEL_LOW,
608 + [CNS21XX_IRQ_I2C] = IRQ_TYPE_LEVEL_LOW,
609 + [CNS21XX_IRQ_USB_VBUS] = IRQ_TYPE_EDGE_RISING,
610 + [CNS21XX_IRQ_EXT_29] = IRQ_TYPE_NONE,
611 + [CNS21XX_IRQ_EXT_30] = IRQ_TYPE_NONE,
612 + [CNS21XX_IRQ_HSDMAC] = IRQ_TYPE_EDGE_RISING,
613 +};
614 +
615 +static void __iomem *cns21xx_intc_base;
616 +
617 +static inline void cns21xx_intc_writel(u32 val, unsigned int reg)
618 +{
619 + __raw_writel(val, cns21xx_intc_base + reg);
620 +}
621 +
622 +static inline u32 cns21xx_intc_readl(unsigned int reg)
623 +{
624 + return __raw_readl(cns21xx_intc_base + reg);
625 +}
626 +
627 +static void cns21xx_irq_ack(struct irq_data *d)
628 +{
629 + cns21xx_intc_writel(1 << d->irq, INTC_EDGE_INTERRUPT_SOURCE_CLEAR_REG);
630 +}
631 +
632 +static void cns21xx_irq_mask(struct irq_data *d)
633 +{
634 + cns21xx_intc_writel(1 << d->irq, INTC_INTERRUPT_MASK_REG);
635 +}
636 +
637 +static void cns21xx_irq_unmask(struct irq_data *d)
638 +{
639 + cns21xx_intc_writel(1 << d->irq, INTC_INTERRUPT_MASK_CLEAR_REG);
640 +}
641 +
642 +static struct irq_chip cns21xx_irq_chip = {
643 + .name = "INTC",
644 + .irq_ack = cns21xx_irq_ack,
645 + .irq_mask = cns21xx_irq_mask,
646 + .irq_unmask = cns21xx_irq_unmask,
647 +};
648 +
649 +static struct resource cns21xx_intc_resource = {
650 + .name = "INTC",
651 + .flags = IORESOURCE_MEM,
652 + .start = CNS21XX_INTC_BASE,
653 + .end = CNS21XX_INTC_BASE + INTC_SIZE - 1,
654 +};
655 +
656 +void __init cns21xx_init_irq(void)
657 +{
658 + unsigned int mode = 0;
659 + unsigned int level = 0;
660 + int i;
661 +
662 + /*
663 + * Disable arch_idle() by default since it is buggy
664 + * For more info see arch/arm/mach-cns21xx/include/mach/system.h
665 + */
666 + disable_hlt();
667 +
668 + request_resource(&iomem_resource, &cns21xx_intc_resource);
669 + cns21xx_intc_base = ioremap(cns21xx_intc_resource.start, INTC_SIZE);
670 +
671 + cns21xx_intc_writel(0xffffffff, INTC_INTERRUPT_MASK_REG);
672 + cns21xx_intc_writel(0xffffffff, INTC_EDGE_INTERRUPT_SOURCE_CLEAR_REG);
673 + cns21xx_intc_writel(0xffffffff, INTC_SOFTWARE_INTERRUPT_CLEAR_REG);
674 + cns21xx_intc_writel(0, INTC_SOFTWARE_PRIORITY_MASK_REG);
675 + cns21xx_intc_writel(0, INTC_FIQ_SELECT_REG);
676 + cns21xx_intc_writel(0, INTC_VECTOR_INTERRUPT_ENABLE_REG);
677 +
678 + for (i = 0; i < ARRAY_SIZE(cns21xx_irq_types); i++) {
679 + irq_flow_handler_t handler;
680 +
681 + switch (cns21xx_irq_types[i]) {
682 + case IRQ_TYPE_EDGE_RISING:
683 + handler = handle_edge_irq;
684 + mode |= (1 << i);
685 + break;
686 +
687 + case IRQ_TYPE_EDGE_FALLING:
688 + handler = handle_edge_irq;
689 + mode |= (1 << i);
690 + level |= (1 << i);
691 + break;
692 +
693 + case IRQ_TYPE_LEVEL_LOW:
694 + handler = handle_level_irq;
695 + level |= (1 << i);
696 + break;
697 +
698 + case IRQ_TYPE_LEVEL_HIGH:
699 + case IRQ_TYPE_NONE:
700 + handler = handle_level_irq;
701 + break;
702 +
703 + default:
704 + BUG();
705 + break;
706 + }
707 +
708 + irq_set_chip(i, &cns21xx_irq_chip);
709 + irq_set_handler(i, handler);
710 + set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
711 + }
712 +
713 + cns21xx_intc_writel(mode, INTC_INTERRUPT_TRIGGER_MODE_REG);
714 + cns21xx_intc_writel(level, INTC_INTERRUPT_TRIGGER_LEVEL_REG);
715 +}
716 --- /dev/null
717 +++ b/arch/arm/mach-cns21xx/time.c
718 @@ -0,0 +1,28 @@
719 +/*
720 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
721 + *
722 + * This file is free software; you can redistribute it and/or modify
723 + * it under the terms of the GNU General Public License, Version 2, as
724 + * published by the Free Software Foundation.
725 + */
726 +
727 +#include <linux/init.h>
728 +#include <linux/irq.h>
729 +
730 +#include <asm/mach/time.h>
731 +
732 +#include <plat/time.h>
733 +#include <mach/hardware.h>
734 +#include <mach/cns21xx.h>
735 +
736 +#include "common.h"
737 +
738 +static void __init cns21xx_timer_init(void)
739 +{
740 + fa_timer_init(CNS21XX_TIMER_BASE, CNS21XX_IRQ_TIMER1, FA_TIMER1,
741 + cns21xx_get_apb_freq());
742 +}
743 +
744 +struct sys_timer cns21xx_timer = {
745 + .init = cns21xx_timer_init,
746 +};
747 --- /dev/null
748 +++ b/arch/arm/mach-cns21xx/include/mach/cns21xx_powermgmt.h
749 @@ -0,0 +1,591 @@
750 +/*
751 + * Copyright (c) 2008 Cavium Networks
752 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
753 + *
754 + * This file is free software; you can redistribute it and/or modify
755 + * it under the terms of the GNU General Public License, Version 2, as
756 + * published by the Free Software Foundation.
757 + */
758 +
759 +#ifndef _CNS21XX_POWERMGMT_H
760 +#define _CNS21XX_POWERMGMT_H
761 +
762 +#define PWRMGT_MEM_MAP_VALUE(reg_offset) \
763 + (*((u32 volatile *)(CNS21XX_CPM_BASE_VIRT + reg_offset)))
764 +
765 +/*
766 + * define access macros
767 + */
768 +#define PWRMGT_CLOCK_GATE_CONTROL0_REG PWRMGT_MEM_MAP_VALUE(0x00)
769 +#define PWRMGT_CLOCK_GATE_CONTROL1_REG PWRMGT_MEM_MAP_VALUE(0x04)
770 +#define PWRMGT_SOFTWARE_RESET_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x08)
771 +#define PWRMGT_SYSTEM_CLOCK_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x0C)
772 +#define PWRMGT_PLL_POWER_DOWN_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x10)
773 +#define PWRMGT_CPU_INITIALIZATION_REG PWRMGT_MEM_MAP_VALUE(0x14)
774 +#define PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x1C)
775 +#define PWRMGT_USB_DEVICE_POWERMGT_REG PWRMGT_MEM_MAP_VALUE(0x20)
776 +#define PWRMGT_REGULATOR_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x24)
777 +#define PWRMGT_RTC_XTAL_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x28)
778 +#define PWRMGT_PLL250_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x2C)
779 +
780 +
781 +/*
782 + * define constants macros
783 + */
784 +#define PWRMGT_GLOBAL_SOFTWARE_RESET_MASK_BIT_INDEX 0
785 +#define PWRMGT_PCMCIA_SOFTWARE_RESET_BIT_INDEX 1
786 +#define PWRMGT_IDE_SOFTWARE_RESET_BIT_INDEX 2
787 +#define PWRMGT_VIC_SOFTWARE_RESET_BIT_INDEX 3
788 +#define PWRMGT_DMA_SOFTWARE_RESET_BIT_INDEX 4
789 +#define PWRMGT_NIC_SOFTWARE_RESET_BIT_INDEX 5
790 +#define PWRMGT_USB_HOST_SOFTWARE_RESET_BIT_INDEX 6
791 +#define PWRMGT_PCI_BRIDGE_SOFTWARE_RESET_BIT_INDEX 7
792 +#define PWRMGT_P2S_SOFTWARE_RESET_BIT_INDEX 8
793 +#define PWRMGT_UART0_SOFTWARE_RESET_BIT_INDEX 9
794 +#define PWRMGT_UART1_SOFTWARE_RESET_BIT_INDEX 10
795 +#define PWRMGT_TIMER_SOFTWARE_RESET_BIT_INDEX 11
796 +#define PWRMGT_WDTIMER_SOFTWARE_RESET_BIT_INDEX 12
797 +#define PWRMGT_GPIO_SOFTWARE_RESET_BIT_INDEX 13
798 +#define PWRMGT_USB_DEVICE_SOFTWARE_RESET_BIT_INDEX 14
799 +#define PWRMGT_FAST_ETHERNET_PHY_SOFTWARE_RESET_BIT_INDEX 15
800 +#define PWRMGT_HSDMA_SOFTWARE_RESET_BIT_INDEX 16
801 +
802 +#define PWRMGT_PLL_FREQUENCY_175MHZ (0 << 0)
803 +#define PWRMGT_PLL_FREQUENCY_200MHZ (1 << 0)
804 +#define PWRMGT_PLL_FREQUENCY_225MHZ (2 << 0)
805 +#define PWRMGT_PLL_FREQUENCY_250MHZ (3 << 0)
806 +
807 +#define PWRMGT_CPUCLK_DIVIDER_BY_1 (0 << 2)
808 +#define PWRMGT_CPUCLK_DIVIDER_BY_2 (1 << 2)
809 +#define PWRMGT_CPUCLK_DIVIDER_BY_3 (2 << 2)
810 +#define PWRMGT_CPUCLK_DIVIDER_BY_4 (3 << 2)
811 +
812 +#define PWRMGT_HCLK_DIVIDER_BY_1 (0 << 4)
813 +#define PWRMGT_HCLK_DIVIDER_BY_2 (1 << 4)
814 +#define PWRMGT_HCLK_DIVIDER_BY_3 (2 << 4)
815 +#define PWRMGT_HCLK_DIVIDER_BY_4 (3 << 4)
816 +
817 +#define PWRMGT_HCLK_SOURCE_FCLK (0 << 6)
818 +#define PWRMGT_HCLK_SOURCE_125MHZ (1 << 6)
819 +
820 +#define PWRMGT_PCLK_DIVIDER_BY_1 (0 << 8)
821 +#define PWRMGT_PCLK_DIVIDER_BY_2 (1 << 8)
822 +#define PWRMGT_PCLK_DIVIDER_BY_3 (2 << 8)
823 +#define PWRMGT_PCLK_DIVIDER_BY_4 (3 << 8)
824 +
825 +#define PWRMGT_PCICLK_DIVIDER_BY_1 (0 << 10)
826 +#define PWRMGT_PCICLK_DIVIDER_BY_2 (1 << 10)
827 +#define PWRMGT_PCICLK_DIVIDER_BY_3 (2 << 10)
828 +#define PWRMGT_PCICLK_DIVIDER_BY_4 (3 << 10)
829 +
830 +
831 +#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_1 1
832 +#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_2 2
833 +#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_3 3
834 +#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_4 4
835 +
836 +#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_1 1
837 +#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_2 2
838 +#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_3 3
839 +#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_4 4
840 +
841 +#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_1 1
842 +#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_2 2
843 +#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_3 3
844 +#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_4 4
845 +
846 +/*
847 + * Macro defines for Clock Gate Control
848 + */
849 +#define HAL_PWRMGT_DISABLE_DRAMC_CLOCK() \
850 +{ \
851 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1); \
852 +}
853 +
854 +
855 +#define HAL_PWRMGT_ENABLE_NIC_CLOCK() \
856 +{ \
857 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 0); \
858 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x0F << 20); \
859 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 5); \
860 +}
861 +
862 +#define HAL_PWRMGT_DISABLE_NIC_CLOCK() \
863 +{ \
864 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x0F << 20); \
865 +}
866 +
867 +
868 +#define HAL_PWRMGT_ENABLE_PCI_BRIDGE_33M_CLOCK() \
869 +{ \
870 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 1); \
871 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 10); \
872 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 10); \
873 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 28) | (0x1 << 30); \
874 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 7); \
875 +}
876 +
877 +#define HAL_PWRMGT_ENABLE_PCI_BRIDGE_66M_CLOCK() \
878 +{ \
879 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 1); \
880 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 10); \
881 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x0 << 10); \
882 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 28) | (0x1 << 30); \
883 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 7); \
884 +}
885 +
886 +#define HAL_PWRMGT_DISABLE_PCI_CLOCK() \
887 +{ \
888 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 28) | (0x1 << 30)); \
889 +}
890 +
891 +
892 +#define HAL_PWRMGT_ENABLE_USB_CLOCK() \
893 +{ \
894 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0xF << 1); \
895 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 24); \
896 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 28); \
897 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 6) | (0x1 << 14); \
898 +}
899 +
900 +#define HAL_PWRMGT_DISABLE_USB_CLOCK() \
901 +{ \
902 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1 << 24); \
903 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 28); \
904 +}
905 +
906 +
907 +#define HAL_PWRMGT_ENABLE_DMA_CLOCK() \
908 +{ \
909 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 16); \
910 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 4); \
911 +}
912 +
913 +#define HAL_PWRMGT_DISABLE_DMA_CLOCK() \
914 +{ \
915 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1 << 16); \
916 +}
917 +
918 +
919 +#define HAL_PWRMGT_ENABLE_IDE_CLOCK() \
920 +{ \
921 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 8) | (0x1 << 9); \
922 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 2); \
923 +}
924 +
925 +#define HAL_PWRMGT_DISABLE_IDE_CLOCK() \
926 +{ \
927 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 8) | (0x1 << 9)); \
928 +}
929 +
930 +
931 +#define HAL_PWRMGT_ENABLE_UART0_CLOCK() \
932 +{ \
933 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~((0x1 << 1) | (0x1 << 2) | (0x1 << 5)); \
934 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 12); \
935 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 9); \
936 +}
937 +
938 +#define HAL_PWRMGT_DISABLE_UART0_CLOCK() \
939 +{ \
940 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 12); \
941 +}
942 +
943 +
944 +#define HAL_PWRMGT_ENABLE_UART1_CLOCK() \
945 +{ \
946 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~((0x1 << 1) | (0x1 << 2) | (0x1 << 5)); \
947 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 13); \
948 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 10); \
949 +}
950 +
951 +#define HAL_PWRMGT_DISABLE_UART1_CLOCK() \
952 +{ \
953 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 13); \
954 +}
955 +
956 +
957 +#define HAL_PWRMGT_ENABLE_PCMCIA_CLOCK() \
958 +{ \
959 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 4) | (0x1 << 5); \
960 +}
961 +
962 +#define HAL_PWRMGT_DISABLE_PCMCIA_CLOCK() \
963 +{ \
964 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 4) | (0x1 << 5)); \
965 +}
966 +
967 +
968 +#define HAL_PWRMGT_ENABLE_GPIO_CLOCK() \
969 +{ \
970 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 25); \
971 +}
972 +
973 +#define HAL_PWRMGT_DISABLE_GPIO_CLOCK() \
974 +{ \
975 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 25); \
976 +}
977 +
978 +
979 +#define HAL_PWRMGT_ENABLE_WDTIMER_CLOCK() \
980 +{ \
981 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 21) | (0x1 << 22); \
982 +}
983 +
984 +#define HAL_PWRMGT_DISABLE_WDTIMER_CLOCK() \
985 +{ \
986 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 21) | (0x1 << 22)); \
987 +}
988 +
989 +
990 +#define HAL_PWRMGT_ENABLE_RTC_CLOCK() \
991 +{ \
992 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 23); \
993 +}
994 +
995 +#define HAL_PWRMGT_DISABLE_RTC_CLOCK() \
996 +{ \
997 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 23); \
998 +}
999 +
1000 +
1001 +#define HAL_PWRMGT_ENABLE_TIMER_CLOCK() \
1002 +{ \
1003 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 17) | (0x1 << 18) | (0x1 << 19); \
1004 +}
1005 +
1006 +#define HAL_PWRMGT_DISABLE_TIMER_CLOCK() \
1007 +{ \
1008 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 17) | (0x1 << 18) | (0x1 << 19)); \
1009 +}
1010 +
1011 +
1012 +#define HAL_PWRMGT_ENABLE_I2C_CLOCK() \
1013 +{ \
1014 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 1); \
1015 +}
1016 +
1017 +#define HAL_PWRMGT_DISABLE_I2C_CLOCK() \
1018 +{ \
1019 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 1); \
1020 +}
1021 +
1022 +
1023 +#define HAL_PWRMGT_ENABLE_I2S_CLOCK() \
1024 +{ \
1025 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~((0x1 << 5) | (0x1 << 6)); \
1026 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 1) | (0x1 << 10); \
1027 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 8); \
1028 +}
1029 +
1030 +#define HAL_PWRMGT_DISABLE_I2S_CLOCK() \
1031 +{ \
1032 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 1) | (0x1 << 10)); \
1033 +}
1034 +
1035 +
1036 +#define HAL_PWRMGT_ENABLE_PCM_CLOCK() \
1037 +{ \
1038 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 5); \
1039 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 1) | (0x1 << 6); \
1040 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 8); \
1041 +}
1042 +
1043 +#define HAL_PWRMGT_DISABLE_PCM_CLOCK() \
1044 +{ \
1045 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 1) | (0x1 << 6)); \
1046 +}
1047 +
1048 +
1049 +#define HAL_PWRMGT_ENABLE_SPI_CLOCK() \
1050 +{ \
1051 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 0) | (0x1 << 1); \
1052 +}
1053 +
1054 +#define HAL_PWRMGT_DISABLE_SPI_CLOCK() \
1055 +{ \
1056 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 0) | (0x1 << 1)); \
1057 +}
1058 +
1059 +
1060 +#define HAL_PWRMGT_ENABLE_VIC_CLOCK() \
1061 +{ \
1062 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 12); \
1063 +}
1064 +
1065 +#define HAL_PWRMGT_DISABLE_VIC_CLOCK() \
1066 +{ \
1067 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1 << 12); \
1068 +}
1069 +
1070 +
1071 +#define HAL_PWRMGT_ENABLE_SMC_CLOCK() \
1072 +{ \
1073 + PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 4) | (0x1 << 5); \
1074 +}
1075 +
1076 +#define HAL_PWRMGT_DISABLE_SMC_CLOCK() \
1077 +{ \
1078 + PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 4) | (0x1 << 5)); \
1079 +}
1080 +
1081 +
1082 +#define HAL_PWRMGT_ENABLE_HSDMA_CLOCK() \
1083 +{ \
1084 + PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 29); \
1085 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 16); \
1086 +}
1087 +
1088 +#define HAL_PWRMGT_DISABLE_HSDMA_CLOCK() \
1089 +{ \
1090 + PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 29); \
1091 +}
1092 +
1093 +
1094 +
1095 +/*
1096 + * Macro defines for Reset Control
1097 + */
1098 +#define HAL_PWRMGT_GLOBAL_SOFTWARE_RESET() \
1099 +{ \
1100 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1); \
1101 + PWRMGT_SOFTWARE_RESET_CONTROL_REG &= ~(0x1); \
1102 +}
1103 +
1104 +
1105 +/*
1106 + * Macro defines for System Clock Control
1107 + */
1108 +#define HAL_PWRMGT_SET_PLL_FREQUENCY_175MHZ() \
1109 +{ \
1110 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1111 +}
1112 +
1113 +
1114 +#define HAL_PWRMGT_SET_PLL_FREQUENCY_200MHZ() \
1115 +{ \
1116 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1117 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= 0x1; \
1118 +}
1119 +
1120 +
1121 +#define HAL_PWRMGT_SET_PLL_FREQUENCY_225MHZ() \
1122 +{ \
1123 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1124 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= 0x2; \
1125 +}
1126 +
1127 +
1128 +#define HAL_PWRMGT_SET_PLL_FREQUENCY_250MHZ() \
1129 +{ \
1130 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1131 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= 0x3; \
1132 +}
1133 +
1134 +
1135 +#define HAL_PWRMGT_CONFIG_PLLCLK_TO_CPUCLK_RATIO(ratio) \
1136 +{ \
1137 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 2); \
1138 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (((ratio - 1) & 0x3) << 2); \
1139 +}
1140 +
1141 +
1142 +#define HAL_PWRMGT_CONFIG_CPUCLK_TO_HCLK_RATIO(ratio) \
1143 +{ \
1144 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 4); \
1145 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (((ratio - 1) & 0x3) << 4); \
1146 +}
1147 +
1148 +
1149 +#define HAL_PWRMGT_HCLK_SOURCE_FCLK() \
1150 +{ \
1151 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x1 << 6); \
1152 +}
1153 +
1154 +
1155 +#define HAL_PWRMGT_HCLK_SOURCE_125MHZ() \
1156 +{ \
1157 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 6); \
1158 +}
1159 +
1160 +
1161 +#define HAL_PWRMGT_GIGA_NIC_CLOCK_SOURCE_HCLK() \
1162 +{ \
1163 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x1 << 7); \
1164 +}
1165 +
1166 +
1167 +#define HAL_PWRMGT_GIGA_NIC_CLOCK_SOURCE_62_5MHZ() \
1168 +{ \
1169 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 7); \
1170 +}
1171 +
1172 +
1173 +#define HAL_PWRMGT_CONFIG_HCLK_TO_PCLK_RATIO(ratio) \
1174 +{ \
1175 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 8); \
1176 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (((ratio - 1) & 0x3) << 8); \
1177 +}
1178 +
1179 +
1180 +#define HAL_PWRMGT_I2S_CLOCK_SOURCE_8192000HZ() \
1181 +{ \
1182 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 12); \
1183 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x0 << 12); \
1184 +}
1185 +
1186 +
1187 +#define HAL_PWRMGT_I2S_CLOCK_SOURCE_11289600HZ() \
1188 +{ \
1189 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 12); \
1190 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 12); \
1191 +}
1192 +
1193 +
1194 +#define HAL_PWRMGT_I2S_CLOCK_SOURCE_12288000HZ() \
1195 +{ \
1196 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 12); \
1197 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x2 << 12); \
1198 +}
1199 +
1200 +
1201 +#define HAL_PWRMGT_CONFIGURE_MDC_CLOCK_DIVIDER(divided_value) \
1202 +{ \
1203 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 14); \
1204 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= ((divided_value & 0x3) << 14); \
1205 +}
1206 +
1207 +
1208 +#define HAL_PWRMGT_CONFIGURE_CLOCK_OUT_PIN(pin_source_select, divided_value) \
1209 +{ \
1210 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3F << 16); \
1211 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= ((pin_source_select & 0xF) << 16); \
1212 + PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= ((divided_value & 0x3) << 20); \
1213 +}
1214 +
1215 +
1216 +/*
1217 + * Macro defines for PLL Power Down Control
1218 + */
1219 +#define HAL_PWRMGT_POWER_DOWN_SYSTEM_XTAL_PAD() \
1220 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 7)
1221 +
1222 +#define HAL_PWRMGT_POWER_ON_SYSTEM_XTAL_PAD() \
1223 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 7)
1224 +
1225 +
1226 +#define HAL_PWRMGT_POWER_DOWN_PLL_X5() \
1227 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 0)
1228 +
1229 +#define HAL_PWRMGT_POWER_ON_PLL_X5() \
1230 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 0)
1231 +
1232 +
1233 +#define HAL_PWRMGT_POWER_DOWN_PLL_X8() \
1234 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 1)
1235 +
1236 +#define HAL_PWRMGT_POWER_ON_PLL_X8() \
1237 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 1)
1238 +
1239 +
1240 +#define HAL_PWRMGT_POWER_DOWN_PLL_X3() \
1241 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 2)
1242 +
1243 +#define HAL_PWRMGT_POWER_ON_PLL_X3() \
1244 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 2)
1245 +
1246 +
1247 +#define HAL_PWRMGT_POWER_DOWN_USBH_PHY_PLL() \
1248 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 3)
1249 +
1250 +#define HAL_PWRMGT_POWER_ON_USBH_PHY_PLL() \
1251 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 3)
1252 +
1253 +
1254 +#define HAL_PWRMGT_POWER_DOWN_USBD_PHY_PLL() \
1255 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 4)
1256 +
1257 +#define HAL_PWRMGT_POWER_ON_USBD_PHY_PLL() \
1258 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 4)
1259 +
1260 +
1261 +#define HAL_PWRMGT_POWER_DOWN_PLL_X2250() \
1262 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 5)
1263 +
1264 +#define HAL_PWRMGT_POWER_ON_PLL_X2250() \
1265 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 5)
1266 +
1267 +
1268 +#define HAL_PWRMGT_POWER_DOWN_PLL_X7() \
1269 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 6)
1270 +
1271 +#define HAL_PWRMGT_POWER_ON_PLL_X7() \
1272 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 6)
1273 +
1274 +
1275 +#define HAL_PWRMGT_POWER_DOWN_ALL_PLL() \
1276 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG = 0x7F;
1277 +
1278 +#define HAL_PWRMGT_POWER_ON_ALL_PLL() \
1279 + PWRMGT_PLL_POWER_DOWN_CONTROL_REG = 0;
1280 +
1281 +
1282 +/*
1283 + * Macro defines for Pad Drive Strength Control
1284 + */
1285 +#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_PCMCIA_CARDBUS_MODE() \
1286 +{ \
1287 + PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x3 << 0); \
1288 +}
1289 +
1290 +#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_PCI_MODE() \
1291 +{ \
1292 + PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x3 << 0); \
1293 + PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG |= (0x1 << 0); \
1294 +}
1295 +
1296 +#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_MII_MODE() \
1297 +{ \
1298 + PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG |= (0x1 << 2); \
1299 +}
1300 +
1301 +#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_RGMII_MODE() \
1302 +{ \
1303 + PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x1 << 2); \
1304 +}
1305 +
1306 +#define HAL_PWRMGT_ENABLE_MII_PAD_SIGNAL_NOT_BOUNDED() \
1307 +{ \
1308 + PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG |= (0x1 << 3); \
1309 +}
1310 +
1311 +#define HAL_PWRMGT_DISABLE_MII_PAD_SIGNAL_NOT_BOUNDED() \
1312 +{ \
1313 + PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x1 << 3); \
1314 +}
1315 +
1316 +
1317 +/*
1318 + * Macro defines for USB Device Power Management
1319 + */
1320 +#define HAL_PWRMGT_REMOTE_WAKEUP_USB_HOST() \
1321 +{ \
1322 + PWRMGT_USB_DEVICE_POWERMGT_REG |= (0x1 << 4); \
1323 +}
1324 +
1325 +#define HAL_PWRMGT_USB_DEVICE_PHY_CLOCK_SOURCE_EXTERNAL_12MHZ() \
1326 +{ \
1327 + PWRMGT_USB_DEVICE_POWERMGT_REG &= ~(0x1 << 5); \
1328 +}
1329 +
1330 +#define HAL_PWRMGT_USB_DEVICE_PHY_CLOCK_SOURCE_INTERNAL_12MHZ() \
1331 +{ \
1332 + PWRMGT_USB_DEVICE_POWERMGT_REG |= (0x1 << 5); \
1333 +}
1334 +
1335 +
1336 +/*
1337 + * Macro defines for Regulator Control
1338 + */
1339 +
1340 +#endif /* _CNS21XX_POWERMGMT_H */
1341 --- /dev/null
1342 +++ b/arch/arm/mach-cns21xx/include/mach/cns21xx.h
1343 @@ -0,0 +1,88 @@
1344 +/*
1345 + * Copyright (c) 2008 Cavium Networks
1346 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
1347 + *
1348 + * This file is free software; you can redistribute it and/or modify
1349 + * it under the terms of the GNU General Public License, Version 2, as
1350 + * published by the Free Software Foundation.
1351 + */
1352 +
1353 +#ifndef _CNS21XX_H
1354 +#define _CNS21XX_H
1355 +
1356 +#define CNS21XX_FLASH_BANK0_BASE 0x10000000
1357 +#define CNS21XX_FLASH_BANK1_BASE 0x11000000
1358 +#define CNS21XX_FLASH_BANK2_BASE 0x12000000
1359 +#define CNS21XX_FLASH_BANK3_BASE 0x13000000
1360 +#define CNS21XX_PCMCIA_ATTR_BASE 0x14000000
1361 +#define CNS21XX_PCMCIA_MEM_BASE 0x15000000
1362 +#define CNS21XX_PCMCIA_IO_BASE 0x16000000
1363 +#define CNS21XX_IDE_DEVICE_BASE 0x18000000
1364 +#define CNS21XX_SDRAM_MEMORY_BASE 0x20000000
1365 +#define CNS21XX_GDMAC_BASE 0x60000000
1366 +#define CNS21XX_NIC_BASE 0x70000000
1367 +#define CNS21XX_SPI_BASE 0x71000000
1368 +#define CNS21XX_PCM_BASE 0x71000000
1369 +#define CNS21XX_I2C_BASE 0x71000000
1370 +#define CNS21XX_I2S_BASE 0x71000000
1371 +#define CNS21XX_DDRC_BASE 0x72000000
1372 +#define CNS21XX_SMC_BASE 0x73000000
1373 +#define CNS21XX_PCMCIA_CTRL_BASE 0x73000000
1374 +#define CNS21XX_IDE_CTRL_BASE 0x74000000
1375 +#define CNS21XX_MISC_BASE 0x76000000
1376 +#define CNS21XX_CPM_BASE 0x77000000
1377 +#define CNS21XX_UART0_BASE 0x78000000
1378 +#define CNS21XX_UART1_BASE 0x78800000
1379 +#define CNS21XX_TIMER_BASE 0x79000000
1380 +#define CNS21XX_WDT_BASE 0x7a000000
1381 +#define CNS21XX_RTC_BASE 0x7b000000
1382 +#define CNS21XX_GPIOA_BASE 0x7c000000
1383 +#define CNS21XX_GPIOB_BASE 0x7c800000
1384 +#define CNS21XX_PCI_CFGDATA_BASE 0xa0000000
1385 +#define CNS21XX_PCI_CFGADDR_BASE 0xa4000000
1386 +#define CNS21XX_PCI_IO_BASE 0xa8000000
1387 +#define CNS21XX_PCI_MEMORY_BASE 0xb0000000
1388 +#define CNS21XX_OHCI_CONFIG_BASE 0xc0000000
1389 +#define CNS21XX_OHCI_CTRL_BASE 0xc4000000
1390 +#define CNS21XX_EHCI_CONFIG_BASE 0xc8000000
1391 +#define CNS21XX_EHCI_CTRL_BASE 0xcc000000
1392 +#define CNS21XX_USB_DEVICE_BASE 0xd0000000
1393 +#define CNS21XX_INTC_BASE 0xfffff000
1394 +
1395 +#define CNS21XX_FLASH_BANK0_BASE_VIRT 0xe0000000
1396 +#define CNS21XX_FLASH_BANK1_BASE_VIRT 0xe2000000
1397 +#define CNS21XX_FLASH_BANK2_BASE_VIRT 0xe4000000
1398 +#define CNS21XX_FLASH_BANK3_BASE_VIRT 0xe8000000
1399 +#define CNS21XX_IDE_DEVICE_BASE_VIRT 0xfef00000
1400 +#define CNS21XX_GDMAC_BASE_VIRT 0xfef01000
1401 +#define CNS21XX_NIC_BASE_VIRT 0xfef02000
1402 +#define CNS21XX_SPI_BASE_VIRT 0xfef03000
1403 +#define CNS21XX_PCM_BASE_VIRT 0xfef04000
1404 +#define CNS21XX_I2C_BASE_VIRT 0xfef05000
1405 +#define CNS21XX_I2S_BASE_VIRT 0xfef06000
1406 +#define CNS21XX_DDRC_BASE_VIRT 0xfef07000
1407 +#define CNS21XX_SMC_BASE_VIRT 0xfef08000
1408 +#define CNS21XX_PCMCIA_CTRL_BASE_VIRT 0xfef09000
1409 +#define CNS21XX_IDE_CTRL_BASE_VIRT 0xfef0A000
1410 +#define CNS21XX_MISC_BASE_VIRT 0xfef0B000
1411 +#define CNS21XX_CPM_BASE_VIRT 0xfef0C000
1412 +#define CNS21XX_UART0_BASE_VIRT 0xfef0D000
1413 +#define CNS21XX_UART1_BASE_VIRT 0xfef0E000
1414 +#define CNS21XX_TIMER_BASE_VIRT 0xfef0F000
1415 +#define CNS21XX_WDT_BASE_VIRT 0xfef10000
1416 +#define CNS21XX_RTC_BASE_VIRT 0xfef11000
1417 +#define CNS21XX_GPIOA_BASE_VIRT 0xfef12000
1418 +#define CNS21XX_GPIOB_BASE_VIRT 0xfef13000
1419 +#define CNS21XX_PCI_CFGDATA_BASE_VIRT 0xfef14000
1420 +#define CNS21XX_PCI_CFGADDR_BASE_VIRT 0xfef15000
1421 +#define CNS21XX_OHCI_CONFIG_BASE_VIRT 0xfef16000
1422 +#define CNS21XX_OHCI_CTRL_BASE_VIRT 0xfef17000
1423 +#define CNS21XX_EHCI_CONFIG_BASE_VIRT 0xfef18000
1424 +#define CNS21XX_EHCI_CTRL_BASE_VIRT 0xfef19000
1425 +#define CNS21XX_USB_DEVICE_BASE_VIRT 0xfef1a000
1426 +#define CNS21XX_INTC_BASE_VIRT 0xfef1b000
1427 +
1428 +#define CNS21XX_PHYS_IO CNS21XX_UART0_BASE
1429 +#define CNS21XX_IO_PAGE_OFFSET ((CNS21XX_UART0_BASE_VIRT) >> 18) & 0xfffc
1430 +
1431 +#endif /* _CNS21XX_H */
1432 --- /dev/null
1433 +++ b/arch/arm/mach-cns21xx/core.c
1434 @@ -0,0 +1,85 @@
1435 +/*
1436 + * Copyright (c) 2008 Cavium Networks
1437 + * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
1438 + *
1439 + * This file is free software; you can redistribute it and/or modify
1440 + * it under the terms of the GNU General Public License, Version 2, as
1441 + * published by the Free Software Foundation.
1442 + */
1443 +
1444 +#include <linux/kernel.h>
1445 +
1446 +#include <mach/hardware.h>
1447 +#include <mach/cns21xx.h>
1448 +#include <mach/cns21xx_powermgmt.h>
1449 +
1450 +static unsigned long cns21xx_pll_freq;
1451 +static unsigned long cns21xx_cpu_freq;
1452 +static unsigned long cns21xx_ahb_freq;
1453 +static unsigned long cns21xx_apb_freq;
1454 +
1455 +static void cns21xx_init_freq(void)
1456 +{
1457 + static int freq_init_done;
1458 + unsigned int t;
1459 +
1460 + if (freq_init_done)
1461 + return;
1462 +
1463 + t = PWRMGT_SYSTEM_CLOCK_CONTROL_REG;
1464 + switch (t & 0x3) {
1465 + case 0x00:
1466 + cns21xx_pll_freq = 175000000;
1467 + break;
1468 +
1469 + case 0x01:
1470 + cns21xx_pll_freq = 200000000;
1471 + break;
1472 +
1473 + case 0x02:
1474 + cns21xx_pll_freq = 225000000;
1475 + break;
1476 +
1477 + case 0x03:
1478 + cns21xx_pll_freq = 250000000;
1479 + break;
1480 + }
1481 +
1482 + cns21xx_cpu_freq = cns21xx_pll_freq / (((t >> 2) & 0x3) + 1);
1483 + cns21xx_ahb_freq = cns21xx_cpu_freq / (((t >> 4) & 0x3) + 1);
1484 + cns21xx_apb_freq = cns21xx_ahb_freq / (((t >> 8) & 0x3) + 1);
1485 +
1486 + freq_init_done = 1;
1487 +}
1488 +
1489 +unsigned long cns21xx_get_pll_freq(void)
1490 +{
1491 + cns21xx_init_freq();
1492 + return cns21xx_pll_freq;
1493 +}
1494 +
1495 +unsigned long cns21xx_get_cpu_freq(void)
1496 +{
1497 + cns21xx_init_freq();
1498 + return cns21xx_cpu_freq;
1499 +}
1500 +
1501 +unsigned long cns21xx_get_ahb_freq(void)
1502 +{
1503 + cns21xx_init_freq();
1504 + return cns21xx_ahb_freq;
1505 +}
1506 +
1507 +unsigned long cns21xx_get_apb_freq(void)
1508 +{
1509 + cns21xx_init_freq();
1510 + return cns21xx_apb_freq;
1511 +}
1512 +
1513 +void cns21xx_restart(char mode, const char *cmd)
1514 +{
1515 + PWRMGT_SOFTWARE_RESET_CONTROL_REG |=
1516 + (1UL << PWRMGT_GLOBAL_SOFTWARE_RESET_MASK_BIT_INDEX);
1517 + PWRMGT_SOFTWARE_RESET_CONTROL_REG &=
1518 + ~(1UL << PWRMGT_GLOBAL_SOFTWARE_RESET_MASK_BIT_INDEX);
1519 +}
1520 --- a/arch/arm/mm/Kconfig
1521 +++ b/arch/arm/mm/Kconfig
1522 @@ -863,6 +863,7 @@ config ARM_L1_CACHE_SHIFT_6
1523 config ARM_L1_CACHE_SHIFT
1524 int
1525 default 6 if ARM_L1_CACHE_SHIFT_6
1526 + default 4 if ARM_L1_CACHE_SHIFT_4
1527 default 5
1528
1529 config ARM_DMA_MEM_BUFFERABLE
1530 --- a/arch/arm/mm/cache-fa.S
1531 +++ b/arch/arm/mm/cache-fa.S
1532 @@ -28,7 +28,7 @@
1533 /*
1534 * The total size of the data cache.
1535 */
1536 -#ifdef CONFIG_ARCH_GEMINI
1537 +#if (defined(CONFIG_ARCH_GEMINI) || defined(CONFIG_ARCH_CNS21XX))
1538 #define CACHE_DSIZE 8192
1539 #else
1540 #define CACHE_DSIZE 16384
1541 --- /dev/null
1542 +++ b/arch/arm/mach-cns21xx/include/mach/cns21xx_misc.h
1543 @@ -0,0 +1,507 @@
1544 +/*******************************************************************************
1545 + *
1546 + * Copyright (c) 2008 Cavium Networks
1547 + *
1548 + * This file is free software; you can redistribute it and/or modify
1549 + * it under the terms of the GNU General Public License, Version 2, as
1550 + * published by the Free Software Foundation.
1551 + *
1552 + * This file is distributed in the hope that it will be useful,
1553 + * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
1554 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1555 + * NONINFRINGEMENT. See the GNU General Public License for more details.
1556 + *
1557 + * You should have received a copy of the GNU General Public License
1558 + * along with this file; if not, write to the Free Software
1559 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
1560 + * visit http://www.gnu.org/licenses/.
1561 + *
1562 + * This file may also be available under a different license from Cavium.
1563 + * Contact Cavium Networks for more information
1564 + *
1565 + ******************************************************************************/
1566 +
1567 +#ifndef _STAR_MISC_H_
1568 +#define _STAR_MISC_H_
1569 +
1570 +#include <mach/cns21xx.h>
1571 +
1572 +#define MISC_MEM_MAP_VALUE(reg_offset) \
1573 + (*((u32 volatile *)(CNS21XX_MISC_BASE_VIRT + reg_offset)))
1574 +
1575 +/*
1576 + * define access macros
1577 + */
1578 +#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00)
1579 +#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04)
1580 +#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08)
1581 +#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C)
1582 +#define MISC_PCI_CONTROL_BROKEN_MASK_REG MISC_MEM_MAP_VALUE(0x10)
1583 +#define MISC_PCI_BROKEN_STATUS_REG MISC_MEM_MAP_VALUE(0x14)
1584 +#define MISC_PCI_DEVICE_VENDOR_ID_REG MISC_MEM_MAP_VALUE(0x18)
1585 +#define MISC_USB_HOST_PHY_CONTROL_TEST_REG MISC_MEM_MAP_VALUE(0x1C)
1586 +#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x20)
1587 +#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x24)
1588 +#define MISC_GPIOA_RESISTOR_CONFIG_REG MISC_MEM_MAP_VALUE(0x28)
1589 +#define MISC_GPIOA_DRIVE_STRENGTH_CONFIG_REG MISC_MEM_MAP_VALUE(0x2C)
1590 +#define MISC_FAST_ETHERNET_PHY_CONFIG_REG MISC_MEM_MAP_VALUE(0x30)
1591 +#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x38)
1592 +#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x3C)
1593 +
1594 +#define MISC_E_FUSE_0_REG MISC_MEM_MAP_VALUE(0x60)
1595 +#define MISC_E_FUSE_1_REG MISC_MEM_MAP_VALUE(0x64)
1596 +
1597 +
1598 +/*
1599 + * define constants macros
1600 + */
1601 +#define MISC_PARALLEL_FLASH_BOOT 0
1602 +#define MISC_SPI_SERIAL_FLASH_BOOT 1
1603 +
1604 +#define MISC_LITTLE_ENDIAN 0
1605 +#define MISC_BIG_ENDIAN 1
1606 +
1607 +#define MISC_FARADAY_ICE 0
1608 +#define MISC_ARM_ICE 1
1609 +
1610 +#define MISC_EXT_INT29_PINS ((0x1 << 0))
1611 +#define MISC_EXT_INT30_PINS ((0x1 << 1))
1612 +#define MISC_EXT_INT31_PINS ((0x1 << 2))
1613 +#define MISC_I2C_PINS ((0x1 << 13) | (0x1 << 14))
1614 +#define MISC_I2S_PINS ((0x1 << 15) | (0x1 << 16) | (0x1 << 17))
1615 +#define MISC_I2SSD_PINS (1 << 15)
1616 +#define MISC_I2SWS_PINS (1 << 16)
1617 +#define MISC_I2SCLK_PINS (1 << 17)
1618 +#define MISC_PCM_PINS ((0x1 << 18) | (0x1 << 19) | (0x1 << 20) | (0x1 << 21))
1619 +#define MISC_PCMDR_PINS (1 << 18)
1620 +#define MISC_PCMDT_PINS (1 << 19)
1621 +#define MISC_PCMFS_PINS (1 << 20)
1622 +#define MISC_PCMCLK_PINS (1 << 21)
1623 +#define MISC_LED0_PINS ((0x1 << 22))
1624 +#define MISC_LED1_PINS ((0x1 << 23))
1625 +#define MISC_LED2_PINS ((0x1 << 24))
1626 +#define MISC_LED012_PINS ((0x1 << 22) | (0x1 << 23) | (0x1 << 24))
1627 +#define MISC_WDTIMER_RESET_PINS ((0x1 << 25))
1628 +#define MISC_SPIDR_PINS (0x1 << 26)
1629 +#define MISC_SPICLK_PINS (0x1 << 27)
1630 +#define MISC_SPICSN0_PINS (0x1 << 28)
1631 +#define MISC_SPICSN1_PINS (0x1 << 29)
1632 +#define MISC_SPICSN2_PINS (0x1 << 30)
1633 +#define MISC_SPICSN3_PINS (0x1 << 31)
1634 +#define MISC_SPI_PINS ((0x1 << 26) | (0x1 << 27) | (0x1 << 28) | (0x1 << 29) | (0x1 << 30) | (0x1 << 31))
1635 +#define MISC_MDC_MDIO_PINS ((0x1 << 0) | (0x1 << 1))
1636 +#define MISC_NIC_COL_PINS ((0x1 << 2))
1637 +#define MISC_IDE_PINS ((0xFF << 3))
1638 +#define MISC_SRAM_BANK1_PINS ((0x1 << 11) | (0x1 << 14))
1639 +#define MISC_SRAM_BANK2_PINS ((0x1 << 12) | (0x1 << 15))
1640 +#define MISC_SRAM_BANK3_PINS ((0x1 << 13) | (0x1 << 16))
1641 +#define MISC_PCMCIA_PINS ((0x1 << 17) | (0x1 << 18) | (0x1 << 19) | (0x1 << 20))
1642 +#define MISC_UART1_PINS ((0x1 << 21) | (0x1 << 22))
1643 +#define MISC_PCI_PINS (((u32)0x1FF << 23))
1644 +
1645 +#define MISC_UART0_ACT0_Pin (0x1 << 2)
1646 +#define MISC_UART1_ACT1_Pin (0x1 << 3)
1647 +
1648 +#define MISC_GPIOA_PIN_0 0
1649 +#define MISC_GPIOA_PIN_1 1
1650 +#define MISC_GPIOA_PIN_2 2
1651 +#define MISC_GPIOA_PIN_3 3
1652 +#define MISC_GPIOA_PIN_4 4
1653 +#define MISC_GPIOA_PIN_5 5
1654 +#define MISC_GPIOA_PIN_6 6
1655 +#define MISC_GPIOA_PIN_7 7
1656 +#define MISC_GPIOA_PIN_8 8
1657 +#define MISC_GPIOA_PIN_9 9
1658 +#define MISC_GPIOA_PIN_10 10
1659 +
1660 +#define MISC_GPIOA_75K_RESISTOR_PULL_DOWN 1
1661 +#define MISC_GPIOA_75K_RESISTOR_PULL_UP 2
1662 +#define MISC_GPIOA_75K_RESISTOR_PULL_KEEPER 3
1663 +
1664 +#define MISC_GPIOA_DRIVE_STRENGTH_4MA 0
1665 +#define MISC_GPIOA_DRIVE_STRENGTH_8MA 1
1666 +
1667 +
1668 +/*
1669 + * macro declarations
1670 + */
1671 +#define HAL_MISC_ENABLE_SPI_SERIAL_FLASH_BANK_ACCESS() \
1672 +{ \
1673 + (MISC_CHIP_CONFIG_REG) |= (0x1 << 4); \
1674 +}
1675 +
1676 +#define HAL_MISC_DISABLE_SPI_SERIAL_FLASH_BANK_ACCESS() \
1677 +{ \
1678 + (MISC_CHIP_CONFIG_REG) &= ~(0x1 << 4); \
1679 +}
1680 +
1681 +
1682 +/*
1683 + * Macro defines for GPIOA and GPIOB Pin Enable Register
1684 + */
1685 +#define HAL_MISC_ENABLE_EXT_INT29_PINS() \
1686 +{ \
1687 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_EXT_INT29_PINS); \
1688 +}
1689 +
1690 +#define HAL_MISC_DISABLE_EXT_INT29_PINS() \
1691 +{ \
1692 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_EXT_INT29_PINS); \
1693 +}
1694 +
1695 +#define HAL_MISC_ENABLE_EXT_INT30_PINS() \
1696 +{ \
1697 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_EXT_INT30_PINS); \
1698 +}
1699 +
1700 +#define HAL_MISC_DISABLE_EXT_INT30_PINS() \
1701 +{ \
1702 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_EXT_INT30_PINS); \
1703 +}
1704 +
1705 +#define HAL_MISC_ENABLE_I2C_PINS() \
1706 +{ \
1707 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_I2C_PINS); \
1708 +}
1709 +
1710 +#define HAL_MISC_DISABLE_I2C_PINS() \
1711 +{ \
1712 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2C_PINS); \
1713 +}
1714 +
1715 +#define HAL_MISC_ENABLE_I2S_PINS() \
1716 +{ \
1717 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_I2S_PINS); \
1718 +}
1719 +
1720 +#define HAL_MISC_DISABLE_I2S_PINS() \
1721 +{ \
1722 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2S_PINS); \
1723 +}
1724 +
1725 +#define HAL_MISC_DISABLE_I2SSD_PINS() \
1726 +{ \
1727 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2SSD_PINS); \
1728 +}
1729 +
1730 +#define HAL_MISC_DISABLE_I2SWS_PINS() \
1731 +{ \
1732 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2SWS_PINS); \
1733 +}
1734 +
1735 +#define HAL_MISC_DISABLE_I2SCLK_PINS() \
1736 +{ \
1737 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2SCLK_PINS); \
1738 +}
1739 +
1740 +#define HAL_MISC_ENABLE_PCM_PINS() \
1741 +{ \
1742 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_PCM_PINS); \
1743 +}
1744 +
1745 +#define HAL_MISC_DISABLE_PCM_PINS() \
1746 +{ \
1747 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCM_PINS); \
1748 +}
1749 +
1750 +#define HAL_MISC_DISABLE_PCMDR_PINS() \
1751 +{ \
1752 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMDR_PINS); \
1753 +}
1754 +
1755 +#define HAL_MISC_DISABLE_PCMDT_PINS() \
1756 +{ \
1757 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMDT_PINS); \
1758 +}
1759 +
1760 +#define HAL_MISC_DISABLE_PCMFS_PINS() \
1761 +{ \
1762 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMFS_PINS); \
1763 +}
1764 +
1765 +#define HAL_MISC_DISABLE_PCMCLK_PINS() \
1766 +{ \
1767 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMCLK_PINS); \
1768 +}
1769 +
1770 +#define HAL_MISC_ENABLE_LED0_PINS() \
1771 +{ \
1772 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED0_PINS); \
1773 +}
1774 +
1775 +#define HAL_MISC_DISABLE_LED0_PINS() \
1776 +{ \
1777 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED0_PINS); \
1778 +}
1779 +
1780 +#define HAL_MISC_ENABLE_LED1_PINS() \
1781 +{ \
1782 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED1_PINS); \
1783 +}
1784 +
1785 +#define HAL_MISC_DISABLE_LED1_PINS() \
1786 +{ \
1787 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED1_PINS); \
1788 +}
1789 +
1790 +#define HAL_MISC_ENABLE_LED2_PINS() \
1791 +{ \
1792 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED2_PINS); \
1793 +}
1794 +
1795 +#define HAL_MISC_DISABLE_LED2_PINS() \
1796 +{ \
1797 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED2_PINS); \
1798 +}
1799 +
1800 +#define HAL_MISC_ENABLE_LED012_PINS() \
1801 +{ \
1802 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED012_PINS); \
1803 +}
1804 +
1805 +#define HAL_MISC_DISABLE_LED012_PINS() \
1806 +{ \
1807 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED012_PINS); \
1808 +}
1809 +
1810 +#define HAL_MISC_ENABLE_WDTIMER_RESET_PINS() \
1811 +{ \
1812 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_WDTIMER_RESET_PINS); \
1813 +}
1814 +
1815 +#define HAL_MISC_DISABLE_WDTIMER_RESET_PINS() \
1816 +{ \
1817 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_WDTIMER_RESET_PINS); \
1818 +}
1819 +
1820 +#define HAL_MISC_ENABLE_SPI_PINS() \
1821 +{ \
1822 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPI_PINS); \
1823 +}
1824 +
1825 +#define HAL_MISC_ENABLE_SPIDR_PINS() \
1826 +{ \
1827 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPIDR_PINS); \
1828 +}
1829 +
1830 +#define HAL_MISC_ENABLE_SPICLK_PINS() \
1831 +{ \
1832 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICLK_PINS); \
1833 +}
1834 +
1835 +#define HAL_MISC_ENABLE_SPICSN0_PINS() \
1836 +{ \
1837 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN0_PINS); \
1838 +}
1839 +
1840 +#define HAL_MISC_ENABLE_SPICSN0_PINS() \
1841 +{ \
1842 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN0_PINS); \
1843 +}
1844 +
1845 +#define HAL_MISC_ENABLE_SPICSN1_PINS() \
1846 +{ \
1847 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN1_PINS); \
1848 +}
1849 +
1850 +#define HAL_MISC_ENABLE_SPICSN2_PINS() \
1851 +{ \
1852 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN2_PINS); \
1853 +}
1854 +
1855 +#define HAL_MISC_ENABLE_SPICSN3_PINS() \
1856 +{ \
1857 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN3_PINS); \
1858 +}
1859 +
1860 +#define HAL_MISC_DISABLE_SPI_PINS() \
1861 +{ \
1862 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPI_PINS); \
1863 +}
1864 +
1865 +#define HAL_MISC_DISABLE_SPIDR_PINS() \
1866 +{ \
1867 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPIDR_PINS); \
1868 +}
1869 +
1870 +#define HAL_MISC_DISABLE_SPICLK_PINS() \
1871 +{ \
1872 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICLK_PINS); \
1873 +}
1874 +
1875 +#define HAL_MISC_DISABLE_SPICSN0_PINS() \
1876 +{ \
1877 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN0_PINS); \
1878 +}
1879 +
1880 +#define HAL_MISC_DISABLE_SPICSN1_PINS() \
1881 +{ \
1882 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN1_PINS); \
1883 +}
1884 +
1885 +#define HAL_MISC_DISABLE_SPICSN2_PINS() \
1886 +{ \
1887 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN2_PINS); \
1888 +}
1889 +
1890 +#define HAL_MISC_DISABLE_SPICSN3_PINS() \
1891 +{ \
1892 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN3_PINS); \
1893 +}
1894 +
1895 +#define HAL_MISC_ENABLE_UART0_ACT0_PIN() \
1896 +{ \
1897 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_UART0_ACT0_Pin); \
1898 +}
1899 +
1900 +#define HAL_MISC_DISABLE_UART0_ACT0_PIN() \
1901 +{ \
1902 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_UART0_ACT0_Pin); \
1903 +}
1904 +
1905 +#define HAL_MISC_ENABLE_UART1_ACT1_PIN() \
1906 +{ \
1907 + (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_UART1_ACT1_Pin); \
1908 +}
1909 +
1910 +#define HAL_MISC_DISABLE_UART1_ACT1_PIN() \
1911 +{ \
1912 + (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_UART1_ACT1_Pin); \
1913 +}
1914 +
1915 +#define HAL_MISC_ENABLE_MDC_MDIO_PINS() \
1916 +{ \
1917 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_MDC_MDIO_PINS); \
1918 +}
1919 +
1920 +#define HAL_MISC_DISABLE_MDC_MDIO_PINS() \
1921 +{ \
1922 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_MDC_MDIO_PINS); \
1923 +}
1924 +
1925 +#define HAL_MISC_ENABLE_NIC_COL_PINS() \
1926 +{ \
1927 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_NIC_COL_PINS); \
1928 +}
1929 +
1930 +#define HAL_MISC_DISABLE_NIC_COL_PINS() \
1931 +{ \
1932 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_NIC_COL_PINS); \
1933 +}
1934 +
1935 +#define HAL_MISC_ENABLE_IDE_PINS() \
1936 +{ \
1937 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_IDE_PINS); \
1938 +}
1939 +
1940 +#define HAL_MISC_DISABLE_IDE_PINS() \
1941 +{ \
1942 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_IDE_PINS); \
1943 +}
1944 +
1945 +#define HAL_MISC_ENABLE_SRAM_BANK1_PINS() \
1946 +{ \
1947 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_SRAM_BANK1_PINS); \
1948 +}
1949 +
1950 +#define HAL_MISC_DISABLE_SRAM_BANK1_PINS() \
1951 +{ \
1952 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_SRAM_BANK1_PINS); \
1953 +}
1954 +
1955 +#define HAL_MISC_ENABLE_SRAM_BANK2_PINS() \
1956 +{ \
1957 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_SRAM_BANK2_PINS); \
1958 +}
1959 +
1960 +#define HAL_MISC_DISABLE_SRAM_BANK2_PINS() \
1961 +{ \
1962 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_SRAM_BANK2_PINS); \
1963 +}
1964 +
1965 +#define HAL_MISC_ENABLE_SRAM_BANK3_PINS() \
1966 +{ \
1967 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_SRAM_BANK3_PINS); \
1968 +}
1969 +
1970 +#define HAL_MISC_DISABLE_SRAM_BANK3_PINS() \
1971 +{ \
1972 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_SRAM_BANK3_PINS); \
1973 +}
1974 +
1975 +#define HAL_MISC_ENABLE_PCMCIA_PINS() \
1976 +{ \
1977 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_PCMCIA_PINS); \
1978 +}
1979 +
1980 +#define HAL_MISC_DISABLE_PCMCIA_PINS() \
1981 +{ \
1982 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_PCMCIA_PINS); \
1983 +}
1984 +
1985 +#define HAL_MISC_ENABLE_UART1_PINS() \
1986 +{ \
1987 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_UART1_PINS); \
1988 +}
1989 +
1990 +#define HAL_MISC_DISABLE_UART1_PINS() \
1991 +{ \
1992 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_UART1_PINS); \
1993 +}
1994 +
1995 +#define HAL_MISC_ENABLE_PCI_PINS() \
1996 +{ \
1997 + (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_PCI_PINS); \
1998 +}
1999 +
2000 +#define HAL_MISC_DISABLE_PCI_PINS() \
2001 +{ \
2002 + (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_PCI_PINS); \
2003 +}
2004 +
2005 +#define HAL_MISC_ENABLE_ALL_SHARED_GPIO_PINS() \
2006 +{ \
2007 + (MISC_GPIOA_PIN_ENABLE_REG) = (0x0); \
2008 + (MISC_GPIOB_PIN_ENABLE_REG) = (0x0); \
2009 +}
2010 +
2011 +#define HAL_MISC_DISABLE_ALL_SHARED_GPIO_PINS() \
2012 +{ \
2013 + (MISC_GPIOA_PIN_ENABLE_REG) = (0xFFFFFFFF); \
2014 + (MISC_GPIOB_PIN_ENABLE_REG) = (0xFFFFFFFF); \
2015 +}
2016 +
2017 +#define HAL_MISC_CONFIGURE_GPIOA_RESISTOR(pin_index, value) \
2018 +{ \
2019 + (MISC_GPIOA_RESISTOR_CONFIG_REG) &= ~(0x3 << (2 * pin_index)); \
2020 + (MISC_GPIOA_RESISTOR_CONFIG_REG) |= ((value & 0x3) << (2 * pin_index)); \
2021 +}
2022 +
2023 +#define HAL_MISC_CONFIGURE_GPIOA_DRIVE_STRENGTH(pin_index, value) \
2024 +{ \
2025 + (MISC_GPIOA_DRIVE_STRENGTH_CONFIG_REG) &= ~(0x1 << pin_index); \
2026 + (MISC_GPIOA_DRIVE_STRENGTH_CONFIG_REG) |= (value << pin_index); \
2027 +}
2028 +
2029 +#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE0() \
2030 +{ \
2031 + (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x0); \
2032 +}
2033 +
2034 +#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE1() \
2035 +{ \
2036 + (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x1); \
2037 +}
2038 +
2039 +#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE2() \
2040 +{ \
2041 + (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x2); \
2042 +}
2043 +
2044 +#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE3() \
2045 +{ \
2046 + (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x3); \
2047 +}
2048 +
2049 +
2050 +#endif // end of #ifndef _STAR_MISC_H_
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