target/linux/cns3xxx/files/drivers/usb/dwc/otg_hcd_queue.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
   3  * $Revision: #33 $
   4  * $Date: 2008/07/15 $
   5  * $Change: 1064918 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 /**
  36  * @file
  37  *
  38  * This file contains the functions to manage Queue Heads and Queue
  39  * Transfer Descriptors.
  40  */
  41 #include <linux/kernel.h>
  42 #include <linux/module.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/device.h>
  46 #include <linux/errno.h>
  47 #include <linux/list.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/string.h>
  50 #include <linux/version.h>
  51
  52 #include <mach/irqs.h>
  53
  54 #include "otg_driver.h"
  55 #include "otg_hcd.h"
  56 #include "otg_regs.h"
  57
  58 /**
  59  * This function allocates and initializes a QH.
  60  *
  61  * @param hcd The HCD state structure for the DWC OTG controller.
  62  * @param[in] urb Holds the information about the device/endpoint that we need
  63  * to initialize the QH.
  64  *
  65  * @return Returns pointer to the newly allocated QH, or NULL on error. */
  66 dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, struct urb *urb)
  67 {
  68         dwc_otg_qh_t *qh;
  69
  70         /* Allocate memory */
  71         /** @todo add memflags argument */
  72         qh = dwc_otg_hcd_qh_alloc ();
  73         if (qh == NULL) {
  74                 return NULL;
  75         }
  76
  77         dwc_otg_hcd_qh_init (hcd, qh, urb);
  78         return qh;
  79 }
  80
  81 /** Free each QTD in the QH's QTD-list then free the QH.  QH should already be
  82  * removed from a list.  QTD list should already be empty if called from URB
  83  * Dequeue.
  84  *
  85  * @param[in] hcd HCD instance.
  86  * @param[in] qh The QH to free.
  87  */
  88 void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
  89 {
  90         dwc_otg_qtd_t *qtd;
  91         struct list_head *pos;
  92         //unsigned long flags;
  93
  94         /* Free each QTD in the QTD list */
  95
  96 #ifdef CONFIG_SMP
  97         //the spinlock is locked before this function get called,
  98         //but in case the lock is needed, the check function is preserved
  99
 100         //but in non-SMP mode, all spinlock is lockable.
 101         //don't do the test in non-SMP mode
 102
 103         if(spin_trylock(&hcd->lock)) {
 104                 printk("%s: It is not supposed to be lockable!!\n",__func__);
 105                 BUG();
 106         }
 107 #endif
 108 //      SPIN_LOCK_IRQSAVE(&hcd->lock, flags)
 109         for (pos = qh->qtd_list.next;
 110              pos != &qh->qtd_list;
 111              pos = qh->qtd_list.next)
 112         {
 113                 list_del (pos);
 114                 qtd = dwc_list_to_qtd (pos);
 115                 dwc_otg_hcd_qtd_free (qtd);
 116         }
 117 //      SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
 118
 119         kfree (qh);
 120         return;
 121 }
 122
 123 /** Initializes a QH structure.
 124  *
 125  * @param[in] hcd The HCD state structure for the DWC OTG controller.
 126  * @param[in] qh The QH to init.
 127  * @param[in] urb Holds the information about the device/endpoint that we need
 128  * to initialize the QH. */
 129 #define SCHEDULE_SLOP 10
 130 void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb)
 131 {
 132         char *speed, *type;
 133         memset (qh, 0, sizeof (dwc_otg_qh_t));
 134
 135         /* Initialize QH */
 136         switch (usb_pipetype(urb->pipe)) {
 137         case PIPE_CONTROL:
 138                 qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
 139                 break;
 140         case PIPE_BULK:
 141                 qh->ep_type = USB_ENDPOINT_XFER_BULK;
 142                 break;
 143         case PIPE_ISOCHRONOUS:
 144                 qh->ep_type = USB_ENDPOINT_XFER_ISOC;
 145                 break;
 146         case PIPE_INTERRUPT:
 147                 qh->ep_type = USB_ENDPOINT_XFER_INT;
 148                 break;
 149         }
 150
 151         qh->ep_is_in = usb_pipein(urb->pipe) ? 1 : 0;
 152
 153         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
 154         qh->maxp = usb_maxpacket(urb->dev, urb->pipe, !(usb_pipein(urb->pipe)));
 155         INIT_LIST_HEAD(&qh->qtd_list);
 156         INIT_LIST_HEAD(&qh->qh_list_entry);
 157         qh->channel = NULL;
 158         qh->speed = urb->dev->speed;
 159
 160         /* FS/LS Enpoint on HS Hub
 161          * NOT virtual root hub */
 162         qh->do_split = 0;
 163         if (((urb->dev->speed == USB_SPEED_LOW) ||
 164              (urb->dev->speed == USB_SPEED_FULL)) &&
 165             (urb->dev->tt) && (urb->dev->tt->hub) && (urb->dev->tt->hub->devnum != 1))
 166         {
 167                 DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
 168                            usb_pipeendpoint(urb->pipe), urb->dev->tt->hub->devnum,
 169                            urb->dev->ttport);
 170                 qh->do_split = 1;
 171         }
 172
 173         if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
 174             qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
 175                 /* Compute scheduling parameters once and save them. */
 176                 hprt0_data_t hprt;
 177
 178                 /** @todo Account for split transfers in the bus time. */
 179                 int bytecount = dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
 180                 qh->usecs = NS_TO_US(usb_calc_bus_time(urb->dev->speed,
 181                                                usb_pipein(urb->pipe),
 182                                                (qh->ep_type == USB_ENDPOINT_XFER_ISOC),
 183                                                bytecount));
 184
 185                 /* Start in a slightly future (micro)frame. */
 186                 qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
 187                                                      SCHEDULE_SLOP);
 188                 qh->interval = urb->interval;
 189 #if 0
 190                 /* Increase interrupt polling rate for debugging. */
 191                 if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
 192                         qh->interval = 8;
 193                 }
 194 #endif
 195                 hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0);
 196                 if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
 197                     ((urb->dev->speed == USB_SPEED_LOW) ||
 198                      (urb->dev->speed == USB_SPEED_FULL))) {
 199                         qh->interval *= 8;
 200                         qh->sched_frame |= 0x7;
 201                         qh->start_split_frame = qh->sched_frame;
 202                 }
 203
 204         }
 205
 206         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
 207         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - qh = %p\n", qh);
 208         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Device Address = %d\n",
 209                     urb->dev->devnum);
 210         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Endpoint %d, %s\n",
 211                     usb_pipeendpoint(urb->pipe),
 212                     usb_pipein(urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
 213
 214         qh->nak_frame = 0xffff;
 215
 216         switch(urb->dev->speed) {
 217         case USB_SPEED_LOW:
 218                 speed = "low";
 219                 break;
 220         case USB_SPEED_FULL:
 221                 speed = "full";
 222                 break;
 223         case USB_SPEED_HIGH:
 224                 speed = "high";
 225                 break;
 226         default:
 227                 speed = "?";
 228                 break;
 229         }
 230         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Speed = %s\n", speed);
 231
 232         switch (qh->ep_type) {
 233         case USB_ENDPOINT_XFER_ISOC:
 234                 type = "isochronous";
 235                 break;
 236         case USB_ENDPOINT_XFER_INT:
 237                 type = "interrupt";
 238                 break;
 239         case USB_ENDPOINT_XFER_CONTROL:
 240                 type = "control";
 241                 break;
 242         case USB_ENDPOINT_XFER_BULK:
 243                 type = "bulk";
 244                 break;
 245         default:
 246                 type = "?";
 247                 break;
 248         }
 249         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Type = %s\n",type);
 250
 251 #ifdef DEBUG
 252         if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
 253                 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
 254                             qh->usecs);
 255                 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
 256                             qh->interval);
 257         }
 258 #endif
 259
 260         return;
 261 }
 262
 263 /**
 264  * Microframe scheduler
 265  * track the total use in hcd->frame_usecs
 266  * keep each qh use in qh->frame_usecs
 267  * when surrendering the qh then donate the time back
 268  */
 269 static const u16 max_uframe_usecs[] = { 100, 100, 100, 100, 100, 100, 30, 0 };
 270
 271 /*
 272  * called from dwc_otg_hcd.c:dwc_otg_hcd_init
 273  */
 274 int init_hcd_usecs(dwc_otg_hcd_t *hcd)
 275 {
 276         int i;
 277
 278         for (i = 0; i < 8; i++)
 279                 hcd->frame_usecs[i] = max_uframe_usecs[i];
 280
 281         return 0;
 282 }
 283
 284 static int find_single_uframe(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 285 {
 286         int i;
 287         u16 utime;
 288         int t_left;
 289         int ret;
 290         int done;
 291
 292         ret = -1;
 293         utime = qh->usecs;
 294         t_left = utime;
 295         i = 0;
 296         done = 0;
 297         while (done == 0) {
 298                 /* At the start hcd->frame_usecs[i] = max_uframe_usecs[i]; */
 299                 if (utime <= hcd->frame_usecs[i]) {
 300                         hcd->frame_usecs[i] -= utime;
 301                         qh->frame_usecs[i] += utime;
 302                         t_left -= utime;
 303                         ret = i;
 304                         done = 1;
 305                         return ret;
 306                 } else {
 307                         i++;
 308                         if (i == 8) {
 309                                 done = 1;
 310                                 ret = -1;
 311                         }
 312                 }
 313         }
 314         return ret;
 315 }
 316
 317 /*
 318  * use this for FS apps that can span multiple uframes
 319  */
 320 static int find_multi_uframe(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 321 {
 322         int i;
 323         int j;
 324         u16 utime;
 325         int t_left;
 326         int ret;
 327         int done;
 328         u16 xtime;
 329
 330         ret = -1;
 331         utime = qh->usecs;
 332         t_left = utime;
 333         i = 0;
 334         done = 0;
 335 loop:
 336         while (done == 0) {
 337                 if (hcd->frame_usecs[i] <= 0) {
 338                         i++;
 339                         if (i == 8) {
 340                                 done = 1;
 341                                 ret = -1;
 342                         }
 343                         goto loop;
 344                 }
 345
 346                 /*
 347                  * We need n consequtive slots so use j as a start slot.
 348                  * j plus j+1 must be enough time (for now)
 349                  */
 350                 xtime = hcd->frame_usecs[i];
 351                 for (j = i + 1; j < 8; j++) {
 352                         /*
 353                          * if we add this frame remaining time to xtime we may
 354                          * be OK, if not we need to test j for a complete frame.
 355                          */
 356                         if ((xtime + hcd->frame_usecs[j]) < utime) {
 357                                 if (hcd->frame_usecs[j] < max_uframe_usecs[j]) {
 358                                         j = 8;
 359                                         ret = -1;
 360                                         continue;
 361                                 }
 362                         }
 363                         if (xtime >= utime) {
 364                                 ret = i;
 365                                 j = 8;  /* stop loop with a good value ret */
 366                                 continue;
 367                         }
 368                         /* add the frame time to x time */
 369                         xtime += hcd->frame_usecs[j];
 370                         /* we must have a fully available next frame or break */
 371                         if ((xtime < utime) &&
 372                             (hcd->frame_usecs[j] == max_uframe_usecs[j])) {
 373                                 ret = -1;
 374                                 j = 8;  /* stop loop with a bad value ret */
 375                                 continue;
 376                         }
 377                 }
 378                 if (ret >= 0) {
 379                         t_left = utime;
 380                         for (j = i; (t_left > 0) && (j < 8); j++) {
 381                                 t_left -= hcd->frame_usecs[j];
 382                                 if (t_left <= 0) {
 383                                         qh->frame_usecs[j] +=
 384                                             hcd->frame_usecs[j] + t_left;
 385                                         hcd->frame_usecs[j] = -t_left;
 386                                         ret = i;
 387                                         done = 1;
 388                                 } else {
 389                                         qh->frame_usecs[j] +=
 390                                             hcd->frame_usecs[j];
 391                                         hcd->frame_usecs[j] = 0;
 392                                 }
 393                         }
 394                 } else {
 395                         i++;
 396                         if (i == 8) {
 397                                 done = 1;
 398                                 ret = -1;
 399                         }
 400                 }
 401         }
 402         return ret;
 403 }
 404
 405 static int find_uframe(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 406 {
 407         int ret = -1;
 408
 409         if (qh->speed == USB_SPEED_HIGH)
 410                 /* if this is a hs transaction we need a full frame */
 411                 ret = find_single_uframe(hcd, qh);
 412         else
 413                 /* FS transaction may need a sequence of frames */
 414                 ret = find_multi_uframe(hcd, qh);
 415
 416         return ret;
 417 }
 418
 419 /**
 420  * Checks that the max transfer size allowed in a host channel is large enough
 421  * to handle the maximum data transfer in a single (micro)frame for a periodic
 422  * transfer.
 423  *
 424  * @param hcd The HCD state structure for the DWC OTG controller.
 425  * @param qh QH for a periodic endpoint.
 426  *
 427  * @return 0 if successful, negative error code otherwise.
 428  */
 429 static int check_max_xfer_size(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 430 {
 431         int             status;
 432         uint32_t        max_xfer_size;
 433         uint32_t        max_channel_xfer_size;
 434
 435         status = 0;
 436
 437         max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
 438         max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
 439
 440         if (max_xfer_size > max_channel_xfer_size) {
 441                 DWC_NOTICE("%s: Periodic xfer length %d > "
 442                             "max xfer length for channel %d\n",
 443                             __func__, max_xfer_size, max_channel_xfer_size);
 444                 status = -ENOSPC;
 445         }
 446
 447         return status;
 448 }
 449
 450 /**
 451  * Schedules an interrupt or isochronous transfer in the periodic schedule.
 452  */
 453 static int schedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 454 {
 455         int status;
 456         struct usb_bus *bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
 457         int frame;
 458         int num_channels;
 459
 460         num_channels = hcd->core_if->core_params->host_channels;
 461
 462         if ((hcd->periodic_channels < num_channels - 1)) {
 463           if (hcd->periodic_channels + hcd->nakking_channels >= num_channels) {
 464             /* All non-periodic channels are nakking? Halt
 465              * one to make room (as long as there is at
 466              * least one channel for non-periodic transfers,
 467              * all the blocking non-periodics can time-share
 468              * that one channel. */
 469             dwc_hc_t *hc = dwc_otg_halt_nakking_channel(hcd);
 470             if (hc)
 471               DWC_DEBUGPL(DBG_HCD, "Out of Host Channels for periodic transfer - Halting channel %d (dev %d ep%d%s)\n", hc->hc_num, hc->dev_addr, hc->ep_num, (hc->ep_is_in ? "in" : "out"));
 472           }
 473           /* It could be that all channels are currently occupied,
 474            * but in that case one will be freed up soon (either
 475            * because it completed or because it was forced to halt
 476            * above). */
 477         }
 478         status = find_uframe(hcd, qh);
 479         frame = -1;
 480         if (status == 0) {
 481                 frame = 7;
 482         } else {
 483                 if (status > 0)
 484                         frame = status - 1;
 485         }
 486         /* Set the new frame up */
 487         if (frame > -1) {
 488                 qh->sched_frame &= ~0x7;
 489                 qh->sched_frame |= (frame & 7);
 490         }
 491         if (status != -1)
 492                 status = 0;
 493         if (status) {
 494                 pr_notice("%s: Insufficient periodic bandwidth for "
 495                           "periodic transfer.\n", __func__);
 496                 return status;
 497         }
 498         status = check_max_xfer_size(hcd, qh);
 499         if (status) {
 500                 pr_notice("%s: Channel max transfer size too small "
 501                           "for periodic transfer.\n", __func__);
 502                 return status;
 503         }
 504         /* Always start in the inactive schedule. */
 505         list_add_tail(&qh->qh_list_entry, &hcd->periodic_sched_inactive);
 506
 507         hcd->periodic_channels++;
 508
 509         /* Update claimed usecs per (micro)frame. */
 510         hcd->periodic_usecs += qh->usecs;
 511
 512         /*
 513          * Update average periodic bandwidth claimed and # periodic reqs for
 514          * usbfs.
 515          */
 516         bus->bandwidth_allocated += qh->usecs / qh->interval;
 517
 518         if (qh->ep_type == USB_ENDPOINT_XFER_INT)
 519                 bus->bandwidth_int_reqs++;
 520         else
 521                 bus->bandwidth_isoc_reqs++;
 522
 523         return status;
 524 }
 525
 526 /**
 527  * This function adds a QH to either the non periodic or periodic schedule if
 528  * it is not already in the schedule. If the QH is already in the schedule, no
 529  * action is taken.
 530  *
 531  * @return 0 if successful, negative error code otherwise.
 532  */
 533 int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 534 {
 535         //unsigned long flags;
 536         int status = 0;
 537
 538 #ifdef CONFIG_SMP
 539         //the spinlock is locked before this function get called,
 540         //but in case the lock is needed, the check function is preserved
 541         //but in non-SMP mode, all spinlock is lockable.
 542         //don't do the test in non-SMP mode
 543
 544         if(spin_trylock(&hcd->lock)) {
 545                 printk("%s: It is not supposed to be lockable!!\n",__func__);
 546                 BUG();
 547         }
 548 #endif
 549 //      SPIN_LOCK_IRQSAVE(&hcd->lock, flags)
 550
 551         if (!list_empty(&qh->qh_list_entry)) {
 552                 /* QH already in a schedule. */
 553                 goto done;
 554         }
 555
 556         /* Add the new QH to the appropriate schedule */
 557         if (dwc_qh_is_non_per(qh)) {
 558                 /* Always start in the inactive schedule. */
 559                 list_add_tail(&qh->qh_list_entry, &hcd->non_periodic_sched_inactive);
 560         } else {
 561                 status = schedule_periodic(hcd, qh);
 562         }
 563
 564  done:
 565 //      SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags)
 566
 567         return status;
 568 }
 569
 570 /**
 571  * Removes an interrupt or isochronous transfer from the periodic schedule.
 572  */
 573 static void deschedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 574 {
 575         struct usb_bus *bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
 576         int i;
 577
 578         list_del_init(&qh->qh_list_entry);
 579
 580         hcd->periodic_channels--;
 581
 582         /* Update claimed usecs per (micro)frame. */
 583         hcd->periodic_usecs -= qh->usecs;
 584         for (i = 0; i < 8; i++) {
 585                 hcd->frame_usecs[i] += qh->frame_usecs[i];
 586                 qh->frame_usecs[i] = 0;
 587         }
 588         /*
 589          * Update average periodic bandwidth claimed and # periodic reqs for
 590          * usbfs.
 591          */
 592         bus->bandwidth_allocated -= qh->usecs / qh->interval;
 593
 594         if (qh->ep_type == USB_ENDPOINT_XFER_INT)
 595                 bus->bandwidth_int_reqs--;
 596         else
 597                 bus->bandwidth_isoc_reqs--;
 598 }
 599
 600 /**
 601  * Removes a QH from either the non-periodic or periodic schedule.  Memory is
 602  * not freed.
 603  *
 604  * @param[in] hcd The HCD state structure.
 605  * @param[in] qh QH to remove from schedule. */
 606 void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 607 {
 608         //unsigned long flags;
 609
 610 #ifdef CONFIG_SMP
 611         //the spinlock is locked before this function get called,
 612         //but in case the lock is needed, the check function is preserved
 613         //but in non-SMP mode, all spinlock is lockable.
 614         //don't do the test in non-SMP mode
 615
 616         if(spin_trylock(&hcd->lock)) {
 617                 printk("%s: It is not supposed to be lockable!!\n",__func__);
 618                 BUG();
 619         }
 620 #endif
 621 //      SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
 622
 623         if (list_empty(&qh->qh_list_entry)) {
 624                 /* QH is not in a schedule. */
 625                 goto done;
 626         }
 627
 628         if (dwc_qh_is_non_per(qh)) {
 629                 if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
 630                         hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
 631                 }
 632                 list_del_init(&qh->qh_list_entry);
 633         } else {
 634                 deschedule_periodic(hcd, qh);
 635         }
 636
 637  done:
 638 //      SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
 639         return;
 640 }
 641
 642 /**
 643  * Deactivates a QH. For non-periodic QHs, removes the QH from the active
 644  * non-periodic schedule. The QH is added to the inactive non-periodic
 645  * schedule if any QTDs are still attached to the QH.
 646  *
 647  * For periodic QHs, the QH is removed from the periodic queued schedule. If
 648  * there are any QTDs still attached to the QH, the QH is added to either the
 649  * periodic inactive schedule or the periodic ready schedule and its next
 650  * scheduled frame is calculated. The QH is placed in the ready schedule if
 651  * the scheduled frame has been reached already. Otherwise it's placed in the
 652  * inactive schedule. If there are no QTDs attached to the QH, the QH is
 653  * completely removed from the periodic schedule.
 654  */
 655 void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_next_periodic_split)
 656 {
 657         if (dwc_qh_is_non_per(qh)) {
 658                 dwc_otg_hcd_qh_remove(hcd, qh);
 659                 if (!list_empty(&qh->qtd_list)) {
 660                         /* Add back to inactive non-periodic schedule. */
 661                         dwc_otg_hcd_qh_add(hcd, qh);
 662                 }
 663         } else {
 664                 uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd));
 665
 666                 if (qh->do_split) {
 667                         /* Schedule the next continuing periodic split transfer */
 668                         if (sched_next_periodic_split) {
 669
 670                                 qh->sched_frame = frame_number;
 671                                 if (dwc_frame_num_le(frame_number,
 672                                                      dwc_frame_num_inc(qh->start_split_frame, 1))) {
 673                                         /*
 674                                          * Allow one frame to elapse after start
 675                                          * split microframe before scheduling
 676                                          * complete split, but DONT if we are
 677                                          * doing the next start split in the
 678                                          * same frame for an ISOC out.
 679                                          */
 680                                         if ((qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (qh->ep_is_in != 0)) {
 681                                                 qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, 1);
 682                                         }
 683                                 }
 684                         } else {
 685                                 qh->sched_frame = dwc_frame_num_inc(qh->start_split_frame,
 686                                                                      qh->interval);
 687                                 if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
 688                                         qh->sched_frame = frame_number;
 689                                 }
 690                                 qh->sched_frame |= 0x7;
 691                                 qh->start_split_frame = qh->sched_frame;
 692                         }
 693                 } else {
 694                         qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval);
 695                         if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
 696                                 qh->sched_frame = frame_number;
 697                         }
 698                 }
 699
 700                 if (list_empty(&qh->qtd_list)) {
 701                         dwc_otg_hcd_qh_remove(hcd, qh);
 702                 } else {
 703                         /*
 704                          * Remove from periodic_sched_queued and move to
 705                          * appropriate queue.
 706                          */
 707                         if (qh->sched_frame == frame_number) {
 708                                 list_move(&qh->qh_list_entry,
 709                                           &hcd->periodic_sched_ready);
 710                         } else {
 711                                 list_move(&qh->qh_list_entry,
 712                                           &hcd->periodic_sched_inactive);
 713                         }
 714                 }
 715         }
 716 }
 717
 718 /**
 719  * This function allocates and initializes a QTD.
 720  *
 721  * @param[in] urb The URB to create a QTD from.  Each URB-QTD pair will end up
 722  * pointing to each other so each pair should have a unique correlation.
 723  *
 724  * @return Returns pointer to the newly allocated QTD, or NULL on error. */
 725 dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb)
 726 {
 727         dwc_otg_qtd_t *qtd;
 728
 729         qtd = dwc_otg_hcd_qtd_alloc ();
 730         if (qtd == NULL) {
 731                 return NULL;
 732         }
 733
 734         dwc_otg_hcd_qtd_init (qtd, urb);
 735         return qtd;
 736 }
 737
 738 /**
 739  * Initializes a QTD structure.
 740  *
 741  * @param[in] qtd The QTD to initialize.
 742  * @param[in] urb The URB to use for initialization.  */
 743 void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb)
 744 {
 745         memset (qtd, 0, sizeof (dwc_otg_qtd_t));
 746         qtd->urb = urb;
 747         if (usb_pipecontrol(urb->pipe)) {
 748                 /*
 749                  * The only time the QTD data toggle is used is on the data
 750                  * phase of control transfers. This phase always starts with
 751                  * DATA1.
 752                  */
 753                 qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
 754                 qtd->control_phase = DWC_OTG_CONTROL_SETUP;
 755         }
 756
 757         /* start split */
 758         qtd->complete_split = 0;
 759         qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
 760         qtd->isoc_split_offset = 0;
 761
 762         /* Store the qtd ptr in the urb to reference what QTD. */
 763         urb->hcpriv = qtd;
 764         return;
 765 }
 766
 767 /**
 768  * This function adds a QTD to the QTD-list of a QH.  It will find the correct
 769  * QH to place the QTD into.  If it does not find a QH, then it will create a
 770  * new QH. If the QH to which the QTD is added is not currently scheduled, it
 771  * is placed into the proper schedule based on its EP type.
 772  *
 773  * @param[in] qtd The QTD to add
 774  * @param[in] dwc_otg_hcd The DWC HCD structure
 775  *
 776  * @return 0 if successful, negative error code otherwise.
 777  */
 778 int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd,
 779                          dwc_otg_hcd_t *dwc_otg_hcd)
 780 {
 781         struct usb_host_endpoint *ep;
 782         dwc_otg_qh_t *qh;
 783         int retval = 0;
 784
 785         struct urb *urb = qtd->urb;
 786
 787         /*
 788          * Get the QH which holds the QTD-list to insert to. Create QH if it
 789          * doesn't exist.
 790          */
 791         usb_hcd_link_urb_to_ep(dwc_otg_hcd_to_hcd(dwc_otg_hcd), urb);
 792         ep = dwc_urb_to_endpoint(urb);
 793         qh = (dwc_otg_qh_t *)ep->hcpriv;
 794         if (qh == NULL) {
 795                 qh = dwc_otg_hcd_qh_create (dwc_otg_hcd, urb);
 796                 if (qh == NULL) {
 797                         usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(dwc_otg_hcd), urb);
 798                         retval = -ENOMEM;
 799                         goto done;
 800                 }
 801                 ep->hcpriv = qh;
 802         }
 803
 804         retval = dwc_otg_hcd_qh_add(dwc_otg_hcd, qh);
 805         if (retval == 0) {
 806                 list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
 807         } else {
 808                 usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(dwc_otg_hcd), urb);
 809         }
 810
 811  done:
 812         return retval;
 813 }
 814
 815 #endif /* DWC_DEVICE_ONLY */