target/linux/cns3xxx/patches-3.0/003-cns3xxx_l2cache.patch

   1 CNS3xxx SOCs have L310-compatible cache controller, so let's use it.
   2
   3 With this patch benchmarking with 'gzip' shows that performance is
   4 doubled, and I'm still able to boot full-fledged userland over NFS
   5 (using PCIe NIC), so the support should be pretty robust.
   6
   7 Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
   8 ---
   9
  10  arch/arm/mach-cns3xxx/cns3420vb.c |    2 +
  11  arch/arm/mach-cns3xxx/core.c      |   43 +++++++++++++++++++++++++++++++++++++
  12  arch/arm/mach-cns3xxx/core.h      |    6 +++++
  13  arch/arm/mm/Kconfig               |    2 +-
  14  4 files changed, 52 insertions(+), 1 deletions(-)
  15
  16 --- a/arch/arm/mach-cns3xxx/cns3420vb.c
  17 +++ b/arch/arm/mach-cns3xxx/cns3420vb.c
  18 @@ -192,6 +192,8 @@ static struct platform_device *cns3420_p
  19
  20  static void __init cns3420_init(void)
  21  {
  22 +       cns3xxx_l2x0_init();
  23 +
  24         platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
  25
  26         cns3xxx_ahci_init();
  27 --- a/arch/arm/mach-cns3xxx/core.c
  28 +++ b/arch/arm/mach-cns3xxx/core.c
  29 @@ -16,6 +16,7 @@
  30  #include <asm/mach/time.h>
  31  #include <asm/mach/irq.h>
  32  #include <asm/hardware/gic.h>
  33 +#include <asm/hardware/cache-l2x0.h>
  34  #include <mach/cns3xxx.h>
  35  #include "core.h"
  36
  37 @@ -244,3 +245,45 @@ static void __init cns3xxx_timer_init(vo
  38  struct sys_timer cns3xxx_timer = {
  39         .init = cns3xxx_timer_init,
  40  };
  41 +
  42 +#ifdef CONFIG_CACHE_L2X0
  43 +
  44 +void __init cns3xxx_l2x0_init(void)
  45 +{
  46 +       void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
  47 +       u32 val;
  48 +
  49 +       if (WARN_ON(!base))
  50 +               return;
  51 +
  52 +       /*
  53 +        * Tag RAM Control register
  54 +        *
  55 +        * bit[10:8]    - 1 cycle of write accesses latency
  56 +        * bit[6:4]     - 1 cycle of read accesses latency
  57 +        * bit[3:0]     - 1 cycle of setup latency
  58 +        *
  59 +        * 1 cycle of latency for setup, read and write accesses
  60 +        */
  61 +       val = readl(base + L2X0_TAG_LATENCY_CTRL);
  62 +       val &= 0xfffff888;
  63 +       writel(val, base + L2X0_TAG_LATENCY_CTRL);
  64 +
  65 +       /*
  66 +        * Data RAM Control register
  67 +        *
  68 +        * bit[10:8]    - 1 cycles of write accesses latency
  69 +        * bit[6:4]     - 1 cycles of read accesses latency
  70 +        * bit[3:0]     - 1 cycle of setup latency
  71 +        *
  72 +        * 1 cycle of latency for setup, read and write accesses
  73 +        */
  74 +       val = readl(base + L2X0_DATA_LATENCY_CTRL);
  75 +       val &= 0xfffff888;
  76 +       writel(val, base + L2X0_DATA_LATENCY_CTRL);
  77 +
  78 +       /* 32 KiB, 8-way, parity disable */
  79 +       l2x0_init(base, 0x00540000, 0xfe000fff);
  80 +}
  81 +
  82 +#endif /* CONFIG_CACHE_L2X0 */
  83 --- a/arch/arm/mach-cns3xxx/core.h
  84 +++ b/arch/arm/mach-cns3xxx/core.h
  85 @@ -13,6 +13,12 @@
  86
  87  extern struct sys_timer cns3xxx_timer;
  88
  89 +#ifdef CONFIG_CACHE_L2X0
  90 +void __init cns3xxx_l2x0_init(void);
  91 +#else
  92 +static inline void cns3xxx_l2x0_init(void) {}
  93 +#endif /* CONFIG_CACHE_L2X0 */
  94 +
  95  void __init cns3xxx_map_io(void);
  96  void __init cns3xxx_init_irq(void);
  97  void cns3xxx_power_off(void);
  98 --- a/arch/arm/mm/Kconfig
  99 +++ b/arch/arm/mm/Kconfig
 100 @@ -821,7 +821,7 @@ config CACHE_L2X0
 101         depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
 102                    REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
 103                    ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
 104 -                  ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
 105 +                  ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_CNS3XXX
 106         default y
 107         select OUTER_CACHE
 108         select OUTER_CACHE_SYNC