target/linux/danube/files/arch/mips/danube/pci.c

   1 #include <linux/types.h>
   2 #include <linux/pci.h>
   3 #include <linux/kernel.h>
   4 #include <linux/init.h>
   5 #include <linux/delay.h>
   6 #include <linux/mm.h>
   7 #include <asm/danube/danube.h>
   8 #include <asm/danube/danube_irq.h>
   9 #include <asm/addrspace.h>
  10 #include <linux/vmalloc.h>
  11
  12 #define DANUBE_PCI_MEM_BASE    0x18000000
  13 #define DANUBE_PCI_MEM_SIZE    0x02000000
  14 #define DANUBE_PCI_IO_BASE     0x1AE00000
  15 #define DANUBE_PCI_IO_SIZE     0x00200000
  16
  17 #define DANUBE_PCI_CFG_BUSNUM_SHF 16
  18 #define DANUBE_PCI_CFG_DEVNUM_SHF 11
  19 #define DANUBE_PCI_CFG_FUNNUM_SHF 8
  20
  21 #define PCI_ACCESS_READ  0
  22 #define PCI_ACCESS_WRITE 1
  23
  24 static int danube_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
  25 static int danube_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
  26
  27 struct pci_ops danube_pci_ops = {
  28         .read = danube_pci_read_config_dword,
  29         .write = danube_pci_write_config_dword
  30 };
  31
  32 static struct resource pci_io_resource = {
  33         .name = "io pci IO space",
  34         .start = DANUBE_PCI_IO_BASE,
  35         .end = DANUBE_PCI_IO_BASE + DANUBE_PCI_IO_SIZE - 1,
  36         .flags = IORESOURCE_IO
  37 };
  38
  39 static struct resource pci_mem_resource = {
  40         .name = "ext pci memory space",
  41         .start = DANUBE_PCI_MEM_BASE,
  42         .end = DANUBE_PCI_MEM_BASE + DANUBE_PCI_MEM_SIZE - 1,
  43         .flags = IORESOURCE_MEM
  44 };
  45
  46 static struct pci_controller danube_pci_controller = {
  47         .pci_ops = &danube_pci_ops,
  48         .mem_resource = &pci_mem_resource,
  49         .mem_offset     = 0x00000000UL,
  50         .io_resource = &pci_io_resource,
  51         .io_offset      = 0x00000000UL,
  52 };
  53
  54 static u32 danube_pci_mapped_cfg;
  55
  56 static int
  57 danube_pci_config_access(unsigned char access_type,
  58                 struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
  59 {
  60         unsigned long cfg_base;
  61         unsigned long flags;
  62
  63         u32 temp;
  64
  65         /* Danube support slot from 0 to 15 */
  66         /* dev_fn 0&0x68 (AD29) is danube itself */
  67         if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
  68                         || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
  69                 return 1;
  70
  71         local_irq_save(flags);
  72
  73         cfg_base = danube_pci_mapped_cfg;
  74         cfg_base |= (bus->number << DANUBE_PCI_CFG_BUSNUM_SHF) | (devfn <<
  75                         DANUBE_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
  76
  77         /* Perform access */
  78         if (access_type == PCI_ACCESS_WRITE)
  79         {
  80 #ifdef CONFIG_DANUBE_PCI_HW_SWAP
  81                 writel(swab32(*data), ((u32*)cfg_base));
  82 #else
  83                 writel(*data, ((u32*)cfg_base));
  84 #endif
  85         } else {
  86                 *data = readl(((u32*)(cfg_base)));
  87 #ifdef CONFIG_DANUBE_PCI_HW_SWAP
  88                 *data = swab32(*data);
  89 #endif
  90         }
  91         wmb();
  92
  93         /* clean possible Master abort */
  94         cfg_base = (danube_pci_mapped_cfg | (0x0 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
  95         temp = readl(((u32*)(cfg_base)));
  96 #ifdef CONFIG_DANUBE_PCI_HW_SWAP
  97         temp = swab32 (temp);
  98 #endif
  99         cfg_base = (danube_pci_mapped_cfg | (0x68 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
 100         writel(temp, ((u32*)cfg_base));
 101
 102         local_irq_restore(flags);
 103
 104         if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
 105                 return 1;
 106
 107         return 0;
 108 }
 109
 110 static int danube_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
 111                 int where, int size, u32 * val)
 112 {
 113         u32 data = 0;
 114
 115         if (danube_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 116                 return PCIBIOS_DEVICE_NOT_FOUND;
 117
 118         if (size == 1)
 119                 *val = (data >> ((where & 3) << 3)) & 0xff;
 120         else if (size == 2)
 121                 *val = (data >> ((where & 3) << 3)) & 0xffff;
 122         else
 123                 *val = data;
 124
 125         return PCIBIOS_SUCCESSFUL;
 126 }
 127
 128 static int danube_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
 129                 int where, int size, u32 val)
 130 {
 131         u32 data = 0;
 132
 133         if (size == 4)
 134         {
 135                 data = val;
 136         } else {
 137                 if (danube_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 138                         return PCIBIOS_DEVICE_NOT_FOUND;
 139
 140                 if (size == 1)
 141                         data = (data & ~(0xff << ((where & 3) << 3))) |
 142                                 (val << ((where & 3) << 3));
 143                 else if (size == 2)
 144                         data = (data & ~(0xffff << ((where & 3) << 3))) |
 145                                 (val << ((where & 3) << 3));
 146         }
 147
 148         if (danube_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 149                 return PCIBIOS_DEVICE_NOT_FOUND;
 150
 151         return PCIBIOS_SUCCESSFUL;
 152 }
 153
 154
 155 int pcibios_plat_dev_init(struct pci_dev *dev){
 156         u8 pin;
 157
 158         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
 159
 160         switch(pin) {
 161                 case 0:
 162                         break;
 163                 case 1:
 164                         //falling edge level triggered:0x4, low level:0xc, rising edge:0x2
 165                         printk("%s:%s[%d] %08X \n", __FILE__, __func__, __LINE__, dev->irq);
 166                         writel(readl(DANUBE_EBU_PCC_CON) | 0xc, DANUBE_EBU_PCC_CON);
 167                         writel(readl(DANUBE_EBU_PCC_IEN) | 0x10, DANUBE_EBU_PCC_IEN);
 168                         break;
 169                 case 2:
 170                 case 3:
 171                 case 4:
 172                         printk ("WARNING: interrupt pin %d not supported yet!\n", pin);
 173                 default:
 174                         printk ("WARNING: invalid interrupt pin %d\n", pin);
 175                         return 1;
 176         }
 177
 178         return 0;
 179 }
 180
 181 static void __init danube_pci_startup (void){
 182         /*initialize the first PCI device--danube itself */
 183         u32 temp_buffer;
 184         /*TODO: trigger reset */
 185         writel(readl(DANUBE_CGU_IFCCR) & ~0xf00000, DANUBE_CGU_IFCCR);
 186         writel(readl(DANUBE_CGU_IFCCR) | 0x800000, DANUBE_CGU_IFCCR);
 187         /* PCIS of IF_CLK of CGU   : 1 =>PCI Clock output
 188            0 =>clock input
 189            PADsel of PCI_CR of CGU : 1 =>From CGU
 190            : 0 =>From pad
 191          */
 192         writel(readl(DANUBE_CGU_IFCCR) | (1 << 16), DANUBE_CGU_IFCCR);
 193         writel((1 << 31) | (1 << 30), DANUBE_CGU_PCICR);
 194
 195         /* prepare GPIO */
 196         /* PCI_RST: P1.5 ALT 01 */
 197         //pliu20060613: start
 198         writel(readl(DANUBE_GPIO_P1_OUT) | (1 << 5), DANUBE_GPIO_P1_OUT);
 199         writel(readl(DANUBE_GPIO_P1_OD) | (1 << 5), DANUBE_GPIO_P1_OD);
 200         writel(readl(DANUBE_GPIO_P1_DIR) | (1 << 5), DANUBE_GPIO_P1_DIR);
 201         writel(readl(DANUBE_GPIO_P1_ALTSEL1) & ~(1 << 5), DANUBE_GPIO_P1_ALTSEL1);
 202         writel(readl(DANUBE_GPIO_P1_ALTSEL0) & ~(1 << 5), DANUBE_GPIO_P1_ALTSEL0);
 203         //pliu20060613: end
 204         /* PCI_REQ1: P1.13 ALT 01 */
 205         /* PCI_GNT1: P1.14 ALT 01 */
 206         writel(readl(DANUBE_GPIO_P1_DIR) & ~0x2000, DANUBE_GPIO_P1_DIR);
 207         writel(readl(DANUBE_GPIO_P1_DIR) | 0x4000, DANUBE_GPIO_P1_DIR);
 208         writel(readl(DANUBE_GPIO_P1_ALTSEL1) & ~0x6000, DANUBE_GPIO_P1_ALTSEL1);
 209         writel(readl(DANUBE_GPIO_P1_ALTSEL0) | 0x6000, DANUBE_GPIO_P1_ALTSEL0);
 210         /* PCI_REQ2: P1.15 ALT 10 */
 211         /* PCI_GNT2: P1.7 ALT 10 */
 212
 213
 214         /* enable auto-switching between PCI and EBU */
 215         writel(0xa, PCI_CR_CLK_CTRL);
 216         /* busy, i.e. configuration is not done, PCI access has to be retried */
 217         writel(readl(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
 218         wmb ();
 219         /* BUS Master/IO/MEM access */
 220         writel(readl(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
 221
 222         temp_buffer = readl(PCI_CR_PC_ARB);
 223         /* enable external 2 PCI masters */
 224         temp_buffer &= (~(0xf << 16));
 225         /* enable internal arbiter */
 226         temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
 227         /* enable internal PCI master reqest */
 228         temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
 229
 230         /* enable EBU reqest */
 231         temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
 232
 233         /* enable all external masters request */
 234         temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
 235         writel(temp_buffer, PCI_CR_PC_ARB);
 236
 237         wmb ();
 238
 239         /* FPI ==> PCI MEM address mapping */
 240         /* base: 0xb8000000 == > 0x18000000 */
 241         /* size: 8x4M = 32M */
 242         writel(0x18000000, PCI_CR_FCI_ADDR_MAP0);
 243         writel(0x18400000, PCI_CR_FCI_ADDR_MAP1);
 244         writel(0x18800000, PCI_CR_FCI_ADDR_MAP2);
 245         writel(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
 246         writel(0x19000000, PCI_CR_FCI_ADDR_MAP4);
 247         writel(0x19400000, PCI_CR_FCI_ADDR_MAP5);
 248         writel(0x19800000, PCI_CR_FCI_ADDR_MAP6);
 249         writel(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
 250
 251         /* FPI ==> PCI IO address mapping */
 252         /* base: 0xbAE00000 == > 0xbAE00000 */
 253         /* size: 2M */
 254         writel(0xbae00000, PCI_CR_FCI_ADDR_MAP11hg);
 255
 256         /* PCI ==> FPI address mapping */
 257         /* base: 0x0 ==> 0x0 */
 258         /* size: 32M */
 259         /* BAR1 32M map to SDR address */
 260         writel(0x0e000008, PCI_CR_BAR11MASK);
 261         writel(0, PCI_CR_PCI_ADDR_MAP11);
 262         writel(0, PCI_CS_BASE_ADDR1);
 263 #ifdef CONFIG_DANUBE_PCI_HW_SWAP
 264         /* both TX and RX endian swap are enabled */
 265         DANUBE_PCI_REG32 (PCI_CR_PCI_EOI_REG) |= 3;
 266         wmb ();
 267 #endif
 268         /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
 269         writel(readl(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
 270         writel(readl(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
 271         /*use 8 dw burse length */
 272         writel(0x303, PCI_CR_FCI_BURST_LENGTH);
 273
 274         writel(readl(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
 275         wmb();
 276         writel(readl(DANUBE_GPIO_P1_OUT) & ~(1 << 5), DANUBE_GPIO_P1_OUT);
 277         wmb();
 278         mdelay (1);
 279         writel(readl(DANUBE_GPIO_P1_OUT) | (1 << 5), DANUBE_GPIO_P1_OUT);
 280 }
 281
 282 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
 283         printk("\n\n\n%s:%s[%d] %d %d\n", __FILE__, __func__, __LINE__, slot, pin);
 284         switch (slot) {
 285                 case 13:
 286                         /* IDSEL = AD29 --> USB Host Controller */
 287                         return (INT_NUM_IM1_IRL0 + 17);
 288                 case 14:
 289                         /* IDSEL = AD30 --> mini PCI connector */
 290                         //return (INT_NUM_IM1_IRL0 + 14);
 291                         return (INT_NUM_IM0_IRL0 + 22);
 292                 default:
 293                         printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin);
 294                         return 0;
 295         }
 296 }
 297
 298 int pcibios_init(void){
 299         extern int pci_probe_only;
 300
 301         pci_probe_only = 0;
 302         printk ("PCI: Probing PCI hardware on host bus 0.\n");
 303
 304         danube_pci_startup ();
 305
 306         //      DANUBE_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
 307         danube_pci_mapped_cfg = ioremap_nocache(0x17000000, 0x800 * 16);
 308         printk("Danube PCI mapped to 0x%08X\n", (unsigned long)danube_pci_mapped_cfg);
 309
 310         danube_pci_controller.io_map_base = (unsigned long)ioremap(DANUBE_PCI_IO_BASE, DANUBE_PCI_IO_SIZE - 1);
 311
 312         printk("Danube PCI I/O mapped to 0x%08X\n", (unsigned long)danube_pci_controller.io_map_base);
 313
 314         register_pci_controller(&danube_pci_controller);
 315
 316         return 0;
 317 }
 318
 319 arch_initcall(pcibios_init);