target/linux/generic-2.4/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h

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  64
  65
  66 #ifndef __INCmvCpuIfRegsh
  67 #define __INCmvCpuIfRegsh
  68
  69 /****************************************/
  70 /* ARM Control and Status Registers Map */
  71 /****************************************/
  72
  73 #define CPU_CONFIG_REG                          0x20100
  74 #define CPU_CTRL_STAT_REG                       0x20104
  75 #define CPU_RSTOUTN_MASK_REG                    0x20108
  76 #define CPU_SYS_SOFT_RST_REG                    0x2010C
  77 #define CPU_AHB_MBUS_CAUSE_INT_REG              0x20110
  78 #define CPU_AHB_MBUS_MASK_INT_REG               0x20114
  79 #define CPU_FTDLL_CONFIG_REG                    0x20120
  80 #define CPU_L2_CONFIG_REG                       0x20128
  81
  82
  83
  84 /* ARM Configuration register */
  85 /* CPU_CONFIG_REG (CCR) */
  86
  87
  88 /* Reset vector location */
  89 #define CCR_VEC_INIT_LOC_OFFS                   1
  90 #define CCR_VEC_INIT_LOC_MASK                   BIT1
  91 /* reset at 0x00000000 */
  92 #define CCR_VEC_INIT_LOC_0000                   (0 << CCR_VEC_INIT_LOC_OFFS)
  93 /* reset at 0xFFFF0000 */
  94 #define CCR_VEC_INIT_LOC_FF00                   (1 << CCR_VEC_INIT_LOC_OFFS)
  95
  96
  97 #define CCR_AHB_ERROR_PROP_OFFS                 2
  98 #define CCR_AHB_ERROR_PROP_MASK                 BIT2
  99 /* Erros are not propogated to AHB */
 100 #define CCR_AHB_ERROR_PROP_NO_INDICATE          (0 << CCR_AHB_ERROR_PROP_OFFS)
 101 /* Erros are propogated to AHB */
 102 #define CCR_AHB_ERROR_PROP_INDICATE             (1 << CCR_AHB_ERROR_PROP_OFFS)
 103
 104
 105 #define CCR_ENDIAN_INIT_OFFS                    3
 106 #define CCR_ENDIAN_INIT_MASK                    BIT3
 107 #define CCR_ENDIAN_INIT_LITTLE                  (0 << CCR_ENDIAN_INIT_OFFS)
 108 #define CCR_ENDIAN_INIT_BIG                     (1 << CCR_ENDIAN_INIT_OFFS)
 109
 110
 111 #define CCR_INCR_EN_OFFS                        4
 112 #define CCR_INCR_EN_MASK                        BIT4
 113 #define CCR_INCR_EN                             BIT4
 114
 115
 116 #define CCR_NCB_BLOCKING_OFFS                   5
 117 #define CCR_NCB_BLOCKING_MASK                   (1 << CCR_NCB_BLOCKING_OFFS)
 118 #define CCR_NCB_BLOCKING_NON                    (0 << CCR_NCB_BLOCKING_OFFS)
 119 #define CCR_NCB_BLOCKING_EN                     (1 << CCR_NCB_BLOCKING_OFFS)
 120
 121 #define CCR_CPU_2_MBUSL_TICK_DRV_OFFS           8
 122 #define CCR_CPU_2_MBUSL_TICK_DRV_MASK           (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS)
 123 #define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS          12
 124 #define CCR_CPU_2_MBUSL_TICK_SMPL_MASK          (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)
 125 #define CCR_ICACH_PREF_BUF_ENABLE               BIT16
 126 #define CCR_DCACH_PREF_BUF_ENABLE               BIT17
 127
 128 /* Ratio options for CPU to DDR for 6281/6192/6190 */
 129 #define CPU_2_DDR_CLK_1x3           4
 130 #define CPU_2_DDR_CLK_1x4           6
 131
 132 /* Ratio options for CPU to DDR for 6281 only */
 133 #define CPU_2_DDR_CLK_2x9           7
 134 #define CPU_2_DDR_CLK_1x5           8
 135 #define CPU_2_DDR_CLK_1x6           9
 136
 137 /* Ratio options for CPU to DDR for 6180 only */
 138 #define CPU_2_DDR_CLK_1x3_1         0x5
 139 #define CPU_2_DDR_CLK_1x4_1         0x6
 140
 141 /* Default values for CPU to Mbus-L DDR Interface Tick Driver and       */
 142 /* CPU to Mbus-L Tick Sample fields in CPU config register              */
 143
 144 #define TICK_DRV_1x1    0
 145 #define TICK_DRV_1x2    0
 146 #define TICK_DRV_1x3    1
 147 #define TICK_DRV_1x4    2
 148 #define TICK_SMPL_1x1   0
 149 #define TICK_SMPL_1x2   1
 150 #define TICK_SMPL_1x3   0
 151 #define TICK_SMPL_1x4   0
 152
 153 #define CPU_2_MBUSL_DDR_CLK_1x2                                         \
 154                  ((TICK_DRV_1x2  << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) |    \
 155                   (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
 156 #define CPU_2_MBUSL_DDR_CLK_1x3                                         \
 157                  ((TICK_DRV_1x3  << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) |    \
 158                   (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
 159 #define CPU_2_MBUSL_DDR_CLK_1x4                                         \
 160                  ((TICK_DRV_1x4  << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) |    \
 161                   (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
 162
 163 /* ARM Control and Status register */
 164 /* CPU_CTRL_STAT_REG (CCSR) */
 165
 166
 167 /*
 168 This is used to block PCI express\PCI from access Socrates/Feroceon GP
 169 while ARM boot is still in progress
 170 */
 171
 172 #define CCSR_PCI_ACCESS_OFFS                    0
 173 #define CCSR_PCI_ACCESS_MASK                    BIT0
 174 #define CCSR_PCI_ACCESS_ENABLE                  (0 << CCSR_PCI_ACCESS_OFFS)
 175 #define CCSR_PCI_ACCESS_DISBALE                 (1 << CCSR_PCI_ACCESS_OFFS)
 176
 177 #define CCSR_ARM_RESET                          BIT1
 178 #define CCSR_SELF_INT                           BIT2
 179 #define CCSR_BIG_ENDIAN                         BIT15
 180
 181
 182 /* RSTOUTn Mask Register */
 183 /* CPU_RSTOUTN_MASK_REG (CRMR) */
 184
 185 #define CRMR_PEX_RST_OUT_OFFS                   0
 186 #define CRMR_PEX_RST_OUT_MASK                   BIT0
 187 #define CRMR_PEX_RST_OUT_ENABLE                 (1 << CRMR_PEX_RST_OUT_OFFS)
 188 #define CRMR_PEX_RST_OUT_DISABLE                (0 << CRMR_PEX_RST_OUT_OFFS)
 189
 190 #define CRMR_WD_RST_OUT_OFFS                    1
 191 #define CRMR_WD_RST_OUT_MASK                    BIT1
 192 #define CRMR_WD_RST_OUT_ENABLE                  (1 << CRMR_WD_RST_OUT_OFFS)
 193 #define CRMR_WD_RST_OUT_DISBALE                 (0 << CRMR_WD_RST_OUT_OFFS)
 194
 195 #define CRMR_SOFT_RST_OUT_OFFS                  2
 196 #define CRMR_SOFT_RST_OUT_MASK                  BIT2
 197 #define CRMR_SOFT_RST_OUT_ENABLE                (1 << CRMR_SOFT_RST_OUT_OFFS)
 198 #define CRMR_SOFT_RST_OUT_DISBALE               (0 << CRMR_SOFT_RST_OUT_OFFS)
 199
 200 /* System Software Reset Register */
 201 /* CPU_SYS_SOFT_RST_REG (CSSRR) */
 202
 203 #define CSSRR_SYSTEM_SOFT_RST                   BIT0
 204
 205 /* AHB to Mbus Bridge Interrupt Cause Register*/
 206 /* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */
 207
 208 #define CAMCIR_ARM_SELF_INT                     BIT0
 209 #define CAMCIR_ARM_TIMER0_INT_REQ               BIT1
 210 #define CAMCIR_ARM_TIMER1_INT_REQ               BIT2
 211 #define CAMCIR_ARM_WD_TIMER_INT_REQ             BIT3
 212
 213
 214 /* AHB to Mbus Bridge Interrupt Mask Register*/
 215 /* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */
 216
 217 #define CAMCIR_ARM_SELF_INT_OFFS                0
 218 #define CAMCIR_ARM_SELF_INT_MASK                BIT0
 219 #define CAMCIR_ARM_SELF_INT_EN                  (1 << CAMCIR_ARM_SELF_INT_OFFS)
 220 #define CAMCIR_ARM_SELF_INT_DIS                 (0 << CAMCIR_ARM_SELF_INT_OFFS)
 221
 222
 223 #define CAMCIR_ARM_TIMER0_INT_REQ_OFFS          1
 224 #define CAMCIR_ARM_TIMER0_INT_REQ_MASK          BIT1
 225 #define CAMCIR_ARM_TIMER0_INT_REQ_EN            (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS)
 226 #define CAMCIR_ARM_TIMER0_INT_REQ_DIS           (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS)
 227
 228 #define CAMCIR_ARM_TIMER1_INT_REQ_OFFS          2
 229 #define CAMCIR_ARM_TIMER1_INT_REQ_MASK          BIT2
 230 #define CAMCIR_ARM_TIMER1_INT_REQ_EN            (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS)
 231 #define CAMCIR_ARM_TIMER1_INT_REQ_DIS           (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS)
 232
 233 #define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS        3
 234 #define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK        BIT3
 235 #define CAMCIR_ARM_WD_TIMER_INT_REQ_EN          (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS)
 236 #define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS         (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS)
 237
 238 /* CPU FTDLL Config register (CFCR) fields */
 239 #define CFCR_FTDLL_ICACHE_TAG_OFFS              0
 240 #define CFCR_FTDLL_ICACHE_TAG_MASK              (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS)
 241 #define CFCR_FTDLL_DCACHE_TAG_OFFS              8
 242 #define CFCR_FTDLL_DCACHE_TAG_MASK              (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS)
 243 #define CFCR_FTDLL_OVERWRITE_ENABLE             (1 << 15)
 244 /* For Orion 2 D2 only */
 245 #define CFCR_MRVL_CPU_ID_OFFS                   16
 246 #define CFCR_MRVL_CPU_ID_MASK                   (0x1 << CFCR_MRVL_CPU_ID_OFFS)
 247 #define CFCR_ARM_CPU_ID                         (0x0 << CFCR_MRVL_CPU_ID_OFFS)
 248 #define CFCR_MRVL_CPU_ID                        (0x1 << CFCR_MRVL_CPU_ID_OFFS)
 249 #define CFCR_VFP_SUB_ARC_NUM_OFFS               7
 250 #define CFCR_VFP_SUB_ARC_NUM_MASK               (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS)
 251 #define CFCR_VFP_SUB_ARC_NUM_1                  (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS)
 252 #define CFCR_VFP_SUB_ARC_NUM_2                  (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS)
 253
 254 /* CPU_L2_CONFIG_REG fields */
 255 #ifdef MV_CPU_LE
 256 #define CL2CR_L2_ECC_EN_OFFS                    2
 257 #define CL2CR_L2_WT_MODE_OFFS                   4
 258 #else
 259 #define CL2CR_L2_ECC_EN_OFFS                    26
 260 #define CL2CR_L2_WT_MODE_OFFS                   28
 261 #endif
 262
 263 #define CL2CR_L2_ECC_EN_MASK                    (1 << CL2CR_L2_ECC_EN_OFFS)
 264 #define CL2CR_L2_WT_MODE_MASK                   (1 << CL2CR_L2_WT_MODE_OFFS)
 265
 266 /*******************************************/
 267 /* Main Interrupt Controller Registers Map */
 268 /*******************************************/
 269
 270 #define CPU_MAIN_INT_CAUSE_REG                  0x20200
 271 #define CPU_MAIN_IRQ_MASK_REG                   0x20204
 272 #define CPU_MAIN_FIQ_MASK_REG                   0x20208
 273 #define CPU_ENPOINT_MASK_REG                    0x2020C
 274 #define CPU_MAIN_INT_CAUSE_HIGH_REG             0x20210
 275 #define CPU_MAIN_IRQ_MASK_HIGH_REG              0x20214
 276 #define CPU_MAIN_FIQ_MASK_HIGH_REG              0x20218
 277 #define CPU_ENPOINT_MASK_HIGH_REG               0x2021C
 278
 279
 280 /*******************************************/
 281 /* ARM Doorbell Registers Map              */
 282 /*******************************************/
 283
 284 #define CPU_HOST_TO_ARM_DRBL_REG                0x20400
 285 #define CPU_HOST_TO_ARM_MASK_REG                0x20404
 286 #define CPU_ARM_TO_HOST_DRBL_REG                0x20408
 287 #define CPU_ARM_TO_HOST_MASK_REG                0x2040C
 288
 289
 290
 291 /* CPU control register map */
 292 /* Set bits means value is about to change according to new value */
 293 #define CPU_CONFIG_DEFAULT_MASK                 (CCR_VEC_INIT_LOC_MASK  | CCR_AHB_ERROR_PROP_MASK)
 294
 295 #define CPU_CONFIG_DEFAULT                      (CCR_VEC_INIT_LOC_FF00)
 296
 297 /* CPU Control and status defaults */
 298 #define CPU_CTRL_STAT_DEFAULT_MASK              (CCSR_PCI_ACCESS_MASK)
 299
 300
 301 #define CPU_CTRL_STAT_DEFAULT                   (CCSR_PCI_ACCESS_ENABLE)
 302
 303 #endif /* __INCmvCpuIfRegsh */
 304