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[openwrt/svn-archive/archive.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366RB ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/platform_device.h>
17 #include <linux/delay.h>
18 #include <linux/skbuff.h>
19 #include <linux/rtl8366rb.h>
20
21 #include "rtl8366_smi.h"
22
23 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
24 #define RTL8366RB_DRIVER_VER "0.2.3"
25
26 #define RTL8366RB_PHY_NO_MAX 4
27 #define RTL8366RB_PHY_PAGE_MAX 7
28 #define RTL8366RB_PHY_ADDR_MAX 31
29 #define RTL8366RB_PHY_WAN 4
30
31 /* Switch Global Configuration register */
32 #define RTL8366RB_SGCR 0x0000
33 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
34 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
35 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
36 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
38 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
39 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
40 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
41 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
42
43 /* Port Enable Control register */
44 #define RTL8366RB_PECR 0x0001
45
46 /* Switch Security Control registers */
47 #define RTL8366RB_SSCR0 0x0002
48 #define RTL8366RB_SSCR1 0x0003
49 #define RTL8366RB_SSCR2 0x0004
50 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
51
52 #define RTL8366RB_RESET_CTRL_REG 0x0100
53 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
54 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
55
56 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
57 #define RTL8366RB_CHIP_VERSION_MASK 0xf
58 #define RTL8366RB_CHIP_ID_REG 0x0509
59 #define RTL8366RB_CHIP_ID_8366 0x5937
60
61 /* PHY registers control */
62 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
63 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
64
65 #define RTL8366RB_PHY_CTRL_READ 1
66 #define RTL8366RB_PHY_CTRL_WRITE 0
67
68 #define RTL8366RB_PHY_REG_MASK 0x1f
69 #define RTL8366RB_PHY_PAGE_OFFSET 5
70 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
71 #define RTL8366RB_PHY_NO_OFFSET 9
72 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
73
74 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
75
76 /* LED control registers */
77 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
78 #define RTL8366RB_LED_BLINKRATE_BIT 0
79 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
80
81 #define RTL8366RB_LED_CTRL_REG 0x0431
82 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
83 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
84
85 #define RTL8366RB_MIB_COUNT 33
86 #define RTL8366RB_GLOBAL_MIB_COUNT 1
87 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
88 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
89 #define RTL8366RB_MIB_CTRL_REG 0x13F0
90 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
91 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
92 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
93 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
94 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
95
96 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
97 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
98 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
99 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
100 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
101
102
103 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
104 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
105
106
107 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
108 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
109 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
110
111 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
112
113
114 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
115 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
116 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
117 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
118 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
119 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
120 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
121
122
123 #define RTL8366RB_PORT_NUM_CPU 5
124 #define RTL8366RB_NUM_PORTS 6
125 #define RTL8366RB_NUM_VLANS 16
126 #define RTL8366RB_NUM_LEDGROUPS 4
127 #define RTL8366RB_NUM_VIDS 4096
128 #define RTL8366RB_PRIORITYMAX 7
129 #define RTL8366RB_FIDMAX 7
130
131
132 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
133 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
134 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
135 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
136 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
137
138 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
139
140 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
141 RTL8366RB_PORT_2 | \
142 RTL8366RB_PORT_3 | \
143 RTL8366RB_PORT_4 | \
144 RTL8366RB_PORT_5 | \
145 RTL8366RB_PORT_CPU)
146
147 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
148 RTL8366RB_PORT_2 | \
149 RTL8366RB_PORT_3 | \
150 RTL8366RB_PORT_4 | \
151 RTL8366RB_PORT_5)
152
153 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
154 RTL8366RB_PORT_2 | \
155 RTL8366RB_PORT_3 | \
156 RTL8366RB_PORT_4)
157
158 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
159
160 #define RTL8366RB_VLAN_VID_MASK 0xfff
161 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12
162 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7
163 #define RTL8366RB_VLAN_UNTAG_SHIFT 8
164 #define RTL8366RB_VLAN_UNTAG_MASK 0xff
165 #define RTL8366RB_VLAN_MEMBER_MASK 0xff
166 #define RTL8366RB_VLAN_FID_MASK 0x7
167
168
169 /* Port ingress bandwidth control */
170 #define RTL8366RB_IB_BASE 0x0200
171 #define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + pnum)
172 #define RTL8366RB_IB_BDTH_MASK 0x3fff
173 #define RTL8366RB_IB_PREIFG_OFFSET 14
174 #define RTL8366RB_IB_PREIFG_MASK (1 << RTL8366RB_IB_PREIFG_OFFSET)
175
176 /* Port egress bandwidth control */
177 #define RTL8366RB_EB_BASE 0x02d1
178 #define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + pnum)
179 #define RTL8366RB_EB_BDTH_MASK 0x3fff
180 #define RTL8366RB_EB_PREIFG_REG 0x02f8
181 #define RTL8366RB_EB_PREIFG_OFFSET 9
182 #define RTL8366RB_EB_PREIFG_MASK (1 << RTL8366RB_EB_PREIFG_OFFSET)
183
184 #define RTL8366RB_BDTH_SW_MAX 1048512
185 #define RTL8366RB_BDTH_UNIT 64
186 #define RTL8366RB_BDTH_REG_DEFAULT 16383
187
188 /* QOS */
189 #define RTL8366RB_QOS_BIT 15
190 #define RTL8366RB_QOS_MASK (1 << RTL8366RB_QOS_BIT)
191 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
192 #define RTL8366RB_QOS_DEFAULT_PREIFG 1
193
194
195 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
196 { 0, 0, 4, "IfInOctets" },
197 { 0, 4, 4, "EtherStatsOctets" },
198 { 0, 8, 2, "EtherStatsUnderSizePkts" },
199 { 0, 10, 2, "EtherFragments" },
200 { 0, 12, 2, "EtherStatsPkts64Octets" },
201 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
202 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
203 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
204 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
205 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
206 { 0, 24, 2, "EtherOversizeStats" },
207 { 0, 26, 2, "EtherStatsJabbers" },
208 { 0, 28, 2, "IfInUcastPkts" },
209 { 0, 30, 2, "EtherStatsMulticastPkts" },
210 { 0, 32, 2, "EtherStatsBroadcastPkts" },
211 { 0, 34, 2, "EtherStatsDropEvents" },
212 { 0, 36, 2, "Dot3StatsFCSErrors" },
213 { 0, 38, 2, "Dot3StatsSymbolErrors" },
214 { 0, 40, 2, "Dot3InPauseFrames" },
215 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
216 { 0, 44, 4, "IfOutOctets" },
217 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
218 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
219 { 0, 52, 2, "Dot3sDeferredTransmissions" },
220 { 0, 54, 2, "Dot3StatsLateCollisions" },
221 { 0, 56, 2, "EtherStatsCollisions" },
222 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
223 { 0, 60, 2, "Dot3OutPauseFrames" },
224 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
225 { 0, 64, 2, "Dot1dTpPortInDiscards" },
226 { 0, 66, 2, "IfOutUcastPkts" },
227 { 0, 68, 2, "IfOutMulticastPkts" },
228 { 0, 70, 2, "IfOutBroadcastPkts" },
229 };
230
231 #define REG_WR(_smi, _reg, _val) \
232 do { \
233 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
234 if (err) \
235 return err; \
236 } while (0)
237
238 #define REG_RMW(_smi, _reg, _mask, _val) \
239 do { \
240 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
241 if (err) \
242 return err; \
243 } while (0)
244
245 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
246 {
247 int timeout = 10;
248 u32 data;
249
250 rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
251 RTL8366RB_CHIP_CTRL_RESET_HW);
252 do {
253 msleep(1);
254 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
255 return -EIO;
256
257 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
258 break;
259 } while (--timeout);
260
261 if (!timeout) {
262 printk("Timeout waiting for the switch to reset\n");
263 return -EIO;
264 }
265
266 return 0;
267 }
268
269 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
270 {
271 int err;
272
273 /* set maximum packet length to 1536 bytes */
274 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
275 RTL8366RB_SGCR_MAX_LENGTH_1536);
276
277 /* enable all ports */
278 REG_WR(smi, RTL8366RB_PECR, 0);
279
280 /* enable learning for all ports */
281 REG_WR(smi, RTL8366RB_SSCR0, 0);
282
283 /* enable auto ageing for all ports */
284 REG_WR(smi, RTL8366RB_SSCR1, 0);
285
286 /*
287 * discard VLAN tagged packets if the port is not a member of
288 * the VLAN with which the packets is associated.
289 */
290 REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
291
292 /* don't drop packets whose DA has not been learned */
293 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
294
295 return 0;
296 }
297
298 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
299 u32 phy_no, u32 page, u32 addr, u32 *data)
300 {
301 u32 reg;
302 int ret;
303
304 if (phy_no > RTL8366RB_PHY_NO_MAX)
305 return -EINVAL;
306
307 if (page > RTL8366RB_PHY_PAGE_MAX)
308 return -EINVAL;
309
310 if (addr > RTL8366RB_PHY_ADDR_MAX)
311 return -EINVAL;
312
313 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
314 RTL8366RB_PHY_CTRL_READ);
315 if (ret)
316 return ret;
317
318 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
319 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
320 (addr & RTL8366RB_PHY_REG_MASK);
321
322 ret = rtl8366_smi_write_reg(smi, reg, 0);
323 if (ret)
324 return ret;
325
326 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
327 if (ret)
328 return ret;
329
330 return 0;
331 }
332
333 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
334 u32 phy_no, u32 page, u32 addr, u32 data)
335 {
336 u32 reg;
337 int ret;
338
339 if (phy_no > RTL8366RB_PHY_NO_MAX)
340 return -EINVAL;
341
342 if (page > RTL8366RB_PHY_PAGE_MAX)
343 return -EINVAL;
344
345 if (addr > RTL8366RB_PHY_ADDR_MAX)
346 return -EINVAL;
347
348 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
349 RTL8366RB_PHY_CTRL_WRITE);
350 if (ret)
351 return ret;
352
353 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
354 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
355 (addr & RTL8366RB_PHY_REG_MASK);
356
357 ret = rtl8366_smi_write_reg(smi, reg, data);
358 if (ret)
359 return ret;
360
361 return 0;
362 }
363
364 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
365 int port, unsigned long long *val)
366 {
367 int i;
368 int err;
369 u32 addr, data;
370 u64 mibvalue;
371
372 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
373 return -EINVAL;
374
375 addr = RTL8366RB_MIB_COUNTER_BASE +
376 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
377 rtl8366rb_mib_counters[counter].offset;
378
379 /*
380 * Writing access counter address first
381 * then ASIC will prepare 64bits counter wait for being retrived
382 */
383 data = 0; /* writing data will be discard by ASIC */
384 err = rtl8366_smi_write_reg(smi, addr, data);
385 if (err)
386 return err;
387
388 /* read MIB control register */
389 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
390 if (err)
391 return err;
392
393 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
394 return -EBUSY;
395
396 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
397 return -EIO;
398
399 mibvalue = 0;
400 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
401 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
402 if (err)
403 return err;
404
405 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
406 }
407
408 *val = mibvalue;
409 return 0;
410 }
411
412 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
413 struct rtl8366_vlan_4k *vlan4k)
414 {
415 u32 data[3];
416 int err;
417 int i;
418
419 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
420
421 if (vid >= RTL8366RB_NUM_VIDS)
422 return -EINVAL;
423
424 /* write VID */
425 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
426 vid & RTL8366RB_VLAN_VID_MASK);
427 if (err)
428 return err;
429
430 /* write table access control word */
431 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
432 RTL8366RB_TABLE_VLAN_READ_CTRL);
433 if (err)
434 return err;
435
436 for (i = 0; i < 3; i++) {
437 err = rtl8366_smi_read_reg(smi,
438 RTL8366RB_VLAN_TABLE_READ_BASE + i,
439 &data[i]);
440 if (err)
441 return err;
442 }
443
444 vlan4k->vid = vid;
445 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
446 RTL8366RB_VLAN_UNTAG_MASK;
447 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
448 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
449
450 return 0;
451 }
452
453 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
454 const struct rtl8366_vlan_4k *vlan4k)
455 {
456 u32 data[3];
457 int err;
458 int i;
459
460 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
461 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
462 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
463 vlan4k->fid > RTL8366RB_FIDMAX)
464 return -EINVAL;
465
466 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
467 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
468 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
469 RTL8366RB_VLAN_UNTAG_SHIFT);
470 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
471
472 for (i = 0; i < 3; i++) {
473 err = rtl8366_smi_write_reg(smi,
474 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
475 data[i]);
476 if (err)
477 return err;
478 }
479
480 /* write table access control word */
481 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
482 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
483
484 return err;
485 }
486
487 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
488 struct rtl8366_vlan_mc *vlanmc)
489 {
490 u32 data[3];
491 int err;
492 int i;
493
494 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
495
496 if (index >= RTL8366RB_NUM_VLANS)
497 return -EINVAL;
498
499 for (i = 0; i < 3; i++) {
500 err = rtl8366_smi_read_reg(smi,
501 RTL8366RB_VLAN_MC_BASE(index) + i,
502 &data[i]);
503 if (err)
504 return err;
505 }
506
507 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
508 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
509 RTL8366RB_VLAN_PRIORITY_MASK;
510 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
511 RTL8366RB_VLAN_UNTAG_MASK;
512 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
513 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
514
515 return 0;
516 }
517
518 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
519 const struct rtl8366_vlan_mc *vlanmc)
520 {
521 u32 data[3];
522 int err;
523 int i;
524
525 if (index >= RTL8366RB_NUM_VLANS ||
526 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
527 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
528 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
529 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
530 vlanmc->fid > RTL8366RB_FIDMAX)
531 return -EINVAL;
532
533 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
534 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
535 RTL8366RB_VLAN_PRIORITY_SHIFT);
536 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
537 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
538 RTL8366RB_VLAN_UNTAG_SHIFT);
539 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
540
541 for (i = 0; i < 3; i++) {
542 err = rtl8366_smi_write_reg(smi,
543 RTL8366RB_VLAN_MC_BASE(index) + i,
544 data[i]);
545 if (err)
546 return err;
547 }
548
549 return 0;
550 }
551
552 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
553 {
554 u32 data;
555 int err;
556
557 if (port >= RTL8366RB_NUM_PORTS)
558 return -EINVAL;
559
560 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
561 &data);
562 if (err)
563 return err;
564
565 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
566 RTL8366RB_PORT_VLAN_CTRL_MASK;
567
568 return 0;
569
570 }
571
572 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
573 {
574 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
575 return -EINVAL;
576
577 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
578 RTL8366RB_PORT_VLAN_CTRL_MASK <<
579 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
580 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
581 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
582 }
583
584 static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
585 {
586 unsigned max = RTL8366RB_NUM_VLANS;
587
588 if (smi->vlan4k_enabled)
589 max = RTL8366RB_NUM_VIDS - 1;
590
591 if (vlan == 0 || vlan >= max)
592 return 0;
593
594 return 1;
595 }
596
597 static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
598 {
599 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
600 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
601 }
602
603 static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
604 {
605 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
606 RTL8366RB_SGCR_EN_VLAN_4KTB,
607 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
608 }
609
610 static int rtl8366rb_enable_port(struct rtl8366_smi *smi, int port, int enable)
611 {
612 return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, (1 << port),
613 (enable) ? 0 : (1 << port));
614 }
615
616 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
617 const struct switch_attr *attr,
618 struct switch_val *val)
619 {
620 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
621
622 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
623 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
624 }
625
626 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
627 const struct switch_attr *attr,
628 struct switch_val *val)
629 {
630 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
631 u32 data;
632
633 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
634
635 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
636
637 return 0;
638 }
639
640 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
641 const struct switch_attr *attr,
642 struct switch_val *val)
643 {
644 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
645
646 if (val->value.i >= 6)
647 return -EINVAL;
648
649 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
650 RTL8366RB_LED_BLINKRATE_MASK,
651 val->value.i);
652 }
653
654 static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
655 const struct switch_attr *attr,
656 struct switch_val *val)
657 {
658 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
659 u32 data;
660
661 rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
662 val->value.i = !data;
663
664 return 0;
665 }
666
667
668 static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
669 const struct switch_attr *attr,
670 struct switch_val *val)
671 {
672 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
673 u32 portmask = 0;
674 int err = 0;
675
676 if (!val->value.i)
677 portmask = RTL8366RB_PORT_ALL;
678
679 /* set learning for all ports */
680 REG_WR(smi, RTL8366RB_SSCR0, portmask);
681
682 /* set auto ageing for all ports */
683 REG_WR(smi, RTL8366RB_SSCR1, portmask);
684
685 return 0;
686 }
687
688
689 static const char *rtl8366rb_speed_str(unsigned speed)
690 {
691 switch (speed) {
692 case 0:
693 return "10baseT";
694 case 1:
695 return "100baseT";
696 case 2:
697 return "1000baseT";
698 }
699
700 return "unknown";
701 }
702
703 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
704 const struct switch_attr *attr,
705 struct switch_val *val)
706 {
707 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
708 u32 len = 0, data = 0;
709
710 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
711 return -EINVAL;
712
713 memset(smi->buf, '\0', sizeof(smi->buf));
714 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
715 (val->port_vlan / 2), &data);
716
717 if (val->port_vlan % 2)
718 data = data >> 8;
719
720 if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
721 len = snprintf(smi->buf, sizeof(smi->buf),
722 "port:%d link:up speed:%s %s-duplex %s%s%s",
723 val->port_vlan,
724 rtl8366rb_speed_str(data &
725 RTL8366RB_PORT_STATUS_SPEED_MASK),
726 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
727 "full" : "half",
728 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
729 "tx-pause ": "",
730 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
731 "rx-pause " : "",
732 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
733 "nway ": "");
734 } else {
735 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
736 val->port_vlan);
737 }
738
739 val->value.s = smi->buf;
740 val->len = len;
741
742 return 0;
743 }
744
745 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
746 const struct switch_attr *attr,
747 struct switch_val *val)
748 {
749 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
750 u32 data;
751 u32 mask;
752 u32 reg;
753
754 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
755 return -EINVAL;
756
757 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
758 reg = RTL8366RB_LED_BLINKRATE_REG;
759 mask = 0xF << 4;
760 data = val->value.i << 4;
761 } else {
762 reg = RTL8366RB_LED_CTRL_REG;
763 mask = 0xF << (val->port_vlan * 4),
764 data = val->value.i << (val->port_vlan * 4);
765 }
766
767 return rtl8366_smi_rmwr(smi, reg, mask, data);
768 }
769
770 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
771 const struct switch_attr *attr,
772 struct switch_val *val)
773 {
774 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
775 u32 data = 0;
776
777 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
778 return -EINVAL;
779
780 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
781 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
782
783 return 0;
784 }
785
786 static int rtl8366rb_sw_set_port_disable(struct switch_dev *dev,
787 const struct switch_attr *attr,
788 struct switch_val *val)
789 {
790 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
791 u32 mask, data;
792
793 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
794 return -EINVAL;
795
796 mask = 1 << val->port_vlan ;
797 if (val->value.i)
798 data = mask;
799 else
800 data = 0;
801
802 return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data);
803 }
804
805 static int rtl8366rb_sw_get_port_disable(struct switch_dev *dev,
806 const struct switch_attr *attr,
807 struct switch_val *val)
808 {
809 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
810 u32 data;
811
812 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
813 return -EINVAL;
814
815 rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data);
816 if (data & (1 << val->port_vlan))
817 val->value.i = 1;
818 else
819 val->value.i = 0;
820
821 return 0;
822 }
823
824 static int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev,
825 const struct switch_attr *attr,
826 struct switch_val *val)
827 {
828 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
829
830 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
831 return -EINVAL;
832
833 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
834 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
835 else
836 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
837
838 return rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan),
839 RTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK,
840 val->value.i |
841 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET));
842
843 }
844
845 static int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev,
846 const struct switch_attr *attr,
847 struct switch_val *val)
848 {
849 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
850 u32 data;
851
852 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
853 return -EINVAL;
854
855 rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data);
856 data &= RTL8366RB_IB_BDTH_MASK;
857 if (data < RTL8366RB_IB_BDTH_MASK)
858 data += 1;
859
860 val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
861
862 return 0;
863 }
864
865 static int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev,
866 const struct switch_attr *attr,
867 struct switch_val *val)
868 {
869 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
870
871 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
872 return -EINVAL;
873
874 rtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG,
875 RTL8366RB_EB_PREIFG_MASK,
876 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET));
877
878 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
879 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
880 else
881 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
882
883 return rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan),
884 RTL8366RB_EB_BDTH_MASK, val->value.i );
885
886 }
887
888 static int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev,
889 const struct switch_attr *attr,
890 struct switch_val *val)
891 {
892 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
893 u32 data;
894
895 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
896 return -EINVAL;
897
898 rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data);
899 data &= RTL8366RB_EB_BDTH_MASK;
900 if (data < RTL8366RB_EB_BDTH_MASK)
901 data += 1;
902
903 val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
904
905 return 0;
906 }
907
908 static int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev,
909 const struct switch_attr *attr,
910 struct switch_val *val)
911 {
912 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
913 u32 data;
914
915 if (val->value.i)
916 data = RTL8366RB_QOS_MASK;
917 else
918 data = 0;
919
920 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data);
921 }
922
923 static int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev,
924 const struct switch_attr *attr,
925 struct switch_val *val)
926 {
927 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
928 u32 data;
929
930 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
931 if (data & RTL8366RB_QOS_MASK)
932 val->value.i = 1;
933 else
934 val->value.i = 0;
935
936 return 0;
937 }
938
939 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
940 const struct switch_attr *attr,
941 struct switch_val *val)
942 {
943 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
944
945 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
946 return -EINVAL;
947
948 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
949 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
950 }
951
952 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
953 {
954 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
955 int err;
956
957 err = rtl8366rb_reset_chip(smi);
958 if (err)
959 return err;
960
961 err = rtl8366rb_hw_init(smi);
962 if (err)
963 return err;
964
965 return rtl8366_reset_vlan(smi);
966 }
967
968 static struct switch_attr rtl8366rb_globals[] = {
969 {
970 .type = SWITCH_TYPE_INT,
971 .name = "enable_learning",
972 .description = "Enable learning, enable aging",
973 .set = rtl8366rb_sw_set_learning_enable,
974 .get = rtl8366rb_sw_get_learning_enable,
975 .max = 1
976 }, {
977 .type = SWITCH_TYPE_INT,
978 .name = "enable_vlan",
979 .description = "Enable VLAN mode",
980 .set = rtl8366_sw_set_vlan_enable,
981 .get = rtl8366_sw_get_vlan_enable,
982 .max = 1,
983 .ofs = 1
984 }, {
985 .type = SWITCH_TYPE_INT,
986 .name = "enable_vlan4k",
987 .description = "Enable VLAN 4K mode",
988 .set = rtl8366_sw_set_vlan_enable,
989 .get = rtl8366_sw_get_vlan_enable,
990 .max = 1,
991 .ofs = 2
992 }, {
993 .type = SWITCH_TYPE_NOVAL,
994 .name = "reset_mibs",
995 .description = "Reset all MIB counters",
996 .set = rtl8366rb_sw_reset_mibs,
997 }, {
998 .type = SWITCH_TYPE_INT,
999 .name = "blinkrate",
1000 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1001 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1002 .set = rtl8366rb_sw_set_blinkrate,
1003 .get = rtl8366rb_sw_get_blinkrate,
1004 .max = 5
1005 }, {
1006 .type = SWITCH_TYPE_INT,
1007 .name = "enable_qos",
1008 .description = "Enable QOS",
1009 .set = rtl8366rb_sw_set_qos_enable,
1010 .get = rtl8366rb_sw_get_qos_enable,
1011 .max = 1
1012 },
1013 };
1014
1015 static struct switch_attr rtl8366rb_port[] = {
1016 {
1017 .type = SWITCH_TYPE_STRING,
1018 .name = "link",
1019 .description = "Get port link information",
1020 .max = 1,
1021 .set = NULL,
1022 .get = rtl8366rb_sw_get_port_link,
1023 }, {
1024 .type = SWITCH_TYPE_NOVAL,
1025 .name = "reset_mib",
1026 .description = "Reset single port MIB counters",
1027 .set = rtl8366rb_sw_reset_port_mibs,
1028 }, {
1029 .type = SWITCH_TYPE_STRING,
1030 .name = "mib",
1031 .description = "Get MIB counters for port",
1032 .max = 33,
1033 .set = NULL,
1034 .get = rtl8366_sw_get_port_mib,
1035 }, {
1036 .type = SWITCH_TYPE_INT,
1037 .name = "led",
1038 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1039 .max = 15,
1040 .set = rtl8366rb_sw_set_port_led,
1041 .get = rtl8366rb_sw_get_port_led,
1042 }, {
1043 .type = SWITCH_TYPE_INT,
1044 .name = "disable",
1045 .description = "Get/Set port state (enabled or disabled)",
1046 .max = 1,
1047 .set = rtl8366rb_sw_set_port_disable,
1048 .get = rtl8366rb_sw_get_port_disable,
1049 }, {
1050 .type = SWITCH_TYPE_INT,
1051 .name = "rate_in",
1052 .description = "Get/Set port ingress (incoming) bandwidth limit in kbps",
1053 .max = RTL8366RB_BDTH_SW_MAX,
1054 .set = rtl8366rb_sw_set_port_rate_in,
1055 .get = rtl8366rb_sw_get_port_rate_in,
1056 }, {
1057 .type = SWITCH_TYPE_INT,
1058 .name = "rate_out",
1059 .description = "Get/Set port egress (outgoing) bandwidth limit in kbps",
1060 .max = RTL8366RB_BDTH_SW_MAX,
1061 .set = rtl8366rb_sw_set_port_rate_out,
1062 .get = rtl8366rb_sw_get_port_rate_out,
1063 },
1064 };
1065
1066 static struct switch_attr rtl8366rb_vlan[] = {
1067 {
1068 .type = SWITCH_TYPE_STRING,
1069 .name = "info",
1070 .description = "Get vlan information",
1071 .max = 1,
1072 .set = NULL,
1073 .get = rtl8366_sw_get_vlan_info,
1074 }, {
1075 .type = SWITCH_TYPE_INT,
1076 .name = "fid",
1077 .description = "Get/Set vlan FID",
1078 .max = RTL8366RB_FIDMAX,
1079 .set = rtl8366_sw_set_vlan_fid,
1080 .get = rtl8366_sw_get_vlan_fid,
1081 },
1082 };
1083
1084 static const struct switch_dev_ops rtl8366_ops = {
1085 .attr_global = {
1086 .attr = rtl8366rb_globals,
1087 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1088 },
1089 .attr_port = {
1090 .attr = rtl8366rb_port,
1091 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1092 },
1093 .attr_vlan = {
1094 .attr = rtl8366rb_vlan,
1095 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1096 },
1097
1098 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1099 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1100 .get_port_pvid = rtl8366_sw_get_port_pvid,
1101 .set_port_pvid = rtl8366_sw_set_port_pvid,
1102 .reset_switch = rtl8366rb_sw_reset_switch,
1103 };
1104
1105 static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
1106 {
1107 struct switch_dev *dev = &smi->sw_dev;
1108 int err;
1109
1110 dev->name = "RTL8366RB";
1111 dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
1112 dev->ports = RTL8366RB_NUM_PORTS;
1113 dev->vlans = RTL8366RB_NUM_VIDS;
1114 dev->ops = &rtl8366_ops;
1115 dev->devname = dev_name(smi->parent);
1116
1117 err = register_switch(dev, NULL);
1118 if (err)
1119 dev_err(smi->parent, "switch registration failed\n");
1120
1121 return err;
1122 }
1123
1124 static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
1125 {
1126 unregister_switch(&smi->sw_dev);
1127 }
1128
1129 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1130 {
1131 struct rtl8366_smi *smi = bus->priv;
1132 u32 val = 0;
1133 int err;
1134
1135 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1136 if (err)
1137 return 0xffff;
1138
1139 return val;
1140 }
1141
1142 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1143 {
1144 struct rtl8366_smi *smi = bus->priv;
1145 u32 t;
1146 int err;
1147
1148 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1149 /* flush write */
1150 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1151
1152 return err;
1153 }
1154
1155 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1156 {
1157 return (bus->read == rtl8366rb_mii_read &&
1158 bus->write == rtl8366rb_mii_write);
1159 }
1160
1161 static int rtl8366rb_setup(struct rtl8366_smi *smi)
1162 {
1163 int ret;
1164
1165 ret = rtl8366rb_reset_chip(smi);
1166 if (ret)
1167 return ret;
1168
1169 ret = rtl8366rb_hw_init(smi);
1170 return ret;
1171 }
1172
1173 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1174 {
1175 u32 chip_id = 0;
1176 u32 chip_ver = 0;
1177 int ret;
1178
1179 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1180 if (ret) {
1181 dev_err(smi->parent, "unable to read chip id\n");
1182 return ret;
1183 }
1184
1185 switch (chip_id) {
1186 case RTL8366RB_CHIP_ID_8366:
1187 break;
1188 default:
1189 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1190 return -ENODEV;
1191 }
1192
1193 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1194 &chip_ver);
1195 if (ret) {
1196 dev_err(smi->parent, "unable to read chip version\n");
1197 return ret;
1198 }
1199
1200 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1201 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1202
1203 return 0;
1204 }
1205
1206 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1207 .detect = rtl8366rb_detect,
1208 .setup = rtl8366rb_setup,
1209
1210 .mii_read = rtl8366rb_mii_read,
1211 .mii_write = rtl8366rb_mii_write,
1212
1213 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1214 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1215 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1216 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1217 .get_mc_index = rtl8366rb_get_mc_index,
1218 .set_mc_index = rtl8366rb_set_mc_index,
1219 .get_mib_counter = rtl8366rb_get_mib_counter,
1220 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1221 .enable_vlan = rtl8366rb_enable_vlan,
1222 .enable_vlan4k = rtl8366rb_enable_vlan4k,
1223 .enable_port = rtl8366rb_enable_port,
1224 };
1225
1226 static int __devinit rtl8366rb_probe(struct platform_device *pdev)
1227 {
1228 static int rtl8366_smi_version_printed;
1229 struct rtl8366rb_platform_data *pdata;
1230 struct rtl8366_smi *smi;
1231 int err;
1232
1233 if (!rtl8366_smi_version_printed++)
1234 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1235 " version " RTL8366RB_DRIVER_VER"\n");
1236
1237 pdata = pdev->dev.platform_data;
1238 if (!pdata) {
1239 dev_err(&pdev->dev, "no platform data specified\n");
1240 err = -EINVAL;
1241 goto err_out;
1242 }
1243
1244 smi = rtl8366_smi_alloc(&pdev->dev);
1245 if (!smi) {
1246 err = -ENOMEM;
1247 goto err_out;
1248 }
1249
1250 smi->gpio_sda = pdata->gpio_sda;
1251 smi->gpio_sck = pdata->gpio_sck;
1252 smi->ops = &rtl8366rb_smi_ops;
1253 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1254 smi->num_ports = RTL8366RB_NUM_PORTS;
1255 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1256 smi->mib_counters = rtl8366rb_mib_counters;
1257 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1258
1259 err = rtl8366_smi_init(smi);
1260 if (err)
1261 goto err_free_smi;
1262
1263 platform_set_drvdata(pdev, smi);
1264
1265 err = rtl8366rb_switch_init(smi);
1266 if (err)
1267 goto err_clear_drvdata;
1268
1269 return 0;
1270
1271 err_clear_drvdata:
1272 platform_set_drvdata(pdev, NULL);
1273 rtl8366_smi_cleanup(smi);
1274 err_free_smi:
1275 kfree(smi);
1276 err_out:
1277 return err;
1278 }
1279
1280 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1281 {
1282 if (!rtl8366rb_mii_bus_match(phydev->bus))
1283 return -EINVAL;
1284
1285 return 0;
1286 }
1287
1288 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1289 {
1290 /* phy 4 might be connected to a second mac, allow aneg config */
1291 if (phydev->addr == RTL8366RB_PHY_WAN)
1292 return genphy_config_aneg(phydev);
1293
1294 return 0;
1295 }
1296
1297 static struct phy_driver rtl8366rb_phy_driver = {
1298 .phy_id = 0x001cc960,
1299 .name = "Realtek RTL8366RB",
1300 .phy_id_mask = 0x1ffffff0,
1301 .features = PHY_GBIT_FEATURES,
1302 .config_aneg = rtl8366rb_phy_config_aneg,
1303 .config_init = rtl8366rb_phy_config_init,
1304 .read_status = genphy_read_status,
1305 .driver = {
1306 .owner = THIS_MODULE,
1307 },
1308 };
1309
1310 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1311 {
1312 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1313
1314 if (smi) {
1315 rtl8366rb_switch_cleanup(smi);
1316 platform_set_drvdata(pdev, NULL);
1317 rtl8366_smi_cleanup(smi);
1318 kfree(smi);
1319 }
1320
1321 return 0;
1322 }
1323
1324 static struct platform_driver rtl8366rb_driver = {
1325 .driver = {
1326 .name = RTL8366RB_DRIVER_NAME,
1327 .owner = THIS_MODULE,
1328 },
1329 .probe = rtl8366rb_probe,
1330 .remove = __devexit_p(rtl8366rb_remove),
1331 };
1332
1333 static int __init rtl8366rb_module_init(void)
1334 {
1335 int ret;
1336 ret = platform_driver_register(&rtl8366rb_driver);
1337 if (ret)
1338 return ret;
1339
1340 ret = phy_driver_register(&rtl8366rb_phy_driver);
1341 if (ret)
1342 goto err_platform_unregister;
1343
1344 return 0;
1345
1346 err_platform_unregister:
1347 platform_driver_unregister(&rtl8366rb_driver);
1348 return ret;
1349 }
1350 module_init(rtl8366rb_module_init);
1351
1352 static void __exit rtl8366rb_module_exit(void)
1353 {
1354 phy_driver_unregister(&rtl8366rb_phy_driver);
1355 platform_driver_unregister(&rtl8366rb_driver);
1356 }
1357 module_exit(rtl8366rb_module_exit);
1358
1359 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1360 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1361 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1362 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1363 MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
1364 MODULE_LICENSE("GPL v2");
1365 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
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