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generic: rtl8366: introduce rtl8366_smi_rmwr function
[openwrt/svn-archive/archive.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366rb.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
29
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
33
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
36 #define RTL8366_CHIP_CTRL_VLAN_4KTB (1 << 14)
37
38 #define RTL8366_RESET_CTRL_REG 0x0100
39 #define RTL8366_CHIP_CTRL_RESET_HW 1
40 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
41
42 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x050A
43 #define RTL8366S_CHIP_VERSION_MASK 0xf
44 #define RTL8366S_CHIP_ID_REG 0x0509
45 #define RTL8366S_CHIP_ID_8366 0x5937
46
47 /* PHY registers control */
48 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8000
49 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8002
50
51 #define RTL8366S_PHY_CTRL_READ 1
52 #define RTL8366S_PHY_CTRL_WRITE 0
53
54 #define RTL8366S_PHY_REG_MASK 0x1f
55 #define RTL8366S_PHY_PAGE_OFFSET 5
56 #define RTL8366S_PHY_PAGE_MASK (0xf << 5)
57 #define RTL8366S_PHY_NO_OFFSET 9
58 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
59
60 /* LED control registers */
61 #define RTL8366_LED_BLINKRATE_REG 0x0430
62 #define RTL8366_LED_BLINKRATE_BIT 0
63 #define RTL8366_LED_BLINKRATE_MASK 0x0007
64
65 #define RTL8366_LED_CTRL_REG 0x0431
66 #define RTL8366_LED_0_1_CTRL_REG 0x0432
67 #define RTL8366_LED_2_3_CTRL_REG 0x0433
68
69 #define RTL8366S_MIB_COUNT 33
70 #define RTL8366S_GLOBAL_MIB_COUNT 1
71 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0050
72 #define RTL8366S_MIB_COUNTER_BASE 0x1000
73 #define RTL8366S_MIB_CTRL_REG 0x13F0
74 #define RTL8366S_MIB_CTRL_USER_MASK 0x0FFC
75 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
76 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0001
77
78 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
79 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
80 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
81
82
83 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0063
84 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
85 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
86 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
87 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
88
89
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018C
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
92
93
94 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
95 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
96 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
97
98 #define RTL8366S_VLAN_MEMCONF_BASE 0x0020
99
100
101 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0014
102 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
103 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
104 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
105 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
106 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
107 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
108
109
110 #define RTL8366_PORT_NUM_CPU 5
111 #define RTL8366_NUM_PORTS 6
112 #define RTL8366_NUM_VLANS 16
113 #define RTL8366_NUM_LEDGROUPS 4
114 #define RTL8366_NUM_VIDS 4096
115 #define RTL8366S_PRIORITYMAX 7
116 #define RTL8366S_FIDMAX 7
117
118
119 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
120 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
121 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
122 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
123 #define RTL8366_PORT_5 (1 << 4) /* In userspace port 4 */
124
125 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
126
127 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
128 RTL8366_PORT_2 | \
129 RTL8366_PORT_3 | \
130 RTL8366_PORT_4 | \
131 RTL8366_PORT_5 | \
132 RTL8366_PORT_CPU)
133
134 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
135 RTL8366_PORT_2 | \
136 RTL8366_PORT_3 | \
137 RTL8366_PORT_4 | \
138 RTL8366_PORT_5)
139
140 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
141 RTL8366_PORT_2 | \
142 RTL8366_PORT_3 | \
143 RTL8366_PORT_4)
144
145 #define RTL8366_PORT_ALL_INTERNAL RTL8366_PORT_CPU
146
147 struct rtl8366rb {
148 struct device *parent;
149 struct rtl8366_smi smi;
150 struct switch_dev dev;
151 char buf[4096];
152 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
153 struct dentry *debugfs_root;
154 #endif
155 };
156
157 struct rtl8366rb_vlan_mc {
158 u16 reserved2:1;
159 u16 priority:3;
160 u16 vid:12;
161 u16 untag:8;
162 u16 member:8;
163 u16 stag_mbr:8;
164 u16 stag_idx:3;
165 u16 reserved1:2;
166 u16 fid:3;
167 };
168
169 struct rtl8366rb_vlan_4k {
170 u16 reserved1:4;
171 u16 vid:12;
172 u16 untag:8;
173 u16 member:8;
174 u16 reserved2:13;
175 u16 fid:3;
176 };
177
178 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
179 u16 gl_dbg_reg;
180 #endif
181
182 struct mib_counter {
183 unsigned offset;
184 unsigned length;
185 const char *name;
186 };
187
188 static struct mib_counter rtl8366rb_mib_counters[RTL8366S_MIB_COUNT] = {
189 { 0, 4, "IfInOctets" },
190 { 4, 4, "EtherStatsOctets" },
191 { 8, 2, "EtherStatsUnderSizePkts" },
192 { 10, 2, "EtherFragments" },
193 { 12, 2, "EtherStatsPkts64Octets" },
194 { 14, 2, "EtherStatsPkts65to127Octets" },
195 { 16, 2, "EtherStatsPkts128to255Octets" },
196 { 18, 2, "EtherStatsPkts256to511Octets" },
197 { 20, 2, "EtherStatsPkts512to1023Octets" },
198 { 22, 2, "EtherStatsPkts1024to1518Octets" },
199 { 24, 2, "EtherOversizeStats" },
200 { 26, 2, "EtherStatsJabbers" },
201 { 28, 2, "IfInUcastPkts" },
202 { 30, 2, "EtherStatsMulticastPkts" },
203 { 32, 2, "EtherStatsBroadcastPkts" },
204 { 34, 2, "EtherStatsDropEvents" },
205 { 36, 2, "Dot3StatsFCSErrors" },
206 { 38, 2, "Dot3StatsSymbolErrors" },
207 { 40, 2, "Dot3InPauseFrames" },
208 { 42, 2, "Dot3ControlInUnknownOpcodes" },
209 { 44, 4, "IfOutOctets" },
210 { 48, 2, "Dot3StatsSingleCollisionFrames" },
211 { 50, 2, "Dot3StatMultipleCollisionFrames" },
212 { 52, 2, "Dot3sDeferredTransmissions" },
213 { 54, 2, "Dot3StatsLateCollisions" },
214 { 56, 2, "EtherStatsCollisions" },
215 { 58, 2, "Dot3StatsExcessiveCollisions" },
216 { 60, 2, "Dot3OutPauseFrames" },
217 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
218 { 64, 2, "Dot1dTpPortInDiscards" },
219 { 66, 2, "IfOutUcastPkts" },
220 { 68, 2, "IfOutMulticastPkts" },
221 { 70, 2, "IfOutBroadcastPkts" },
222 };
223
224 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
225 {
226 return container_of(smi, struct rtl8366rb, smi);
227 }
228
229 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
230 {
231 return container_of(sw, struct rtl8366rb, dev);
232 }
233
234 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
235 {
236 struct rtl8366rb *rtl = sw_to_rtl8366rb(sw);
237 return &rtl->smi;
238 }
239
240 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
241 {
242 int timeout = 10;
243 u32 data;
244
245 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
246 RTL8366_CHIP_CTRL_RESET_HW);
247 do {
248 msleep(1);
249 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
250 return -EIO;
251
252 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
253 break;
254 } while (--timeout);
255
256 if (!timeout) {
257 printk("Timeout waiting for the switch to reset\n");
258 return -EIO;
259 }
260
261 return 0;
262 }
263
264 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
265 u32 phy_no, u32 page, u32 addr, u32 *data)
266 {
267 u32 reg;
268 int ret;
269
270 if (phy_no > RTL8366S_PHY_NO_MAX)
271 return -EINVAL;
272
273 if (page > RTL8366S_PHY_PAGE_MAX)
274 return -EINVAL;
275
276 if (addr > RTL8366S_PHY_ADDR_MAX)
277 return -EINVAL;
278
279 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
280 RTL8366S_PHY_CTRL_READ);
281 if (ret)
282 return ret;
283
284 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
285 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
286 (addr & RTL8366S_PHY_REG_MASK);
287
288 ret = rtl8366_smi_write_reg(smi, reg, 0);
289 if (ret)
290 return ret;
291
292 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
293 if (ret)
294 return ret;
295
296 return 0;
297 }
298
299 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
300 u32 phy_no, u32 page, u32 addr, u32 data)
301 {
302 u32 reg;
303 int ret;
304
305 if (phy_no > RTL8366S_PHY_NO_MAX)
306 return -EINVAL;
307
308 if (page > RTL8366S_PHY_PAGE_MAX)
309 return -EINVAL;
310
311 if (addr > RTL8366S_PHY_ADDR_MAX)
312 return -EINVAL;
313
314 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
315 RTL8366S_PHY_CTRL_WRITE);
316 if (ret)
317 return ret;
318
319 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
320 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
321 (addr & RTL8366S_PHY_REG_MASK);
322
323 ret = rtl8366_smi_write_reg(smi, reg, data);
324 if (ret)
325 return ret;
326
327 return 0;
328 }
329
330 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
331 int port, unsigned long long *val)
332 {
333 int i;
334 int err;
335 u32 addr, data;
336 u64 mibvalue;
337
338 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
339 return -EINVAL;
340
341 addr = RTL8366S_MIB_COUNTER_BASE +
342 RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) +
343 rtl8366rb_mib_counters[counter].offset;
344
345 /*
346 * Writing access counter address first
347 * then ASIC will prepare 64bits counter wait for being retrived
348 */
349 data = 0; /* writing data will be discard by ASIC */
350 err = rtl8366_smi_write_reg(smi, addr, data);
351 if (err)
352 return err;
353
354 /* read MIB control register */
355 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
356 if (err)
357 return err;
358
359 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
360 return -EBUSY;
361
362 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
363 return -EIO;
364
365 mibvalue = 0;
366 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
367 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
368 if (err)
369 return err;
370
371 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
372 }
373
374 *val = mibvalue;
375 return 0;
376 }
377
378 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
379 struct rtl8366_vlan_4k *vlan4k)
380 {
381 struct rtl8366rb_vlan_4k vlan4k_priv;
382 int err;
383 u32 data;
384 u16 *tableaddr;
385
386 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
387 vlan4k_priv.vid = vid;
388
389 if (vid >= RTL8366_NUM_VIDS)
390 return -EINVAL;
391
392 tableaddr = (u16 *)&vlan4k_priv;
393
394 /* write VID */
395 data = *tableaddr;
396 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
397 if (err)
398 return err;
399
400 /* write table access control word */
401 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
402 RTL8366S_TABLE_VLAN_READ_CTRL);
403 if (err)
404 return err;
405
406 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
407 if (err)
408 return err;
409
410 *tableaddr = data;
411 tableaddr++;
412
413 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
414 &data);
415 if (err)
416 return err;
417
418 *tableaddr = data;
419 tableaddr++;
420
421 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 2,
422 &data);
423 if (err)
424 return err;
425 *tableaddr = data;
426
427 vlan4k->vid = vid;
428 vlan4k->untag = vlan4k_priv.untag;
429 vlan4k->member = vlan4k_priv.member;
430 vlan4k->fid = vlan4k_priv.fid;
431
432 return 0;
433 }
434
435 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
436 const struct rtl8366_vlan_4k *vlan4k)
437 {
438 struct rtl8366rb_vlan_4k vlan4k_priv;
439 int err;
440 u32 data;
441 u16 *tableaddr;
442
443 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
444 vlan4k->member > RTL8366_PORT_ALL ||
445 vlan4k->untag > RTL8366_PORT_ALL ||
446 vlan4k->fid > RTL8366S_FIDMAX)
447 return -EINVAL;
448
449 vlan4k_priv.vid = vlan4k->vid;
450 vlan4k_priv.untag = vlan4k->untag;
451 vlan4k_priv.member = vlan4k->member;
452 vlan4k_priv.fid = vlan4k->fid;
453
454 tableaddr = (u16 *)&vlan4k_priv;
455
456 data = *tableaddr;
457
458 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
459 if (err)
460 return err;
461
462 tableaddr++;
463
464 data = *tableaddr;
465
466 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
467 data);
468 if (err)
469 return err;
470
471 tableaddr++;
472
473 data = *tableaddr;
474
475 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 2,
476 data);
477 if (err)
478 return err;
479
480 /* write table access control word */
481 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
482 RTL8366S_TABLE_VLAN_WRITE_CTRL);
483
484 return err;
485 }
486
487 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
488 struct rtl8366_vlan_mc *vlanmc)
489 {
490 struct rtl8366rb_vlan_mc vlanmc_priv;
491 int err;
492 u32 addr;
493 u32 data;
494 u16 *tableaddr;
495
496 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
497
498 if (index >= RTL8366_NUM_VLANS)
499 return -EINVAL;
500
501 tableaddr = (u16 *)&vlanmc_priv;
502
503 addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
504 err = rtl8366_smi_read_reg(smi, addr, &data);
505 if (err)
506 return err;
507
508 *tableaddr = data;
509 tableaddr++;
510
511 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
512 err = rtl8366_smi_read_reg(smi, addr, &data);
513 if (err)
514 return err;
515
516 *tableaddr = data;
517 tableaddr++;
518
519 addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
520 err = rtl8366_smi_read_reg(smi, addr, &data);
521 if (err)
522 return err;
523
524 *tableaddr = data;
525
526 vlanmc->vid = vlanmc_priv.vid;
527 vlanmc->priority = vlanmc_priv.priority;
528 vlanmc->untag = vlanmc_priv.untag;
529 vlanmc->member = vlanmc_priv.member;
530 vlanmc->fid = vlanmc_priv.fid;
531
532 return 0;
533 }
534
535 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
536 const struct rtl8366_vlan_mc *vlanmc)
537 {
538 struct rtl8366rb_vlan_mc vlanmc_priv;
539 int err;
540 u32 addr;
541 u32 data;
542 u16 *tableaddr;
543
544 if (index >= RTL8366_NUM_VLANS ||
545 vlanmc->vid >= RTL8366_NUM_VIDS ||
546 vlanmc->priority > RTL8366S_PRIORITYMAX ||
547 vlanmc->member > RTL8366_PORT_ALL ||
548 vlanmc->untag > RTL8366_PORT_ALL ||
549 vlanmc->fid > RTL8366S_FIDMAX)
550 return -EINVAL;
551
552 vlanmc_priv.vid = vlanmc->vid;
553 vlanmc_priv.priority = vlanmc->priority;
554 vlanmc_priv.untag = vlanmc->untag;
555 vlanmc_priv.member = vlanmc->member;
556 vlanmc_priv.stag_mbr = 0;
557 vlanmc_priv.stag_idx = 0;
558 vlanmc_priv.fid = vlanmc->fid;
559
560 addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
561
562 tableaddr = (u16 *)&vlanmc_priv;
563 data = *tableaddr;
564
565 err = rtl8366_smi_write_reg(smi, addr, data);
566 if (err)
567 return err;
568
569 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
570
571 tableaddr++;
572 data = *tableaddr;
573
574 err = rtl8366_smi_write_reg(smi, addr, data);
575 if (err)
576 return err;
577
578 addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
579
580 tableaddr++;
581 data = *tableaddr;
582
583 err = rtl8366_smi_write_reg(smi, addr, data);
584 if (err)
585 return err;
586 return 0;
587 }
588
589 static int rtl8366rb_get_port_vlan_index(struct rtl8366_smi *smi, int port,
590 int *val)
591 {
592 u32 data;
593 int err;
594
595 if (port >= RTL8366_NUM_PORTS)
596 return -EINVAL;
597
598 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
599 &data);
600 if (err)
601 return err;
602
603 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
604 RTL8366S_PORT_VLAN_CTRL_MASK;
605
606 return 0;
607
608 }
609
610 static int rtl8366rb_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
611 int *val)
612 {
613 struct rtl8366_vlan_mc vlanmc;
614 int err;
615 int index;
616
617 err = rtl8366rb_get_port_vlan_index(smi, port, &index);
618 if (err)
619 return err;
620
621 err = rtl8366rb_get_vlan_mc(smi, index, &vlanmc);
622 if (err)
623 return err;
624
625 *val = vlanmc.vid;
626 return 0;
627 }
628
629 static int rtl8366rb_set_port_vlan_index(struct rtl8366_smi *smi, int port,
630 int index)
631 {
632 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
633 return -EINVAL;
634
635 return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
636 RTL8366S_PORT_VLAN_CTRL_MASK <<
637 RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
638 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
639 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
640 }
641
642 static int rtl8366rb_set_vlan_port_pvid(struct rtl8366_smi *smi, int port,
643 int val)
644 {
645 int i;
646 struct rtl8366_vlan_mc vlanmc;
647 struct rtl8366_vlan_4k vlan4k;
648
649 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
650 return -EINVAL;
651
652 /* Updating the 4K entry; lookup it and change the port member set */
653 rtl8366rb_get_vlan_4k(smi, val, &vlan4k);
654 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
655 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
656 rtl8366rb_set_vlan_4k(smi, &vlan4k);
657
658 /*
659 * For the 16 entries more work needs to be done. First see if such
660 * VID is already there and change it
661 */
662 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
663 rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
664
665 /* Try to find an existing vid and update port member set */
666 if (val == vlanmc.vid) {
667 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
668 rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
669
670 /* Now update PVID register settings */
671 rtl8366rb_set_port_vlan_index(smi, port, i);
672
673 return 0;
674 }
675 }
676
677 /*
678 * PVID could not be found from vlan table. Replace unused (one that
679 * has no member ports) with new one
680 */
681 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
682 rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
683
684 /*
685 * See if this vlan member configuration is unused. It is
686 * unused if member set contains no ports or CPU port only
687 */
688 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
689 vlanmc.vid = val;
690 vlanmc.priority = 0;
691 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
692 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
693 vlanmc.fid = 0;
694
695 rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
696
697 /* Now update PVID register settings */
698 rtl8366rb_set_port_vlan_index(smi, port, i);
699
700 return 0;
701 }
702 }
703
704 dev_err(smi->parent,
705 "All 16 vlan member configurations are in use\n");
706
707 return -EINVAL;
708 }
709
710
711 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
712 {
713 return rtl8366_smi_rmwr(smi, RTL8366_CHIP_GLOBAL_CTRL_REG,
714 RTL8366_CHIP_CTRL_VLAN,
715 (enable) ? RTL8366_CHIP_CTRL_VLAN : 0);
716 }
717
718 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
719 {
720 return rtl8366_smi_rmwr(smi, RTL8366_CHIP_GLOBAL_CTRL_REG,
721 RTL8366_CHIP_CTRL_VLAN_4KTB,
722 (enable) ? RTL8366_CHIP_CTRL_VLAN_4KTB : 0);
723 }
724
725 static int rtl8366rb_reset_vlan(struct rtl8366_smi *smi)
726 {
727 struct rtl8366_vlan_4k vlan4k;
728 struct rtl8366_vlan_mc vlanmc;
729 int err;
730 int i;
731
732 /* clear 16 VLAN member configuration */
733 vlanmc.vid = 0;
734 vlanmc.priority = 0;
735 vlanmc.member = 0;
736 vlanmc.untag = 0;
737 vlanmc.fid = 0;
738 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
739 err = rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
740 if (err)
741 return err;
742 }
743
744 /* Set a default VLAN with vid 1 to 4K table for all ports */
745 vlan4k.vid = 1;
746 vlan4k.member = RTL8366_PORT_ALL;
747 vlan4k.untag = RTL8366_PORT_ALL;
748 vlan4k.fid = 0;
749 err = rtl8366rb_set_vlan_4k(smi, &vlan4k);
750 if (err)
751 return err;
752
753 /* Set all ports PVID to default VLAN */
754 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
755 err = rtl8366rb_set_vlan_port_pvid(smi, i, 0);
756 if (err)
757 return err;
758 }
759
760 return 0;
761 }
762
763 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
764 static int rtl8366rb_debugfs_open(struct inode *inode, struct file *file)
765 {
766 file->private_data = inode->i_private;
767 return 0;
768 }
769
770 static ssize_t rtl8366rb_read_debugfs_mibs(struct file *file,
771 char __user *user_buf,
772 size_t count, loff_t *ppos)
773 {
774 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
775 struct rtl8366_smi *smi = &rtl->smi;
776 int i, j, len = 0;
777 char *buf = rtl->buf;
778
779 len += snprintf(buf + len, sizeof(rtl->buf) - len,
780 "%-36s %12s %12s %12s %12s %12s %12s\n",
781 "Counter",
782 "Port 0", "Port 1", "Port 2",
783 "Port 3", "Port 4", "Port 5");
784
785 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
786 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%-36s ",
787 rtl8366rb_mib_counters[i].name);
788 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
789 unsigned long long counter = 0;
790
791 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
792 len += snprintf(buf + len,
793 sizeof(rtl->buf) - len,
794 "%12llu ", counter);
795 else
796 len += snprintf(buf + len,
797 sizeof(rtl->buf) - len,
798 "%12s ", "error");
799 }
800 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
801 }
802
803 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
804 }
805
806 static ssize_t rtl8366rb_read_debugfs_vlan(struct file *file,
807 char __user *user_buf,
808 size_t count, loff_t *ppos)
809 {
810 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
811 struct rtl8366_smi *smi = &rtl->smi;
812 int i, j, len = 0;
813 char *buf = rtl->buf;
814
815 len += snprintf(buf + len, sizeof(rtl->buf) - len,
816 "VLAN Member Config:\n");
817 len += snprintf(buf + len, sizeof(rtl->buf) - len,
818 "\t id \t vid \t prio \t member \t untag \t fid "
819 "\tports\n");
820
821 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
822 struct rtl8366_vlan_mc vlanmc;
823
824 rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
825
826 len += snprintf(buf + len, sizeof(rtl->buf) - len,
827 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
828 "\t", i, vlanmc.vid, vlanmc.priority,
829 vlanmc.member, vlanmc.untag, vlanmc.fid);
830
831 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
832 int index = 0;
833 if (!rtl8366rb_get_port_vlan_index(smi, j, &index)) {
834 if (index == i)
835 len += snprintf(buf + len,
836 sizeof(rtl->buf) - len,
837 "%d", j);
838 }
839 }
840 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
841 }
842
843 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
844 }
845
846 static ssize_t rtl8366rb_read_debugfs_reg(struct file *file,
847 char __user *user_buf,
848 size_t count, loff_t *ppos)
849 {
850 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
851 struct rtl8366_smi *smi = &rtl->smi;
852 u32 t, reg = gl_dbg_reg;
853 int err, len = 0;
854 char *buf = rtl->buf;
855
856 memset(buf, '\0', sizeof(rtl->buf));
857
858 err = rtl8366_smi_read_reg(smi, reg, &t);
859 if (err) {
860 len += snprintf(buf, sizeof(rtl->buf),
861 "Read failed (reg: 0x%04x)\n", reg);
862 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
863 }
864
865 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
866 reg, t);
867
868 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
869 }
870
871 static ssize_t rtl8366rb_write_debugfs_reg(struct file *file,
872 const char __user *user_buf,
873 size_t count, loff_t *ppos)
874 {
875 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
876 struct rtl8366_smi *smi = &rtl->smi;
877 unsigned long data;
878 u32 reg = gl_dbg_reg;
879 int err;
880 size_t len;
881 char *buf = rtl->buf;
882
883 len = min(count, sizeof(rtl->buf) - 1);
884 if (copy_from_user(buf, user_buf, len)) {
885 dev_err(rtl->parent, "copy from user failed\n");
886 return -EFAULT;
887 }
888
889 buf[len] = '\0';
890 if (len > 0 && buf[len - 1] == '\n')
891 buf[len - 1] = '\0';
892
893
894 if (strict_strtoul(buf, 16, &data)) {
895 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
896 } else {
897 err = rtl8366_smi_write_reg(smi, reg, data);
898 if (err) {
899 dev_err(rtl->parent,
900 "writing reg 0x%04x val 0x%04lx failed\n",
901 reg, data);
902 }
903 }
904
905 return count;
906 }
907
908 static const struct file_operations fops_rtl8366rb_regs = {
909 .read = rtl8366rb_read_debugfs_reg,
910 .write = rtl8366rb_write_debugfs_reg,
911 .open = rtl8366rb_debugfs_open,
912 .owner = THIS_MODULE
913 };
914
915 static const struct file_operations fops_rtl8366rb_vlan = {
916 .read = rtl8366rb_read_debugfs_vlan,
917 .open = rtl8366rb_debugfs_open,
918 .owner = THIS_MODULE
919 };
920
921 static const struct file_operations fops_rtl8366rb_mibs = {
922 .read = rtl8366rb_read_debugfs_mibs,
923 .open = rtl8366rb_debugfs_open,
924 .owner = THIS_MODULE
925 };
926
927 static void rtl8366rb_debugfs_init(struct rtl8366rb *rtl)
928 {
929 struct dentry *node;
930 struct dentry *root;
931
932 if (!rtl->debugfs_root)
933 rtl->debugfs_root = debugfs_create_dir("rtl8366rb", NULL);
934
935 if (!rtl->debugfs_root) {
936 dev_err(rtl->parent, "Unable to create debugfs dir\n");
937 return;
938 }
939 root = rtl->debugfs_root;
940
941 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &gl_dbg_reg);
942 if (!node) {
943 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
944 "reg");
945 return;
946 }
947
948 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
949 &fops_rtl8366rb_regs);
950 if (!node) {
951 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
952 "val");
953 return;
954 }
955
956 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
957 &fops_rtl8366rb_vlan);
958 if (!node) {
959 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
960 "vlan");
961 return;
962 }
963
964 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
965 &fops_rtl8366rb_mibs);
966 if (!node) {
967 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
968 "mibs");
969 return;
970 }
971 }
972
973 static void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl)
974 {
975 if (rtl->debugfs_root) {
976 debugfs_remove_recursive(rtl->debugfs_root);
977 rtl->debugfs_root = NULL;
978 }
979 }
980
981 #else
982 static inline void rtl8366rb_debugfs_init(struct rtl8366rb *rtl) {}
983 static inline void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl) {}
984 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
985
986 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
987 const struct switch_attr *attr,
988 struct switch_val *val)
989 {
990 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
991 int err = 0;
992
993 if (val->value.i == 1)
994 err = rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
995
996 return err;
997 }
998
999 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
1000 const struct switch_attr *attr,
1001 struct switch_val *val)
1002 {
1003 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1004 u32 data;
1005
1006 if (attr->ofs == 1) {
1007 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1008
1009 if (data & RTL8366_CHIP_CTRL_VLAN)
1010 val->value.i = 1;
1011 else
1012 val->value.i = 0;
1013 } else if (attr->ofs == 2) {
1014 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1015
1016 if (data & RTL8366_CHIP_CTRL_VLAN_4KTB)
1017 val->value.i = 1;
1018 else
1019 val->value.i = 0;
1020 }
1021
1022 return 0;
1023 }
1024
1025 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
1026 const struct switch_attr *attr,
1027 struct switch_val *val)
1028 {
1029 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1030 u32 data;
1031
1032 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1033
1034 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1035
1036 return 0;
1037 }
1038
1039 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
1040 const struct switch_attr *attr,
1041 struct switch_val *val)
1042 {
1043 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1044
1045 if (val->value.i >= 6)
1046 return -EINVAL;
1047
1048 return rtl8366_smi_rmwr(smi, RTL8366_LED_BLINKRATE_REG,
1049 RTL8366_LED_BLINKRATE_MASK,
1050 val->value.i);
1051 }
1052
1053 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
1054 const struct switch_attr *attr,
1055 struct switch_val *val)
1056 {
1057 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1058
1059 if (attr->ofs == 1)
1060 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
1061 else
1062 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
1063 }
1064
1065 static const char *rtl8366rb_speed_str(unsigned speed)
1066 {
1067 switch (speed) {
1068 case 0:
1069 return "10baseT";
1070 case 1:
1071 return "100baseT";
1072 case 2:
1073 return "1000baseT";
1074 }
1075
1076 return "unknown";
1077 }
1078
1079 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
1080 const struct switch_attr *attr,
1081 struct switch_val *val)
1082 {
1083 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1084 struct rtl8366_smi *smi = &rtl->smi;
1085 u32 len = 0, data = 0;
1086
1087 if (val->port_vlan >= RTL8366_NUM_PORTS)
1088 return -EINVAL;
1089
1090 memset(rtl->buf, '\0', sizeof(rtl->buf));
1091 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1092 (val->port_vlan / 2), &data);
1093
1094 if (val->port_vlan % 2)
1095 data = data >> 8;
1096
1097 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
1098 len = snprintf(rtl->buf, sizeof(rtl->buf),
1099 "port:%d link:up speed:%s %s-duplex %s%s%s",
1100 val->port_vlan,
1101 rtl8366rb_speed_str(data &
1102 RTL8366S_PORT_STATUS_SPEED_MASK),
1103 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1104 "full" : "half",
1105 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1106 "tx-pause ": "",
1107 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1108 "rx-pause " : "",
1109 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
1110 "nway ": "");
1111 } else {
1112 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1113 val->port_vlan);
1114 }
1115
1116 val->value.s = rtl->buf;
1117 val->len = len;
1118
1119 return 0;
1120 }
1121
1122 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
1123 const struct switch_attr *attr,
1124 struct switch_val *val)
1125 {
1126 int i;
1127 u32 len = 0;
1128 struct rtl8366_vlan_mc vlanmc;
1129 struct rtl8366_vlan_4k vlan4k;
1130 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1131 struct rtl8366_smi *smi = &rtl->smi;
1132 char *buf = rtl->buf;
1133
1134 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1135 return -EINVAL;
1136
1137 memset(buf, '\0', sizeof(rtl->buf));
1138
1139 rtl8366rb_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1140 rtl8366rb_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
1141
1142 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1143 val->port_vlan);
1144
1145 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1146 int index = 0;
1147 if (!rtl8366rb_get_port_vlan_index(smi, i, &index) &&
1148 index == val->port_vlan)
1149 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1150 "%d", i);
1151 }
1152 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1153
1154 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1155 "\t\t vid \t prio \t member \t untag \t fid\n");
1156 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1157 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1158 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1159 vlanmc.vid, vlanmc.priority, vlanmc.member,
1160 vlanmc.untag, vlanmc.fid);
1161 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1162 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1163 "%d \t \t 0x%04x \t 0x%04x \t %d",
1164 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1165
1166 val->value.s = buf;
1167 val->len = len;
1168
1169 return 0;
1170 }
1171
1172 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
1173 const struct switch_attr *attr,
1174 struct switch_val *val)
1175 {
1176 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1177 u32 data;
1178 u32 mask;
1179 u32 reg;
1180
1181 if (val->port_vlan >= RTL8366_NUM_PORTS)
1182 return -EINVAL;
1183
1184 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1185 reg = RTL8366_LED_BLINKRATE_REG;
1186 mask = 0xF << 4;
1187 data = val->value.i << 4;
1188 } else {
1189 reg = RTL8366_LED_CTRL_REG;
1190 mask = 0xF << (val->port_vlan * 4),
1191 data = val->value.i << (val->port_vlan * 4);
1192 }
1193
1194 return rtl8366_smi_rmwr(smi, RTL8366_LED_BLINKRATE_REG, mask, data);
1195 }
1196
1197 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
1198 const struct switch_attr *attr,
1199 struct switch_val *val)
1200 {
1201 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1202 u32 data = 0;
1203
1204 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1205 return -EINVAL;
1206
1207 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1208 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1209
1210 return 0;
1211 }
1212
1213 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
1214 const struct switch_attr *attr,
1215 struct switch_val *val)
1216 {
1217 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1218
1219 if (val->port_vlan >= RTL8366_NUM_PORTS)
1220 return -EINVAL;
1221
1222 return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
1223 0, (1 << (val->port_vlan + 3)));
1224 }
1225
1226 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
1227 const struct switch_attr *attr,
1228 struct switch_val *val)
1229 {
1230 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1231 struct rtl8366_smi *smi = &rtl->smi;
1232 int i, len = 0;
1233 unsigned long long counter = 0;
1234 char *buf = rtl->buf;
1235
1236 if (val->port_vlan >= RTL8366_NUM_PORTS)
1237 return -EINVAL;
1238
1239 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1240 "Port %d MIB counters\n",
1241 val->port_vlan);
1242
1243 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
1244 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1245 "%-36s: ", rtl8366rb_mib_counters[i].name);
1246 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1247 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1248 "%llu\n", counter);
1249 else
1250 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1251 "%s\n", "error");
1252 }
1253
1254 val->value.s = buf;
1255 val->len = len;
1256 return 0;
1257 }
1258
1259 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
1260 struct switch_val *val)
1261 {
1262 struct rtl8366_vlan_mc vlanmc;
1263 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1264 struct switch_port *port;
1265 int i;
1266
1267 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1268 return -EINVAL;
1269
1270 rtl8366rb_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1271
1272 port = &val->value.ports[0];
1273 val->len = 0;
1274 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1275 if (!(vlanmc.member & BIT(i)))
1276 continue;
1277
1278 port->id = i;
1279 port->flags = (vlanmc.untag & BIT(i)) ?
1280 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1281 val->len++;
1282 port++;
1283 }
1284 return 0;
1285 }
1286
1287 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
1288 struct switch_val *val)
1289 {
1290 struct rtl8366_vlan_mc vlanmc;
1291 struct rtl8366_vlan_4k vlan4k;
1292 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1293 struct switch_port *port;
1294 int i;
1295
1296 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1297 return -EINVAL;
1298
1299 rtl8366rb_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1300 rtl8366rb_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
1301
1302 vlanmc.untag = 0;
1303 vlanmc.member = 0;
1304
1305 port = &val->value.ports[0];
1306 for (i = 0; i < val->len; i++, port++) {
1307 vlanmc.member |= BIT(port->id);
1308
1309 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1310 vlanmc.untag |= BIT(port->id);
1311 }
1312
1313 vlan4k.member = vlanmc.member;
1314 vlan4k.untag = vlanmc.untag;
1315
1316 rtl8366rb_set_vlan_mc(smi, val->port_vlan, &vlanmc);
1317 rtl8366rb_set_vlan_4k(smi, &vlan4k);
1318 return 0;
1319 }
1320
1321 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1322 {
1323 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1324 return rtl8366rb_get_vlan_port_pvid(smi, port, val);
1325 }
1326
1327 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1328 {
1329 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1330 return rtl8366rb_set_vlan_port_pvid(smi, port, val);
1331 }
1332
1333 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
1334 {
1335 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1336 int err;
1337
1338 err = rtl8366rb_reset_chip(smi);
1339 if (err)
1340 return err;
1341
1342 return rtl8366rb_reset_vlan(smi);
1343 }
1344
1345 static struct switch_attr rtl8366rb_globals[] = {
1346 {
1347 .type = SWITCH_TYPE_INT,
1348 .name = "enable_vlan",
1349 .description = "Enable VLAN mode",
1350 .set = rtl8366rb_sw_set_vlan_enable,
1351 .get = rtl8366rb_sw_get_vlan_enable,
1352 .max = 1,
1353 .ofs = 1
1354 }, {
1355 .type = SWITCH_TYPE_INT,
1356 .name = "enable_vlan4k",
1357 .description = "Enable VLAN 4K mode",
1358 .set = rtl8366rb_sw_set_vlan_enable,
1359 .get = rtl8366rb_sw_get_vlan_enable,
1360 .max = 1,
1361 .ofs = 2
1362 }, {
1363 .type = SWITCH_TYPE_INT,
1364 .name = "reset_mibs",
1365 .description = "Reset all MIB counters",
1366 .set = rtl8366rb_sw_reset_mibs,
1367 .get = NULL,
1368 .max = 1
1369 }, {
1370 .type = SWITCH_TYPE_INT,
1371 .name = "blinkrate",
1372 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1373 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1374 .set = rtl8366rb_sw_set_blinkrate,
1375 .get = rtl8366rb_sw_get_blinkrate,
1376 .max = 5
1377 },
1378 };
1379
1380 static struct switch_attr rtl8366rb_port[] = {
1381 {
1382 .type = SWITCH_TYPE_STRING,
1383 .name = "link",
1384 .description = "Get port link information",
1385 .max = 1,
1386 .set = NULL,
1387 .get = rtl8366rb_sw_get_port_link,
1388 }, {
1389 .type = SWITCH_TYPE_INT,
1390 .name = "reset_mib",
1391 .description = "Reset single port MIB counters",
1392 .max = 1,
1393 .set = rtl8366rb_sw_reset_port_mibs,
1394 .get = NULL,
1395 }, {
1396 .type = SWITCH_TYPE_STRING,
1397 .name = "mib",
1398 .description = "Get MIB counters for port",
1399 .max = 33,
1400 .set = NULL,
1401 .get = rtl8366rb_sw_get_port_mib,
1402 }, {
1403 .type = SWITCH_TYPE_INT,
1404 .name = "led",
1405 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1406 .max = 15,
1407 .set = rtl8366rb_sw_set_port_led,
1408 .get = rtl8366rb_sw_get_port_led,
1409 },
1410 };
1411
1412 static struct switch_attr rtl8366rb_vlan[] = {
1413 {
1414 .type = SWITCH_TYPE_STRING,
1415 .name = "info",
1416 .description = "Get vlan information",
1417 .max = 1,
1418 .set = NULL,
1419 .get = rtl8366rb_sw_get_vlan_info,
1420 },
1421 };
1422
1423 /* template */
1424 static struct switch_dev rtl8366_switch_dev = {
1425 .name = "RTL8366S",
1426 .cpu_port = RTL8366_PORT_NUM_CPU,
1427 .ports = RTL8366_NUM_PORTS,
1428 .vlans = RTL8366_NUM_VLANS,
1429 .attr_global = {
1430 .attr = rtl8366rb_globals,
1431 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1432 },
1433 .attr_port = {
1434 .attr = rtl8366rb_port,
1435 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1436 },
1437 .attr_vlan = {
1438 .attr = rtl8366rb_vlan,
1439 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1440 },
1441
1442 .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1443 .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1444 .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1445 .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1446 .reset_switch = rtl8366rb_sw_reset_switch,
1447 };
1448
1449 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1450 {
1451 struct switch_dev *dev = &rtl->dev;
1452 int err;
1453
1454 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1455 dev->priv = rtl;
1456 dev->devname = dev_name(rtl->parent);
1457
1458 err = register_switch(dev, NULL);
1459 if (err)
1460 dev_err(rtl->parent, "switch registration failed\n");
1461
1462 return err;
1463 }
1464
1465 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1466 {
1467 unregister_switch(&rtl->dev);
1468 }
1469
1470 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1471 {
1472 struct rtl8366_smi *smi = bus->priv;
1473 u32 val = 0;
1474 int err;
1475
1476 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1477 if (err)
1478 return 0xffff;
1479
1480 return val;
1481 }
1482
1483 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1484 {
1485 struct rtl8366_smi *smi = bus->priv;
1486 u32 t;
1487 int err;
1488
1489 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1490 /* flush write */
1491 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1492
1493 return err;
1494 }
1495
1496 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1497 {
1498 return (bus->read == rtl8366rb_mii_read &&
1499 bus->write == rtl8366rb_mii_write);
1500 }
1501
1502 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1503 {
1504 struct rtl8366_smi *smi = &rtl->smi;
1505 int ret;
1506
1507 ret = rtl8366rb_reset_chip(smi);
1508 if (ret)
1509 return ret;
1510
1511 rtl8366rb_debugfs_init(rtl);
1512 return 0;
1513 }
1514
1515 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1516 {
1517 u32 chip_id = 0;
1518 u32 chip_ver = 0;
1519 int ret;
1520
1521 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1522 if (ret) {
1523 dev_err(smi->parent, "unable to read chip id\n");
1524 return ret;
1525 }
1526
1527 switch (chip_id) {
1528 case RTL8366S_CHIP_ID_8366:
1529 break;
1530 default:
1531 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1532 return -ENODEV;
1533 }
1534
1535 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1536 &chip_ver);
1537 if (ret) {
1538 dev_err(smi->parent, "unable to read chip version\n");
1539 return ret;
1540 }
1541
1542 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1543 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1544
1545 return 0;
1546 }
1547
1548 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1549 .detect = rtl8366rb_detect,
1550 .mii_read = rtl8366rb_mii_read,
1551 .mii_write = rtl8366rb_mii_write,
1552 };
1553
1554 static int __init rtl8366rb_probe(struct platform_device *pdev)
1555 {
1556 static int rtl8366_smi_version_printed;
1557 struct rtl8366rb_platform_data *pdata;
1558 struct rtl8366rb *rtl;
1559 struct rtl8366_smi *smi;
1560 int err;
1561
1562 if (!rtl8366_smi_version_printed++)
1563 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1564 " version " RTL8366S_DRIVER_VER"\n");
1565
1566 pdata = pdev->dev.platform_data;
1567 if (!pdata) {
1568 dev_err(&pdev->dev, "no platform data specified\n");
1569 err = -EINVAL;
1570 goto err_out;
1571 }
1572
1573 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1574 if (!rtl) {
1575 dev_err(&pdev->dev, "no memory for private data\n");
1576 err = -ENOMEM;
1577 goto err_out;
1578 }
1579
1580 rtl->parent = &pdev->dev;
1581
1582 smi = &rtl->smi;
1583 smi->parent = &pdev->dev;
1584 smi->gpio_sda = pdata->gpio_sda;
1585 smi->gpio_sck = pdata->gpio_sck;
1586 smi->ops = &rtl8366rb_smi_ops;
1587
1588 err = rtl8366_smi_init(smi);
1589 if (err)
1590 goto err_free_rtl;
1591
1592 platform_set_drvdata(pdev, rtl);
1593
1594 err = rtl8366rb_setup(rtl);
1595 if (err)
1596 goto err_clear_drvdata;
1597
1598 err = rtl8366rb_switch_init(rtl);
1599 if (err)
1600 goto err_clear_drvdata;
1601
1602 return 0;
1603
1604 err_clear_drvdata:
1605 platform_set_drvdata(pdev, NULL);
1606 rtl8366_smi_cleanup(smi);
1607 err_free_rtl:
1608 kfree(rtl);
1609 err_out:
1610 return err;
1611 }
1612
1613 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1614 {
1615 if (!rtl8366rb_mii_bus_match(phydev->bus))
1616 return -EINVAL;
1617
1618 return 0;
1619 }
1620
1621 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1622 {
1623 return 0;
1624 }
1625
1626 static struct phy_driver rtl8366rb_phy_driver = {
1627 .phy_id = 0x001cc960,
1628 .name = "Realtek RTL8366RB",
1629 .phy_id_mask = 0x1ffffff0,
1630 .features = PHY_GBIT_FEATURES,
1631 .config_aneg = rtl8366rb_phy_config_aneg,
1632 .config_init = rtl8366rb_phy_config_init,
1633 .read_status = genphy_read_status,
1634 .driver = {
1635 .owner = THIS_MODULE,
1636 },
1637 };
1638
1639 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1640 {
1641 struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1642
1643 if (rtl) {
1644 rtl8366rb_switch_cleanup(rtl);
1645 rtl8366rb_debugfs_remove(rtl);
1646 platform_set_drvdata(pdev, NULL);
1647 rtl8366_smi_cleanup(&rtl->smi);
1648 kfree(rtl);
1649 }
1650
1651 return 0;
1652 }
1653
1654 static struct platform_driver rtl8366rb_driver = {
1655 .driver = {
1656 .name = RTL8366RB_DRIVER_NAME,
1657 .owner = THIS_MODULE,
1658 },
1659 .probe = rtl8366rb_probe,
1660 .remove = __devexit_p(rtl8366rb_remove),
1661 };
1662
1663 static int __init rtl8366rb_module_init(void)
1664 {
1665 int ret;
1666 ret = platform_driver_register(&rtl8366rb_driver);
1667 if (ret)
1668 return ret;
1669
1670 ret = phy_driver_register(&rtl8366rb_phy_driver);
1671 if (ret)
1672 goto err_platform_unregister;
1673
1674 return 0;
1675
1676 err_platform_unregister:
1677 platform_driver_unregister(&rtl8366rb_driver);
1678 return ret;
1679 }
1680 module_init(rtl8366rb_module_init);
1681
1682 static void __exit rtl8366rb_module_exit(void)
1683 {
1684 phy_driver_unregister(&rtl8366rb_phy_driver);
1685 platform_driver_unregister(&rtl8366rb_driver);
1686 }
1687 module_exit(rtl8366rb_module_exit);
1688
1689 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1690 MODULE_VERSION(RTL8366S_DRIVER_VER);
1691 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1692 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1693 MODULE_LICENSE("GPL v2");
1694 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
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