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[openwrt/svn-archive/archive.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366s.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366s.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
29
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
33
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
36
37 #define RTL8366_RESET_CTRL_REG 0x0100
38 #define RTL8366_CHIP_CTRL_RESET_HW 1
39 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
40
41 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
42 #define RTL8366S_CHIP_VERSION_MASK 0xf
43 #define RTL8366S_CHIP_ID_REG 0x0105
44 #define RTL8366S_CHIP_ID_8366 0x8366
45
46 /* PHY registers control */
47 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
48 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
49
50 #define RTL8366S_PHY_CTRL_READ 1
51 #define RTL8366S_PHY_CTRL_WRITE 0
52
53 #define RTL8366S_PHY_REG_MASK 0x1f
54 #define RTL8366S_PHY_PAGE_OFFSET 5
55 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
56 #define RTL8366S_PHY_NO_OFFSET 9
57 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
58
59 /* LED control registers */
60 #define RTL8366_LED_BLINKRATE_REG 0x0420
61 #define RTL8366_LED_BLINKRATE_BIT 0
62 #define RTL8366_LED_BLINKRATE_MASK 0x0007
63
64 #define RTL8366_LED_CTRL_REG 0x0421
65 #define RTL8366_LED_0_1_CTRL_REG 0x0422
66 #define RTL8366_LED_2_3_CTRL_REG 0x0423
67
68 #define RTL8366S_MIB_COUNT 33
69 #define RTL8366S_GLOBAL_MIB_COUNT 1
70 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
71 #define RTL8366S_MIB_COUNTER_BASE 0x1000
72 #define RTL8366S_MIB_CTRL_REG 0x11F0
73 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
74 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
75 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
76
77 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
78 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
79 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
80
81
82 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
83 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
84 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
85 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
86 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
87
88
89 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
90 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
91
92 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
93
94 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
95 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
96 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
97
98 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
99
100
101 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
102 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
103 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
104 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
105 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
106 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
107 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
108
109
110 #define RTL8366_PORT_NUM_CPU 5
111 #define RTL8366_NUM_PORTS 6
112 #define RTL8366_NUM_VLANS 16
113 #define RTL8366_NUM_LEDGROUPS 4
114 #define RTL8366_NUM_VIDS 4096
115 #define RTL8366S_PRIORITYMAX 7
116 #define RTL8366S_FIDMAX 7
117
118
119 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
120 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
121 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
122 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
123
124 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
125 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
126
127 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
128 RTL8366_PORT_2 | \
129 RTL8366_PORT_3 | \
130 RTL8366_PORT_4 | \
131 RTL8366_PORT_UNKNOWN | \
132 RTL8366_PORT_CPU)
133
134 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
135 RTL8366_PORT_2 | \
136 RTL8366_PORT_3 | \
137 RTL8366_PORT_4 | \
138 RTL8366_PORT_UNKNOWN)
139
140 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
141 RTL8366_PORT_2 | \
142 RTL8366_PORT_3 | \
143 RTL8366_PORT_4)
144
145 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
146 RTL8366_PORT_CPU)
147
148 struct rtl8366s {
149 struct device *parent;
150 struct rtl8366_smi smi;
151 struct switch_dev dev;
152 char buf[4096];
153 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
154 struct dentry *debugfs_root;
155 #endif
156 };
157
158 struct rtl8366s_vlan_mc {
159 u16 reserved2:1;
160 u16 priority:3;
161 u16 vid:12;
162
163 u16 reserved1:1;
164 u16 fid:3;
165 u16 untag:6;
166 u16 member:6;
167 };
168
169 struct rtl8366s_vlan_4k {
170 u16 reserved1:4;
171 u16 vid:12;
172
173 u16 reserved2:1;
174 u16 fid:3;
175 u16 untag:6;
176 u16 member:6;
177 };
178
179 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
180 u16 g_dbg_reg;
181 #endif
182
183 struct mib_counter {
184 unsigned offset;
185 unsigned length;
186 const char *name;
187 };
188
189 static struct mib_counter rtl8366s_mib_counters[RTL8366S_MIB_COUNT] = {
190 { 0, 4, "IfInOctets" },
191 { 4, 4, "EtherStatsOctets" },
192 { 8, 2, "EtherStatsUnderSizePkts" },
193 { 10, 2, "EtherFragments" },
194 { 12, 2, "EtherStatsPkts64Octets" },
195 { 14, 2, "EtherStatsPkts65to127Octets" },
196 { 16, 2, "EtherStatsPkts128to255Octets" },
197 { 18, 2, "EtherStatsPkts256to511Octets" },
198 { 20, 2, "EtherStatsPkts512to1023Octets" },
199 { 22, 2, "EtherStatsPkts1024to1518Octets" },
200 { 24, 2, "EtherOversizeStats" },
201 { 26, 2, "EtherStatsJabbers" },
202 { 28, 2, "IfInUcastPkts" },
203 { 30, 2, "EtherStatsMulticastPkts" },
204 { 32, 2, "EtherStatsBroadcastPkts" },
205 { 34, 2, "EtherStatsDropEvents" },
206 { 36, 2, "Dot3StatsFCSErrors" },
207 { 38, 2, "Dot3StatsSymbolErrors" },
208 { 40, 2, "Dot3InPauseFrames" },
209 { 42, 2, "Dot3ControlInUnknownOpcodes" },
210 { 44, 4, "IfOutOctets" },
211 { 48, 2, "Dot3StatsSingleCollisionFrames" },
212 { 50, 2, "Dot3StatMultipleCollisionFrames" },
213 { 52, 2, "Dot3sDeferredTransmissions" },
214 { 54, 2, "Dot3StatsLateCollisions" },
215 { 56, 2, "EtherStatsCollisions" },
216 { 58, 2, "Dot3StatsExcessiveCollisions" },
217 { 60, 2, "Dot3OutPauseFrames" },
218 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
219 { 64, 2, "Dot1dTpPortInDiscards" },
220 { 66, 2, "IfOutUcastPkts" },
221 { 68, 2, "IfOutMulticastPkts" },
222 { 70, 2, "IfOutBroadcastPkts" },
223 };
224
225 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
226 {
227 return container_of(smi, struct rtl8366s, smi);
228 }
229
230 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
231 {
232 return container_of(sw, struct rtl8366s, dev);
233 }
234
235 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
236 {
237 struct rtl8366s *rtl = sw_to_rtl8366s(sw);
238 return &rtl->smi;
239 }
240
241 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
242 {
243 int timeout = 10;
244 u32 data;
245
246 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
247 RTL8366_CHIP_CTRL_RESET_HW);
248 do {
249 msleep(1);
250 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
251 return -EIO;
252
253 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
254 break;
255 } while (--timeout);
256
257 if (!timeout) {
258 printk("Timeout waiting for the switch to reset\n");
259 return -EIO;
260 }
261
262 return 0;
263 }
264
265 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
266 u32 phy_no, u32 page, u32 addr, u32 *data)
267 {
268 u32 reg;
269 int ret;
270
271 if (phy_no > RTL8366S_PHY_NO_MAX)
272 return -EINVAL;
273
274 if (page > RTL8366S_PHY_PAGE_MAX)
275 return -EINVAL;
276
277 if (addr > RTL8366S_PHY_ADDR_MAX)
278 return -EINVAL;
279
280 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
281 RTL8366S_PHY_CTRL_READ);
282 if (ret)
283 return ret;
284
285 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
286 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
287 (addr & RTL8366S_PHY_REG_MASK);
288
289 ret = rtl8366_smi_write_reg(smi, reg, 0);
290 if (ret)
291 return ret;
292
293 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
294 if (ret)
295 return ret;
296
297 return 0;
298 }
299
300 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
301 u32 phy_no, u32 page, u32 addr, u32 data)
302 {
303 u32 reg;
304 int ret;
305
306 if (phy_no > RTL8366S_PHY_NO_MAX)
307 return -EINVAL;
308
309 if (page > RTL8366S_PHY_PAGE_MAX)
310 return -EINVAL;
311
312 if (addr > RTL8366S_PHY_ADDR_MAX)
313 return -EINVAL;
314
315 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
316 RTL8366S_PHY_CTRL_WRITE);
317 if (ret)
318 return ret;
319
320 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
321 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
322 (addr & RTL8366S_PHY_REG_MASK);
323
324 ret = rtl8366_smi_write_reg(smi, reg, data);
325 if (ret)
326 return ret;
327
328 return 0;
329 }
330
331 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
332 int port, unsigned long long *val)
333 {
334 int i;
335 int err;
336 u32 addr, data;
337 u64 mibvalue;
338
339 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
340 return -EINVAL;
341
342 addr = RTL8366S_MIB_COUNTER_BASE +
343 RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) +
344 rtl8366s_mib_counters[counter].offset;
345
346 /*
347 * Writing access counter address first
348 * then ASIC will prepare 64bits counter wait for being retrived
349 */
350 data = 0; /* writing data will be discard by ASIC */
351 err = rtl8366_smi_write_reg(smi, addr, data);
352 if (err)
353 return err;
354
355 /* read MIB control register */
356 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
357 if (err)
358 return err;
359
360 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
361 return -EBUSY;
362
363 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
364 return -EIO;
365
366 mibvalue = 0;
367 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
368 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
369 if (err)
370 return err;
371
372 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
373 }
374
375 *val = mibvalue;
376 return 0;
377 }
378
379 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
380 struct rtl8366_vlan_4k *vlan4k)
381 {
382 struct rtl8366s_vlan_4k vlan4k_priv;
383 int err;
384 u32 data;
385 u16 *tableaddr;
386
387 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
388 vlan4k_priv.vid = vid;
389
390 if (vid >= RTL8366_NUM_VIDS)
391 return -EINVAL;
392
393 tableaddr = (u16 *)&vlan4k_priv;
394
395 /* write VID */
396 data = *tableaddr;
397 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
398 if (err)
399 return err;
400
401 /* write table access control word */
402 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
403 RTL8366S_TABLE_VLAN_READ_CTRL);
404 if (err)
405 return err;
406
407 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
408 if (err)
409 return err;
410
411 *tableaddr = data;
412 tableaddr++;
413
414 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
415 &data);
416 if (err)
417 return err;
418
419 *tableaddr = data;
420
421 vlan4k->vid = vid;
422 vlan4k->untag = vlan4k_priv.untag;
423 vlan4k->member = vlan4k_priv.member;
424 vlan4k->fid = vlan4k_priv.fid;
425
426 return 0;
427 }
428
429 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
430 const struct rtl8366_vlan_4k *vlan4k)
431 {
432 struct rtl8366s_vlan_4k vlan4k_priv;
433 int err;
434 u32 data;
435 u16 *tableaddr;
436
437 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
438 vlan4k->member > RTL8366_PORT_ALL ||
439 vlan4k->untag > RTL8366_PORT_ALL ||
440 vlan4k->fid > RTL8366S_FIDMAX)
441 return -EINVAL;
442
443 vlan4k_priv.vid = vlan4k->vid;
444 vlan4k_priv.untag = vlan4k->untag;
445 vlan4k_priv.member = vlan4k->member;
446 vlan4k_priv.fid = vlan4k->fid;
447
448 tableaddr = (u16 *)&vlan4k_priv;
449
450 data = *tableaddr;
451
452 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
453 if (err)
454 return err;
455
456 tableaddr++;
457
458 data = *tableaddr;
459
460 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
461 data);
462 if (err)
463 return err;
464
465 /* write table access control word */
466 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
467 RTL8366S_TABLE_VLAN_WRITE_CTRL);
468
469 return err;
470 }
471
472 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
473 struct rtl8366_vlan_mc *vlanmc)
474 {
475 struct rtl8366s_vlan_mc vlanmc_priv;
476 int err;
477 u32 addr;
478 u32 data;
479 u16 *tableaddr;
480
481 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
482
483 if (index >= RTL8366_NUM_VLANS)
484 return -EINVAL;
485
486 tableaddr = (u16 *)&vlanmc_priv;
487
488 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
489 err = rtl8366_smi_read_reg(smi, addr, &data);
490 if (err)
491 return err;
492
493 *tableaddr = data;
494 tableaddr++;
495
496 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
497 err = rtl8366_smi_read_reg(smi, addr, &data);
498 if (err)
499 return err;
500
501 *tableaddr = data;
502
503 vlanmc->vid = vlanmc_priv.vid;
504 vlanmc->priority = vlanmc_priv.priority;
505 vlanmc->untag = vlanmc_priv.untag;
506 vlanmc->member = vlanmc_priv.member;
507 vlanmc->fid = vlanmc_priv.fid;
508
509 return 0;
510 }
511
512 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
513 const struct rtl8366_vlan_mc *vlanmc)
514 {
515 struct rtl8366s_vlan_mc vlanmc_priv;
516 int err;
517 u32 addr;
518 u32 data;
519 u16 *tableaddr;
520
521 if (index >= RTL8366_NUM_VLANS ||
522 vlanmc->vid >= RTL8366_NUM_VIDS ||
523 vlanmc->priority > RTL8366S_PRIORITYMAX ||
524 vlanmc->member > RTL8366_PORT_ALL ||
525 vlanmc->untag > RTL8366_PORT_ALL ||
526 vlanmc->fid > RTL8366S_FIDMAX)
527 return -EINVAL;
528
529 vlanmc_priv.vid = vlanmc->vid;
530 vlanmc_priv.priority = vlanmc->priority;
531 vlanmc_priv.untag = vlanmc->untag;
532 vlanmc_priv.member = vlanmc->member;
533 vlanmc_priv.fid = vlanmc->fid;
534
535 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
536
537 tableaddr = (u16 *)&vlanmc_priv;
538 data = *tableaddr;
539
540 err = rtl8366_smi_write_reg(smi, addr, data);
541 if (err)
542 return err;
543
544 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
545
546 tableaddr++;
547 data = *tableaddr;
548
549 err = rtl8366_smi_write_reg(smi, addr, data);
550 if (err)
551 return err;
552
553 return 0;
554 }
555
556 static int rtl8366s_get_port_vlan_index(struct rtl8366_smi *smi, int port,
557 int *val)
558 {
559 u32 data;
560 int err;
561
562 if (port >= RTL8366_NUM_PORTS)
563 return -EINVAL;
564
565 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
566 &data);
567 if (err)
568 return err;
569
570 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
571 RTL8366S_PORT_VLAN_CTRL_MASK;
572
573 return 0;
574
575 }
576
577 static int rtl8366s_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
578 int *val)
579 {
580 struct rtl8366_vlan_mc vlanmc;
581 int err;
582 int index;
583
584 err = rtl8366s_get_port_vlan_index(smi, port, &index);
585 if (err)
586 return err;
587
588 err = rtl8366s_get_vlan_mc(smi, index, &vlanmc);
589 if (err)
590 return err;
591
592 *val = vlanmc.vid;
593 return 0;
594 }
595
596 static int rtl8366s_set_port_vlan_index(struct rtl8366_smi *smi, int port,
597 int index)
598 {
599 u32 data;
600 int err;
601
602 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
603 return -EINVAL;
604
605 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
606 &data);
607 if (err)
608 return err;
609
610 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
611 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
612 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
613 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
614
615 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
616 data);
617 return err;
618 }
619
620 static int rtl8366s_set_vlan_port_pvid(struct rtl8366_smi *smi, int port, int val)
621 {
622 int i;
623 struct rtl8366_vlan_mc vlanmc;
624 struct rtl8366_vlan_4k vlan4k;
625
626 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
627 return -EINVAL;
628
629 /* Updating the 4K entry; lookup it and change the port member set */
630 rtl8366s_get_vlan_4k(smi, val, &vlan4k);
631 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
632 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
633 rtl8366s_set_vlan_4k(smi, &vlan4k);
634
635 /*
636 * For the 16 entries more work needs to be done. First see if such
637 * VID is already there and change it
638 */
639 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
640 rtl8366s_get_vlan_mc(smi, i, &vlanmc);
641
642 /* Try to find an existing vid and update port member set */
643 if (val == vlanmc.vid) {
644 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
645 rtl8366s_set_vlan_mc(smi, i, &vlanmc);
646
647 /* Now update PVID register settings */
648 rtl8366s_set_port_vlan_index(smi, port, i);
649
650 return 0;
651 }
652 }
653
654 /*
655 * PVID could not be found from vlan table. Replace unused (one that
656 * has no member ports) with new one
657 */
658 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
659 rtl8366s_get_vlan_mc(smi, i, &vlanmc);
660
661 /*
662 * See if this vlan member configuration is unused. It is
663 * unused if member set contains no ports or CPU port only
664 */
665 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
666 vlanmc.vid = val;
667 vlanmc.priority = 0;
668 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
669 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
670 vlanmc.fid = 0;
671
672 rtl8366s_set_vlan_mc(smi, i, &vlanmc);
673
674 /* Now update PVID register settings */
675 rtl8366s_set_port_vlan_index(smi, port, i);
676
677 return 0;
678 }
679 }
680
681 dev_err(smi->parent,
682 "All 16 vlan member configurations are in use\n");
683
684 return -EINVAL;
685 }
686
687
688 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
689 {
690 u32 data = 0;
691
692 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
693
694 if (enable)
695 data |= RTL8366_CHIP_CTRL_VLAN;
696 else
697 data &= ~RTL8366_CHIP_CTRL_VLAN;
698
699 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
700 }
701
702 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
703 {
704 u32 data = 0;
705
706 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
707
708 if (enable)
709 data |= 1;
710 else
711 data &= ~1;
712
713 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
714 }
715
716 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
717 {
718 struct rtl8366_vlan_4k vlan4k;
719 struct rtl8366_vlan_mc vlanmc;
720 int err;
721 int i;
722
723 /* clear 16 VLAN member configuration */
724 vlanmc.vid = 0;
725 vlanmc.priority = 0;
726 vlanmc.member = 0;
727 vlanmc.untag = 0;
728 vlanmc.fid = 0;
729 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
730 err = rtl8366s_set_vlan_mc(smi, i, &vlanmc);
731 if (err)
732 return err;
733 }
734
735 /* Set a default VLAN with vid 1 to 4K table for all ports */
736 vlan4k.vid = 1;
737 vlan4k.member = RTL8366_PORT_ALL;
738 vlan4k.untag = RTL8366_PORT_ALL;
739 vlan4k.fid = 0;
740 err = rtl8366s_set_vlan_4k(smi, &vlan4k);
741 if (err)
742 return err;
743
744 /* Set all ports PVID to default VLAN */
745 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
746 err = rtl8366s_set_vlan_port_pvid(smi, i, 0);
747 if (err)
748 return err;
749 }
750
751 return 0;
752 }
753
754 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
755 static int rtl8366s_debugfs_open(struct inode *inode, struct file *file)
756 {
757 file->private_data = inode->i_private;
758 return 0;
759 }
760
761 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
762 char __user *user_buf,
763 size_t count, loff_t *ppos)
764 {
765 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
766 struct rtl8366_smi *smi = &rtl->smi;
767 int i, j, len = 0;
768 char *buf = rtl->buf;
769
770 len += snprintf(buf + len, sizeof(rtl->buf) - len,
771 "%-36s %12s %12s %12s %12s %12s %12s\n",
772 "Counter",
773 "Port 0", "Port 1", "Port 2",
774 "Port 3", "Port 4", "Port 5");
775
776 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
777 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%-36s ",
778 rtl8366s_mib_counters[i].name);
779 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
780 unsigned long long counter = 0;
781
782 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
783 len += snprintf(buf + len,
784 sizeof(rtl->buf) - len,
785 "%12llu ", counter);
786 else
787 len += snprintf(buf + len,
788 sizeof(rtl->buf) - len,
789 "%12s ", "error");
790 }
791 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
792 }
793
794 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
795 }
796
797 static ssize_t rtl8366s_read_debugfs_vlan(struct file *file,
798 char __user *user_buf,
799 size_t count, loff_t *ppos)
800 {
801 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
802 struct rtl8366_smi *smi = &rtl->smi;
803 int i, j, len = 0;
804 char *buf = rtl->buf;
805
806 len += snprintf(buf + len, sizeof(rtl->buf) - len,
807 "VLAN Member Config:\n");
808 len += snprintf(buf + len, sizeof(rtl->buf) - len,
809 "\t id \t vid \t prio \t member \t untag \t fid "
810 "\tports\n");
811
812 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
813 struct rtl8366_vlan_mc vlanmc;
814
815 rtl8366s_get_vlan_mc(smi, i, &vlanmc);
816
817 len += snprintf(buf + len, sizeof(rtl->buf) - len,
818 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
819 "\t", i, vlanmc.vid, vlanmc.priority,
820 vlanmc.member, vlanmc.untag, vlanmc.fid);
821
822 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
823 int index = 0;
824 if (!rtl8366s_get_port_vlan_index(smi, j, &index)) {
825 if (index == i)
826 len += snprintf(buf + len,
827 sizeof(rtl->buf) - len,
828 "%d", j);
829 }
830 }
831 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
832 }
833
834 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
835 }
836
837 static ssize_t rtl8366s_read_debugfs_reg(struct file *file,
838 char __user *user_buf,
839 size_t count, loff_t *ppos)
840 {
841 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
842 struct rtl8366_smi *smi = &rtl->smi;
843 u32 t, reg = g_dbg_reg;
844 int err, len = 0;
845 char *buf = rtl->buf;
846
847 memset(buf, '\0', sizeof(rtl->buf));
848
849 err = rtl8366_smi_read_reg(smi, reg, &t);
850 if (err) {
851 len += snprintf(buf, sizeof(rtl->buf),
852 "Read failed (reg: 0x%04x)\n", reg);
853 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
854 }
855
856 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
857 reg, t);
858
859 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
860 }
861
862 static ssize_t rtl8366s_write_debugfs_reg(struct file *file,
863 const char __user *user_buf,
864 size_t count, loff_t *ppos)
865 {
866 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
867 struct rtl8366_smi *smi = &rtl->smi;
868 unsigned long data;
869 u32 reg = g_dbg_reg;
870 int err;
871 size_t len;
872 char *buf = rtl->buf;
873
874 len = min(count, sizeof(rtl->buf) - 1);
875 if (copy_from_user(buf, user_buf, len)) {
876 dev_err(rtl->parent, "copy from user failed\n");
877 return -EFAULT;
878 }
879
880 buf[len] = '\0';
881 if (len > 0 && buf[len - 1] == '\n')
882 buf[len - 1] = '\0';
883
884
885 if (strict_strtoul(buf, 16, &data)) {
886 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
887 } else {
888 err = rtl8366_smi_write_reg(smi, reg, data);
889 if (err) {
890 dev_err(rtl->parent,
891 "writing reg 0x%04x val 0x%04lx failed\n",
892 reg, data);
893 }
894 }
895
896 return count;
897 }
898
899 static const struct file_operations fops_rtl8366s_regs = {
900 .read = rtl8366s_read_debugfs_reg,
901 .write = rtl8366s_write_debugfs_reg,
902 .open = rtl8366s_debugfs_open,
903 .owner = THIS_MODULE
904 };
905
906 static const struct file_operations fops_rtl8366s_vlan = {
907 .read = rtl8366s_read_debugfs_vlan,
908 .open = rtl8366s_debugfs_open,
909 .owner = THIS_MODULE
910 };
911
912 static const struct file_operations fops_rtl8366s_mibs = {
913 .read = rtl8366s_read_debugfs_mibs,
914 .open = rtl8366s_debugfs_open,
915 .owner = THIS_MODULE
916 };
917
918 static void rtl8366s_debugfs_init(struct rtl8366s *rtl)
919 {
920 struct dentry *node;
921 struct dentry *root;
922
923 if (!rtl->debugfs_root)
924 rtl->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
925
926 if (!rtl->debugfs_root) {
927 dev_err(rtl->parent, "Unable to create debugfs dir\n");
928 return;
929 }
930 root = rtl->debugfs_root;
931
932 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
933 if (!node) {
934 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
935 "reg");
936 return;
937 }
938
939 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
940 &fops_rtl8366s_regs);
941 if (!node) {
942 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
943 "val");
944 return;
945 }
946
947 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
948 &fops_rtl8366s_vlan);
949 if (!node) {
950 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
951 "vlan");
952 return;
953 }
954
955 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
956 &fops_rtl8366s_mibs);
957 if (!node) {
958 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
959 "mibs");
960 return;
961 }
962 }
963
964 static void rtl8366s_debugfs_remove(struct rtl8366s *rtl)
965 {
966 if (rtl->debugfs_root) {
967 debugfs_remove_recursive(rtl->debugfs_root);
968 rtl->debugfs_root = NULL;
969 }
970 }
971
972 #else
973 static inline void rtl8366s_debugfs_init(struct rtl8366s *rtl) {}
974 static inline void rtl8366s_debugfs_remove(struct rtl8366s *rtl) {}
975 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
976
977 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
978 const struct switch_attr *attr,
979 struct switch_val *val)
980 {
981 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
982 u32 data = 0;
983
984 if (val->value.i == 1) {
985 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
986 data |= (1 << 2);
987 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
988 }
989
990 return 0;
991 }
992
993 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
994 const struct switch_attr *attr,
995 struct switch_val *val)
996 {
997 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
998 u32 data;
999
1000 if (attr->ofs == 1) {
1001 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1002
1003 if (data & RTL8366_CHIP_CTRL_VLAN)
1004 val->value.i = 1;
1005 else
1006 val->value.i = 0;
1007 } else if (attr->ofs == 2) {
1008 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1009
1010 if (data & 0x0001)
1011 val->value.i = 1;
1012 else
1013 val->value.i = 0;
1014 }
1015
1016 return 0;
1017 }
1018
1019 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
1020 const struct switch_attr *attr,
1021 struct switch_val *val)
1022 {
1023 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1024 u32 data;
1025
1026 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1027
1028 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1029
1030 return 0;
1031 }
1032
1033 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
1034 const struct switch_attr *attr,
1035 struct switch_val *val)
1036 {
1037 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1038 u32 data;
1039
1040 if (val->value.i >= 6)
1041 return -EINVAL;
1042
1043 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1044
1045 data &= ~RTL8366_LED_BLINKRATE_MASK;
1046 data |= val->value.i;
1047
1048 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1049
1050 return 0;
1051 }
1052
1053 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
1054 const struct switch_attr *attr,
1055 struct switch_val *val)
1056 {
1057 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1058
1059 if (attr->ofs == 1)
1060 return rtl8366s_vlan_set_vlan(smi, val->value.i);
1061 else
1062 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
1063 }
1064
1065 static const char *rtl8366s_speed_str(unsigned speed)
1066 {
1067 switch (speed) {
1068 case 0:
1069 return "10baseT";
1070 case 1:
1071 return "100baseT";
1072 case 2:
1073 return "1000baseT";
1074 }
1075
1076 return "unknown";
1077 }
1078
1079 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
1080 const struct switch_attr *attr,
1081 struct switch_val *val)
1082 {
1083 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1084 struct rtl8366_smi *smi = &rtl->smi;
1085 u32 len = 0, data = 0;
1086
1087 if (val->port_vlan >= RTL8366_NUM_PORTS)
1088 return -EINVAL;
1089
1090 memset(rtl->buf, '\0', sizeof(rtl->buf));
1091 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1092 (val->port_vlan / 2), &data);
1093
1094 if (val->port_vlan % 2)
1095 data = data >> 8;
1096
1097 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
1098 len = snprintf(rtl->buf, sizeof(rtl->buf),
1099 "port:%d link:up speed:%s %s-duplex %s%s%s",
1100 val->port_vlan,
1101 rtl8366s_speed_str(data &
1102 RTL8366S_PORT_STATUS_SPEED_MASK),
1103 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1104 "full" : "half",
1105 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1106 "tx-pause ": "",
1107 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1108 "rx-pause " : "",
1109 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
1110 "nway ": "");
1111 } else {
1112 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1113 val->port_vlan);
1114 }
1115
1116 val->value.s = rtl->buf;
1117 val->len = len;
1118
1119 return 0;
1120 }
1121
1122 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
1123 const struct switch_attr *attr,
1124 struct switch_val *val)
1125 {
1126 int i;
1127 u32 len = 0;
1128 struct rtl8366_vlan_mc vlanmc;
1129 struct rtl8366_vlan_4k vlan4k;
1130 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1131 struct rtl8366_smi *smi = &rtl->smi;
1132 char *buf = rtl->buf;
1133
1134 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1135 return -EINVAL;
1136
1137 memset(buf, '\0', sizeof(rtl->buf));
1138
1139 rtl8366s_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1140 rtl8366s_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
1141
1142 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1143 val->port_vlan);
1144
1145 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1146 int index = 0;
1147 if (!rtl8366s_get_port_vlan_index(smi, i, &index) &&
1148 index == val->port_vlan)
1149 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1150 "%d", i);
1151 }
1152 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1153
1154 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1155 "\t\t vid \t prio \t member \t untag \t fid\n");
1156 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1157 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1158 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1159 vlanmc.vid, vlanmc.priority, vlanmc.member,
1160 vlanmc.untag, vlanmc.fid);
1161 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1162 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1163 "%d \t \t 0x%04x \t 0x%04x \t %d",
1164 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1165
1166 val->value.s = buf;
1167 val->len = len;
1168
1169 return 0;
1170 }
1171
1172 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
1173 const struct switch_attr *attr,
1174 struct switch_val *val)
1175 {
1176 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1177 u32 data = 0;
1178
1179 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1180 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1181 return -EINVAL;
1182
1183 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1184 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1185 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1186 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1187 } else {
1188 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1189 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1190 (val->value.i << (val->port_vlan * 4));
1191 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1192 }
1193
1194 return 0;
1195 }
1196
1197 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
1198 const struct switch_attr *attr,
1199 struct switch_val *val)
1200 {
1201 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1202 u32 data = 0;
1203
1204 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1205 return -EINVAL;
1206
1207 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1208 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1209
1210 return 0;
1211 }
1212
1213 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
1214 const struct switch_attr *attr,
1215 struct switch_val *val)
1216 {
1217 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1218 u32 data = 0;
1219
1220 if (val->port_vlan >= RTL8366_NUM_PORTS)
1221 return -EINVAL;
1222
1223 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1224 data |= (1 << (val->port_vlan + 3));
1225 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1226
1227 return 0;
1228 }
1229
1230 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
1231 const struct switch_attr *attr,
1232 struct switch_val *val)
1233 {
1234 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1235 struct rtl8366_smi *smi = &rtl->smi;
1236 int i, len = 0;
1237 unsigned long long counter = 0;
1238 char *buf = rtl->buf;
1239
1240 if (val->port_vlan >= RTL8366_NUM_PORTS)
1241 return -EINVAL;
1242
1243 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1244 "Port %d MIB counters\n",
1245 val->port_vlan);
1246
1247 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
1248 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1249 "%-36s: ", rtl8366s_mib_counters[i].name);
1250 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1251 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1252 "%llu\n", counter);
1253 else
1254 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1255 "%s\n", "error");
1256 }
1257
1258 val->value.s = buf;
1259 val->len = len;
1260 return 0;
1261 }
1262
1263 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
1264 struct switch_val *val)
1265 {
1266 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1267 struct rtl8366_vlan_mc vlanmc;
1268 struct switch_port *port;
1269 int i;
1270
1271 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1272 return -EINVAL;
1273
1274 rtl8366s_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1275
1276 port = &val->value.ports[0];
1277 val->len = 0;
1278 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1279 if (!(vlanmc.member & BIT(i)))
1280 continue;
1281
1282 port->id = i;
1283 port->flags = (vlanmc.untag & BIT(i)) ?
1284 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1285 val->len++;
1286 port++;
1287 }
1288 return 0;
1289 }
1290
1291 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1292 struct switch_val *val)
1293 {
1294 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1295 struct rtl8366_vlan_mc vlanmc;
1296 struct rtl8366_vlan_4k vlan4k;
1297 struct switch_port *port;
1298 int i;
1299
1300 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1301 return -EINVAL;
1302
1303 rtl8366s_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1304 rtl8366s_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
1305
1306 vlanmc.untag = 0;
1307 vlanmc.member = 0;
1308
1309 port = &val->value.ports[0];
1310 for (i = 0; i < val->len; i++, port++) {
1311 vlanmc.member |= BIT(port->id);
1312
1313 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1314 vlanmc.untag |= BIT(port->id);
1315 }
1316
1317 vlan4k.member = vlanmc.member;
1318 vlan4k.untag = vlanmc.untag;
1319
1320 rtl8366s_set_vlan_mc(smi, val->port_vlan, &vlanmc);
1321 rtl8366s_set_vlan_4k(smi, &vlan4k);
1322 return 0;
1323 }
1324
1325 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1326 {
1327 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1328 return rtl8366s_get_vlan_port_pvid(smi, port, val);
1329 }
1330
1331 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1332 {
1333 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1334 return rtl8366s_set_vlan_port_pvid(smi, port, val);
1335 }
1336
1337 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1338 {
1339 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1340 int err;
1341
1342 err = rtl8366s_reset_chip(smi);
1343 if (err)
1344 return err;
1345
1346 return rtl8366s_reset_vlan(smi);
1347 }
1348
1349 static struct switch_attr rtl8366s_globals[] = {
1350 {
1351 .type = SWITCH_TYPE_INT,
1352 .name = "enable_vlan",
1353 .description = "Enable VLAN mode",
1354 .set = rtl8366s_sw_set_vlan_enable,
1355 .get = rtl8366s_sw_get_vlan_enable,
1356 .max = 1,
1357 .ofs = 1
1358 }, {
1359 .type = SWITCH_TYPE_INT,
1360 .name = "enable_vlan4k",
1361 .description = "Enable VLAN 4K mode",
1362 .set = rtl8366s_sw_set_vlan_enable,
1363 .get = rtl8366s_sw_get_vlan_enable,
1364 .max = 1,
1365 .ofs = 2
1366 }, {
1367 .type = SWITCH_TYPE_INT,
1368 .name = "reset_mibs",
1369 .description = "Reset all MIB counters",
1370 .set = rtl8366s_sw_reset_mibs,
1371 .get = NULL,
1372 .max = 1
1373 }, {
1374 .type = SWITCH_TYPE_INT,
1375 .name = "blinkrate",
1376 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1377 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1378 .set = rtl8366s_sw_set_blinkrate,
1379 .get = rtl8366s_sw_get_blinkrate,
1380 .max = 5
1381 },
1382 };
1383
1384 static struct switch_attr rtl8366s_port[] = {
1385 {
1386 .type = SWITCH_TYPE_STRING,
1387 .name = "link",
1388 .description = "Get port link information",
1389 .max = 1,
1390 .set = NULL,
1391 .get = rtl8366s_sw_get_port_link,
1392 }, {
1393 .type = SWITCH_TYPE_INT,
1394 .name = "reset_mib",
1395 .description = "Reset single port MIB counters",
1396 .max = 1,
1397 .set = rtl8366s_sw_reset_port_mibs,
1398 .get = NULL,
1399 }, {
1400 .type = SWITCH_TYPE_STRING,
1401 .name = "mib",
1402 .description = "Get MIB counters for port",
1403 .max = 33,
1404 .set = NULL,
1405 .get = rtl8366s_sw_get_port_mib,
1406 }, {
1407 .type = SWITCH_TYPE_INT,
1408 .name = "led",
1409 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1410 .max = 15,
1411 .set = rtl8366s_sw_set_port_led,
1412 .get = rtl8366s_sw_get_port_led,
1413 },
1414 };
1415
1416 static struct switch_attr rtl8366s_vlan[] = {
1417 {
1418 .type = SWITCH_TYPE_STRING,
1419 .name = "info",
1420 .description = "Get vlan information",
1421 .max = 1,
1422 .set = NULL,
1423 .get = rtl8366s_sw_get_vlan_info,
1424 },
1425 };
1426
1427 /* template */
1428 static struct switch_dev rtl8366_switch_dev = {
1429 .name = "RTL8366S",
1430 .cpu_port = RTL8366_PORT_NUM_CPU,
1431 .ports = RTL8366_NUM_PORTS,
1432 .vlans = RTL8366_NUM_VLANS,
1433 .attr_global = {
1434 .attr = rtl8366s_globals,
1435 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1436 },
1437 .attr_port = {
1438 .attr = rtl8366s_port,
1439 .n_attr = ARRAY_SIZE(rtl8366s_port),
1440 },
1441 .attr_vlan = {
1442 .attr = rtl8366s_vlan,
1443 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1444 },
1445
1446 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1447 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1448 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1449 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1450 .reset_switch = rtl8366s_sw_reset_switch,
1451 };
1452
1453 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1454 {
1455 struct switch_dev *dev = &rtl->dev;
1456 int err;
1457
1458 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1459 dev->priv = rtl;
1460 dev->devname = dev_name(rtl->parent);
1461
1462 err = register_switch(dev, NULL);
1463 if (err)
1464 dev_err(rtl->parent, "switch registration failed\n");
1465
1466 return err;
1467 }
1468
1469 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1470 {
1471 unregister_switch(&rtl->dev);
1472 }
1473
1474 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1475 {
1476 struct rtl8366_smi *smi = bus->priv;
1477 u32 val = 0;
1478 int err;
1479
1480 err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1481 if (err)
1482 return 0xffff;
1483
1484 return val;
1485 }
1486
1487 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1488 {
1489 struct rtl8366_smi *smi = bus->priv;
1490 u32 t;
1491 int err;
1492
1493 err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1494 /* flush write */
1495 (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1496
1497 return err;
1498 }
1499
1500 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1501 {
1502 return (bus->read == rtl8366s_mii_read &&
1503 bus->write == rtl8366s_mii_write);
1504 }
1505
1506 static int rtl8366s_setup(struct rtl8366s *rtl)
1507 {
1508 struct rtl8366_smi *smi = &rtl->smi;
1509 int ret;
1510
1511 ret = rtl8366s_reset_chip(smi);
1512 if (ret)
1513 return ret;
1514
1515 rtl8366s_debugfs_init(rtl);
1516 return 0;
1517 }
1518
1519 static int rtl8366s_detect(struct rtl8366_smi *smi)
1520 {
1521 u32 chip_id = 0;
1522 u32 chip_ver = 0;
1523 int ret;
1524
1525 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1526 if (ret) {
1527 dev_err(smi->parent, "unable to read chip id\n");
1528 return ret;
1529 }
1530
1531 switch (chip_id) {
1532 case RTL8366S_CHIP_ID_8366:
1533 break;
1534 default:
1535 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1536 return -ENODEV;
1537 }
1538
1539 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1540 &chip_ver);
1541 if (ret) {
1542 dev_err(smi->parent, "unable to read chip version\n");
1543 return ret;
1544 }
1545
1546 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1547 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1548
1549 return 0;
1550 }
1551
1552 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1553 .detect = rtl8366s_detect,
1554 .mii_read = rtl8366s_mii_read,
1555 .mii_write = rtl8366s_mii_write,
1556 };
1557
1558 static int __init rtl8366s_probe(struct platform_device *pdev)
1559 {
1560 static int rtl8366_smi_version_printed;
1561 struct rtl8366s_platform_data *pdata;
1562 struct rtl8366s *rtl;
1563 struct rtl8366_smi *smi;
1564 int err;
1565
1566 if (!rtl8366_smi_version_printed++)
1567 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1568 " version " RTL8366S_DRIVER_VER"\n");
1569
1570 pdata = pdev->dev.platform_data;
1571 if (!pdata) {
1572 dev_err(&pdev->dev, "no platform data specified\n");
1573 err = -EINVAL;
1574 goto err_out;
1575 }
1576
1577 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1578 if (!rtl) {
1579 dev_err(&pdev->dev, "no memory for private data\n");
1580 err = -ENOMEM;
1581 goto err_out;
1582 }
1583
1584 rtl->parent = &pdev->dev;
1585
1586 smi = &rtl->smi;
1587 smi->parent = &pdev->dev;
1588 smi->gpio_sda = pdata->gpio_sda;
1589 smi->gpio_sck = pdata->gpio_sck;
1590 smi->ops = &rtl8366s_smi_ops;
1591
1592 err = rtl8366_smi_init(smi);
1593 if (err)
1594 goto err_free_rtl;
1595
1596 platform_set_drvdata(pdev, rtl);
1597
1598 err = rtl8366s_setup(rtl);
1599 if (err)
1600 goto err_clear_drvdata;
1601
1602 err = rtl8366s_switch_init(rtl);
1603 if (err)
1604 goto err_clear_drvdata;
1605
1606 return 0;
1607
1608 err_clear_drvdata:
1609 platform_set_drvdata(pdev, NULL);
1610 rtl8366_smi_cleanup(smi);
1611 err_free_rtl:
1612 kfree(rtl);
1613 err_out:
1614 return err;
1615 }
1616
1617 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1618 {
1619 if (!rtl8366s_mii_bus_match(phydev->bus))
1620 return -EINVAL;
1621
1622 return 0;
1623 }
1624
1625 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1626 {
1627 return 0;
1628 }
1629
1630 static struct phy_driver rtl8366s_phy_driver = {
1631 .phy_id = 0x001cc960,
1632 .name = "Realtek RTL8366S",
1633 .phy_id_mask = 0x1ffffff0,
1634 .features = PHY_GBIT_FEATURES,
1635 .config_aneg = rtl8366s_phy_config_aneg,
1636 .config_init = rtl8366s_phy_config_init,
1637 .read_status = genphy_read_status,
1638 .driver = {
1639 .owner = THIS_MODULE,
1640 },
1641 };
1642
1643 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1644 {
1645 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1646
1647 if (rtl) {
1648 rtl8366s_switch_cleanup(rtl);
1649 rtl8366s_debugfs_remove(rtl);
1650 platform_set_drvdata(pdev, NULL);
1651 rtl8366_smi_cleanup(&rtl->smi);
1652 kfree(rtl);
1653 }
1654
1655 return 0;
1656 }
1657
1658 static struct platform_driver rtl8366s_driver = {
1659 .driver = {
1660 .name = RTL8366S_DRIVER_NAME,
1661 .owner = THIS_MODULE,
1662 },
1663 .probe = rtl8366s_probe,
1664 .remove = __devexit_p(rtl8366s_remove),
1665 };
1666
1667 static int __init rtl8366s_module_init(void)
1668 {
1669 int ret;
1670 ret = platform_driver_register(&rtl8366s_driver);
1671 if (ret)
1672 return ret;
1673
1674 ret = phy_driver_register(&rtl8366s_phy_driver);
1675 if (ret)
1676 goto err_platform_unregister;
1677
1678 return 0;
1679
1680 err_platform_unregister:
1681 platform_driver_unregister(&rtl8366s_driver);
1682 return ret;
1683 }
1684 module_init(rtl8366s_module_init);
1685
1686 static void __exit rtl8366s_module_exit(void)
1687 {
1688 phy_driver_unregister(&rtl8366s_phy_driver);
1689 platform_driver_unregister(&rtl8366s_driver);
1690 }
1691 module_exit(rtl8366s_module_exit);
1692
1693 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1694 MODULE_VERSION(RTL8366S_DRIVER_VER);
1695 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1696 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1697 MODULE_LICENSE("GPL v2");
1698 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
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