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backfire: generic: rtl8366: introduce rtl8366_smi_rmwr function (backport of r21919)
[openwrt/svn-archive/archive.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366s.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366s.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
29
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
33
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
36
37 #define RTL8366_RESET_CTRL_REG 0x0100
38 #define RTL8366_CHIP_CTRL_RESET_HW 1
39 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
40
41 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
42 #define RTL8366S_CHIP_VERSION_MASK 0xf
43 #define RTL8366S_CHIP_ID_REG 0x0105
44 #define RTL8366S_CHIP_ID_8366 0x8366
45
46 /* PHY registers control */
47 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
48 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
49
50 #define RTL8366S_PHY_CTRL_READ 1
51 #define RTL8366S_PHY_CTRL_WRITE 0
52
53 #define RTL8366S_PHY_REG_MASK 0x1f
54 #define RTL8366S_PHY_PAGE_OFFSET 5
55 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
56 #define RTL8366S_PHY_NO_OFFSET 9
57 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
58
59 /* LED control registers */
60 #define RTL8366_LED_BLINKRATE_REG 0x0420
61 #define RTL8366_LED_BLINKRATE_BIT 0
62 #define RTL8366_LED_BLINKRATE_MASK 0x0007
63
64 #define RTL8366_LED_CTRL_REG 0x0421
65 #define RTL8366_LED_0_1_CTRL_REG 0x0422
66 #define RTL8366_LED_2_3_CTRL_REG 0x0423
67
68 #define RTL8366S_MIB_COUNT 33
69 #define RTL8366S_GLOBAL_MIB_COUNT 1
70 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
71 #define RTL8366S_MIB_COUNTER_BASE 0x1000
72 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
73 #define RTL8366S_MIB_COUNTER_BASE2 0x1180
74 #define RTL8366S_MIB_CTRL_REG 0x11F0
75 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
76 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
77 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
78
79 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
80 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
81 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
82
83
84 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
85 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
86 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
87 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
88 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
89
90
91 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
92 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
93
94 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
95
96 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
97 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
98 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
99
100 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
101
102
103 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
104 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
105 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
106 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
107 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
108 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
109 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
110
111
112 #define RTL8366_PORT_NUM_CPU 5
113 #define RTL8366_NUM_PORTS 6
114 #define RTL8366_NUM_VLANS 16
115 #define RTL8366_NUM_LEDGROUPS 4
116 #define RTL8366_NUM_VIDS 4096
117 #define RTL8366S_PRIORITYMAX 7
118 #define RTL8366S_FIDMAX 7
119
120
121 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
122 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
123 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
124 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
125
126 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
127 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
128
129 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
130 RTL8366_PORT_2 | \
131 RTL8366_PORT_3 | \
132 RTL8366_PORT_4 | \
133 RTL8366_PORT_UNKNOWN | \
134 RTL8366_PORT_CPU)
135
136 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
137 RTL8366_PORT_2 | \
138 RTL8366_PORT_3 | \
139 RTL8366_PORT_4 | \
140 RTL8366_PORT_UNKNOWN)
141
142 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
143 RTL8366_PORT_2 | \
144 RTL8366_PORT_3 | \
145 RTL8366_PORT_4)
146
147 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
148 RTL8366_PORT_CPU)
149
150 struct rtl8366s {
151 struct device *parent;
152 struct rtl8366_smi smi;
153 struct switch_dev dev;
154 char buf[4096];
155 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
156 struct dentry *debugfs_root;
157 #endif
158 };
159
160 struct rtl8366s_vlan_mc {
161 u16 reserved2:1;
162 u16 priority:3;
163 u16 vid:12;
164
165 u16 reserved1:1;
166 u16 fid:3;
167 u16 untag:6;
168 u16 member:6;
169 };
170
171 struct rtl8366s_vlan_4k {
172 u16 reserved1:4;
173 u16 vid:12;
174
175 u16 reserved2:1;
176 u16 fid:3;
177 u16 untag:6;
178 u16 member:6;
179 };
180
181 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
182 u16 g_dbg_reg;
183 #endif
184
185 struct mib_counter {
186 unsigned base;
187 unsigned offset;
188 unsigned length;
189 const char *name;
190 };
191
192 static struct mib_counter rtl8366s_mib_counters[RTL8366S_MIB_COUNT] = {
193 { 0, 0, 4, "IfInOctets" },
194 { 0, 4, 4, "EtherStatsOctets" },
195 { 0, 8, 2, "EtherStatsUnderSizePkts" },
196 { 0, 10, 2, "EtherFragments" },
197 { 0, 12, 2, "EtherStatsPkts64Octets" },
198 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
199 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
200 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
201 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
202 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
203 { 0, 24, 2, "EtherOversizeStats" },
204 { 0, 26, 2, "EtherStatsJabbers" },
205 { 0, 28, 2, "IfInUcastPkts" },
206 { 0, 30, 2, "EtherStatsMulticastPkts" },
207 { 0, 32, 2, "EtherStatsBroadcastPkts" },
208 { 0, 34, 2, "EtherStatsDropEvents" },
209 { 0, 36, 2, "Dot3StatsFCSErrors" },
210 { 0, 38, 2, "Dot3StatsSymbolErrors" },
211 { 0, 40, 2, "Dot3InPauseFrames" },
212 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
213 { 0, 44, 4, "IfOutOctets" },
214 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
215 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
216 { 0, 52, 2, "Dot3sDeferredTransmissions" },
217 { 0, 54, 2, "Dot3StatsLateCollisions" },
218 { 0, 56, 2, "EtherStatsCollisions" },
219 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
220 { 0, 60, 2, "Dot3OutPauseFrames" },
221 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
222
223 /*
224 * The following counters are accessible at a different
225 * base address.
226 */
227 { 1, 0, 2, "Dot1dTpPortInDiscards" },
228 { 1, 2, 2, "IfOutUcastPkts" },
229 { 1, 4, 2, "IfOutMulticastPkts" },
230 { 1, 6, 2, "IfOutBroadcastPkts" },
231 };
232
233 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
234 {
235 return container_of(smi, struct rtl8366s, smi);
236 }
237
238 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
239 {
240 return container_of(sw, struct rtl8366s, dev);
241 }
242
243 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
244 {
245 struct rtl8366s *rtl = sw_to_rtl8366s(sw);
246 return &rtl->smi;
247 }
248
249 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
250 {
251 int timeout = 10;
252 u32 data;
253
254 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
255 RTL8366_CHIP_CTRL_RESET_HW);
256 do {
257 msleep(1);
258 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
259 return -EIO;
260
261 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
262 break;
263 } while (--timeout);
264
265 if (!timeout) {
266 printk("Timeout waiting for the switch to reset\n");
267 return -EIO;
268 }
269
270 return 0;
271 }
272
273 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
274 u32 phy_no, u32 page, u32 addr, u32 *data)
275 {
276 u32 reg;
277 int ret;
278
279 if (phy_no > RTL8366S_PHY_NO_MAX)
280 return -EINVAL;
281
282 if (page > RTL8366S_PHY_PAGE_MAX)
283 return -EINVAL;
284
285 if (addr > RTL8366S_PHY_ADDR_MAX)
286 return -EINVAL;
287
288 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
289 RTL8366S_PHY_CTRL_READ);
290 if (ret)
291 return ret;
292
293 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
294 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
295 (addr & RTL8366S_PHY_REG_MASK);
296
297 ret = rtl8366_smi_write_reg(smi, reg, 0);
298 if (ret)
299 return ret;
300
301 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
302 if (ret)
303 return ret;
304
305 return 0;
306 }
307
308 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
309 u32 phy_no, u32 page, u32 addr, u32 data)
310 {
311 u32 reg;
312 int ret;
313
314 if (phy_no > RTL8366S_PHY_NO_MAX)
315 return -EINVAL;
316
317 if (page > RTL8366S_PHY_PAGE_MAX)
318 return -EINVAL;
319
320 if (addr > RTL8366S_PHY_ADDR_MAX)
321 return -EINVAL;
322
323 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
324 RTL8366S_PHY_CTRL_WRITE);
325 if (ret)
326 return ret;
327
328 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
329 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
330 (addr & RTL8366S_PHY_REG_MASK);
331
332 ret = rtl8366_smi_write_reg(smi, reg, data);
333 if (ret)
334 return ret;
335
336 return 0;
337 }
338
339 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
340 int port, unsigned long long *val)
341 {
342 int i;
343 int err;
344 u32 addr, data;
345 u64 mibvalue;
346
347 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
348 return -EINVAL;
349
350 switch (rtl8366s_mib_counters[counter].base) {
351 case 0:
352 addr = RTL8366S_MIB_COUNTER_BASE +
353 RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
354 break;
355
356 case 1:
357 addr = RTL8366S_MIB_COUNTER_BASE2 +
358 RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
359 break;
360
361 default:
362 return -EINVAL;
363 }
364
365 addr += rtl8366s_mib_counters[counter].offset;
366
367 /*
368 * Writing access counter address first
369 * then ASIC will prepare 64bits counter wait for being retrived
370 */
371 data = 0; /* writing data will be discard by ASIC */
372 err = rtl8366_smi_write_reg(smi, addr, data);
373 if (err)
374 return err;
375
376 /* read MIB control register */
377 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
378 if (err)
379 return err;
380
381 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
382 return -EBUSY;
383
384 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
385 return -EIO;
386
387 mibvalue = 0;
388 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
389 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
390 if (err)
391 return err;
392
393 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
394 }
395
396 *val = mibvalue;
397 return 0;
398 }
399
400 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
401 struct rtl8366_vlan_4k *vlan4k)
402 {
403 struct rtl8366s_vlan_4k vlan4k_priv;
404 int err;
405 u32 data;
406 u16 *tableaddr;
407
408 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
409 vlan4k_priv.vid = vid;
410
411 if (vid >= RTL8366_NUM_VIDS)
412 return -EINVAL;
413
414 tableaddr = (u16 *)&vlan4k_priv;
415
416 /* write VID */
417 data = *tableaddr;
418 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
419 if (err)
420 return err;
421
422 /* write table access control word */
423 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
424 RTL8366S_TABLE_VLAN_READ_CTRL);
425 if (err)
426 return err;
427
428 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
429 if (err)
430 return err;
431
432 *tableaddr = data;
433 tableaddr++;
434
435 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
436 &data);
437 if (err)
438 return err;
439
440 *tableaddr = data;
441
442 vlan4k->vid = vid;
443 vlan4k->untag = vlan4k_priv.untag;
444 vlan4k->member = vlan4k_priv.member;
445 vlan4k->fid = vlan4k_priv.fid;
446
447 return 0;
448 }
449
450 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
451 const struct rtl8366_vlan_4k *vlan4k)
452 {
453 struct rtl8366s_vlan_4k vlan4k_priv;
454 int err;
455 u32 data;
456 u16 *tableaddr;
457
458 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
459 vlan4k->member > RTL8366_PORT_ALL ||
460 vlan4k->untag > RTL8366_PORT_ALL ||
461 vlan4k->fid > RTL8366S_FIDMAX)
462 return -EINVAL;
463
464 vlan4k_priv.vid = vlan4k->vid;
465 vlan4k_priv.untag = vlan4k->untag;
466 vlan4k_priv.member = vlan4k->member;
467 vlan4k_priv.fid = vlan4k->fid;
468
469 tableaddr = (u16 *)&vlan4k_priv;
470
471 data = *tableaddr;
472
473 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
474 if (err)
475 return err;
476
477 tableaddr++;
478
479 data = *tableaddr;
480
481 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
482 data);
483 if (err)
484 return err;
485
486 /* write table access control word */
487 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
488 RTL8366S_TABLE_VLAN_WRITE_CTRL);
489
490 return err;
491 }
492
493 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
494 struct rtl8366_vlan_mc *vlanmc)
495 {
496 struct rtl8366s_vlan_mc vlanmc_priv;
497 int err;
498 u32 addr;
499 u32 data;
500 u16 *tableaddr;
501
502 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
503
504 if (index >= RTL8366_NUM_VLANS)
505 return -EINVAL;
506
507 tableaddr = (u16 *)&vlanmc_priv;
508
509 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
510 err = rtl8366_smi_read_reg(smi, addr, &data);
511 if (err)
512 return err;
513
514 *tableaddr = data;
515 tableaddr++;
516
517 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
518 err = rtl8366_smi_read_reg(smi, addr, &data);
519 if (err)
520 return err;
521
522 *tableaddr = data;
523
524 vlanmc->vid = vlanmc_priv.vid;
525 vlanmc->priority = vlanmc_priv.priority;
526 vlanmc->untag = vlanmc_priv.untag;
527 vlanmc->member = vlanmc_priv.member;
528 vlanmc->fid = vlanmc_priv.fid;
529
530 return 0;
531 }
532
533 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
534 const struct rtl8366_vlan_mc *vlanmc)
535 {
536 struct rtl8366s_vlan_mc vlanmc_priv;
537 int err;
538 u32 addr;
539 u32 data;
540 u16 *tableaddr;
541
542 if (index >= RTL8366_NUM_VLANS ||
543 vlanmc->vid >= RTL8366_NUM_VIDS ||
544 vlanmc->priority > RTL8366S_PRIORITYMAX ||
545 vlanmc->member > RTL8366_PORT_ALL ||
546 vlanmc->untag > RTL8366_PORT_ALL ||
547 vlanmc->fid > RTL8366S_FIDMAX)
548 return -EINVAL;
549
550 vlanmc_priv.vid = vlanmc->vid;
551 vlanmc_priv.priority = vlanmc->priority;
552 vlanmc_priv.untag = vlanmc->untag;
553 vlanmc_priv.member = vlanmc->member;
554 vlanmc_priv.fid = vlanmc->fid;
555
556 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
557
558 tableaddr = (u16 *)&vlanmc_priv;
559 data = *tableaddr;
560
561 err = rtl8366_smi_write_reg(smi, addr, data);
562 if (err)
563 return err;
564
565 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
566
567 tableaddr++;
568 data = *tableaddr;
569
570 err = rtl8366_smi_write_reg(smi, addr, data);
571 if (err)
572 return err;
573
574 return 0;
575 }
576
577 static int rtl8366s_get_port_vlan_index(struct rtl8366_smi *smi, int port,
578 int *val)
579 {
580 u32 data;
581 int err;
582
583 if (port >= RTL8366_NUM_PORTS)
584 return -EINVAL;
585
586 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
587 &data);
588 if (err)
589 return err;
590
591 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
592 RTL8366S_PORT_VLAN_CTRL_MASK;
593
594 return 0;
595
596 }
597
598 static int rtl8366s_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
599 int *val)
600 {
601 struct rtl8366_vlan_mc vlanmc;
602 int err;
603 int index;
604
605 err = rtl8366s_get_port_vlan_index(smi, port, &index);
606 if (err)
607 return err;
608
609 err = rtl8366s_get_vlan_mc(smi, index, &vlanmc);
610 if (err)
611 return err;
612
613 *val = vlanmc.vid;
614 return 0;
615 }
616
617 static int rtl8366s_set_port_vlan_index(struct rtl8366_smi *smi, int port,
618 int index)
619 {
620 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
621 return -EINVAL;
622
623 return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
624 RTL8366S_PORT_VLAN_CTRL_MASK <<
625 RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
626 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
627 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
628 }
629
630 static int rtl8366s_set_vlan_port_pvid(struct rtl8366_smi *smi, int port, int val)
631 {
632 int i;
633 struct rtl8366_vlan_mc vlanmc;
634 struct rtl8366_vlan_4k vlan4k;
635
636 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
637 return -EINVAL;
638
639 /* Updating the 4K entry; lookup it and change the port member set */
640 rtl8366s_get_vlan_4k(smi, val, &vlan4k);
641 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
642 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
643 rtl8366s_set_vlan_4k(smi, &vlan4k);
644
645 /*
646 * For the 16 entries more work needs to be done. First see if such
647 * VID is already there and change it
648 */
649 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
650 rtl8366s_get_vlan_mc(smi, i, &vlanmc);
651
652 /* Try to find an existing vid and update port member set */
653 if (val == vlanmc.vid) {
654 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
655 rtl8366s_set_vlan_mc(smi, i, &vlanmc);
656
657 /* Now update PVID register settings */
658 rtl8366s_set_port_vlan_index(smi, port, i);
659
660 return 0;
661 }
662 }
663
664 /*
665 * PVID could not be found from vlan table. Replace unused (one that
666 * has no member ports) with new one
667 */
668 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
669 rtl8366s_get_vlan_mc(smi, i, &vlanmc);
670
671 /*
672 * See if this vlan member configuration is unused. It is
673 * unused if member set contains no ports or CPU port only
674 */
675 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
676 vlanmc.vid = val;
677 vlanmc.priority = 0;
678 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
679 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
680 vlanmc.fid = 0;
681
682 rtl8366s_set_vlan_mc(smi, i, &vlanmc);
683
684 /* Now update PVID register settings */
685 rtl8366s_set_port_vlan_index(smi, port, i);
686
687 return 0;
688 }
689 }
690
691 dev_err(smi->parent,
692 "All 16 vlan member configurations are in use\n");
693
694 return -EINVAL;
695 }
696
697
698 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
699 {
700 return rtl8366_smi_rmwr(smi, RTL8366_CHIP_GLOBAL_CTRL_REG,
701 RTL8366_CHIP_CTRL_VLAN,
702 (enable) ? RTL8366_CHIP_CTRL_VLAN : 0);
703 }
704
705 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
706 {
707 return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
708 1, (enable) ? 1 : 0);
709 }
710
711 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
712 {
713 struct rtl8366_vlan_4k vlan4k;
714 struct rtl8366_vlan_mc vlanmc;
715 int err;
716 int i;
717
718 /* clear 16 VLAN member configuration */
719 vlanmc.vid = 0;
720 vlanmc.priority = 0;
721 vlanmc.member = 0;
722 vlanmc.untag = 0;
723 vlanmc.fid = 0;
724 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
725 err = rtl8366s_set_vlan_mc(smi, i, &vlanmc);
726 if (err)
727 return err;
728 }
729
730 /* Set a default VLAN with vid 1 to 4K table for all ports */
731 vlan4k.vid = 1;
732 vlan4k.member = RTL8366_PORT_ALL;
733 vlan4k.untag = RTL8366_PORT_ALL;
734 vlan4k.fid = 0;
735 err = rtl8366s_set_vlan_4k(smi, &vlan4k);
736 if (err)
737 return err;
738
739 /* Set all ports PVID to default VLAN */
740 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
741 err = rtl8366s_set_vlan_port_pvid(smi, i, 0);
742 if (err)
743 return err;
744 }
745
746 return 0;
747 }
748
749 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
750 static int rtl8366s_debugfs_open(struct inode *inode, struct file *file)
751 {
752 file->private_data = inode->i_private;
753 return 0;
754 }
755
756 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
757 char __user *user_buf,
758 size_t count, loff_t *ppos)
759 {
760 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
761 struct rtl8366_smi *smi = &rtl->smi;
762 int i, j, len = 0;
763 char *buf = rtl->buf;
764
765 len += snprintf(buf + len, sizeof(rtl->buf) - len,
766 "%-36s %12s %12s %12s %12s %12s %12s\n",
767 "Counter",
768 "Port 0", "Port 1", "Port 2",
769 "Port 3", "Port 4", "Port 5");
770
771 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
772 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%-36s ",
773 rtl8366s_mib_counters[i].name);
774 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
775 unsigned long long counter = 0;
776
777 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
778 len += snprintf(buf + len,
779 sizeof(rtl->buf) - len,
780 "%12llu ", counter);
781 else
782 len += snprintf(buf + len,
783 sizeof(rtl->buf) - len,
784 "%12s ", "error");
785 }
786 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
787 }
788
789 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
790 }
791
792 static ssize_t rtl8366s_read_debugfs_vlan(struct file *file,
793 char __user *user_buf,
794 size_t count, loff_t *ppos)
795 {
796 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
797 struct rtl8366_smi *smi = &rtl->smi;
798 int i, j, len = 0;
799 char *buf = rtl->buf;
800
801 len += snprintf(buf + len, sizeof(rtl->buf) - len,
802 "VLAN Member Config:\n");
803 len += snprintf(buf + len, sizeof(rtl->buf) - len,
804 "\t id \t vid \t prio \t member \t untag \t fid "
805 "\tports\n");
806
807 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
808 struct rtl8366_vlan_mc vlanmc;
809
810 rtl8366s_get_vlan_mc(smi, i, &vlanmc);
811
812 len += snprintf(buf + len, sizeof(rtl->buf) - len,
813 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
814 "\t", i, vlanmc.vid, vlanmc.priority,
815 vlanmc.member, vlanmc.untag, vlanmc.fid);
816
817 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
818 int index = 0;
819 if (!rtl8366s_get_port_vlan_index(smi, j, &index)) {
820 if (index == i)
821 len += snprintf(buf + len,
822 sizeof(rtl->buf) - len,
823 "%d", j);
824 }
825 }
826 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
827 }
828
829 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
830 }
831
832 static ssize_t rtl8366s_read_debugfs_reg(struct file *file,
833 char __user *user_buf,
834 size_t count, loff_t *ppos)
835 {
836 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
837 struct rtl8366_smi *smi = &rtl->smi;
838 u32 t, reg = g_dbg_reg;
839 int err, len = 0;
840 char *buf = rtl->buf;
841
842 memset(buf, '\0', sizeof(rtl->buf));
843
844 err = rtl8366_smi_read_reg(smi, reg, &t);
845 if (err) {
846 len += snprintf(buf, sizeof(rtl->buf),
847 "Read failed (reg: 0x%04x)\n", reg);
848 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
849 }
850
851 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
852 reg, t);
853
854 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
855 }
856
857 static ssize_t rtl8366s_write_debugfs_reg(struct file *file,
858 const char __user *user_buf,
859 size_t count, loff_t *ppos)
860 {
861 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
862 struct rtl8366_smi *smi = &rtl->smi;
863 unsigned long data;
864 u32 reg = g_dbg_reg;
865 int err;
866 size_t len;
867 char *buf = rtl->buf;
868
869 len = min(count, sizeof(rtl->buf) - 1);
870 if (copy_from_user(buf, user_buf, len)) {
871 dev_err(rtl->parent, "copy from user failed\n");
872 return -EFAULT;
873 }
874
875 buf[len] = '\0';
876 if (len > 0 && buf[len - 1] == '\n')
877 buf[len - 1] = '\0';
878
879
880 if (strict_strtoul(buf, 16, &data)) {
881 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
882 } else {
883 err = rtl8366_smi_write_reg(smi, reg, data);
884 if (err) {
885 dev_err(rtl->parent,
886 "writing reg 0x%04x val 0x%04lx failed\n",
887 reg, data);
888 }
889 }
890
891 return count;
892 }
893
894 static const struct file_operations fops_rtl8366s_regs = {
895 .read = rtl8366s_read_debugfs_reg,
896 .write = rtl8366s_write_debugfs_reg,
897 .open = rtl8366s_debugfs_open,
898 .owner = THIS_MODULE
899 };
900
901 static const struct file_operations fops_rtl8366s_vlan = {
902 .read = rtl8366s_read_debugfs_vlan,
903 .open = rtl8366s_debugfs_open,
904 .owner = THIS_MODULE
905 };
906
907 static const struct file_operations fops_rtl8366s_mibs = {
908 .read = rtl8366s_read_debugfs_mibs,
909 .open = rtl8366s_debugfs_open,
910 .owner = THIS_MODULE
911 };
912
913 static void rtl8366s_debugfs_init(struct rtl8366s *rtl)
914 {
915 struct dentry *node;
916 struct dentry *root;
917
918 if (!rtl->debugfs_root)
919 rtl->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
920
921 if (!rtl->debugfs_root) {
922 dev_err(rtl->parent, "Unable to create debugfs dir\n");
923 return;
924 }
925 root = rtl->debugfs_root;
926
927 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
928 if (!node) {
929 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
930 "reg");
931 return;
932 }
933
934 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
935 &fops_rtl8366s_regs);
936 if (!node) {
937 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
938 "val");
939 return;
940 }
941
942 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
943 &fops_rtl8366s_vlan);
944 if (!node) {
945 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
946 "vlan");
947 return;
948 }
949
950 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
951 &fops_rtl8366s_mibs);
952 if (!node) {
953 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
954 "mibs");
955 return;
956 }
957 }
958
959 static void rtl8366s_debugfs_remove(struct rtl8366s *rtl)
960 {
961 if (rtl->debugfs_root) {
962 debugfs_remove_recursive(rtl->debugfs_root);
963 rtl->debugfs_root = NULL;
964 }
965 }
966
967 #else
968 static inline void rtl8366s_debugfs_init(struct rtl8366s *rtl) {}
969 static inline void rtl8366s_debugfs_remove(struct rtl8366s *rtl) {}
970 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
971
972 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
973 const struct switch_attr *attr,
974 struct switch_val *val)
975 {
976 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
977 int err = 0;
978
979 if (val->value.i == 1)
980 err = rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
981
982 return err;
983 }
984
985 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
986 const struct switch_attr *attr,
987 struct switch_val *val)
988 {
989 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
990 u32 data;
991
992 if (attr->ofs == 1) {
993 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
994
995 if (data & RTL8366_CHIP_CTRL_VLAN)
996 val->value.i = 1;
997 else
998 val->value.i = 0;
999 } else if (attr->ofs == 2) {
1000 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1001
1002 if (data & 0x0001)
1003 val->value.i = 1;
1004 else
1005 val->value.i = 0;
1006 }
1007
1008 return 0;
1009 }
1010
1011 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
1012 const struct switch_attr *attr,
1013 struct switch_val *val)
1014 {
1015 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1016 u32 data;
1017
1018 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1019
1020 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1021
1022 return 0;
1023 }
1024
1025 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
1026 const struct switch_attr *attr,
1027 struct switch_val *val)
1028 {
1029 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1030
1031 if (val->value.i >= 6)
1032 return -EINVAL;
1033
1034 return rtl8366_smi_rmwr(smi, RTL8366_LED_BLINKRATE_REG,
1035 RTL8366_LED_BLINKRATE_MASK,
1036 val->value.i);
1037 }
1038
1039 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
1040 const struct switch_attr *attr,
1041 struct switch_val *val)
1042 {
1043 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1044
1045 if (attr->ofs == 1)
1046 return rtl8366s_vlan_set_vlan(smi, val->value.i);
1047 else
1048 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
1049 }
1050
1051 static const char *rtl8366s_speed_str(unsigned speed)
1052 {
1053 switch (speed) {
1054 case 0:
1055 return "10baseT";
1056 case 1:
1057 return "100baseT";
1058 case 2:
1059 return "1000baseT";
1060 }
1061
1062 return "unknown";
1063 }
1064
1065 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
1066 const struct switch_attr *attr,
1067 struct switch_val *val)
1068 {
1069 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1070 struct rtl8366_smi *smi = &rtl->smi;
1071 u32 len = 0, data = 0;
1072
1073 if (val->port_vlan >= RTL8366_NUM_PORTS)
1074 return -EINVAL;
1075
1076 memset(rtl->buf, '\0', sizeof(rtl->buf));
1077 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1078 (val->port_vlan / 2), &data);
1079
1080 if (val->port_vlan % 2)
1081 data = data >> 8;
1082
1083 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
1084 len = snprintf(rtl->buf, sizeof(rtl->buf),
1085 "port:%d link:up speed:%s %s-duplex %s%s%s",
1086 val->port_vlan,
1087 rtl8366s_speed_str(data &
1088 RTL8366S_PORT_STATUS_SPEED_MASK),
1089 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1090 "full" : "half",
1091 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1092 "tx-pause ": "",
1093 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1094 "rx-pause " : "",
1095 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
1096 "nway ": "");
1097 } else {
1098 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1099 val->port_vlan);
1100 }
1101
1102 val->value.s = rtl->buf;
1103 val->len = len;
1104
1105 return 0;
1106 }
1107
1108 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
1109 const struct switch_attr *attr,
1110 struct switch_val *val)
1111 {
1112 int i;
1113 u32 len = 0;
1114 struct rtl8366_vlan_mc vlanmc;
1115 struct rtl8366_vlan_4k vlan4k;
1116 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1117 struct rtl8366_smi *smi = &rtl->smi;
1118 char *buf = rtl->buf;
1119
1120 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1121 return -EINVAL;
1122
1123 memset(buf, '\0', sizeof(rtl->buf));
1124
1125 rtl8366s_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1126 rtl8366s_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
1127
1128 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1129 val->port_vlan);
1130
1131 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1132 int index = 0;
1133 if (!rtl8366s_get_port_vlan_index(smi, i, &index) &&
1134 index == val->port_vlan)
1135 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1136 "%d", i);
1137 }
1138 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1139
1140 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1141 "\t\t vid \t prio \t member \t untag \t fid\n");
1142 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1143 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1144 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1145 vlanmc.vid, vlanmc.priority, vlanmc.member,
1146 vlanmc.untag, vlanmc.fid);
1147 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1148 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1149 "%d \t \t 0x%04x \t 0x%04x \t %d",
1150 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1151
1152 val->value.s = buf;
1153 val->len = len;
1154
1155 return 0;
1156 }
1157
1158 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
1159 const struct switch_attr *attr,
1160 struct switch_val *val)
1161 {
1162 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1163 u32 data;
1164 u32 mask;
1165 u32 reg;
1166
1167 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1168 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1169 return -EINVAL;
1170
1171 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1172 reg = RTL8366_LED_BLINKRATE_REG;
1173 mask = 0xF << 4;
1174 data = val->value.i << 4;
1175 } else {
1176 reg = RTL8366_LED_CTRL_REG;
1177 mask = 0xF << (val->port_vlan * 4),
1178 data = val->value.i << (val->port_vlan * 4);
1179 }
1180
1181 return rtl8366_smi_rmwr(smi, RTL8366_LED_BLINKRATE_REG, mask, data);
1182 }
1183
1184 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
1185 const struct switch_attr *attr,
1186 struct switch_val *val)
1187 {
1188 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1189 u32 data = 0;
1190
1191 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1192 return -EINVAL;
1193
1194 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1195 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1196
1197 return 0;
1198 }
1199
1200 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
1201 const struct switch_attr *attr,
1202 struct switch_val *val)
1203 {
1204 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1205
1206 if (val->port_vlan >= RTL8366_NUM_PORTS)
1207 return -EINVAL;
1208
1209
1210 return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
1211 0, (1 << (val->port_vlan + 3)));
1212 }
1213
1214 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
1215 const struct switch_attr *attr,
1216 struct switch_val *val)
1217 {
1218 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1219 struct rtl8366_smi *smi = &rtl->smi;
1220 int i, len = 0;
1221 unsigned long long counter = 0;
1222 char *buf = rtl->buf;
1223
1224 if (val->port_vlan >= RTL8366_NUM_PORTS)
1225 return -EINVAL;
1226
1227 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1228 "Port %d MIB counters\n",
1229 val->port_vlan);
1230
1231 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
1232 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1233 "%-36s: ", rtl8366s_mib_counters[i].name);
1234 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1235 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1236 "%llu\n", counter);
1237 else
1238 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1239 "%s\n", "error");
1240 }
1241
1242 val->value.s = buf;
1243 val->len = len;
1244 return 0;
1245 }
1246
1247 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
1248 struct switch_val *val)
1249 {
1250 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1251 struct rtl8366_vlan_mc vlanmc;
1252 struct switch_port *port;
1253 int i;
1254
1255 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1256 return -EINVAL;
1257
1258 rtl8366s_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1259
1260 port = &val->value.ports[0];
1261 val->len = 0;
1262 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1263 if (!(vlanmc.member & BIT(i)))
1264 continue;
1265
1266 port->id = i;
1267 port->flags = (vlanmc.untag & BIT(i)) ?
1268 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1269 val->len++;
1270 port++;
1271 }
1272 return 0;
1273 }
1274
1275 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1276 struct switch_val *val)
1277 {
1278 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1279 struct rtl8366_vlan_mc vlanmc;
1280 struct rtl8366_vlan_4k vlan4k;
1281 struct switch_port *port;
1282 int i;
1283
1284 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1285 return -EINVAL;
1286
1287 rtl8366s_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1288 rtl8366s_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
1289
1290 vlanmc.untag = 0;
1291 vlanmc.member = 0;
1292
1293 port = &val->value.ports[0];
1294 for (i = 0; i < val->len; i++, port++) {
1295 vlanmc.member |= BIT(port->id);
1296
1297 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1298 vlanmc.untag |= BIT(port->id);
1299 }
1300
1301 vlan4k.member = vlanmc.member;
1302 vlan4k.untag = vlanmc.untag;
1303
1304 rtl8366s_set_vlan_mc(smi, val->port_vlan, &vlanmc);
1305 rtl8366s_set_vlan_4k(smi, &vlan4k);
1306 return 0;
1307 }
1308
1309 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1310 {
1311 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1312 return rtl8366s_get_vlan_port_pvid(smi, port, val);
1313 }
1314
1315 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1316 {
1317 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1318 return rtl8366s_set_vlan_port_pvid(smi, port, val);
1319 }
1320
1321 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1322 {
1323 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1324 int err;
1325
1326 err = rtl8366s_reset_chip(smi);
1327 if (err)
1328 return err;
1329
1330 return rtl8366s_reset_vlan(smi);
1331 }
1332
1333 static struct switch_attr rtl8366s_globals[] = {
1334 {
1335 .type = SWITCH_TYPE_INT,
1336 .name = "enable_vlan",
1337 .description = "Enable VLAN mode",
1338 .set = rtl8366s_sw_set_vlan_enable,
1339 .get = rtl8366s_sw_get_vlan_enable,
1340 .max = 1,
1341 .ofs = 1
1342 }, {
1343 .type = SWITCH_TYPE_INT,
1344 .name = "enable_vlan4k",
1345 .description = "Enable VLAN 4K mode",
1346 .set = rtl8366s_sw_set_vlan_enable,
1347 .get = rtl8366s_sw_get_vlan_enable,
1348 .max = 1,
1349 .ofs = 2
1350 }, {
1351 .type = SWITCH_TYPE_INT,
1352 .name = "reset_mibs",
1353 .description = "Reset all MIB counters",
1354 .set = rtl8366s_sw_reset_mibs,
1355 .get = NULL,
1356 .max = 1
1357 }, {
1358 .type = SWITCH_TYPE_INT,
1359 .name = "blinkrate",
1360 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1361 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1362 .set = rtl8366s_sw_set_blinkrate,
1363 .get = rtl8366s_sw_get_blinkrate,
1364 .max = 5
1365 },
1366 };
1367
1368 static struct switch_attr rtl8366s_port[] = {
1369 {
1370 .type = SWITCH_TYPE_STRING,
1371 .name = "link",
1372 .description = "Get port link information",
1373 .max = 1,
1374 .set = NULL,
1375 .get = rtl8366s_sw_get_port_link,
1376 }, {
1377 .type = SWITCH_TYPE_INT,
1378 .name = "reset_mib",
1379 .description = "Reset single port MIB counters",
1380 .max = 1,
1381 .set = rtl8366s_sw_reset_port_mibs,
1382 .get = NULL,
1383 }, {
1384 .type = SWITCH_TYPE_STRING,
1385 .name = "mib",
1386 .description = "Get MIB counters for port",
1387 .max = 33,
1388 .set = NULL,
1389 .get = rtl8366s_sw_get_port_mib,
1390 }, {
1391 .type = SWITCH_TYPE_INT,
1392 .name = "led",
1393 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1394 .max = 15,
1395 .set = rtl8366s_sw_set_port_led,
1396 .get = rtl8366s_sw_get_port_led,
1397 },
1398 };
1399
1400 static struct switch_attr rtl8366s_vlan[] = {
1401 {
1402 .type = SWITCH_TYPE_STRING,
1403 .name = "info",
1404 .description = "Get vlan information",
1405 .max = 1,
1406 .set = NULL,
1407 .get = rtl8366s_sw_get_vlan_info,
1408 },
1409 };
1410
1411 /* template */
1412 static struct switch_dev rtl8366_switch_dev = {
1413 .name = "RTL8366S",
1414 .cpu_port = RTL8366_PORT_NUM_CPU,
1415 .ports = RTL8366_NUM_PORTS,
1416 .vlans = RTL8366_NUM_VLANS,
1417 .attr_global = {
1418 .attr = rtl8366s_globals,
1419 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1420 },
1421 .attr_port = {
1422 .attr = rtl8366s_port,
1423 .n_attr = ARRAY_SIZE(rtl8366s_port),
1424 },
1425 .attr_vlan = {
1426 .attr = rtl8366s_vlan,
1427 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1428 },
1429
1430 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1431 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1432 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1433 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1434 .reset_switch = rtl8366s_sw_reset_switch,
1435 };
1436
1437 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1438 {
1439 struct switch_dev *dev = &rtl->dev;
1440 int err;
1441
1442 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1443 dev->priv = rtl;
1444 dev->devname = dev_name(rtl->parent);
1445
1446 err = register_switch(dev, NULL);
1447 if (err)
1448 dev_err(rtl->parent, "switch registration failed\n");
1449
1450 return err;
1451 }
1452
1453 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1454 {
1455 unregister_switch(&rtl->dev);
1456 }
1457
1458 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1459 {
1460 struct rtl8366_smi *smi = bus->priv;
1461 u32 val = 0;
1462 int err;
1463
1464 err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1465 if (err)
1466 return 0xffff;
1467
1468 return val;
1469 }
1470
1471 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1472 {
1473 struct rtl8366_smi *smi = bus->priv;
1474 u32 t;
1475 int err;
1476
1477 err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1478 /* flush write */
1479 (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1480
1481 return err;
1482 }
1483
1484 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1485 {
1486 return (bus->read == rtl8366s_mii_read &&
1487 bus->write == rtl8366s_mii_write);
1488 }
1489
1490 static int rtl8366s_setup(struct rtl8366s *rtl)
1491 {
1492 struct rtl8366_smi *smi = &rtl->smi;
1493 int ret;
1494
1495 ret = rtl8366s_reset_chip(smi);
1496 if (ret)
1497 return ret;
1498
1499 rtl8366s_debugfs_init(rtl);
1500 return 0;
1501 }
1502
1503 static int rtl8366s_detect(struct rtl8366_smi *smi)
1504 {
1505 u32 chip_id = 0;
1506 u32 chip_ver = 0;
1507 int ret;
1508
1509 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1510 if (ret) {
1511 dev_err(smi->parent, "unable to read chip id\n");
1512 return ret;
1513 }
1514
1515 switch (chip_id) {
1516 case RTL8366S_CHIP_ID_8366:
1517 break;
1518 default:
1519 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1520 return -ENODEV;
1521 }
1522
1523 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1524 &chip_ver);
1525 if (ret) {
1526 dev_err(smi->parent, "unable to read chip version\n");
1527 return ret;
1528 }
1529
1530 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1531 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1532
1533 return 0;
1534 }
1535
1536 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1537 .detect = rtl8366s_detect,
1538 .mii_read = rtl8366s_mii_read,
1539 .mii_write = rtl8366s_mii_write,
1540 };
1541
1542 static int __init rtl8366s_probe(struct platform_device *pdev)
1543 {
1544 static int rtl8366_smi_version_printed;
1545 struct rtl8366s_platform_data *pdata;
1546 struct rtl8366s *rtl;
1547 struct rtl8366_smi *smi;
1548 int err;
1549
1550 if (!rtl8366_smi_version_printed++)
1551 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1552 " version " RTL8366S_DRIVER_VER"\n");
1553
1554 pdata = pdev->dev.platform_data;
1555 if (!pdata) {
1556 dev_err(&pdev->dev, "no platform data specified\n");
1557 err = -EINVAL;
1558 goto err_out;
1559 }
1560
1561 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1562 if (!rtl) {
1563 dev_err(&pdev->dev, "no memory for private data\n");
1564 err = -ENOMEM;
1565 goto err_out;
1566 }
1567
1568 rtl->parent = &pdev->dev;
1569
1570 smi = &rtl->smi;
1571 smi->parent = &pdev->dev;
1572 smi->gpio_sda = pdata->gpio_sda;
1573 smi->gpio_sck = pdata->gpio_sck;
1574 smi->ops = &rtl8366s_smi_ops;
1575
1576 err = rtl8366_smi_init(smi);
1577 if (err)
1578 goto err_free_rtl;
1579
1580 platform_set_drvdata(pdev, rtl);
1581
1582 err = rtl8366s_setup(rtl);
1583 if (err)
1584 goto err_clear_drvdata;
1585
1586 err = rtl8366s_switch_init(rtl);
1587 if (err)
1588 goto err_clear_drvdata;
1589
1590 return 0;
1591
1592 err_clear_drvdata:
1593 platform_set_drvdata(pdev, NULL);
1594 rtl8366_smi_cleanup(smi);
1595 err_free_rtl:
1596 kfree(rtl);
1597 err_out:
1598 return err;
1599 }
1600
1601 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1602 {
1603 if (!rtl8366s_mii_bus_match(phydev->bus))
1604 return -EINVAL;
1605
1606 return 0;
1607 }
1608
1609 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1610 {
1611 return 0;
1612 }
1613
1614 static struct phy_driver rtl8366s_phy_driver = {
1615 .phy_id = 0x001cc960,
1616 .name = "Realtek RTL8366S",
1617 .phy_id_mask = 0x1ffffff0,
1618 .features = PHY_GBIT_FEATURES,
1619 .config_aneg = rtl8366s_phy_config_aneg,
1620 .config_init = rtl8366s_phy_config_init,
1621 .read_status = genphy_read_status,
1622 .driver = {
1623 .owner = THIS_MODULE,
1624 },
1625 };
1626
1627 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1628 {
1629 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1630
1631 if (rtl) {
1632 rtl8366s_switch_cleanup(rtl);
1633 rtl8366s_debugfs_remove(rtl);
1634 platform_set_drvdata(pdev, NULL);
1635 rtl8366_smi_cleanup(&rtl->smi);
1636 kfree(rtl);
1637 }
1638
1639 return 0;
1640 }
1641
1642 static struct platform_driver rtl8366s_driver = {
1643 .driver = {
1644 .name = RTL8366S_DRIVER_NAME,
1645 .owner = THIS_MODULE,
1646 },
1647 .probe = rtl8366s_probe,
1648 .remove = __devexit_p(rtl8366s_remove),
1649 };
1650
1651 static int __init rtl8366s_module_init(void)
1652 {
1653 int ret;
1654 ret = platform_driver_register(&rtl8366s_driver);
1655 if (ret)
1656 return ret;
1657
1658 ret = phy_driver_register(&rtl8366s_phy_driver);
1659 if (ret)
1660 goto err_platform_unregister;
1661
1662 return 0;
1663
1664 err_platform_unregister:
1665 platform_driver_unregister(&rtl8366s_driver);
1666 return ret;
1667 }
1668 module_init(rtl8366s_module_init);
1669
1670 static void __exit rtl8366s_module_exit(void)
1671 {
1672 phy_driver_unregister(&rtl8366s_phy_driver);
1673 platform_driver_unregister(&rtl8366s_driver);
1674 }
1675 module_exit(rtl8366s_module_exit);
1676
1677 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1678 MODULE_VERSION(RTL8366S_DRIVER_VER);
1679 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1680 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1681 MODULE_LICENSE("GPL v2");
1682 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
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