target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfStaticInit.h

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  64
  65
  66 #ifndef __INCmvDramIfStaticInith
  67 #define __INCmvDramIfStaticInith
  68
  69 #ifdef MV_STATIC_DRAM_ON_BOARD
  70 #define STATIC_DRAM_BANK_1
  71 #undef  STATIC_DRAM_BANK_2
  72 #undef  STATIC_DRAM_BANK_3
  73 #undef  STATIC_DRAM_BANK_4
  74
  75
  76 #ifdef MV_DIMM_TS256MLQ72V5U
  77 #define STATIC_DRAM_BANK_2
  78 #define STATIC_DRAM_BANK_3
  79 #undef  STATIC_DRAM_BANK_4
  80
  81 #define STATIC_SDRAM_CONFIG_REG             0x4724481A  /* offset 0x1400 - DMA reg-0xf1000814 */
  82 #define STATIC_SDRAM_DUNIT_CTRL_REG         0x37707450  /* offset 0x1404 - DMA reg-0xf100081c */
  83 #define STATIC_SDRAM_TIMING_CTRL_LOW_REG    0x11A13330  /* offset 0x1408 - DMA reg-0xf1000824 */
  84 #define STATIC_SDRAM_TIMING_CTRL_HIGH_REG   0x00000601  /* offset 0x140c - DMA reg-0xf1000828 */
  85 #define STATIC_SDRAM_ADDR_CTRL_REG          0x00001CB2  /* offset 0x1410 - DMA reg-0xf1000820 */
  86 #define STATIC_SDRAM_MODE_REG               0x00000642  /* offset 0x141c - DMA reg-0xf1000818 */
  87 #define STATIC_SDRAM_ODT_CTRL_LOW           0x030C030C /*   0x1494  */
  88 #define STATIC_SDRAM_ODT_CTRL_HI            0x00000000 /*   0x1498  */
  89 #define STATIC_SDRAM_DUNIT_ODT_CTRL         0x0000740F /*   0x149c  */
  90 #define STATIC_SDRAM_EXT_MODE               0x00000404 /*   0x1420  */
  91 #define STATIC_SDRAM_DDR2_TIMING_LO         0x00074410 /*   0x1428  */
  92 #define STATIC_SDRAM_DDR2_TIMING_HI         0x00007441 /*   0x147C  */
  93
  94 #define STATIC_SDRAM_RANK0_SIZE_DIMM0       0x3FFF /* size bank0 dimm0   - DMA reg-0xf1000810 */
  95 #define STATIC_SDRAM_RANK1_SIZE_DIMM0       0x3FFF /* size bank1 dimm0   */
  96 #define STATIC_SDRAM_RANK0_SIZE_DIMM1       0x3FFF /* size bank0 dimm1   */
  97 #define STATIC_SDRAM_RANK1_SIZE_DIMM1       0x0    /* size bank1 dimm1   */
  98
  99 #endif /* TS256MLQ72V5U */
 100
 101
 102 #ifdef MV_MT9VDDT3272AG
 103 /* one DIMM 256M  */
 104 #define STATIC_SDRAM_CONFIG_REG             0x5820040d  /* offset 0x1400 - DMA reg-0xf1000814 */
 105 #define STATIC_SDRAM_DUNIT_CTRL_REG         0xC4000540  /* offset 0x1404 - DMA reg-0xf100081c */
 106 #define STATIC_SDRAM_TIMING_CTRL_LOW_REG    0x01602220  /* offset 0x1408 - DMA reg-0xf1000824 */
 107 #define STATIC_SDRAM_TIMING_CTRL_HIGH_REG   0x0000000b  /* offset 0x140c - DMA reg-0xf1000828 */
 108 #define STATIC_SDRAM_ADDR_CTRL_REG          0x00000012  /* offset 0x1410 - DMA reg-0xf1000820 */
 109 #define STATIC_SDRAM_MODE_REG               0x00000062  /* offset 0x141c - DMA reg-0xf1000818 */
 110 #define STATIC_SDRAM_RANK0_SIZE_DIMM0       0x0fff /* size bank0 dimm0   - DMA reg-0xf1000810 */
 111 #define STATIC_SDRAM_RANK0_SIZE_DIMM1       0x0    /* size bank0 dimm1   */
 112
 113 #endif /* MV_MT9VDDT3272AG */
 114
 115
 116
 117 #ifdef MV_D27RB12P
 118 /*
 119 Two DIMM 512M + ECC enabled, Registered DIMM  CAS Latency 2.5
 120 */
 121
 122 #define STATIC_SDRAM_CONFIG_REG             0x6826081E  /* offset 0x1400 - DMA reg-0xf1000814 */
 123 #define STATIC_SDRAM_DUNIT_CTRL_REG         0xC5000540  /* offset 0x1404 - DMA reg-0xf100081c */
 124 #define STATIC_SDRAM_TIMING_CTRL_LOW_REG    0x01501220  /* offset 0x1408 - DMA reg-0xf1000824 */
 125 #define STATIC_SDRAM_TIMING_CTRL_HIGH_REG   0x00000009  /* offset 0x140c - DMA reg-0xf1000828 */
 126 #define STATIC_SDRAM_ADDR_CTRL_REG          0x00000012  /* offset 0x1410 - DMA reg-0xf1000820 */
 127 #define STATIC_SDRAM_MODE_REG               0x00000062  /* offset 0x141c - DMA reg-0xf1000818 */
 128 #define STATIC_SDRAM_RANK0_SIZE_DIMM0       0x0FFF /* size bank0 dimm0   - DMA reg-0xf1000810 */
 129 #define STATIC_SDRAM_RANK0_SIZE_DIMM1       0x0FFF    /* size bank0 dimm1   */
 130
 131 #define STATIC_DRAM_BANK_2
 132
 133 #define STATIC_DRAM_BANK_3
 134 #define STATIC_DRAM_BANK_4
 135
 136 #endif /*  mv_D27RB12P  */
 137
 138 #ifdef RD_MV645XX
 139
 140 #define STATIC_MEM_TYPE                         MEM_TYPE_DDR2
 141 #define STATIC_DIMM_INFO_BANK0_SIZE             256
 142 /* DDR2 boards 256 MB*/
 143
 144 #define STATIC_SDRAM_RANK0_SIZE_DIMM0           0x00000fff /* size bank0 dimm0   - DMA reg-0xf1000810 */
 145 #define STATIC_SDRAM_CONFIG_REG                 0x07190618
 146 #define STATIC_SDRAM_MODE_REG                   0x00000432
 147 #define STATIC_SDRAM_DUNIT_CTRL_REG             0xf4a03440
 148 #define STATIC_SDRAM_ADDR_CTRL_REG              0x00000022
 149 #define STATIC_SDRAM_TIMING_CTRL_LOW_REG        0x11712220
 150 #define STATIC_SDRAM_TIMING_CTRL_HIGH_REG       0x00000504
 151 #define STATIC_SDRAM_ODT_CTRL_LOW               0x84210000
 152 #define STATIC_SDRAM_ODT_CTRL_HI                0x00000000
 153 #define STATIC_SDRAM_DUNIT_ODT_CTRL             0x0000780f
 154 #define STATIC_SDRAM_EXT_MODE                   0x00000440
 155 #define STATIC_SDRAM_DDR2_TIMING_LO             0x00063300
 156 #define STATIC_SDRAM_DDR2_TIMING_HI             0x00006330
 157 #endif /* RD_MV645XX */
 158
 159 #if MV_DIMM_M3783354CZ3_CE6
 160
 161 #define STATIC_SDRAM_RANK0_SIZE_DIMM0           0x00000FFF /* 0x2010 size bank0 dimm0   - DMA reg-0xf1000810 */
 162 #define STATIC_SDRAM_CONFIG_REG                 0x07190618 /*   0x1400  */
 163 #define STATIC_SDRAM_MODE_REG                   0x00000432 /*   0x141c  */
 164 #define STATIC_SDRAM_DUNIT_CTRL_REG             0xf4a03440 /*   0x1404  */
 165 #define STATIC_SDRAM_ADDR_CTRL_REG              0x00000022 /*   0x1410  */
 166 #define STATIC_SDRAM_TIMING_CTRL_LOW_REG        0x11712220 /*   0x1408  */
 167 #define STATIC_SDRAM_TIMING_CTRL_HIGH_REG       0x00000504 /*   0x140c  */
 168 #define STATIC_SDRAM_ODT_CTRL_LOW               0x84210000 /*   0x1494  */
 169 #define STATIC_SDRAM_ODT_CTRL_HI                0x00000000 /*   0x1498  */
 170 #define STATIC_SDRAM_DUNIT_ODT_CTRL             0x0000780f /*   0x149c  */
 171 #define STATIC_SDRAM_EXT_MODE                   0x00000440 /*   0x1420  */
 172 #define STATIC_SDRAM_DDR2_TIMING_LO             0x00063300 /*   0x1428  */
 173 #define STATIC_SDRAM_DDR2_TIMING_HI             0x00006330 /*   0x147C  */
 174
 175 #endif /* MV_DIMM_M3783354CZ3_CE6 */
 176
 177 #endif /* MV_STATIC_DRAM_ON_BOARD */
 178 #endif /* __INCmvDramIfStaticInith */
 179