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[openwrt/svn-archive/archive.git] / target / linux / generic / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366rb.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
28 #define RTL8366RB_DRIVER_VER "0.2.2"
29
30 #define RTL8366RB_PHY_NO_MAX 4
31 #define RTL8366RB_PHY_PAGE_MAX 7
32 #define RTL8366RB_PHY_ADDR_MAX 31
33
34 #define RTL8366RB_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366RB_CHIP_CTRL_VLAN (1 << 13)
36 #define RTL8366RB_CHIP_CTRL_VLAN_4KTB (1 << 14)
37
38 /* Switch Global Configuration register */
39 #define RTL8366RB_SGCR 0x0000
40 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
41 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
42 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
43 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
44 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
45 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
46 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
47
48 /* Port Enable Control register */
49 #define RTL8366RB_PECR 0x0001
50
51 /* Switch Security Control registers */
52 #define RTL8366RB_SSCR0 0x0002
53 #define RTL8366RB_SSCR1 0x0003
54 #define RTL8366RB_SSCR2 0x0004
55 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
56
57 #define RTL8366RB_RESET_CTRL_REG 0x0100
58 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
59 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
60
61 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
62 #define RTL8366RB_CHIP_VERSION_MASK 0xf
63 #define RTL8366RB_CHIP_ID_REG 0x0509
64 #define RTL8366RB_CHIP_ID_8366 0x5937
65
66 /* PHY registers control */
67 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
68 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
69
70 #define RTL8366RB_PHY_CTRL_READ 1
71 #define RTL8366RB_PHY_CTRL_WRITE 0
72
73 #define RTL8366RB_PHY_REG_MASK 0x1f
74 #define RTL8366RB_PHY_PAGE_OFFSET 5
75 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
76 #define RTL8366RB_PHY_NO_OFFSET 9
77 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
78
79 /* LED control registers */
80 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
81 #define RTL8366RB_LED_BLINKRATE_BIT 0
82 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
83
84 #define RTL8366RB_LED_CTRL_REG 0x0431
85 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
86 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
87
88 #define RTL8366RB_MIB_COUNT 33
89 #define RTL8366RB_GLOBAL_MIB_COUNT 1
90 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
91 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
92 #define RTL8366RB_MIB_CTRL_REG 0x13F0
93 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
94 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
95 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
96 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
97 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
98
99 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
100 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
101 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
102 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
103 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
104
105
106 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
107 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
108
109
110 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
111 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
112 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
113
114 #define RTL8366RB_VLAN_MEMCONF_BASE 0x0020
115
116
117 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
118 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
119 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
120 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
121 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
122 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
123 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
124
125
126 #define RTL8366RB_PORT_NUM_CPU 5
127 #define RTL8366RB_NUM_PORTS 6
128 #define RTL8366RB_NUM_VLANS 16
129 #define RTL8366RB_NUM_LEDGROUPS 4
130 #define RTL8366RB_NUM_VIDS 4096
131 #define RTL8366RB_PRIORITYMAX 7
132 #define RTL8366RB_FIDMAX 7
133
134
135 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
136 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
137 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
138 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
139 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
140
141 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
142
143 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
144 RTL8366RB_PORT_2 | \
145 RTL8366RB_PORT_3 | \
146 RTL8366RB_PORT_4 | \
147 RTL8366RB_PORT_5 | \
148 RTL8366RB_PORT_CPU)
149
150 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
151 RTL8366RB_PORT_2 | \
152 RTL8366RB_PORT_3 | \
153 RTL8366RB_PORT_4 | \
154 RTL8366RB_PORT_5)
155
156 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
157 RTL8366RB_PORT_2 | \
158 RTL8366RB_PORT_3 | \
159 RTL8366RB_PORT_4)
160
161 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
162
163 struct rtl8366rb {
164 struct device *parent;
165 struct rtl8366_smi smi;
166 struct switch_dev dev;
167 char buf[4096];
168 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
169 struct dentry *debugfs_root;
170 #endif
171 };
172
173 struct rtl8366rb_vlan_mc {
174 u16 reserved2:1;
175 u16 priority:3;
176 u16 vid:12;
177 u16 untag:8;
178 u16 member:8;
179 u16 stag_mbr:8;
180 u16 stag_idx:3;
181 u16 reserved1:2;
182 u16 fid:3;
183 };
184
185 struct rtl8366rb_vlan_4k {
186 u16 reserved1:4;
187 u16 vid:12;
188 u16 untag:8;
189 u16 member:8;
190 u16 reserved2:13;
191 u16 fid:3;
192 };
193
194 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
195 u16 gl_dbg_reg;
196 #endif
197
198 struct mib_counter {
199 unsigned offset;
200 unsigned length;
201 const char *name;
202 };
203
204 static struct mib_counter rtl8366rb_mib_counters[RTL8366RB_MIB_COUNT] = {
205 { 0, 4, "IfInOctets" },
206 { 4, 4, "EtherStatsOctets" },
207 { 8, 2, "EtherStatsUnderSizePkts" },
208 { 10, 2, "EtherFragments" },
209 { 12, 2, "EtherStatsPkts64Octets" },
210 { 14, 2, "EtherStatsPkts65to127Octets" },
211 { 16, 2, "EtherStatsPkts128to255Octets" },
212 { 18, 2, "EtherStatsPkts256to511Octets" },
213 { 20, 2, "EtherStatsPkts512to1023Octets" },
214 { 22, 2, "EtherStatsPkts1024to1518Octets" },
215 { 24, 2, "EtherOversizeStats" },
216 { 26, 2, "EtherStatsJabbers" },
217 { 28, 2, "IfInUcastPkts" },
218 { 30, 2, "EtherStatsMulticastPkts" },
219 { 32, 2, "EtherStatsBroadcastPkts" },
220 { 34, 2, "EtherStatsDropEvents" },
221 { 36, 2, "Dot3StatsFCSErrors" },
222 { 38, 2, "Dot3StatsSymbolErrors" },
223 { 40, 2, "Dot3InPauseFrames" },
224 { 42, 2, "Dot3ControlInUnknownOpcodes" },
225 { 44, 4, "IfOutOctets" },
226 { 48, 2, "Dot3StatsSingleCollisionFrames" },
227 { 50, 2, "Dot3StatMultipleCollisionFrames" },
228 { 52, 2, "Dot3sDeferredTransmissions" },
229 { 54, 2, "Dot3StatsLateCollisions" },
230 { 56, 2, "EtherStatsCollisions" },
231 { 58, 2, "Dot3StatsExcessiveCollisions" },
232 { 60, 2, "Dot3OutPauseFrames" },
233 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
234 { 64, 2, "Dot1dTpPortInDiscards" },
235 { 66, 2, "IfOutUcastPkts" },
236 { 68, 2, "IfOutMulticastPkts" },
237 { 70, 2, "IfOutBroadcastPkts" },
238 };
239
240 #define REG_WR(_smi, _reg, _val) \
241 do { \
242 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
243 if (err) \
244 return err; \
245 } while (0)
246
247 #define REG_RMW(_smi, _reg, _mask, _val) \
248 do { \
249 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
250 if (err) \
251 return err; \
252 } while (0)
253
254 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
255 {
256 return container_of(smi, struct rtl8366rb, smi);
257 }
258
259 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
260 {
261 return container_of(sw, struct rtl8366rb, dev);
262 }
263
264 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
265 {
266 struct rtl8366rb *rtl = sw_to_rtl8366rb(sw);
267 return &rtl->smi;
268 }
269
270 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
271 {
272 int timeout = 10;
273 u32 data;
274
275 rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
276 RTL8366RB_CHIP_CTRL_RESET_HW);
277 do {
278 msleep(1);
279 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
280 return -EIO;
281
282 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
283 break;
284 } while (--timeout);
285
286 if (!timeout) {
287 printk("Timeout waiting for the switch to reset\n");
288 return -EIO;
289 }
290
291 return 0;
292 }
293
294 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
295 {
296 int err;
297
298 /* set maximum packet length to 1536 bytes */
299 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
300 RTL8366RB_SGCR_MAX_LENGTH_1536);
301
302 /* enable all ports */
303 REG_WR(smi, RTL8366RB_PECR, 0);
304
305 /* disable learning for all ports */
306 REG_WR(smi, RTL8366RB_SSCR0, RTL8366RB_PORT_ALL);
307
308 /* disable auto ageing for all ports */
309 REG_WR(smi, RTL8366RB_SSCR1, RTL8366RB_PORT_ALL);
310
311 /* don't drop packets whose DA has not been learned */
312 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
313
314 return 0;
315 }
316
317 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
318 u32 phy_no, u32 page, u32 addr, u32 *data)
319 {
320 u32 reg;
321 int ret;
322
323 if (phy_no > RTL8366RB_PHY_NO_MAX)
324 return -EINVAL;
325
326 if (page > RTL8366RB_PHY_PAGE_MAX)
327 return -EINVAL;
328
329 if (addr > RTL8366RB_PHY_ADDR_MAX)
330 return -EINVAL;
331
332 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
333 RTL8366RB_PHY_CTRL_READ);
334 if (ret)
335 return ret;
336
337 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
338 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
339 (addr & RTL8366RB_PHY_REG_MASK);
340
341 ret = rtl8366_smi_write_reg(smi, reg, 0);
342 if (ret)
343 return ret;
344
345 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
346 if (ret)
347 return ret;
348
349 return 0;
350 }
351
352 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
353 u32 phy_no, u32 page, u32 addr, u32 data)
354 {
355 u32 reg;
356 int ret;
357
358 if (phy_no > RTL8366RB_PHY_NO_MAX)
359 return -EINVAL;
360
361 if (page > RTL8366RB_PHY_PAGE_MAX)
362 return -EINVAL;
363
364 if (addr > RTL8366RB_PHY_ADDR_MAX)
365 return -EINVAL;
366
367 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
368 RTL8366RB_PHY_CTRL_WRITE);
369 if (ret)
370 return ret;
371
372 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
373 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
374 (addr & RTL8366RB_PHY_REG_MASK);
375
376 ret = rtl8366_smi_write_reg(smi, reg, data);
377 if (ret)
378 return ret;
379
380 return 0;
381 }
382
383 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
384 int port, unsigned long long *val)
385 {
386 int i;
387 int err;
388 u32 addr, data;
389 u64 mibvalue;
390
391 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
392 return -EINVAL;
393
394 addr = RTL8366RB_MIB_COUNTER_BASE +
395 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
396 rtl8366rb_mib_counters[counter].offset;
397
398 /*
399 * Writing access counter address first
400 * then ASIC will prepare 64bits counter wait for being retrived
401 */
402 data = 0; /* writing data will be discard by ASIC */
403 err = rtl8366_smi_write_reg(smi, addr, data);
404 if (err)
405 return err;
406
407 /* read MIB control register */
408 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
409 if (err)
410 return err;
411
412 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
413 return -EBUSY;
414
415 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
416 return -EIO;
417
418 mibvalue = 0;
419 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
420 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
421 if (err)
422 return err;
423
424 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
425 }
426
427 *val = mibvalue;
428 return 0;
429 }
430
431 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
432 struct rtl8366_vlan_4k *vlan4k)
433 {
434 struct rtl8366rb_vlan_4k vlan4k_priv;
435 int err;
436 u32 data;
437 u16 *tableaddr;
438
439 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
440 vlan4k_priv.vid = vid;
441
442 if (vid >= RTL8366RB_NUM_VIDS)
443 return -EINVAL;
444
445 tableaddr = (u16 *)&vlan4k_priv;
446
447 /* write VID */
448 data = *tableaddr;
449 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
450 if (err)
451 return err;
452
453 /* write table access control word */
454 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
455 RTL8366RB_TABLE_VLAN_READ_CTRL);
456 if (err)
457 return err;
458
459 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE, &data);
460 if (err)
461 return err;
462
463 *tableaddr = data;
464 tableaddr++;
465
466 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 1,
467 &data);
468 if (err)
469 return err;
470
471 *tableaddr = data;
472 tableaddr++;
473
474 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 2,
475 &data);
476 if (err)
477 return err;
478 *tableaddr = data;
479
480 vlan4k->vid = vid;
481 vlan4k->untag = vlan4k_priv.untag;
482 vlan4k->member = vlan4k_priv.member;
483 vlan4k->fid = vlan4k_priv.fid;
484
485 return 0;
486 }
487
488 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
489 const struct rtl8366_vlan_4k *vlan4k)
490 {
491 struct rtl8366rb_vlan_4k vlan4k_priv;
492 int err;
493 u32 data;
494 u16 *tableaddr;
495
496 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
497 vlan4k->member > RTL8366RB_PORT_ALL ||
498 vlan4k->untag > RTL8366RB_PORT_ALL ||
499 vlan4k->fid > RTL8366RB_FIDMAX)
500 return -EINVAL;
501
502 vlan4k_priv.vid = vlan4k->vid;
503 vlan4k_priv.untag = vlan4k->untag;
504 vlan4k_priv.member = vlan4k->member;
505 vlan4k_priv.fid = vlan4k->fid;
506
507 tableaddr = (u16 *)&vlan4k_priv;
508
509 data = *tableaddr;
510
511 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
512 if (err)
513 return err;
514
515 tableaddr++;
516
517 data = *tableaddr;
518
519 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 1,
520 data);
521 if (err)
522 return err;
523
524 tableaddr++;
525
526 data = *tableaddr;
527
528 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 2,
529 data);
530 if (err)
531 return err;
532
533 /* write table access control word */
534 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
535 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
536
537 return err;
538 }
539
540 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
541 struct rtl8366_vlan_mc *vlanmc)
542 {
543 struct rtl8366rb_vlan_mc vlanmc_priv;
544 int err;
545 u32 addr;
546 u32 data;
547 u16 *tableaddr;
548
549 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
550
551 if (index >= RTL8366RB_NUM_VLANS)
552 return -EINVAL;
553
554 tableaddr = (u16 *)&vlanmc_priv;
555
556 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
557 err = rtl8366_smi_read_reg(smi, addr, &data);
558 if (err)
559 return err;
560
561 *tableaddr = data;
562 tableaddr++;
563
564 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
565 err = rtl8366_smi_read_reg(smi, addr, &data);
566 if (err)
567 return err;
568
569 *tableaddr = data;
570 tableaddr++;
571
572 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
573 err = rtl8366_smi_read_reg(smi, addr, &data);
574 if (err)
575 return err;
576
577 *tableaddr = data;
578
579 vlanmc->vid = vlanmc_priv.vid;
580 vlanmc->priority = vlanmc_priv.priority;
581 vlanmc->untag = vlanmc_priv.untag;
582 vlanmc->member = vlanmc_priv.member;
583 vlanmc->fid = vlanmc_priv.fid;
584
585 return 0;
586 }
587
588 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
589 const struct rtl8366_vlan_mc *vlanmc)
590 {
591 struct rtl8366rb_vlan_mc vlanmc_priv;
592 int err;
593 u32 addr;
594 u32 data;
595 u16 *tableaddr;
596
597 if (index >= RTL8366RB_NUM_VLANS ||
598 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
599 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
600 vlanmc->member > RTL8366RB_PORT_ALL ||
601 vlanmc->untag > RTL8366RB_PORT_ALL ||
602 vlanmc->fid > RTL8366RB_FIDMAX)
603 return -EINVAL;
604
605 vlanmc_priv.vid = vlanmc->vid;
606 vlanmc_priv.priority = vlanmc->priority;
607 vlanmc_priv.untag = vlanmc->untag;
608 vlanmc_priv.member = vlanmc->member;
609 vlanmc_priv.stag_mbr = 0;
610 vlanmc_priv.stag_idx = 0;
611 vlanmc_priv.fid = vlanmc->fid;
612
613 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
614
615 tableaddr = (u16 *)&vlanmc_priv;
616 data = *tableaddr;
617
618 err = rtl8366_smi_write_reg(smi, addr, data);
619 if (err)
620 return err;
621
622 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
623
624 tableaddr++;
625 data = *tableaddr;
626
627 err = rtl8366_smi_write_reg(smi, addr, data);
628 if (err)
629 return err;
630
631 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
632
633 tableaddr++;
634 data = *tableaddr;
635
636 err = rtl8366_smi_write_reg(smi, addr, data);
637 if (err)
638 return err;
639 return 0;
640 }
641
642 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
643 {
644 u32 data;
645 int err;
646
647 if (port >= RTL8366RB_NUM_PORTS)
648 return -EINVAL;
649
650 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
651 &data);
652 if (err)
653 return err;
654
655 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
656 RTL8366RB_PORT_VLAN_CTRL_MASK;
657
658 return 0;
659
660 }
661
662 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
663 {
664 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
665 return -EINVAL;
666
667 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
668 RTL8366RB_PORT_VLAN_CTRL_MASK <<
669 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
670 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
671 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
672 }
673
674 static int rtl8366rb_set_vlan(struct rtl8366_smi *smi, int vid, u32 member,
675 u32 untag, u32 fid)
676 {
677 struct rtl8366_vlan_4k vlan4k;
678 int err;
679 int i;
680
681 /* Update the 4K table */
682 err = rtl8366rb_get_vlan_4k(smi, vid, &vlan4k);
683 if (err)
684 return err;
685
686 vlan4k.member = member;
687 vlan4k.untag = untag;
688 vlan4k.fid = fid;
689 err = rtl8366rb_set_vlan_4k(smi, &vlan4k);
690 if (err)
691 return err;
692
693 /* Try to find an existing MC entry for this VID */
694 for (i = 0; i < RTL8366RB_NUM_VLANS; i++) {
695 struct rtl8366_vlan_mc vlanmc;
696
697 err = rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
698 if (err)
699 return err;
700
701 if (vid == vlanmc.vid) {
702 /* update the MC entry */
703 vlanmc.member = member;
704 vlanmc.untag = untag;
705 vlanmc.fid = fid;
706
707 err = rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
708 break;
709 }
710 }
711
712 return err;
713 }
714
715 static int rtl8366rb_get_pvid(struct rtl8366_smi *smi, int port, int *val)
716 {
717 struct rtl8366_vlan_mc vlanmc;
718 int err;
719 int index;
720
721 err = rtl8366rb_get_mc_index(smi, port, &index);
722 if (err)
723 return err;
724
725 err = rtl8366rb_get_vlan_mc(smi, index, &vlanmc);
726 if (err)
727 return err;
728
729 *val = vlanmc.vid;
730 return 0;
731 }
732
733 static int rtl8366rb_mc_is_used(struct rtl8366_smi *smi, int mc_index,
734 int *used)
735 {
736 int err;
737 int i;
738
739 *used = 0;
740 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
741 int index = 0;
742
743 err = rtl8366rb_get_mc_index(smi, i, &index);
744 if (err)
745 return err;
746
747 if (mc_index == index) {
748 *used = 1;
749 break;
750 }
751 }
752
753 return 0;
754 }
755
756 static int rtl8366rb_set_pvid(struct rtl8366_smi *smi, unsigned port,
757 unsigned vid)
758 {
759 struct rtl8366_vlan_mc vlanmc;
760 struct rtl8366_vlan_4k vlan4k;
761 int err;
762 int i;
763
764 /* Try to find an existing MC entry for this VID */
765 for (i = 0; i < RTL8366RB_NUM_VLANS; i++) {
766 err = rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
767 if (err)
768 return err;
769
770 if (vid == vlanmc.vid) {
771 err = rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
772 if (err)
773 return err;
774
775 err = rtl8366rb_set_mc_index(smi, port, i);
776 return err;
777 }
778 }
779
780 /* We have no MC entry for this VID, try to find an empty one */
781 for (i = 0; i < RTL8366RB_NUM_VLANS; i++) {
782 err = rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
783 if (err)
784 return err;
785
786 if (vlanmc.vid == 0 && vlanmc.member == 0) {
787 /* Update the entry from the 4K table */
788 err = rtl8366rb_get_vlan_4k(smi, vid, &vlan4k);
789 if (err)
790 return err;
791
792 vlanmc.vid = vid;
793 vlanmc.member = vlan4k.member;
794 vlanmc.untag = vlan4k.untag;
795 vlanmc.fid = vlan4k.fid;
796 err = rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
797 if (err)
798 return err;
799
800 err = rtl8366rb_set_mc_index(smi, port, i);
801 return err;
802 }
803 }
804
805 /* MC table is full, try to find an unused entry and replace it */
806 for (i = 0; i < RTL8366RB_NUM_VLANS; i++) {
807 int used;
808
809 err = rtl8366rb_mc_is_used(smi, i, &used);
810 if (err)
811 return err;
812
813 if (!used) {
814 /* Update the entry from the 4K table */
815 err = rtl8366rb_get_vlan_4k(smi, vid, &vlan4k);
816 if (err)
817 return err;
818
819 vlanmc.vid = vid;
820 vlanmc.member = vlan4k.member;
821 vlanmc.untag = vlan4k.untag;
822 vlanmc.fid = vlan4k.fid;
823 err = rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
824 if (err)
825 return err;
826
827 err = rtl8366rb_set_mc_index(smi, port, i);
828 return err;
829 }
830 }
831
832 dev_err(smi->parent,
833 "all VLAN member configurations are in use\n");
834
835 return -ENOSPC;
836 }
837
838 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
839 {
840 return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
841 RTL8366RB_CHIP_CTRL_VLAN,
842 (enable) ? RTL8366RB_CHIP_CTRL_VLAN : 0);
843 }
844
845 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
846 {
847 return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
848 RTL8366RB_CHIP_CTRL_VLAN_4KTB,
849 (enable) ? RTL8366RB_CHIP_CTRL_VLAN_4KTB : 0);
850 }
851
852 static int rtl8366rb_reset_vlan(struct rtl8366_smi *smi)
853 {
854 struct rtl8366_vlan_mc vlanmc;
855 int err;
856 int i;
857
858 /* clear VLAN member configurations */
859 vlanmc.vid = 0;
860 vlanmc.priority = 0;
861 vlanmc.member = 0;
862 vlanmc.untag = 0;
863 vlanmc.fid = 0;
864 for (i = 0; i < RTL8366RB_NUM_VLANS; i++) {
865 err = rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
866 if (err)
867 return err;
868 }
869
870 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
871 if (i == RTL8366RB_PORT_CPU)
872 continue;
873
874 err = rtl8366rb_set_vlan(smi, (i + 1),
875 (1 << i) | RTL8366RB_PORT_CPU,
876 (1 << i) | RTL8366RB_PORT_CPU,
877 0);
878 if (err)
879 return err;
880
881 err = rtl8366rb_set_pvid(smi, i, (i + 1));
882 if (err)
883 return err;
884 }
885
886 return 0;
887 }
888
889 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
890 static int rtl8366rb_debugfs_open(struct inode *inode, struct file *file)
891 {
892 file->private_data = inode->i_private;
893 return 0;
894 }
895
896 static ssize_t rtl8366rb_read_debugfs_mibs(struct file *file,
897 char __user *user_buf,
898 size_t count, loff_t *ppos)
899 {
900 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
901 struct rtl8366_smi *smi = &rtl->smi;
902 int i, j, len = 0;
903 char *buf = rtl->buf;
904
905 len += snprintf(buf + len, sizeof(rtl->buf) - len,
906 "%-36s %12s %12s %12s %12s %12s %12s\n",
907 "Counter",
908 "Port 0", "Port 1", "Port 2",
909 "Port 3", "Port 4", "Port 5");
910
911 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
912 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%-36s ",
913 rtl8366rb_mib_counters[i].name);
914 for (j = 0; j < RTL8366RB_NUM_PORTS; ++j) {
915 unsigned long long counter = 0;
916
917 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
918 len += snprintf(buf + len,
919 sizeof(rtl->buf) - len,
920 "%12llu ", counter);
921 else
922 len += snprintf(buf + len,
923 sizeof(rtl->buf) - len,
924 "%12s ", "error");
925 }
926 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
927 }
928
929 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
930 }
931
932 static ssize_t rtl8366rb_read_debugfs_vlan_mc(struct file *file,
933 char __user *user_buf,
934 size_t count, loff_t *ppos)
935 {
936 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
937 struct rtl8366_smi *smi = &rtl->smi;
938 int i, len = 0;
939 char *buf = rtl->buf;
940
941 len += snprintf(buf + len, sizeof(rtl->buf) - len,
942 "%2s %6s %4s %6s %6s %3s\n",
943 "id", "vid","prio", "member", "untag", "fid");
944
945 for (i = 0; i < RTL8366RB_NUM_VLANS; ++i) {
946 struct rtl8366_vlan_mc vlanmc;
947
948 rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
949
950 len += snprintf(buf + len, sizeof(rtl->buf) - len,
951 "%2d %6d %4d 0x%04x 0x%04x %3d\n",
952 i, vlanmc.vid, vlanmc.priority,
953 vlanmc.member, vlanmc.untag, vlanmc.fid);
954 }
955
956 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
957 }
958
959 static ssize_t rtl8366rb_read_debugfs_reg(struct file *file,
960 char __user *user_buf,
961 size_t count, loff_t *ppos)
962 {
963 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
964 struct rtl8366_smi *smi = &rtl->smi;
965 u32 t, reg = gl_dbg_reg;
966 int err, len = 0;
967 char *buf = rtl->buf;
968
969 memset(buf, '\0', sizeof(rtl->buf));
970
971 err = rtl8366_smi_read_reg(smi, reg, &t);
972 if (err) {
973 len += snprintf(buf, sizeof(rtl->buf),
974 "Read failed (reg: 0x%04x)\n", reg);
975 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
976 }
977
978 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
979 reg, t);
980
981 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
982 }
983
984 static ssize_t rtl8366rb_write_debugfs_reg(struct file *file,
985 const char __user *user_buf,
986 size_t count, loff_t *ppos)
987 {
988 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
989 struct rtl8366_smi *smi = &rtl->smi;
990 unsigned long data;
991 u32 reg = gl_dbg_reg;
992 int err;
993 size_t len;
994 char *buf = rtl->buf;
995
996 len = min(count, sizeof(rtl->buf) - 1);
997 if (copy_from_user(buf, user_buf, len)) {
998 dev_err(rtl->parent, "copy from user failed\n");
999 return -EFAULT;
1000 }
1001
1002 buf[len] = '\0';
1003 if (len > 0 && buf[len - 1] == '\n')
1004 buf[len - 1] = '\0';
1005
1006
1007 if (strict_strtoul(buf, 16, &data)) {
1008 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
1009 } else {
1010 err = rtl8366_smi_write_reg(smi, reg, data);
1011 if (err) {
1012 dev_err(rtl->parent,
1013 "writing reg 0x%04x val 0x%04lx failed\n",
1014 reg, data);
1015 }
1016 }
1017
1018 return count;
1019 }
1020
1021 static const struct file_operations fops_rtl8366rb_regs = {
1022 .read = rtl8366rb_read_debugfs_reg,
1023 .write = rtl8366rb_write_debugfs_reg,
1024 .open = rtl8366rb_debugfs_open,
1025 .owner = THIS_MODULE
1026 };
1027
1028 static const struct file_operations fops_rtl8366rb_vlan_mc = {
1029 .read = rtl8366rb_read_debugfs_vlan_mc,
1030 .open = rtl8366rb_debugfs_open,
1031 .owner = THIS_MODULE
1032 };
1033
1034 static const struct file_operations fops_rtl8366rb_mibs = {
1035 .read = rtl8366rb_read_debugfs_mibs,
1036 .open = rtl8366rb_debugfs_open,
1037 .owner = THIS_MODULE
1038 };
1039
1040 static void rtl8366rb_debugfs_init(struct rtl8366rb *rtl)
1041 {
1042 struct dentry *node;
1043 struct dentry *root;
1044
1045 if (!rtl->debugfs_root)
1046 rtl->debugfs_root = debugfs_create_dir("rtl8366rb", NULL);
1047
1048 if (!rtl->debugfs_root) {
1049 dev_err(rtl->parent, "Unable to create debugfs dir\n");
1050 return;
1051 }
1052 root = rtl->debugfs_root;
1053
1054 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &gl_dbg_reg);
1055 if (!node) {
1056 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1057 "reg");
1058 return;
1059 }
1060
1061 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
1062 &fops_rtl8366rb_regs);
1063 if (!node) {
1064 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1065 "val");
1066 return;
1067 }
1068
1069 node = debugfs_create_file("vlan_mc", S_IRUSR, root, rtl,
1070 &fops_rtl8366rb_vlan_mc);
1071 if (!node) {
1072 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1073 "vlan_mc");
1074 return;
1075 }
1076
1077 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
1078 &fops_rtl8366rb_mibs);
1079 if (!node) {
1080 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1081 "mibs");
1082 return;
1083 }
1084 }
1085
1086 static void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl)
1087 {
1088 if (rtl->debugfs_root) {
1089 debugfs_remove_recursive(rtl->debugfs_root);
1090 rtl->debugfs_root = NULL;
1091 }
1092 }
1093
1094 #else
1095 static inline void rtl8366rb_debugfs_init(struct rtl8366rb *rtl) {}
1096 static inline void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl) {}
1097 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
1098
1099 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
1100 const struct switch_attr *attr,
1101 struct switch_val *val)
1102 {
1103 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1104 int err = 0;
1105
1106 if (val->value.i == 1)
1107 err = rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
1108 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
1109
1110 return err;
1111 }
1112
1113 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
1114 const struct switch_attr *attr,
1115 struct switch_val *val)
1116 {
1117 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1118 u32 data;
1119
1120 if (attr->ofs == 1) {
1121 rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
1122
1123 if (data & RTL8366RB_CHIP_CTRL_VLAN)
1124 val->value.i = 1;
1125 else
1126 val->value.i = 0;
1127 } else if (attr->ofs == 2) {
1128 rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
1129
1130 if (data & RTL8366RB_CHIP_CTRL_VLAN_4KTB)
1131 val->value.i = 1;
1132 else
1133 val->value.i = 0;
1134 }
1135
1136 return 0;
1137 }
1138
1139 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
1140 const struct switch_attr *attr,
1141 struct switch_val *val)
1142 {
1143 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1144 u32 data;
1145
1146 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
1147
1148 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
1149
1150 return 0;
1151 }
1152
1153 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
1154 const struct switch_attr *attr,
1155 struct switch_val *val)
1156 {
1157 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1158
1159 if (val->value.i >= 6)
1160 return -EINVAL;
1161
1162 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
1163 RTL8366RB_LED_BLINKRATE_MASK,
1164 val->value.i);
1165 }
1166
1167 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
1168 const struct switch_attr *attr,
1169 struct switch_val *val)
1170 {
1171 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1172
1173 if (attr->ofs == 1)
1174 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
1175 else
1176 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
1177 }
1178
1179 static const char *rtl8366rb_speed_str(unsigned speed)
1180 {
1181 switch (speed) {
1182 case 0:
1183 return "10baseT";
1184 case 1:
1185 return "100baseT";
1186 case 2:
1187 return "1000baseT";
1188 }
1189
1190 return "unknown";
1191 }
1192
1193 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
1194 const struct switch_attr *attr,
1195 struct switch_val *val)
1196 {
1197 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1198 struct rtl8366_smi *smi = &rtl->smi;
1199 u32 len = 0, data = 0;
1200
1201 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
1202 return -EINVAL;
1203
1204 memset(rtl->buf, '\0', sizeof(rtl->buf));
1205 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
1206 (val->port_vlan / 2), &data);
1207
1208 if (val->port_vlan % 2)
1209 data = data >> 8;
1210
1211 if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
1212 len = snprintf(rtl->buf, sizeof(rtl->buf),
1213 "port:%d link:up speed:%s %s-duplex %s%s%s",
1214 val->port_vlan,
1215 rtl8366rb_speed_str(data &
1216 RTL8366RB_PORT_STATUS_SPEED_MASK),
1217 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
1218 "full" : "half",
1219 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
1220 "tx-pause ": "",
1221 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
1222 "rx-pause " : "",
1223 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
1224 "nway ": "");
1225 } else {
1226 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1227 val->port_vlan);
1228 }
1229
1230 val->value.s = rtl->buf;
1231 val->len = len;
1232
1233 return 0;
1234 }
1235
1236 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
1237 const struct switch_attr *attr,
1238 struct switch_val *val)
1239 {
1240 int i;
1241 u32 len = 0;
1242 struct rtl8366_vlan_4k vlan4k;
1243 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1244 struct rtl8366_smi *smi = &rtl->smi;
1245 char *buf = rtl->buf;
1246 int err;
1247
1248 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1249 return -EINVAL;
1250
1251 memset(buf, '\0', sizeof(rtl->buf));
1252
1253 err = rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1254 if (err)
1255 return err;
1256
1257 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1258 "VLAN %d: Ports: '", vlan4k.vid);
1259
1260 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1261 if (!(vlan4k.member & (1 << i)))
1262 continue;
1263
1264 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d%s", i,
1265 (vlan4k.untag & (1 << i)) ? "" : "t");
1266 }
1267
1268 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1269 "', members=%04x, untag=%04x, fid=%u",
1270 vlan4k.member, vlan4k.untag, vlan4k.fid);
1271
1272 val->value.s = buf;
1273 val->len = len;
1274
1275 return 0;
1276 }
1277
1278 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
1279 const struct switch_attr *attr,
1280 struct switch_val *val)
1281 {
1282 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1283 u32 data;
1284 u32 mask;
1285 u32 reg;
1286
1287 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
1288 return -EINVAL;
1289
1290 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
1291 reg = RTL8366RB_LED_BLINKRATE_REG;
1292 mask = 0xF << 4;
1293 data = val->value.i << 4;
1294 } else {
1295 reg = RTL8366RB_LED_CTRL_REG;
1296 mask = 0xF << (val->port_vlan * 4),
1297 data = val->value.i << (val->port_vlan * 4);
1298 }
1299
1300 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
1301 }
1302
1303 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
1304 const struct switch_attr *attr,
1305 struct switch_val *val)
1306 {
1307 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1308 u32 data = 0;
1309
1310 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
1311 return -EINVAL;
1312
1313 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
1314 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1315
1316 return 0;
1317 }
1318
1319 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
1320 const struct switch_attr *attr,
1321 struct switch_val *val)
1322 {
1323 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1324
1325 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
1326 return -EINVAL;
1327
1328 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
1329 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
1330 }
1331
1332 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
1333 const struct switch_attr *attr,
1334 struct switch_val *val)
1335 {
1336 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1337 struct rtl8366_smi *smi = &rtl->smi;
1338 int i, len = 0;
1339 unsigned long long counter = 0;
1340 char *buf = rtl->buf;
1341
1342 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
1343 return -EINVAL;
1344
1345 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1346 "Port %d MIB counters\n",
1347 val->port_vlan);
1348
1349 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
1350 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1351 "%-36s: ", rtl8366rb_mib_counters[i].name);
1352 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1353 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1354 "%llu\n", counter);
1355 else
1356 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1357 "%s\n", "error");
1358 }
1359
1360 val->value.s = buf;
1361 val->len = len;
1362 return 0;
1363 }
1364
1365 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
1366 struct switch_val *val)
1367 {
1368 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1369 struct switch_port *port;
1370 struct rtl8366_vlan_4k vlan4k;
1371 int i;
1372
1373 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1374 return -EINVAL;
1375
1376 rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1377
1378 port = &val->value.ports[0];
1379 val->len = 0;
1380 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1381 if (!(vlan4k.member & BIT(i)))
1382 continue;
1383
1384 port->id = i;
1385 port->flags = (vlan4k.untag & BIT(i)) ?
1386 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1387 val->len++;
1388 port++;
1389 }
1390 return 0;
1391 }
1392
1393 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
1394 struct switch_val *val)
1395 {
1396 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1397 struct switch_port *port;
1398 u32 member = 0;
1399 u32 untag = 0;
1400 int i;
1401
1402 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1403 return -EINVAL;
1404
1405 port = &val->value.ports[0];
1406 for (i = 0; i < val->len; i++, port++) {
1407 member |= BIT(port->id);
1408
1409 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1410 untag |= BIT(port->id);
1411 }
1412
1413 return rtl8366rb_set_vlan(smi, val->port_vlan, member, untag, 0);
1414 }
1415
1416 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1417 {
1418 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1419 return rtl8366rb_get_pvid(smi, port, val);
1420 }
1421
1422 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1423 {
1424 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1425 return rtl8366rb_set_pvid(smi, port, val);
1426 }
1427
1428 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
1429 {
1430 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1431 int err;
1432
1433 err = rtl8366rb_reset_chip(smi);
1434 if (err)
1435 return err;
1436
1437 err = rtl8366rb_hw_init(smi);
1438 if (err)
1439 return err;
1440
1441 return rtl8366rb_reset_vlan(smi);
1442 }
1443
1444 static struct switch_attr rtl8366rb_globals[] = {
1445 {
1446 .type = SWITCH_TYPE_INT,
1447 .name = "enable_vlan",
1448 .description = "Enable VLAN mode",
1449 .set = rtl8366rb_sw_set_vlan_enable,
1450 .get = rtl8366rb_sw_get_vlan_enable,
1451 .max = 1,
1452 .ofs = 1
1453 }, {
1454 .type = SWITCH_TYPE_INT,
1455 .name = "enable_vlan4k",
1456 .description = "Enable VLAN 4K mode",
1457 .set = rtl8366rb_sw_set_vlan_enable,
1458 .get = rtl8366rb_sw_get_vlan_enable,
1459 .max = 1,
1460 .ofs = 2
1461 }, {
1462 .type = SWITCH_TYPE_INT,
1463 .name = "reset_mibs",
1464 .description = "Reset all MIB counters",
1465 .set = rtl8366rb_sw_reset_mibs,
1466 .get = NULL,
1467 .max = 1
1468 }, {
1469 .type = SWITCH_TYPE_INT,
1470 .name = "blinkrate",
1471 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1472 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1473 .set = rtl8366rb_sw_set_blinkrate,
1474 .get = rtl8366rb_sw_get_blinkrate,
1475 .max = 5
1476 },
1477 };
1478
1479 static struct switch_attr rtl8366rb_port[] = {
1480 {
1481 .type = SWITCH_TYPE_STRING,
1482 .name = "link",
1483 .description = "Get port link information",
1484 .max = 1,
1485 .set = NULL,
1486 .get = rtl8366rb_sw_get_port_link,
1487 }, {
1488 .type = SWITCH_TYPE_INT,
1489 .name = "reset_mib",
1490 .description = "Reset single port MIB counters",
1491 .max = 1,
1492 .set = rtl8366rb_sw_reset_port_mibs,
1493 .get = NULL,
1494 }, {
1495 .type = SWITCH_TYPE_STRING,
1496 .name = "mib",
1497 .description = "Get MIB counters for port",
1498 .max = 33,
1499 .set = NULL,
1500 .get = rtl8366rb_sw_get_port_mib,
1501 }, {
1502 .type = SWITCH_TYPE_INT,
1503 .name = "led",
1504 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1505 .max = 15,
1506 .set = rtl8366rb_sw_set_port_led,
1507 .get = rtl8366rb_sw_get_port_led,
1508 },
1509 };
1510
1511 static struct switch_attr rtl8366rb_vlan[] = {
1512 {
1513 .type = SWITCH_TYPE_STRING,
1514 .name = "info",
1515 .description = "Get vlan information",
1516 .max = 1,
1517 .set = NULL,
1518 .get = rtl8366rb_sw_get_vlan_info,
1519 },
1520 };
1521
1522 /* template */
1523 static struct switch_dev rtl8366_switch_dev = {
1524 .name = "RTL8366S",
1525 .cpu_port = RTL8366RB_PORT_NUM_CPU,
1526 .ports = RTL8366RB_NUM_PORTS,
1527 .vlans = RTL8366RB_NUM_VLANS,
1528 .attr_global = {
1529 .attr = rtl8366rb_globals,
1530 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1531 },
1532 .attr_port = {
1533 .attr = rtl8366rb_port,
1534 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1535 },
1536 .attr_vlan = {
1537 .attr = rtl8366rb_vlan,
1538 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1539 },
1540
1541 .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1542 .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1543 .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1544 .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1545 .reset_switch = rtl8366rb_sw_reset_switch,
1546 };
1547
1548 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1549 {
1550 struct switch_dev *dev = &rtl->dev;
1551 int err;
1552
1553 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1554 dev->priv = rtl;
1555 dev->devname = dev_name(rtl->parent);
1556
1557 err = register_switch(dev, NULL);
1558 if (err)
1559 dev_err(rtl->parent, "switch registration failed\n");
1560
1561 return err;
1562 }
1563
1564 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1565 {
1566 unregister_switch(&rtl->dev);
1567 }
1568
1569 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1570 {
1571 struct rtl8366_smi *smi = bus->priv;
1572 u32 val = 0;
1573 int err;
1574
1575 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1576 if (err)
1577 return 0xffff;
1578
1579 return val;
1580 }
1581
1582 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1583 {
1584 struct rtl8366_smi *smi = bus->priv;
1585 u32 t;
1586 int err;
1587
1588 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1589 /* flush write */
1590 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1591
1592 return err;
1593 }
1594
1595 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1596 {
1597 return (bus->read == rtl8366rb_mii_read &&
1598 bus->write == rtl8366rb_mii_write);
1599 }
1600
1601 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1602 {
1603 struct rtl8366_smi *smi = &rtl->smi;
1604 int ret;
1605
1606 rtl8366rb_debugfs_init(rtl);
1607
1608 ret = rtl8366rb_reset_chip(smi);
1609 if (ret)
1610 return ret;
1611
1612 ret = rtl8366rb_hw_init(smi);
1613 return ret;
1614 }
1615
1616 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1617 {
1618 u32 chip_id = 0;
1619 u32 chip_ver = 0;
1620 int ret;
1621
1622 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1623 if (ret) {
1624 dev_err(smi->parent, "unable to read chip id\n");
1625 return ret;
1626 }
1627
1628 switch (chip_id) {
1629 case RTL8366RB_CHIP_ID_8366:
1630 break;
1631 default:
1632 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1633 return -ENODEV;
1634 }
1635
1636 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1637 &chip_ver);
1638 if (ret) {
1639 dev_err(smi->parent, "unable to read chip version\n");
1640 return ret;
1641 }
1642
1643 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1644 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1645
1646 return 0;
1647 }
1648
1649 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1650 .detect = rtl8366rb_detect,
1651 .mii_read = rtl8366rb_mii_read,
1652 .mii_write = rtl8366rb_mii_write,
1653 };
1654
1655 static int __init rtl8366rb_probe(struct platform_device *pdev)
1656 {
1657 static int rtl8366_smi_version_printed;
1658 struct rtl8366rb_platform_data *pdata;
1659 struct rtl8366rb *rtl;
1660 struct rtl8366_smi *smi;
1661 int err;
1662
1663 if (!rtl8366_smi_version_printed++)
1664 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1665 " version " RTL8366RB_DRIVER_VER"\n");
1666
1667 pdata = pdev->dev.platform_data;
1668 if (!pdata) {
1669 dev_err(&pdev->dev, "no platform data specified\n");
1670 err = -EINVAL;
1671 goto err_out;
1672 }
1673
1674 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1675 if (!rtl) {
1676 dev_err(&pdev->dev, "no memory for private data\n");
1677 err = -ENOMEM;
1678 goto err_out;
1679 }
1680
1681 rtl->parent = &pdev->dev;
1682
1683 smi = &rtl->smi;
1684 smi->parent = &pdev->dev;
1685 smi->gpio_sda = pdata->gpio_sda;
1686 smi->gpio_sck = pdata->gpio_sck;
1687 smi->ops = &rtl8366rb_smi_ops;
1688
1689 err = rtl8366_smi_init(smi);
1690 if (err)
1691 goto err_free_rtl;
1692
1693 platform_set_drvdata(pdev, rtl);
1694
1695 err = rtl8366rb_setup(rtl);
1696 if (err)
1697 goto err_clear_drvdata;
1698
1699 err = rtl8366rb_switch_init(rtl);
1700 if (err)
1701 goto err_clear_drvdata;
1702
1703 return 0;
1704
1705 err_clear_drvdata:
1706 platform_set_drvdata(pdev, NULL);
1707 rtl8366_smi_cleanup(smi);
1708 err_free_rtl:
1709 kfree(rtl);
1710 err_out:
1711 return err;
1712 }
1713
1714 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1715 {
1716 if (!rtl8366rb_mii_bus_match(phydev->bus))
1717 return -EINVAL;
1718
1719 return 0;
1720 }
1721
1722 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1723 {
1724 return 0;
1725 }
1726
1727 static struct phy_driver rtl8366rb_phy_driver = {
1728 .phy_id = 0x001cc960,
1729 .name = "Realtek RTL8366RB",
1730 .phy_id_mask = 0x1ffffff0,
1731 .features = PHY_GBIT_FEATURES,
1732 .config_aneg = rtl8366rb_phy_config_aneg,
1733 .config_init = rtl8366rb_phy_config_init,
1734 .read_status = genphy_read_status,
1735 .driver = {
1736 .owner = THIS_MODULE,
1737 },
1738 };
1739
1740 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1741 {
1742 struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1743
1744 if (rtl) {
1745 rtl8366rb_switch_cleanup(rtl);
1746 rtl8366rb_debugfs_remove(rtl);
1747 platform_set_drvdata(pdev, NULL);
1748 rtl8366_smi_cleanup(&rtl->smi);
1749 kfree(rtl);
1750 }
1751
1752 return 0;
1753 }
1754
1755 static struct platform_driver rtl8366rb_driver = {
1756 .driver = {
1757 .name = RTL8366RB_DRIVER_NAME,
1758 .owner = THIS_MODULE,
1759 },
1760 .probe = rtl8366rb_probe,
1761 .remove = __devexit_p(rtl8366rb_remove),
1762 };
1763
1764 static int __init rtl8366rb_module_init(void)
1765 {
1766 int ret;
1767 ret = platform_driver_register(&rtl8366rb_driver);
1768 if (ret)
1769 return ret;
1770
1771 ret = phy_driver_register(&rtl8366rb_phy_driver);
1772 if (ret)
1773 goto err_platform_unregister;
1774
1775 return 0;
1776
1777 err_platform_unregister:
1778 platform_driver_unregister(&rtl8366rb_driver);
1779 return ret;
1780 }
1781 module_init(rtl8366rb_module_init);
1782
1783 static void __exit rtl8366rb_module_exit(void)
1784 {
1785 phy_driver_unregister(&rtl8366rb_phy_driver);
1786 platform_driver_unregister(&rtl8366rb_driver);
1787 }
1788 module_exit(rtl8366rb_module_exit);
1789
1790 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1791 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1792 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1793 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1794 MODULE_LICENSE("GPL v2");
1795 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
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