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kernel: update bcma and ssb to version master-2012-04-12 from wireless-testing
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-2.6.32 / 025-bcma_backport.patch
1 --- /dev/null
2 +++ b/Documentation/ABI/testing/sysfs-bus-bcma
3 @@ -0,0 +1,31 @@
4 +What: /sys/bus/bcma/devices/.../manuf
5 +Date: May 2011
6 +KernelVersion: 2.6.40
7 +Contact: Rafał Miłecki <zajec5@gmail.com>
8 +Description:
9 + Each BCMA core has it's manufacturer id. See
10 + include/linux/bcma/bcma.h for possible values.
11 +
12 +What: /sys/bus/bcma/devices/.../id
13 +Date: May 2011
14 +KernelVersion: 2.6.40
15 +Contact: Rafał Miłecki <zajec5@gmail.com>
16 +Description:
17 + There are a few types of BCMA cores, they can be identified by
18 + id field.
19 +
20 +What: /sys/bus/bcma/devices/.../rev
21 +Date: May 2011
22 +KernelVersion: 2.6.40
23 +Contact: Rafał Miłecki <zajec5@gmail.com>
24 +Description:
25 + BCMA cores of the same type can still slightly differ depending
26 + on their revision. Use it for detailed programming.
27 +
28 +What: /sys/bus/bcma/devices/.../class
29 +Date: May 2011
30 +KernelVersion: 2.6.40
31 +Contact: Rafał Miłecki <zajec5@gmail.com>
32 +Description:
33 + Each BCMA core is identified by few fields, including class it
34 + belongs to. See include/linux/bcma/bcma.h for possible values.
35 --- a/MAINTAINERS
36 +++ b/MAINTAINERS
37 @@ -4918,6 +4918,13 @@ S: Maintained
38 F: drivers/ssb/
39 F: include/linux/ssb/
40
41 +BROADCOM SPECIFIC AMBA DRIVER (BCMA)
42 +M: Rafał Miłecki <zajec5@gmail.com>
43 +L: linux-wireless@vger.kernel.org
44 +S: Maintained
45 +F: drivers/bcma/
46 +F: include/linux/bcma/
47 +
48 SONY VAIO CONTROL DEVICE DRIVER
49 M: Mattia Dongili <malattia@linux.it>
50 L: linux-acpi@vger.kernel.org
51 --- a/drivers/Kconfig
52 +++ b/drivers/Kconfig
53 @@ -68,6 +68,8 @@ source "drivers/watchdog/Kconfig"
54
55 source "drivers/ssb/Kconfig"
56
57 +source "drivers/bcma/Kconfig"
58 +
59 source "drivers/mfd/Kconfig"
60
61 source "drivers/regulator/Kconfig"
62 --- a/drivers/Makefile
63 +++ b/drivers/Makefile
64 @@ -107,6 +107,7 @@ obj-$(CONFIG_HID) += hid/
65 obj-$(CONFIG_PPC_PS3) += ps3/
66 obj-$(CONFIG_OF) += of/
67 obj-$(CONFIG_SSB) += ssb/
68 +obj-$(CONFIG_BCMA) += bcma/
69 obj-$(CONFIG_VLYNQ) += vlynq/
70 obj-$(CONFIG_STAGING) += staging/
71 obj-y += platform/
72 --- /dev/null
73 +++ b/drivers/bcma/Kconfig
74 @@ -0,0 +1,57 @@
75 +config BCMA_POSSIBLE
76 + bool
77 + depends on HAS_IOMEM && HAS_DMA
78 + default y
79 +
80 +menu "Broadcom specific AMBA"
81 + depends on BCMA_POSSIBLE
82 +
83 +config BCMA
84 + tristate "BCMA support"
85 + depends on BCMA_POSSIBLE
86 + help
87 + Bus driver for Broadcom specific Advanced Microcontroller Bus
88 + Architecture.
89 +
90 +# Support for Block-I/O. SELECT this from the driver that needs it.
91 +config BCMA_BLOCKIO
92 + bool
93 + depends on BCMA
94 +
95 +config BCMA_HOST_PCI_POSSIBLE
96 + bool
97 + depends on BCMA && PCI = y
98 + default y
99 +
100 +config BCMA_HOST_PCI
101 + bool "Support for BCMA on PCI-host bus"
102 + depends on BCMA_HOST_PCI_POSSIBLE
103 +
104 +config BCMA_DRIVER_PCI_HOSTMODE
105 + bool "Driver for PCI core working in hostmode"
106 + depends on BCMA && MIPS && BCMA_HOST_PCI
107 + help
108 + PCI core hostmode operation (external PCI bus).
109 +
110 +config BCMA_HOST_SOC
111 + bool
112 + depends on BCMA_DRIVER_MIPS
113 +
114 +config BCMA_DRIVER_MIPS
115 + bool "BCMA Broadcom MIPS core driver"
116 + depends on BCMA && MIPS
117 + help
118 + Driver for the Broadcom MIPS core attached to Broadcom specific
119 + Advanced Microcontroller Bus.
120 +
121 + If unsure, say N
122 +
123 +config BCMA_DEBUG
124 + bool "BCMA debugging"
125 + depends on BCMA
126 + help
127 + This turns on additional debugging messages.
128 +
129 + If unsure, say N
130 +
131 +endmenu
132 --- /dev/null
133 +++ b/drivers/bcma/Makefile
134 @@ -0,0 +1,10 @@
135 +bcma-y += main.o scan.o core.o sprom.o
136 +bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
137 +bcma-y += driver_pci.o
138 +bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
139 +bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
140 +bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
141 +bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
142 +obj-$(CONFIG_BCMA) += bcma.o
143 +
144 +ccflags-$(CONFIG_BCMA_DEBUG) := -DDEBUG
145 --- /dev/null
146 +++ b/drivers/bcma/README
147 @@ -0,0 +1,19 @@
148 +Broadcom introduced new bus as replacement for older SSB. It is based on AMBA,
149 +however from programming point of view there is nothing AMBA specific we use.
150 +
151 +Standard AMBA drivers are platform specific, have hardcoded addresses and use
152 +AMBA standard fields like CID and PID.
153 +
154 +In case of Broadcom's cards every device consists of:
155 +1) Broadcom specific AMBA device. It is put on AMBA bus, but can not be treated
156 + as standard AMBA device. Reading it's CID or PID can cause machine lockup.
157 +2) AMBA standard devices called ports or wrappers. They have CIDs (AMBA_CID)
158 + and PIDs (0x103BB369), but we do not use that info for anything. One of that
159 + devices is used for managing Broadcom specific core.
160 +
161 +Addresses of AMBA devices are not hardcoded in driver and have to be read from
162 +EPROM.
163 +
164 +In this situation we decided to introduce separated bus. It can contain up to
165 +16 devices identified by Broadcom specific fields: manufacturer, id, revision
166 +and class.
167 --- /dev/null
168 +++ b/drivers/bcma/TODO
169 @@ -0,0 +1,3 @@
170 +- Interrupts
171 +- Defines for PCI core driver
172 +- Create kernel Documentation (use info from README)
173 --- /dev/null
174 +++ b/drivers/bcma/bcma_private.h
175 @@ -0,0 +1,59 @@
176 +#ifndef LINUX_BCMA_PRIVATE_H_
177 +#define LINUX_BCMA_PRIVATE_H_
178 +
179 +#ifndef pr_fmt
180 +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
181 +#endif
182 +
183 +#include <linux/bcma/bcma.h>
184 +#include <linux/delay.h>
185 +
186 +#define BCMA_CORE_SIZE 0x1000
187 +
188 +struct bcma_bus;
189 +
190 +/* main.c */
191 +int __devinit bcma_bus_register(struct bcma_bus *bus);
192 +void bcma_bus_unregister(struct bcma_bus *bus);
193 +int __init bcma_bus_early_register(struct bcma_bus *bus,
194 + struct bcma_device *core_cc,
195 + struct bcma_device *core_mips);
196 +#ifdef CONFIG_PM
197 +int bcma_bus_suspend(struct bcma_bus *bus);
198 +int bcma_bus_resume(struct bcma_bus *bus);
199 +#endif
200 +
201 +/* scan.c */
202 +int bcma_bus_scan(struct bcma_bus *bus);
203 +int __init bcma_bus_scan_early(struct bcma_bus *bus,
204 + struct bcma_device_id *match,
205 + struct bcma_device *core);
206 +void bcma_init_bus(struct bcma_bus *bus);
207 +
208 +/* sprom.c */
209 +int bcma_sprom_get(struct bcma_bus *bus);
210 +
211 +/* driver_chipcommon.c */
212 +#ifdef CONFIG_BCMA_DRIVER_MIPS
213 +void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
214 +#endif /* CONFIG_BCMA_DRIVER_MIPS */
215 +
216 +/* driver_chipcommon_pmu.c */
217 +u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
218 +u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
219 +
220 +#ifdef CONFIG_BCMA_HOST_PCI
221 +/* host_pci.c */
222 +extern int __init bcma_host_pci_init(void);
223 +extern void __exit bcma_host_pci_exit(void);
224 +#endif /* CONFIG_BCMA_HOST_PCI */
225 +
226 +/* driver_pci.c */
227 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
228 +
229 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
230 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
231 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
232 +#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
233 +
234 +#endif
235 --- /dev/null
236 +++ b/drivers/bcma/core.c
237 @@ -0,0 +1,126 @@
238 +/*
239 + * Broadcom specific AMBA
240 + * Core ops
241 + *
242 + * Licensed under the GNU/GPL. See COPYING for details.
243 + */
244 +
245 +#include "bcma_private.h"
246 +#include <linux/bcma/bcma.h>
247 +
248 +bool bcma_core_is_enabled(struct bcma_device *core)
249 +{
250 + if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
251 + != BCMA_IOCTL_CLK)
252 + return false;
253 + if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
254 + return false;
255 + return true;
256 +}
257 +EXPORT_SYMBOL_GPL(bcma_core_is_enabled);
258 +
259 +void bcma_core_disable(struct bcma_device *core, u32 flags)
260 +{
261 + if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
262 + return;
263 +
264 + bcma_awrite32(core, BCMA_IOCTL, flags);
265 + bcma_aread32(core, BCMA_IOCTL);
266 + udelay(10);
267 +
268 + bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
269 + udelay(1);
270 +}
271 +EXPORT_SYMBOL_GPL(bcma_core_disable);
272 +
273 +int bcma_core_enable(struct bcma_device *core, u32 flags)
274 +{
275 + bcma_core_disable(core, flags);
276 +
277 + bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC | flags));
278 + bcma_aread32(core, BCMA_IOCTL);
279 +
280 + bcma_awrite32(core, BCMA_RESET_CTL, 0);
281 + udelay(1);
282 +
283 + bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
284 + bcma_aread32(core, BCMA_IOCTL);
285 + udelay(1);
286 +
287 + return 0;
288 +}
289 +EXPORT_SYMBOL_GPL(bcma_core_enable);
290 +
291 +void bcma_core_set_clockmode(struct bcma_device *core,
292 + enum bcma_clkmode clkmode)
293 +{
294 + u16 i;
295 +
296 + WARN_ON(core->id.id != BCMA_CORE_CHIPCOMMON &&
297 + core->id.id != BCMA_CORE_PCIE &&
298 + core->id.id != BCMA_CORE_80211);
299 +
300 + switch (clkmode) {
301 + case BCMA_CLKMODE_FAST:
302 + bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
303 + udelay(64);
304 + for (i = 0; i < 1500; i++) {
305 + if (bcma_read32(core, BCMA_CLKCTLST) &
306 + BCMA_CLKCTLST_HAVEHT) {
307 + i = 0;
308 + break;
309 + }
310 + udelay(10);
311 + }
312 + if (i)
313 + pr_err("HT force timeout\n");
314 + break;
315 + case BCMA_CLKMODE_DYNAMIC:
316 + pr_warning("Dynamic clockmode not supported yet!\n");
317 + break;
318 + }
319 +}
320 +EXPORT_SYMBOL_GPL(bcma_core_set_clockmode);
321 +
322 +void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, bool on)
323 +{
324 + u16 i;
325 +
326 + WARN_ON(req & ~BCMA_CLKCTLST_EXTRESREQ);
327 + WARN_ON(status & ~BCMA_CLKCTLST_EXTRESST);
328 +
329 + if (on) {
330 + bcma_set32(core, BCMA_CLKCTLST, req);
331 + for (i = 0; i < 10000; i++) {
332 + if ((bcma_read32(core, BCMA_CLKCTLST) & status) ==
333 + status) {
334 + i = 0;
335 + break;
336 + }
337 + udelay(10);
338 + }
339 + if (i)
340 + pr_err("PLL enable timeout\n");
341 + } else {
342 + pr_warning("Disabling PLL not supported yet!\n");
343 + }
344 +}
345 +EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
346 +
347 +u32 bcma_core_dma_translation(struct bcma_device *core)
348 +{
349 + switch (core->bus->hosttype) {
350 + case BCMA_HOSTTYPE_SOC:
351 + return 0;
352 + case BCMA_HOSTTYPE_PCI:
353 + if (bcma_aread32(core, BCMA_IOST) & BCMA_IOST_DMA64)
354 + return BCMA_DMA_TRANSLATION_DMA64_CMT;
355 + else
356 + return BCMA_DMA_TRANSLATION_DMA32_CMT;
357 + default:
358 + pr_err("DMA translation unknown for host %d\n",
359 + core->bus->hosttype);
360 + }
361 + return BCMA_DMA_TRANSLATION_NONE;
362 +}
363 +EXPORT_SYMBOL(bcma_core_dma_translation);
364 --- /dev/null
365 +++ b/drivers/bcma/driver_chipcommon.c
366 @@ -0,0 +1,156 @@
367 +/*
368 + * Broadcom specific AMBA
369 + * ChipCommon core driver
370 + *
371 + * Copyright 2005, Broadcom Corporation
372 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
373 + *
374 + * Licensed under the GNU/GPL. See COPYING for details.
375 + */
376 +
377 +#include "bcma_private.h"
378 +#include <linux/bcma/bcma.h>
379 +
380 +static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
381 + u32 mask, u32 value)
382 +{
383 + value &= mask;
384 + value |= bcma_cc_read32(cc, offset) & ~mask;
385 + bcma_cc_write32(cc, offset, value);
386 +
387 + return value;
388 +}
389 +
390 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
391 +{
392 + u32 leddc_on = 10;
393 + u32 leddc_off = 90;
394 +
395 + if (cc->setup_done)
396 + return;
397 +
398 + if (cc->core->id.rev >= 11)
399 + cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
400 + cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
401 + if (cc->core->id.rev >= 35)
402 + cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
403 +
404 + if (cc->core->id.rev >= 20) {
405 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
406 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
407 + }
408 +
409 + if (cc->capabilities & BCMA_CC_CAP_PMU)
410 + bcma_pmu_init(cc);
411 + if (cc->capabilities & BCMA_CC_CAP_PCTL)
412 + pr_err("Power control not implemented!\n");
413 +
414 + if (cc->core->id.rev >= 16) {
415 + if (cc->core->bus->sprom.leddc_on_time &&
416 + cc->core->bus->sprom.leddc_off_time) {
417 + leddc_on = cc->core->bus->sprom.leddc_on_time;
418 + leddc_off = cc->core->bus->sprom.leddc_off_time;
419 + }
420 + bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
421 + ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
422 + (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
423 + }
424 +
425 + cc->setup_done = true;
426 +}
427 +
428 +/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
429 +void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
430 +{
431 + /* instant NMI */
432 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
433 +}
434 +
435 +void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
436 +{
437 + bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
438 +}
439 +
440 +u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
441 +{
442 + return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
443 +}
444 +
445 +u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
446 +{
447 + return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
448 +}
449 +
450 +u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
451 +{
452 + return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
453 +}
454 +
455 +u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
456 +{
457 + return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
458 +}
459 +
460 +u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
461 +{
462 + return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
463 +}
464 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
465 +
466 +u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
467 +{
468 + return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
469 +}
470 +
471 +u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
472 +{
473 + return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
474 +}
475 +
476 +#ifdef CONFIG_BCMA_DRIVER_MIPS
477 +void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
478 +{
479 + unsigned int irq;
480 + u32 baud_base;
481 + u32 i;
482 + unsigned int ccrev = cc->core->id.rev;
483 + struct bcma_serial_port *ports = cc->serial_ports;
484 +
485 + if (ccrev >= 11 && ccrev != 15) {
486 + /* Fixed ALP clock */
487 + baud_base = bcma_pmu_alp_clock(cc);
488 + if (ccrev >= 21) {
489 + /* Turn off UART clock before switching clocksource. */
490 + bcma_cc_write32(cc, BCMA_CC_CORECTL,
491 + bcma_cc_read32(cc, BCMA_CC_CORECTL)
492 + & ~BCMA_CC_CORECTL_UARTCLKEN);
493 + }
494 + /* Set the override bit so we don't divide it */
495 + bcma_cc_write32(cc, BCMA_CC_CORECTL,
496 + bcma_cc_read32(cc, BCMA_CC_CORECTL)
497 + | BCMA_CC_CORECTL_UARTCLK0);
498 + if (ccrev >= 21) {
499 + /* Re-enable the UART clock. */
500 + bcma_cc_write32(cc, BCMA_CC_CORECTL,
501 + bcma_cc_read32(cc, BCMA_CC_CORECTL)
502 + | BCMA_CC_CORECTL_UARTCLKEN);
503 + }
504 + } else {
505 + pr_err("serial not supported on this device ccrev: 0x%x\n",
506 + ccrev);
507 + return;
508 + }
509 +
510 + irq = bcma_core_mips_irq(cc->core);
511 +
512 + /* Determine the registers of the UARTs */
513 + cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
514 + for (i = 0; i < cc->nr_serial_ports; i++) {
515 + ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
516 + (i * 256);
517 + ports[i].irq = irq;
518 + ports[i].baud_base = baud_base;
519 + ports[i].reg_shift = 0;
520 + }
521 +}
522 +#endif /* CONFIG_BCMA_DRIVER_MIPS */
523 --- /dev/null
524 +++ b/drivers/bcma/driver_chipcommon_pmu.c
525 @@ -0,0 +1,310 @@
526 +/*
527 + * Broadcom specific AMBA
528 + * ChipCommon Power Management Unit driver
529 + *
530 + * Copyright 2009, Michael Buesch <m@bues.ch>
531 + * Copyright 2007, Broadcom Corporation
532 + *
533 + * Licensed under the GNU/GPL. See COPYING for details.
534 + */
535 +
536 +#include "bcma_private.h"
537 +#include <linux/bcma/bcma.h>
538 +
539 +static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
540 +{
541 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
542 + bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
543 + return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
544 +}
545 +
546 +void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
547 +{
548 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
549 + bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
550 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
551 +}
552 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
553 +
554 +void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
555 + u32 set)
556 +{
557 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
558 + bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
559 + bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
560 +}
561 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
562 +
563 +void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
564 + u32 offset, u32 mask, u32 set)
565 +{
566 + bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
567 + bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
568 + bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
569 +}
570 +EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
571 +
572 +void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
573 + u32 set)
574 +{
575 + bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
576 + bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
577 + bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
578 +}
579 +EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
580 +
581 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
582 +{
583 + struct bcma_bus *bus = cc->core->bus;
584 +
585 + switch (bus->chipinfo.id) {
586 + case 0x4313:
587 + case 0x4331:
588 + case 43224:
589 + case 43225:
590 + break;
591 + default:
592 + pr_err("PLL init unknown for device 0x%04X\n",
593 + bus->chipinfo.id);
594 + }
595 +}
596 +
597 +static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
598 +{
599 + struct bcma_bus *bus = cc->core->bus;
600 + u32 min_msk = 0, max_msk = 0;
601 +
602 + switch (bus->chipinfo.id) {
603 + case 0x4313:
604 + min_msk = 0x200D;
605 + max_msk = 0xFFFF;
606 + break;
607 + case 0x4331:
608 + case 43224:
609 + case 43225:
610 + break;
611 + default:
612 + pr_err("PMU resource config unknown for device 0x%04X\n",
613 + bus->chipinfo.id);
614 + }
615 +
616 + /* Set the resource masks. */
617 + if (min_msk)
618 + bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
619 + if (max_msk)
620 + bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
621 +}
622 +
623 +void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
624 +{
625 + struct bcma_bus *bus = cc->core->bus;
626 +
627 + switch (bus->chipinfo.id) {
628 + case 0x4313:
629 + case 0x4331:
630 + case 43224:
631 + case 43225:
632 + break;
633 + default:
634 + pr_err("PMU switch/regulators init unknown for device "
635 + "0x%04X\n", bus->chipinfo.id);
636 + }
637 +}
638 +
639 +/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
640 +void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
641 +{
642 + struct bcma_bus *bus = cc->core->bus;
643 + u32 val;
644 +
645 + val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
646 + if (enable) {
647 + val |= BCMA_CHIPCTL_4331_EXTPA_EN;
648 + if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
649 + val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
650 + } else {
651 + val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
652 + val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
653 + }
654 + bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
655 +}
656 +
657 +void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
658 +{
659 + struct bcma_bus *bus = cc->core->bus;
660 +
661 + switch (bus->chipinfo.id) {
662 + case 0x4313:
663 + bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
664 + break;
665 + case 0x4331:
666 + /* BCM4331 workaround is SPROM-related, we put it in sprom.c */
667 + break;
668 + case 43224:
669 + if (bus->chipinfo.rev == 0) {
670 + pr_err("Workarounds for 43224 rev 0 not fully "
671 + "implemented\n");
672 + bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
673 + } else {
674 + bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
675 + }
676 + break;
677 + case 43225:
678 + break;
679 + default:
680 + pr_err("Workarounds unknown for device 0x%04X\n",
681 + bus->chipinfo.id);
682 + }
683 +}
684 +
685 +void bcma_pmu_init(struct bcma_drv_cc *cc)
686 +{
687 + u32 pmucap;
688 +
689 + pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
690 + cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
691 +
692 + pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
693 + pmucap);
694 +
695 + if (cc->pmu.rev == 1)
696 + bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
697 + ~BCMA_CC_PMU_CTL_NOILPONW);
698 + else
699 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
700 + BCMA_CC_PMU_CTL_NOILPONW);
701 +
702 + if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
703 + pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
704 +
705 + bcma_pmu_pll_init(cc);
706 + bcma_pmu_resources_init(cc);
707 + bcma_pmu_swreg_init(cc);
708 + bcma_pmu_workarounds(cc);
709 +}
710 +
711 +u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
712 +{
713 + struct bcma_bus *bus = cc->core->bus;
714 +
715 + switch (bus->chipinfo.id) {
716 + case 0x4716:
717 + case 0x4748:
718 + case 47162:
719 + case 0x4313:
720 + case 0x5357:
721 + case 0x4749:
722 + case 53572:
723 + /* always 20Mhz */
724 + return 20000 * 1000;
725 + case 0x5356:
726 + case 0x5300:
727 + /* always 25Mhz */
728 + return 25000 * 1000;
729 + default:
730 + pr_warning("No ALP clock specified for %04X device, "
731 + "pmu rev. %d, using default %d Hz\n",
732 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
733 + }
734 + return BCMA_CC_PMU_ALP_CLOCK;
735 +}
736 +
737 +/* Find the output of the "m" pll divider given pll controls that start with
738 + * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
739 + */
740 +static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
741 +{
742 + u32 tmp, div, ndiv, p1, p2, fc;
743 + struct bcma_bus *bus = cc->core->bus;
744 +
745 + BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
746 +
747 + BUG_ON(!m || m > 4);
748 +
749 + if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
750 + /* Detect failure in clock setting */
751 + tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
752 + if (tmp & 0x40000)
753 + return 133 * 1000000;
754 + }
755 +
756 + tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
757 + p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
758 + p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
759 +
760 + tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
761 + div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
762 + BCMA_CC_PPL_MDIV_MASK;
763 +
764 + tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
765 + ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
766 +
767 + /* Do calculation in Mhz */
768 + fc = bcma_pmu_alp_clock(cc) / 1000000;
769 + fc = (p1 * ndiv * fc) / p2;
770 +
771 + /* Return clock in Hertz */
772 + return (fc / div) * 1000000;
773 +}
774 +
775 +/* query bus clock frequency for PMU-enabled chipcommon */
776 +u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
777 +{
778 + struct bcma_bus *bus = cc->core->bus;
779 +
780 + switch (bus->chipinfo.id) {
781 + case 0x4716:
782 + case 0x4748:
783 + case 47162:
784 + return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
785 + BCMA_CC_PMU5_MAINPLL_SSB);
786 + case 0x5356:
787 + return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
788 + BCMA_CC_PMU5_MAINPLL_SSB);
789 + case 0x5357:
790 + case 0x4749:
791 + return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
792 + BCMA_CC_PMU5_MAINPLL_SSB);
793 + case 0x5300:
794 + return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
795 + BCMA_CC_PMU5_MAINPLL_SSB);
796 + case 53572:
797 + return 75000000;
798 + default:
799 + pr_warning("No backplane clock specified for %04X device, "
800 + "pmu rev. %d, using default %d Hz\n",
801 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
802 + }
803 + return BCMA_CC_PMU_HT_CLOCK;
804 +}
805 +
806 +/* query cpu clock frequency for PMU-enabled chipcommon */
807 +u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
808 +{
809 + struct bcma_bus *bus = cc->core->bus;
810 +
811 + if (bus->chipinfo.id == 53572)
812 + return 300000000;
813 +
814 + if (cc->pmu.rev >= 5) {
815 + u32 pll;
816 + switch (bus->chipinfo.id) {
817 + case 0x5356:
818 + pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
819 + break;
820 + case 0x5357:
821 + case 0x4749:
822 + pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
823 + break;
824 + default:
825 + pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
826 + break;
827 + }
828 +
829 + /* TODO: if (bus->chipinfo.id == 0x5300)
830 + return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
831 + return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
832 + }
833 +
834 + return bcma_pmu_get_clockcontrol(cc);
835 +}
836 --- /dev/null
837 +++ b/drivers/bcma/driver_pci.c
838 @@ -0,0 +1,225 @@
839 +/*
840 + * Broadcom specific AMBA
841 + * PCI Core
842 + *
843 + * Copyright 2005, 2011, Broadcom Corporation
844 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
845 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
846 + *
847 + * Licensed under the GNU/GPL. See COPYING for details.
848 + */
849 +
850 +#include "bcma_private.h"
851 +#include <linux/bcma/bcma.h>
852 +
853 +/**************************************************
854 + * R/W ops.
855 + **************************************************/
856 +
857 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
858 +{
859 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
860 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
861 + return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
862 +}
863 +
864 +#if 0
865 +static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
866 +{
867 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
868 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
869 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
870 +}
871 +#endif
872 +
873 +static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
874 +{
875 + u32 v;
876 + int i;
877 +
878 + v = BCMA_CORE_PCI_MDIODATA_START;
879 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
880 + v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
881 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
882 + v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
883 + BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
884 + v |= BCMA_CORE_PCI_MDIODATA_TA;
885 + v |= (phy << 4);
886 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
887 +
888 + udelay(10);
889 + for (i = 0; i < 200; i++) {
890 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
891 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
892 + break;
893 + msleep(1);
894 + }
895 +}
896 +
897 +static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
898 +{
899 + int max_retries = 10;
900 + u16 ret = 0;
901 + u32 v;
902 + int i;
903 +
904 + /* enable mdio access to SERDES */
905 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
906 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
907 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
908 +
909 + if (pc->core->id.rev >= 10) {
910 + max_retries = 200;
911 + bcma_pcie_mdio_set_phy(pc, device);
912 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
913 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
914 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
915 + } else {
916 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
917 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
918 + }
919 +
920 + v = BCMA_CORE_PCI_MDIODATA_START;
921 + v |= BCMA_CORE_PCI_MDIODATA_READ;
922 + v |= BCMA_CORE_PCI_MDIODATA_TA;
923 +
924 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
925 + /* Wait for the device to complete the transaction */
926 + udelay(10);
927 + for (i = 0; i < max_retries; i++) {
928 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
929 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
930 + udelay(10);
931 + ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
932 + break;
933 + }
934 + msleep(1);
935 + }
936 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
937 + return ret;
938 +}
939 +
940 +static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
941 + u8 address, u16 data)
942 +{
943 + int max_retries = 10;
944 + u32 v;
945 + int i;
946 +
947 + /* enable mdio access to SERDES */
948 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
949 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
950 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
951 +
952 + if (pc->core->id.rev >= 10) {
953 + max_retries = 200;
954 + bcma_pcie_mdio_set_phy(pc, device);
955 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
956 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
957 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
958 + } else {
959 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
960 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
961 + }
962 +
963 + v = BCMA_CORE_PCI_MDIODATA_START;
964 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
965 + v |= BCMA_CORE_PCI_MDIODATA_TA;
966 + v |= data;
967 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
968 + /* Wait for the device to complete the transaction */
969 + udelay(10);
970 + for (i = 0; i < max_retries; i++) {
971 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
972 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
973 + break;
974 + msleep(1);
975 + }
976 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
977 +}
978 +
979 +/**************************************************
980 + * Workarounds.
981 + **************************************************/
982 +
983 +static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
984 +{
985 + u32 tmp;
986 +
987 + tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
988 + if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
989 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
990 + BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
991 + else
992 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
993 +}
994 +
995 +static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
996 +{
997 + u16 tmp;
998 +
999 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
1000 + BCMA_CORE_PCI_SERDES_RX_CTRL,
1001 + bcma_pcicore_polarity_workaround(pc));
1002 + tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
1003 + BCMA_CORE_PCI_SERDES_PLL_CTRL);
1004 + if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
1005 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
1006 + BCMA_CORE_PCI_SERDES_PLL_CTRL,
1007 + tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
1008 +}
1009 +
1010 +/**************************************************
1011 + * Init.
1012 + **************************************************/
1013 +
1014 +static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
1015 +{
1016 + bcma_pcicore_serdes_workaround(pc);
1017 +}
1018 +
1019 +void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
1020 +{
1021 + if (pc->setup_done)
1022 + return;
1023 +
1024 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
1025 + pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
1026 + if (pc->hostmode)
1027 + bcma_core_pci_hostmode_init(pc);
1028 +#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
1029 +
1030 + if (!pc->hostmode)
1031 + bcma_core_pci_clientmode_init(pc);
1032 +}
1033 +
1034 +int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
1035 + bool enable)
1036 +{
1037 + struct pci_dev *pdev = pc->core->bus->host_pci;
1038 + u32 coremask, tmp;
1039 + int err = 0;
1040 +
1041 + if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
1042 + /* This bcma device is not on a PCI host-bus. So the IRQs are
1043 + * not routed through the PCI core.
1044 + * So we must not enable routing through the PCI core. */
1045 + goto out;
1046 + }
1047 +
1048 + err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
1049 + if (err)
1050 + goto out;
1051 +
1052 + coremask = BIT(core->core_index) << 8;
1053 + if (enable)
1054 + tmp |= coremask;
1055 + else
1056 + tmp &= ~coremask;
1057 +
1058 + err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
1059 +
1060 +out:
1061 + return err;
1062 +}
1063 +EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
1064 --- /dev/null
1065 +++ b/drivers/bcma/host_pci.c
1066 @@ -0,0 +1,292 @@
1067 +/*
1068 + * Broadcom specific AMBA
1069 + * PCI Host
1070 + *
1071 + * Licensed under the GNU/GPL. See COPYING for details.
1072 + */
1073 +
1074 +#include "bcma_private.h"
1075 +#include <linux/slab.h>
1076 +#include <linux/bcma/bcma.h>
1077 +#include <linux/pci.h>
1078 +#include <linux/module.h>
1079 +
1080 +static void bcma_host_pci_switch_core(struct bcma_device *core)
1081 +{
1082 + pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN,
1083 + core->addr);
1084 + pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
1085 + core->wrap);
1086 + core->bus->mapped_core = core;
1087 + pr_debug("Switched to core: 0x%X\n", core->id.id);
1088 +}
1089 +
1090 +/* Provides access to the requested core. Returns base offset that has to be
1091 + * used. It makes use of fixed windows when possible. */
1092 +static u16 bcma_host_pci_provide_access_to_core(struct bcma_device *core)
1093 +{
1094 + switch (core->id.id) {
1095 + case BCMA_CORE_CHIPCOMMON:
1096 + return 3 * BCMA_CORE_SIZE;
1097 + case BCMA_CORE_PCIE:
1098 + return 2 * BCMA_CORE_SIZE;
1099 + }
1100 +
1101 + if (core->bus->mapped_core != core)
1102 + bcma_host_pci_switch_core(core);
1103 + return 0;
1104 +}
1105 +
1106 +static u8 bcma_host_pci_read8(struct bcma_device *core, u16 offset)
1107 +{
1108 + offset += bcma_host_pci_provide_access_to_core(core);
1109 + return ioread8(core->bus->mmio + offset);
1110 +}
1111 +
1112 +static u16 bcma_host_pci_read16(struct bcma_device *core, u16 offset)
1113 +{
1114 + offset += bcma_host_pci_provide_access_to_core(core);
1115 + return ioread16(core->bus->mmio + offset);
1116 +}
1117 +
1118 +static u32 bcma_host_pci_read32(struct bcma_device *core, u16 offset)
1119 +{
1120 + offset += bcma_host_pci_provide_access_to_core(core);
1121 + return ioread32(core->bus->mmio + offset);
1122 +}
1123 +
1124 +static void bcma_host_pci_write8(struct bcma_device *core, u16 offset,
1125 + u8 value)
1126 +{
1127 + offset += bcma_host_pci_provide_access_to_core(core);
1128 + iowrite8(value, core->bus->mmio + offset);
1129 +}
1130 +
1131 +static void bcma_host_pci_write16(struct bcma_device *core, u16 offset,
1132 + u16 value)
1133 +{
1134 + offset += bcma_host_pci_provide_access_to_core(core);
1135 + iowrite16(value, core->bus->mmio + offset);
1136 +}
1137 +
1138 +static void bcma_host_pci_write32(struct bcma_device *core, u16 offset,
1139 + u32 value)
1140 +{
1141 + offset += bcma_host_pci_provide_access_to_core(core);
1142 + iowrite32(value, core->bus->mmio + offset);
1143 +}
1144 +
1145 +#ifdef CONFIG_BCMA_BLOCKIO
1146 +void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
1147 + size_t count, u16 offset, u8 reg_width)
1148 +{
1149 + void __iomem *addr = core->bus->mmio + offset;
1150 + if (core->bus->mapped_core != core)
1151 + bcma_host_pci_switch_core(core);
1152 + switch (reg_width) {
1153 + case sizeof(u8):
1154 + ioread8_rep(addr, buffer, count);
1155 + break;
1156 + case sizeof(u16):
1157 + WARN_ON(count & 1);
1158 + ioread16_rep(addr, buffer, count >> 1);
1159 + break;
1160 + case sizeof(u32):
1161 + WARN_ON(count & 3);
1162 + ioread32_rep(addr, buffer, count >> 2);
1163 + break;
1164 + default:
1165 + WARN_ON(1);
1166 + }
1167 +}
1168 +
1169 +void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
1170 + size_t count, u16 offset, u8 reg_width)
1171 +{
1172 + void __iomem *addr = core->bus->mmio + offset;
1173 + if (core->bus->mapped_core != core)
1174 + bcma_host_pci_switch_core(core);
1175 + switch (reg_width) {
1176 + case sizeof(u8):
1177 + iowrite8_rep(addr, buffer, count);
1178 + break;
1179 + case sizeof(u16):
1180 + WARN_ON(count & 1);
1181 + iowrite16_rep(addr, buffer, count >> 1);
1182 + break;
1183 + case sizeof(u32):
1184 + WARN_ON(count & 3);
1185 + iowrite32_rep(addr, buffer, count >> 2);
1186 + break;
1187 + default:
1188 + WARN_ON(1);
1189 + }
1190 +}
1191 +#endif
1192 +
1193 +static u32 bcma_host_pci_aread32(struct bcma_device *core, u16 offset)
1194 +{
1195 + if (core->bus->mapped_core != core)
1196 + bcma_host_pci_switch_core(core);
1197 + return ioread32(core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
1198 +}
1199 +
1200 +static void bcma_host_pci_awrite32(struct bcma_device *core, u16 offset,
1201 + u32 value)
1202 +{
1203 + if (core->bus->mapped_core != core)
1204 + bcma_host_pci_switch_core(core);
1205 + iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
1206 +}
1207 +
1208 +const struct bcma_host_ops bcma_host_pci_ops = {
1209 + .read8 = bcma_host_pci_read8,
1210 + .read16 = bcma_host_pci_read16,
1211 + .read32 = bcma_host_pci_read32,
1212 + .write8 = bcma_host_pci_write8,
1213 + .write16 = bcma_host_pci_write16,
1214 + .write32 = bcma_host_pci_write32,
1215 +#ifdef CONFIG_BCMA_BLOCKIO
1216 + .block_read = bcma_host_pci_block_read,
1217 + .block_write = bcma_host_pci_block_write,
1218 +#endif
1219 + .aread32 = bcma_host_pci_aread32,
1220 + .awrite32 = bcma_host_pci_awrite32,
1221 +};
1222 +
1223 +static int __devinit bcma_host_pci_probe(struct pci_dev *dev,
1224 + const struct pci_device_id *id)
1225 +{
1226 + struct bcma_bus *bus;
1227 + int err = -ENOMEM;
1228 + const char *name;
1229 + u32 val;
1230 +
1231 + /* Alloc */
1232 + bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1233 + if (!bus)
1234 + goto out;
1235 +
1236 + /* Basic PCI configuration */
1237 + err = pci_enable_device(dev);
1238 + if (err)
1239 + goto err_kfree_bus;
1240 +
1241 + name = dev_name(&dev->dev);
1242 + if (dev->driver && dev->driver->name)
1243 + name = dev->driver->name;
1244 + err = pci_request_regions(dev, name);
1245 + if (err)
1246 + goto err_pci_disable;
1247 + pci_set_master(dev);
1248 +
1249 + /* Disable the RETRY_TIMEOUT register (0x41) to keep
1250 + * PCI Tx retries from interfering with C3 CPU state */
1251 + pci_read_config_dword(dev, 0x40, &val);
1252 + if ((val & 0x0000ff00) != 0)
1253 + pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
1254 +
1255 + /* SSB needed additional powering up, do we have any AMBA PCI cards? */
1256 + if (!dev->is_pcie)
1257 + pr_err("PCI card detected, report problems.\n");
1258 +
1259 + /* Map MMIO */
1260 + err = -ENOMEM;
1261 + bus->mmio = pci_iomap(dev, 0, ~0UL);
1262 + if (!bus->mmio)
1263 + goto err_pci_release_regions;
1264 +
1265 + /* Host specific */
1266 + bus->host_pci = dev;
1267 + bus->hosttype = BCMA_HOSTTYPE_PCI;
1268 + bus->ops = &bcma_host_pci_ops;
1269 +
1270 + /* Register */
1271 + err = bcma_bus_register(bus);
1272 + if (err)
1273 + goto err_pci_unmap_mmio;
1274 +
1275 + pci_set_drvdata(dev, bus);
1276 +
1277 +out:
1278 + return err;
1279 +
1280 +err_pci_unmap_mmio:
1281 + pci_iounmap(dev, bus->mmio);
1282 +err_pci_release_regions:
1283 + pci_release_regions(dev);
1284 +err_pci_disable:
1285 + pci_disable_device(dev);
1286 +err_kfree_bus:
1287 + kfree(bus);
1288 + return err;
1289 +}
1290 +
1291 +static void bcma_host_pci_remove(struct pci_dev *dev)
1292 +{
1293 + struct bcma_bus *bus = pci_get_drvdata(dev);
1294 +
1295 + bcma_bus_unregister(bus);
1296 + pci_iounmap(dev, bus->mmio);
1297 + pci_release_regions(dev);
1298 + pci_disable_device(dev);
1299 + kfree(bus);
1300 + pci_set_drvdata(dev, NULL);
1301 +}
1302 +
1303 +#ifdef CONFIG_PM
1304 +static int bcma_host_pci_suspend(struct device *dev)
1305 +{
1306 + struct pci_dev *pdev = to_pci_dev(dev);
1307 + struct bcma_bus *bus = pci_get_drvdata(pdev);
1308 +
1309 + bus->mapped_core = NULL;
1310 +
1311 + return bcma_bus_suspend(bus);
1312 +}
1313 +
1314 +static int bcma_host_pci_resume(struct device *dev)
1315 +{
1316 + struct pci_dev *pdev = to_pci_dev(dev);
1317 + struct bcma_bus *bus = pci_get_drvdata(pdev);
1318 +
1319 + return bcma_bus_resume(bus);
1320 +}
1321 +
1322 +static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bcma_host_pci_suspend,
1323 + bcma_host_pci_resume);
1324 +#define BCMA_PM_OPS (&bcma_pm_ops)
1325 +
1326 +#else /* CONFIG_PM */
1327 +
1328 +#define BCMA_PM_OPS NULL
1329 +
1330 +#endif /* CONFIG_PM */
1331 +
1332 +static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
1333 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
1334 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
1335 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
1336 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
1337 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
1338 + { 0, },
1339 +};
1340 +MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
1341 +
1342 +static struct pci_driver bcma_pci_bridge_driver = {
1343 + .name = "bcma-pci-bridge",
1344 + .id_table = bcma_pci_bridge_tbl,
1345 + .probe = bcma_host_pci_probe,
1346 + .remove = bcma_host_pci_remove,
1347 + .driver.pm = BCMA_PM_OPS,
1348 +};
1349 +
1350 +int __init bcma_host_pci_init(void)
1351 +{
1352 + return pci_register_driver(&bcma_pci_bridge_driver);
1353 +}
1354 +
1355 +void __exit bcma_host_pci_exit(void)
1356 +{
1357 + pci_unregister_driver(&bcma_pci_bridge_driver);
1358 +}
1359 --- /dev/null
1360 +++ b/drivers/bcma/main.c
1361 @@ -0,0 +1,387 @@
1362 +/*
1363 + * Broadcom specific AMBA
1364 + * Bus subsystem
1365 + *
1366 + * Licensed under the GNU/GPL. See COPYING for details.
1367 + */
1368 +
1369 +#include "bcma_private.h"
1370 +#include <linux/module.h>
1371 +#include <linux/bcma/bcma.h>
1372 +#include <linux/slab.h>
1373 +
1374 +MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
1375 +MODULE_LICENSE("GPL");
1376 +
1377 +/* contains the number the next bus should get. */
1378 +static unsigned int bcma_bus_next_num = 0;
1379 +
1380 +/* bcma_buses_mutex locks the bcma_bus_next_num */
1381 +static DEFINE_MUTEX(bcma_buses_mutex);
1382 +
1383 +static int bcma_bus_match(struct device *dev, struct device_driver *drv);
1384 +static int bcma_device_probe(struct device *dev);
1385 +static int bcma_device_remove(struct device *dev);
1386 +static int bcma_device_uevent(struct device *dev, struct kobj_uevent_env *env);
1387 +
1388 +static ssize_t manuf_show(struct device *dev, struct device_attribute *attr, char *buf)
1389 +{
1390 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1391 + return sprintf(buf, "0x%03X\n", core->id.manuf);
1392 +}
1393 +static ssize_t id_show(struct device *dev, struct device_attribute *attr, char *buf)
1394 +{
1395 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1396 + return sprintf(buf, "0x%03X\n", core->id.id);
1397 +}
1398 +static ssize_t rev_show(struct device *dev, struct device_attribute *attr, char *buf)
1399 +{
1400 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1401 + return sprintf(buf, "0x%02X\n", core->id.rev);
1402 +}
1403 +static ssize_t class_show(struct device *dev, struct device_attribute *attr, char *buf)
1404 +{
1405 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1406 + return sprintf(buf, "0x%X\n", core->id.class);
1407 +}
1408 +static struct device_attribute bcma_device_attrs[] = {
1409 + __ATTR_RO(manuf),
1410 + __ATTR_RO(id),
1411 + __ATTR_RO(rev),
1412 + __ATTR_RO(class),
1413 + __ATTR_NULL,
1414 +};
1415 +
1416 +static struct bus_type bcma_bus_type = {
1417 + .name = "bcma",
1418 + .match = bcma_bus_match,
1419 + .probe = bcma_device_probe,
1420 + .remove = bcma_device_remove,
1421 + .uevent = bcma_device_uevent,
1422 + .dev_attrs = bcma_device_attrs,
1423 +};
1424 +
1425 +struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
1426 +{
1427 + struct bcma_device *core;
1428 +
1429 + list_for_each_entry(core, &bus->cores, list) {
1430 + if (core->id.id == coreid)
1431 + return core;
1432 + }
1433 + return NULL;
1434 +}
1435 +EXPORT_SYMBOL_GPL(bcma_find_core);
1436 +
1437 +static void bcma_release_core_dev(struct device *dev)
1438 +{
1439 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1440 + if (core->io_addr)
1441 + iounmap(core->io_addr);
1442 + if (core->io_wrap)
1443 + iounmap(core->io_wrap);
1444 + kfree(core);
1445 +}
1446 +
1447 +static int bcma_register_cores(struct bcma_bus *bus)
1448 +{
1449 + struct bcma_device *core;
1450 + int err, dev_id = 0;
1451 +
1452 + list_for_each_entry(core, &bus->cores, list) {
1453 + /* We support that cores ourself */
1454 + switch (core->id.id) {
1455 + case BCMA_CORE_CHIPCOMMON:
1456 + case BCMA_CORE_PCI:
1457 + case BCMA_CORE_PCIE:
1458 + case BCMA_CORE_MIPS_74K:
1459 + continue;
1460 + }
1461 +
1462 + core->dev.release = bcma_release_core_dev;
1463 + core->dev.bus = &bcma_bus_type;
1464 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
1465 +
1466 + switch (bus->hosttype) {
1467 + case BCMA_HOSTTYPE_PCI:
1468 + core->dev.parent = &bus->host_pci->dev;
1469 + core->dma_dev = &bus->host_pci->dev;
1470 + core->irq = bus->host_pci->irq;
1471 + break;
1472 + case BCMA_HOSTTYPE_SOC:
1473 + core->dev.dma_mask = &core->dev.coherent_dma_mask;
1474 + core->dma_dev = &core->dev;
1475 + break;
1476 + case BCMA_HOSTTYPE_SDIO:
1477 + break;
1478 + }
1479 +
1480 + err = device_register(&core->dev);
1481 + if (err) {
1482 + pr_err("Could not register dev for core 0x%03X\n",
1483 + core->id.id);
1484 + continue;
1485 + }
1486 + core->dev_registered = true;
1487 + dev_id++;
1488 + }
1489 +
1490 + return 0;
1491 +}
1492 +
1493 +static void bcma_unregister_cores(struct bcma_bus *bus)
1494 +{
1495 + struct bcma_device *core;
1496 +
1497 + list_for_each_entry(core, &bus->cores, list) {
1498 + if (core->dev_registered)
1499 + device_unregister(&core->dev);
1500 + }
1501 +}
1502 +
1503 +int __devinit bcma_bus_register(struct bcma_bus *bus)
1504 +{
1505 + int err;
1506 + struct bcma_device *core;
1507 +
1508 + mutex_lock(&bcma_buses_mutex);
1509 + bus->num = bcma_bus_next_num++;
1510 + mutex_unlock(&bcma_buses_mutex);
1511 +
1512 + /* Scan for devices (cores) */
1513 + err = bcma_bus_scan(bus);
1514 + if (err) {
1515 + pr_err("Failed to scan: %d\n", err);
1516 + return -1;
1517 + }
1518 +
1519 + /* Init CC core */
1520 + core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
1521 + if (core) {
1522 + bus->drv_cc.core = core;
1523 + bcma_core_chipcommon_init(&bus->drv_cc);
1524 + }
1525 +
1526 + /* Init MIPS core */
1527 + core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1528 + if (core) {
1529 + bus->drv_mips.core = core;
1530 + bcma_core_mips_init(&bus->drv_mips);
1531 + }
1532 +
1533 + /* Init PCIE core */
1534 + core = bcma_find_core(bus, BCMA_CORE_PCIE);
1535 + if (core) {
1536 + bus->drv_pci.core = core;
1537 + bcma_core_pci_init(&bus->drv_pci);
1538 + }
1539 +
1540 + /* Try to get SPROM */
1541 + err = bcma_sprom_get(bus);
1542 + if (err == -ENOENT) {
1543 + pr_err("No SPROM available\n");
1544 + } else if (err)
1545 + pr_err("Failed to get SPROM: %d\n", err);
1546 +
1547 + /* Register found cores */
1548 + bcma_register_cores(bus);
1549 +
1550 + pr_info("Bus registered\n");
1551 +
1552 + return 0;
1553 +}
1554 +
1555 +void bcma_bus_unregister(struct bcma_bus *bus)
1556 +{
1557 + bcma_unregister_cores(bus);
1558 +}
1559 +
1560 +int __init bcma_bus_early_register(struct bcma_bus *bus,
1561 + struct bcma_device *core_cc,
1562 + struct bcma_device *core_mips)
1563 +{
1564 + int err;
1565 + struct bcma_device *core;
1566 + struct bcma_device_id match;
1567 +
1568 + bcma_init_bus(bus);
1569 +
1570 + match.manuf = BCMA_MANUF_BCM;
1571 + match.id = BCMA_CORE_CHIPCOMMON;
1572 + match.class = BCMA_CL_SIM;
1573 + match.rev = BCMA_ANY_REV;
1574 +
1575 + /* Scan for chip common core */
1576 + err = bcma_bus_scan_early(bus, &match, core_cc);
1577 + if (err) {
1578 + pr_err("Failed to scan for common core: %d\n", err);
1579 + return -1;
1580 + }
1581 +
1582 + match.manuf = BCMA_MANUF_MIPS;
1583 + match.id = BCMA_CORE_MIPS_74K;
1584 + match.class = BCMA_CL_SIM;
1585 + match.rev = BCMA_ANY_REV;
1586 +
1587 + /* Scan for mips core */
1588 + err = bcma_bus_scan_early(bus, &match, core_mips);
1589 + if (err) {
1590 + pr_err("Failed to scan for mips core: %d\n", err);
1591 + return -1;
1592 + }
1593 +
1594 + /* Init CC core */
1595 + core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
1596 + if (core) {
1597 + bus->drv_cc.core = core;
1598 + bcma_core_chipcommon_init(&bus->drv_cc);
1599 + }
1600 +
1601 + /* Init MIPS core */
1602 + core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1603 + if (core) {
1604 + bus->drv_mips.core = core;
1605 + bcma_core_mips_init(&bus->drv_mips);
1606 + }
1607 +
1608 + pr_info("Early bus registered\n");
1609 +
1610 + return 0;
1611 +}
1612 +
1613 +#ifdef CONFIG_PM
1614 +int bcma_bus_suspend(struct bcma_bus *bus)
1615 +{
1616 + struct bcma_device *core;
1617 +
1618 + list_for_each_entry(core, &bus->cores, list) {
1619 + struct device_driver *drv = core->dev.driver;
1620 + if (drv) {
1621 + struct bcma_driver *adrv = container_of(drv, struct bcma_driver, drv);
1622 + if (adrv->suspend)
1623 + adrv->suspend(core);
1624 + }
1625 + }
1626 + return 0;
1627 +}
1628 +
1629 +int bcma_bus_resume(struct bcma_bus *bus)
1630 +{
1631 + struct bcma_device *core;
1632 +
1633 + /* Init CC core */
1634 + core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
1635 + if (core) {
1636 + bus->drv_cc.setup_done = false;
1637 + bcma_core_chipcommon_init(&bus->drv_cc);
1638 + }
1639 +
1640 + list_for_each_entry(core, &bus->cores, list) {
1641 + struct device_driver *drv = core->dev.driver;
1642 + if (drv) {
1643 + struct bcma_driver *adrv = container_of(drv, struct bcma_driver, drv);
1644 + if (adrv->resume)
1645 + adrv->resume(core);
1646 + }
1647 + }
1648 +
1649 + return 0;
1650 +}
1651 +#endif
1652 +
1653 +int __bcma_driver_register(struct bcma_driver *drv, struct module *owner)
1654 +{
1655 + drv->drv.name = drv->name;
1656 + drv->drv.bus = &bcma_bus_type;
1657 + drv->drv.owner = owner;
1658 +
1659 + return driver_register(&drv->drv);
1660 +}
1661 +EXPORT_SYMBOL_GPL(__bcma_driver_register);
1662 +
1663 +void bcma_driver_unregister(struct bcma_driver *drv)
1664 +{
1665 + driver_unregister(&drv->drv);
1666 +}
1667 +EXPORT_SYMBOL_GPL(bcma_driver_unregister);
1668 +
1669 +static int bcma_bus_match(struct device *dev, struct device_driver *drv)
1670 +{
1671 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1672 + struct bcma_driver *adrv = container_of(drv, struct bcma_driver, drv);
1673 + const struct bcma_device_id *cid = &core->id;
1674 + const struct bcma_device_id *did;
1675 +
1676 + for (did = adrv->id_table; did->manuf || did->id || did->rev; did++) {
1677 + if ((did->manuf == cid->manuf || did->manuf == BCMA_ANY_MANUF) &&
1678 + (did->id == cid->id || did->id == BCMA_ANY_ID) &&
1679 + (did->rev == cid->rev || did->rev == BCMA_ANY_REV) &&
1680 + (did->class == cid->class || did->class == BCMA_ANY_CLASS))
1681 + return 1;
1682 + }
1683 + return 0;
1684 +}
1685 +
1686 +static int bcma_device_probe(struct device *dev)
1687 +{
1688 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1689 + struct bcma_driver *adrv = container_of(dev->driver, struct bcma_driver,
1690 + drv);
1691 + int err = 0;
1692 +
1693 + if (adrv->probe)
1694 + err = adrv->probe(core);
1695 +
1696 + return err;
1697 +}
1698 +
1699 +static int bcma_device_remove(struct device *dev)
1700 +{
1701 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1702 + struct bcma_driver *adrv = container_of(dev->driver, struct bcma_driver,
1703 + drv);
1704 +
1705 + if (adrv->remove)
1706 + adrv->remove(core);
1707 +
1708 + return 0;
1709 +}
1710 +
1711 +static int bcma_device_uevent(struct device *dev, struct kobj_uevent_env *env)
1712 +{
1713 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1714 +
1715 + return add_uevent_var(env,
1716 + "MODALIAS=bcma:m%04Xid%04Xrev%02Xcl%02X",
1717 + core->id.manuf, core->id.id,
1718 + core->id.rev, core->id.class);
1719 +}
1720 +
1721 +static int __init bcma_modinit(void)
1722 +{
1723 + int err;
1724 +
1725 + err = bus_register(&bcma_bus_type);
1726 + if (err)
1727 + return err;
1728 +
1729 +#ifdef CONFIG_BCMA_HOST_PCI
1730 + err = bcma_host_pci_init();
1731 + if (err) {
1732 + pr_err("PCI host initialization failed\n");
1733 + err = 0;
1734 + }
1735 +#endif
1736 +
1737 + return err;
1738 +}
1739 +fs_initcall(bcma_modinit);
1740 +
1741 +static void __exit bcma_modexit(void)
1742 +{
1743 +#ifdef CONFIG_BCMA_HOST_PCI
1744 + bcma_host_pci_exit();
1745 +#endif
1746 + bus_unregister(&bcma_bus_type);
1747 +}
1748 +module_exit(bcma_modexit)
1749 --- /dev/null
1750 +++ b/drivers/bcma/scan.c
1751 @@ -0,0 +1,507 @@
1752 +/*
1753 + * Broadcom specific AMBA
1754 + * Bus scanning
1755 + *
1756 + * Licensed under the GNU/GPL. See COPYING for details.
1757 + */
1758 +
1759 +#include "scan.h"
1760 +#include "bcma_private.h"
1761 +
1762 +#include <linux/bcma/bcma.h>
1763 +#include <linux/bcma/bcma_regs.h>
1764 +#include <linux/pci.h>
1765 +#include <linux/io.h>
1766 +#include <linux/dma-mapping.h>
1767 +#include <linux/slab.h>
1768 +
1769 +struct bcma_device_id_name {
1770 + u16 id;
1771 + const char *name;
1772 +};
1773 +struct bcma_device_id_name bcma_device_names[] = {
1774 + { BCMA_CORE_OOB_ROUTER, "OOB Router" },
1775 + { BCMA_CORE_INVALID, "Invalid" },
1776 + { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
1777 + { BCMA_CORE_ILINE20, "ILine 20" },
1778 + { BCMA_CORE_SRAM, "SRAM" },
1779 + { BCMA_CORE_SDRAM, "SDRAM" },
1780 + { BCMA_CORE_PCI, "PCI" },
1781 + { BCMA_CORE_MIPS, "MIPS" },
1782 + { BCMA_CORE_ETHERNET, "Fast Ethernet" },
1783 + { BCMA_CORE_V90, "V90" },
1784 + { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
1785 + { BCMA_CORE_ADSL, "ADSL" },
1786 + { BCMA_CORE_ILINE100, "ILine 100" },
1787 + { BCMA_CORE_IPSEC, "IPSEC" },
1788 + { BCMA_CORE_UTOPIA, "UTOPIA" },
1789 + { BCMA_CORE_PCMCIA, "PCMCIA" },
1790 + { BCMA_CORE_INTERNAL_MEM, "Internal Memory" },
1791 + { BCMA_CORE_MEMC_SDRAM, "MEMC SDRAM" },
1792 + { BCMA_CORE_OFDM, "OFDM" },
1793 + { BCMA_CORE_EXTIF, "EXTIF" },
1794 + { BCMA_CORE_80211, "IEEE 802.11" },
1795 + { BCMA_CORE_PHY_A, "PHY A" },
1796 + { BCMA_CORE_PHY_B, "PHY B" },
1797 + { BCMA_CORE_PHY_G, "PHY G" },
1798 + { BCMA_CORE_MIPS_3302, "MIPS 3302" },
1799 + { BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
1800 + { BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
1801 + { BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
1802 + { BCMA_CORE_USB20_DEV, "USB 2.0 Device" },
1803 + { BCMA_CORE_SDIO_HOST, "SDIO Host" },
1804 + { BCMA_CORE_ROBOSWITCH, "Roboswitch" },
1805 + { BCMA_CORE_PARA_ATA, "PATA" },
1806 + { BCMA_CORE_SATA_XORDMA, "SATA XOR-DMA" },
1807 + { BCMA_CORE_ETHERNET_GBIT, "GBit Ethernet" },
1808 + { BCMA_CORE_PCIE, "PCIe" },
1809 + { BCMA_CORE_PHY_N, "PHY N" },
1810 + { BCMA_CORE_SRAM_CTL, "SRAM Controller" },
1811 + { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
1812 + { BCMA_CORE_ARM_1176, "ARM 1176" },
1813 + { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
1814 + { BCMA_CORE_PHY_LP, "PHY LP" },
1815 + { BCMA_CORE_PMU, "PMU" },
1816 + { BCMA_CORE_PHY_SSN, "PHY SSN" },
1817 + { BCMA_CORE_SDIO_DEV, "SDIO Device" },
1818 + { BCMA_CORE_ARM_CM3, "ARM CM3" },
1819 + { BCMA_CORE_PHY_HT, "PHY HT" },
1820 + { BCMA_CORE_MIPS_74K, "MIPS 74K" },
1821 + { BCMA_CORE_MAC_GBIT, "GBit MAC" },
1822 + { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
1823 + { BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
1824 + { BCMA_CORE_OCP_OCP_BRIDGE, "OCP to OCP Bridge" },
1825 + { BCMA_CORE_SHARED_COMMON, "Common Shared" },
1826 + { BCMA_CORE_OCP_AHB_BRIDGE, "OCP to AHB Bridge" },
1827 + { BCMA_CORE_SPI_HOST, "SPI Host" },
1828 + { BCMA_CORE_I2S, "I2S" },
1829 + { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
1830 + { BCMA_CORE_SHIM, "SHIM" },
1831 + { BCMA_CORE_DEFAULT, "Default" },
1832 +};
1833 +const char *bcma_device_name(struct bcma_device_id *id)
1834 +{
1835 + int i;
1836 +
1837 + if (id->manuf == BCMA_MANUF_BCM) {
1838 + for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
1839 + if (bcma_device_names[i].id == id->id)
1840 + return bcma_device_names[i].name;
1841 + }
1842 + }
1843 + return "UNKNOWN";
1844 +}
1845 +
1846 +static u32 bcma_scan_read32(struct bcma_bus *bus, u8 current_coreidx,
1847 + u16 offset)
1848 +{
1849 + return readl(bus->mmio + offset);
1850 +}
1851 +
1852 +static void bcma_scan_switch_core(struct bcma_bus *bus, u32 addr)
1853 +{
1854 + if (bus->hosttype == BCMA_HOSTTYPE_PCI)
1855 + pci_write_config_dword(bus->host_pci, BCMA_PCI_BAR0_WIN,
1856 + addr);
1857 +}
1858 +
1859 +static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
1860 +{
1861 + u32 ent = readl(*eromptr);
1862 + (*eromptr)++;
1863 + return ent;
1864 +}
1865 +
1866 +static void bcma_erom_push_ent(u32 **eromptr)
1867 +{
1868 + (*eromptr)--;
1869 +}
1870 +
1871 +static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
1872 +{
1873 + u32 ent = bcma_erom_get_ent(bus, eromptr);
1874 + if (!(ent & SCAN_ER_VALID))
1875 + return -ENOENT;
1876 + if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_CI)
1877 + return -ENOENT;
1878 + return ent;
1879 +}
1880 +
1881 +static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
1882 +{
1883 + u32 ent = bcma_erom_get_ent(bus, eromptr);
1884 + bcma_erom_push_ent(eromptr);
1885 + return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
1886 +}
1887 +
1888 +static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
1889 +{
1890 + u32 ent = bcma_erom_get_ent(bus, eromptr);
1891 + bcma_erom_push_ent(eromptr);
1892 + return (((ent & SCAN_ER_VALID)) &&
1893 + ((ent & SCAN_ER_TAGX) == SCAN_ER_TAG_ADDR) &&
1894 + ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
1895 +}
1896 +
1897 +static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
1898 +{
1899 + u32 ent;
1900 + while (1) {
1901 + ent = bcma_erom_get_ent(bus, eromptr);
1902 + if ((ent & SCAN_ER_VALID) &&
1903 + ((ent & SCAN_ER_TAG) == SCAN_ER_TAG_CI))
1904 + break;
1905 + if (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID))
1906 + break;
1907 + }
1908 + bcma_erom_push_ent(eromptr);
1909 +}
1910 +
1911 +static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
1912 +{
1913 + u32 ent = bcma_erom_get_ent(bus, eromptr);
1914 + if (!(ent & SCAN_ER_VALID))
1915 + return -ENOENT;
1916 + if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_MP)
1917 + return -ENOENT;
1918 + return ent;
1919 +}
1920 +
1921 +static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
1922 + u32 type, u8 port)
1923 +{
1924 + u32 addrl, addrh, sizel, sizeh = 0;
1925 + u32 size;
1926 +
1927 + u32 ent = bcma_erom_get_ent(bus, eromptr);
1928 + if ((!(ent & SCAN_ER_VALID)) ||
1929 + ((ent & SCAN_ER_TAGX) != SCAN_ER_TAG_ADDR) ||
1930 + ((ent & SCAN_ADDR_TYPE) != type) ||
1931 + (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
1932 + bcma_erom_push_ent(eromptr);
1933 + return -EINVAL;
1934 + }
1935 +
1936 + addrl = ent & SCAN_ADDR_ADDR;
1937 + if (ent & SCAN_ADDR_AG32)
1938 + addrh = bcma_erom_get_ent(bus, eromptr);
1939 + else
1940 + addrh = 0;
1941 +
1942 + if ((ent & SCAN_ADDR_SZ) == SCAN_ADDR_SZ_SZD) {
1943 + size = bcma_erom_get_ent(bus, eromptr);
1944 + sizel = size & SCAN_SIZE_SZ;
1945 + if (size & SCAN_SIZE_SG32)
1946 + sizeh = bcma_erom_get_ent(bus, eromptr);
1947 + } else
1948 + sizel = SCAN_ADDR_SZ_BASE <<
1949 + ((ent & SCAN_ADDR_SZ) >> SCAN_ADDR_SZ_SHIFT);
1950 +
1951 + return addrl;
1952 +}
1953 +
1954 +static struct bcma_device *bcma_find_core_by_index(struct bcma_bus *bus,
1955 + u16 index)
1956 +{
1957 + struct bcma_device *core;
1958 +
1959 + list_for_each_entry(core, &bus->cores, list) {
1960 + if (core->core_index == index)
1961 + return core;
1962 + }
1963 + return NULL;
1964 +}
1965 +
1966 +static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid)
1967 +{
1968 + struct bcma_device *core;
1969 +
1970 + list_for_each_entry_reverse(core, &bus->cores, list) {
1971 + if (core->id.id == coreid)
1972 + return core;
1973 + }
1974 + return NULL;
1975 +}
1976 +
1977 +static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
1978 + struct bcma_device_id *match, int core_num,
1979 + struct bcma_device *core)
1980 +{
1981 + s32 tmp;
1982 + u8 i, j;
1983 + s32 cia, cib;
1984 + u8 ports[2], wrappers[2];
1985 +
1986 + /* get CIs */
1987 + cia = bcma_erom_get_ci(bus, eromptr);
1988 + if (cia < 0) {
1989 + bcma_erom_push_ent(eromptr);
1990 + if (bcma_erom_is_end(bus, eromptr))
1991 + return -ESPIPE;
1992 + return -EILSEQ;
1993 + }
1994 + cib = bcma_erom_get_ci(bus, eromptr);
1995 + if (cib < 0)
1996 + return -EILSEQ;
1997 +
1998 + /* parse CIs */
1999 + core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT;
2000 + core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT;
2001 + core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT;
2002 + ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT;
2003 + ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT;
2004 + wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT;
2005 + wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT;
2006 + core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT;
2007 +
2008 + if (((core->id.manuf == BCMA_MANUF_ARM) &&
2009 + (core->id.id == 0xFFF)) ||
2010 + (ports[1] == 0)) {
2011 + bcma_erom_skip_component(bus, eromptr);
2012 + return -ENXIO;
2013 + }
2014 +
2015 + /* check if component is a core at all */
2016 + if (wrappers[0] + wrappers[1] == 0) {
2017 + /* we could save addrl of the router
2018 + if (cid == BCMA_CORE_OOB_ROUTER)
2019 + */
2020 + bcma_erom_skip_component(bus, eromptr);
2021 + return -ENXIO;
2022 + }
2023 +
2024 + if (bcma_erom_is_bridge(bus, eromptr)) {
2025 + bcma_erom_skip_component(bus, eromptr);
2026 + return -ENXIO;
2027 + }
2028 +
2029 + if (bcma_find_core_by_index(bus, core_num)) {
2030 + bcma_erom_skip_component(bus, eromptr);
2031 + return -ENODEV;
2032 + }
2033 +
2034 + if (match && ((match->manuf != BCMA_ANY_MANUF &&
2035 + match->manuf != core->id.manuf) ||
2036 + (match->id != BCMA_ANY_ID && match->id != core->id.id) ||
2037 + (match->rev != BCMA_ANY_REV && match->rev != core->id.rev) ||
2038 + (match->class != BCMA_ANY_CLASS && match->class != core->id.class)
2039 + )) {
2040 + bcma_erom_skip_component(bus, eromptr);
2041 + return -ENODEV;
2042 + }
2043 +
2044 + /* get & parse master ports */
2045 + for (i = 0; i < ports[0]; i++) {
2046 + s32 mst_port_d = bcma_erom_get_mst_port(bus, eromptr);
2047 + if (mst_port_d < 0)
2048 + return -EILSEQ;
2049 + }
2050 +
2051 + /* get & parse slave ports */
2052 + for (i = 0; i < ports[1]; i++) {
2053 + for (j = 0; ; j++) {
2054 + tmp = bcma_erom_get_addr_desc(bus, eromptr,
2055 + SCAN_ADDR_TYPE_SLAVE, i);
2056 + if (tmp < 0) {
2057 + /* no more entries for port _i_ */
2058 + /* pr_debug("erom: slave port %d "
2059 + * "has %d descriptors\n", i, j); */
2060 + break;
2061 + } else {
2062 + if (i == 0 && j == 0)
2063 + core->addr = tmp;
2064 + }
2065 + }
2066 + }
2067 +
2068 + /* get & parse master wrappers */
2069 + for (i = 0; i < wrappers[0]; i++) {
2070 + for (j = 0; ; j++) {
2071 + tmp = bcma_erom_get_addr_desc(bus, eromptr,
2072 + SCAN_ADDR_TYPE_MWRAP, i);
2073 + if (tmp < 0) {
2074 + /* no more entries for port _i_ */
2075 + /* pr_debug("erom: master wrapper %d "
2076 + * "has %d descriptors\n", i, j); */
2077 + break;
2078 + } else {
2079 + if (i == 0 && j == 0)
2080 + core->wrap = tmp;
2081 + }
2082 + }
2083 + }
2084 +
2085 + /* get & parse slave wrappers */
2086 + for (i = 0; i < wrappers[1]; i++) {
2087 + u8 hack = (ports[1] == 1) ? 0 : 1;
2088 + for (j = 0; ; j++) {
2089 + tmp = bcma_erom_get_addr_desc(bus, eromptr,
2090 + SCAN_ADDR_TYPE_SWRAP, i + hack);
2091 + if (tmp < 0) {
2092 + /* no more entries for port _i_ */
2093 + /* pr_debug("erom: master wrapper %d "
2094 + * has %d descriptors\n", i, j); */
2095 + break;
2096 + } else {
2097 + if (wrappers[0] == 0 && !i && !j)
2098 + core->wrap = tmp;
2099 + }
2100 + }
2101 + }
2102 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
2103 + core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
2104 + if (!core->io_addr)
2105 + return -ENOMEM;
2106 + core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
2107 + if (!core->io_wrap) {
2108 + iounmap(core->io_addr);
2109 + return -ENOMEM;
2110 + }
2111 + }
2112 + return 0;
2113 +}
2114 +
2115 +void bcma_init_bus(struct bcma_bus *bus)
2116 +{
2117 + s32 tmp;
2118 + struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
2119 +
2120 + if (bus->init_done)
2121 + return;
2122 +
2123 + INIT_LIST_HEAD(&bus->cores);
2124 + bus->nr_cores = 0;
2125 +
2126 + bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
2127 +
2128 + tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
2129 + chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
2130 + chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
2131 + chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
2132 + pr_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
2133 + chipinfo->id, chipinfo->rev, chipinfo->pkg);
2134 +
2135 + bus->init_done = true;
2136 +}
2137 +
2138 +int bcma_bus_scan(struct bcma_bus *bus)
2139 +{
2140 + u32 erombase;
2141 + u32 __iomem *eromptr, *eromend;
2142 +
2143 + int err, core_num = 0;
2144 +
2145 + bcma_init_bus(bus);
2146 +
2147 + erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
2148 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
2149 + eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
2150 + if (!eromptr)
2151 + return -ENOMEM;
2152 + } else {
2153 + eromptr = bus->mmio;
2154 + }
2155 +
2156 + eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
2157 +
2158 + bcma_scan_switch_core(bus, erombase);
2159 +
2160 + while (eromptr < eromend) {
2161 + struct bcma_device *other_core;
2162 + struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
2163 + if (!core)
2164 + return -ENOMEM;
2165 + INIT_LIST_HEAD(&core->list);
2166 + core->bus = bus;
2167 +
2168 + err = bcma_get_next_core(bus, &eromptr, NULL, core_num, core);
2169 + if (err < 0) {
2170 + kfree(core);
2171 + if (err == -ENODEV) {
2172 + core_num++;
2173 + continue;
2174 + } else if (err == -ENXIO) {
2175 + continue;
2176 + } else if (err == -ESPIPE) {
2177 + break;
2178 + }
2179 + return err;
2180 + }
2181 +
2182 + core->core_index = core_num++;
2183 + bus->nr_cores++;
2184 + other_core = bcma_find_core_reverse(bus, core->id.id);
2185 + core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
2186 +
2187 + pr_info("Core %d found: %s "
2188 + "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2189 + core->core_index, bcma_device_name(&core->id),
2190 + core->id.manuf, core->id.id, core->id.rev,
2191 + core->id.class);
2192 +
2193 + list_add(&core->list, &bus->cores);
2194 + }
2195 +
2196 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
2197 + iounmap(eromptr);
2198 +
2199 + return 0;
2200 +}
2201 +
2202 +int __init bcma_bus_scan_early(struct bcma_bus *bus,
2203 + struct bcma_device_id *match,
2204 + struct bcma_device *core)
2205 +{
2206 + u32 erombase;
2207 + u32 __iomem *eromptr, *eromend;
2208 +
2209 + int err = -ENODEV;
2210 + int core_num = 0;
2211 +
2212 + erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
2213 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
2214 + eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
2215 + if (!eromptr)
2216 + return -ENOMEM;
2217 + } else {
2218 + eromptr = bus->mmio;
2219 + }
2220 +
2221 + eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
2222 +
2223 + bcma_scan_switch_core(bus, erombase);
2224 +
2225 + while (eromptr < eromend) {
2226 + memset(core, 0, sizeof(*core));
2227 + INIT_LIST_HEAD(&core->list);
2228 + core->bus = bus;
2229 +
2230 + err = bcma_get_next_core(bus, &eromptr, match, core_num, core);
2231 + if (err == -ENODEV) {
2232 + core_num++;
2233 + continue;
2234 + } else if (err == -ENXIO)
2235 + continue;
2236 + else if (err == -ESPIPE)
2237 + break;
2238 + else if (err < 0)
2239 + return err;
2240 +
2241 + core->core_index = core_num++;
2242 + bus->nr_cores++;
2243 + pr_info("Core %d found: %s "
2244 + "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2245 + core->core_index, bcma_device_name(&core->id),
2246 + core->id.manuf, core->id.id, core->id.rev,
2247 + core->id.class);
2248 +
2249 + list_add(&core->list, &bus->cores);
2250 + err = 0;
2251 + break;
2252 + }
2253 +
2254 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
2255 + iounmap(eromptr);
2256 +
2257 + return err;
2258 +}
2259 --- /dev/null
2260 +++ b/drivers/bcma/scan.h
2261 @@ -0,0 +1,56 @@
2262 +#ifndef BCMA_SCAN_H_
2263 +#define BCMA_SCAN_H_
2264 +
2265 +#define BCMA_ADDR_BASE 0x18000000
2266 +#define BCMA_WRAP_BASE 0x18100000
2267 +
2268 +#define SCAN_ER_VALID 0x00000001
2269 +#define SCAN_ER_TAGX 0x00000006 /* we have to ignore 0x8 bit when checking tag for SCAN_ER_TAG_ADDR */
2270 +#define SCAN_ER_TAG 0x0000000E
2271 +#define SCAN_ER_TAG_CI 0x00000000
2272 +#define SCAN_ER_TAG_MP 0x00000002
2273 +#define SCAN_ER_TAG_ADDR 0x00000004
2274 +#define SCAN_ER_TAG_END 0x0000000E
2275 +#define SCAN_ER_BAD 0xFFFFFFFF
2276 +
2277 +#define SCAN_CIA_CLASS 0x000000F0
2278 +#define SCAN_CIA_CLASS_SHIFT 4
2279 +#define SCAN_CIA_ID 0x000FFF00
2280 +#define SCAN_CIA_ID_SHIFT 8
2281 +#define SCAN_CIA_MANUF 0xFFF00000
2282 +#define SCAN_CIA_MANUF_SHIFT 20
2283 +
2284 +#define SCAN_CIB_NMP 0x000001F0
2285 +#define SCAN_CIB_NMP_SHIFT 4
2286 +#define SCAN_CIB_NSP 0x00003E00
2287 +#define SCAN_CIB_NSP_SHIFT 9
2288 +#define SCAN_CIB_NMW 0x0007C000
2289 +#define SCAN_CIB_NMW_SHIFT 14
2290 +#define SCAN_CIB_NSW 0x00F80000
2291 +#define SCAN_CIB_NSW_SHIFT 17
2292 +#define SCAN_CIB_REV 0xFF000000
2293 +#define SCAN_CIB_REV_SHIFT 24
2294 +
2295 +#define SCAN_ADDR_AG32 0x00000008
2296 +#define SCAN_ADDR_SZ 0x00000030
2297 +#define SCAN_ADDR_SZ_SHIFT 4
2298 +#define SCAN_ADDR_SZ_4K 0x00000000
2299 +#define SCAN_ADDR_SZ_8K 0x00000010
2300 +#define SCAN_ADDR_SZ_16K 0x00000020
2301 +#define SCAN_ADDR_SZ_SZD 0x00000030
2302 +#define SCAN_ADDR_TYPE 0x000000C0
2303 +#define SCAN_ADDR_TYPE_SLAVE 0x00000000
2304 +#define SCAN_ADDR_TYPE_BRIDGE 0x00000040
2305 +#define SCAN_ADDR_TYPE_SWRAP 0x00000080
2306 +#define SCAN_ADDR_TYPE_MWRAP 0x000000C0
2307 +#define SCAN_ADDR_PORT 0x00000F00
2308 +#define SCAN_ADDR_PORT_SHIFT 8
2309 +#define SCAN_ADDR_ADDR 0xFFFFF000
2310 +
2311 +#define SCAN_ADDR_SZ_BASE 0x00001000 /* 4KB */
2312 +
2313 +#define SCAN_SIZE_SZ_ALIGN 0x00000FFF
2314 +#define SCAN_SIZE_SZ 0xFFFFF000
2315 +#define SCAN_SIZE_SG32 0x00000008
2316 +
2317 +#endif /* BCMA_SCAN_H_ */
2318 --- /dev/null
2319 +++ b/include/linux/bcma/bcma.h
2320 @@ -0,0 +1,307 @@
2321 +#ifndef LINUX_BCMA_H_
2322 +#define LINUX_BCMA_H_
2323 +
2324 +#include <linux/pci.h>
2325 +#include <linux/mod_devicetable.h>
2326 +
2327 +#include <linux/bcma/bcma_driver_chipcommon.h>
2328 +#include <linux/bcma/bcma_driver_pci.h>
2329 +#include <linux/bcma/bcma_driver_mips.h>
2330 +#include <linux/ssb/ssb.h> /* SPROM sharing */
2331 +
2332 +#include "bcma_regs.h"
2333 +
2334 +struct bcma_device;
2335 +struct bcma_bus;
2336 +
2337 +enum bcma_hosttype {
2338 + BCMA_HOSTTYPE_PCI,
2339 + BCMA_HOSTTYPE_SDIO,
2340 + BCMA_HOSTTYPE_SOC,
2341 +};
2342 +
2343 +struct bcma_chipinfo {
2344 + u16 id;
2345 + u8 rev;
2346 + u8 pkg;
2347 +};
2348 +
2349 +enum bcma_clkmode {
2350 + BCMA_CLKMODE_FAST,
2351 + BCMA_CLKMODE_DYNAMIC,
2352 +};
2353 +
2354 +struct bcma_host_ops {
2355 + u8 (*read8)(struct bcma_device *core, u16 offset);
2356 + u16 (*read16)(struct bcma_device *core, u16 offset);
2357 + u32 (*read32)(struct bcma_device *core, u16 offset);
2358 + void (*write8)(struct bcma_device *core, u16 offset, u8 value);
2359 + void (*write16)(struct bcma_device *core, u16 offset, u16 value);
2360 + void (*write32)(struct bcma_device *core, u16 offset, u32 value);
2361 +#ifdef CONFIG_BCMA_BLOCKIO
2362 + void (*block_read)(struct bcma_device *core, void *buffer,
2363 + size_t count, u16 offset, u8 reg_width);
2364 + void (*block_write)(struct bcma_device *core, const void *buffer,
2365 + size_t count, u16 offset, u8 reg_width);
2366 +#endif
2367 + /* Agent ops */
2368 + u32 (*aread32)(struct bcma_device *core, u16 offset);
2369 + void (*awrite32)(struct bcma_device *core, u16 offset, u32 value);
2370 +};
2371 +
2372 +/* Core manufacturers */
2373 +#define BCMA_MANUF_ARM 0x43B
2374 +#define BCMA_MANUF_MIPS 0x4A7
2375 +#define BCMA_MANUF_BCM 0x4BF
2376 +
2377 +/* Core class values. */
2378 +#define BCMA_CL_SIM 0x0
2379 +#define BCMA_CL_EROM 0x1
2380 +#define BCMA_CL_CORESIGHT 0x9
2381 +#define BCMA_CL_VERIF 0xB
2382 +#define BCMA_CL_OPTIMO 0xD
2383 +#define BCMA_CL_GEN 0xE
2384 +#define BCMA_CL_PRIMECELL 0xF
2385 +
2386 +/* Core-ID values. */
2387 +#define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
2388 +#define BCMA_CORE_INVALID 0x700
2389 +#define BCMA_CORE_CHIPCOMMON 0x800
2390 +#define BCMA_CORE_ILINE20 0x801
2391 +#define BCMA_CORE_SRAM 0x802
2392 +#define BCMA_CORE_SDRAM 0x803
2393 +#define BCMA_CORE_PCI 0x804
2394 +#define BCMA_CORE_MIPS 0x805
2395 +#define BCMA_CORE_ETHERNET 0x806
2396 +#define BCMA_CORE_V90 0x807
2397 +#define BCMA_CORE_USB11_HOSTDEV 0x808
2398 +#define BCMA_CORE_ADSL 0x809
2399 +#define BCMA_CORE_ILINE100 0x80A
2400 +#define BCMA_CORE_IPSEC 0x80B
2401 +#define BCMA_CORE_UTOPIA 0x80C
2402 +#define BCMA_CORE_PCMCIA 0x80D
2403 +#define BCMA_CORE_INTERNAL_MEM 0x80E
2404 +#define BCMA_CORE_MEMC_SDRAM 0x80F
2405 +#define BCMA_CORE_OFDM 0x810
2406 +#define BCMA_CORE_EXTIF 0x811
2407 +#define BCMA_CORE_80211 0x812
2408 +#define BCMA_CORE_PHY_A 0x813
2409 +#define BCMA_CORE_PHY_B 0x814
2410 +#define BCMA_CORE_PHY_G 0x815
2411 +#define BCMA_CORE_MIPS_3302 0x816
2412 +#define BCMA_CORE_USB11_HOST 0x817
2413 +#define BCMA_CORE_USB11_DEV 0x818
2414 +#define BCMA_CORE_USB20_HOST 0x819
2415 +#define BCMA_CORE_USB20_DEV 0x81A
2416 +#define BCMA_CORE_SDIO_HOST 0x81B
2417 +#define BCMA_CORE_ROBOSWITCH 0x81C
2418 +#define BCMA_CORE_PARA_ATA 0x81D
2419 +#define BCMA_CORE_SATA_XORDMA 0x81E
2420 +#define BCMA_CORE_ETHERNET_GBIT 0x81F
2421 +#define BCMA_CORE_PCIE 0x820
2422 +#define BCMA_CORE_PHY_N 0x821
2423 +#define BCMA_CORE_SRAM_CTL 0x822
2424 +#define BCMA_CORE_MINI_MACPHY 0x823
2425 +#define BCMA_CORE_ARM_1176 0x824
2426 +#define BCMA_CORE_ARM_7TDMI 0x825
2427 +#define BCMA_CORE_PHY_LP 0x826
2428 +#define BCMA_CORE_PMU 0x827
2429 +#define BCMA_CORE_PHY_SSN 0x828
2430 +#define BCMA_CORE_SDIO_DEV 0x829
2431 +#define BCMA_CORE_ARM_CM3 0x82A
2432 +#define BCMA_CORE_PHY_HT 0x82B
2433 +#define BCMA_CORE_MIPS_74K 0x82C
2434 +#define BCMA_CORE_MAC_GBIT 0x82D
2435 +#define BCMA_CORE_DDR12_MEM_CTL 0x82E
2436 +#define BCMA_CORE_PCIE_RC 0x82F /* PCIe Root Complex */
2437 +#define BCMA_CORE_OCP_OCP_BRIDGE 0x830
2438 +#define BCMA_CORE_SHARED_COMMON 0x831
2439 +#define BCMA_CORE_OCP_AHB_BRIDGE 0x832
2440 +#define BCMA_CORE_SPI_HOST 0x833
2441 +#define BCMA_CORE_I2S 0x834
2442 +#define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
2443 +#define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
2444 +#define BCMA_CORE_DEFAULT 0xFFF
2445 +
2446 +#define BCMA_MAX_NR_CORES 16
2447 +
2448 +struct bcma_device {
2449 + struct bcma_bus *bus;
2450 + struct bcma_device_id id;
2451 +
2452 + struct device dev;
2453 + struct device *dma_dev;
2454 +
2455 + unsigned int irq;
2456 + bool dev_registered;
2457 +
2458 + u8 core_index;
2459 + u8 core_unit;
2460 +
2461 + u32 addr;
2462 + u32 wrap;
2463 +
2464 + void __iomem *io_addr;
2465 + void __iomem *io_wrap;
2466 +
2467 + void *drvdata;
2468 + struct list_head list;
2469 +};
2470 +
2471 +static inline void *bcma_get_drvdata(struct bcma_device *core)
2472 +{
2473 + return core->drvdata;
2474 +}
2475 +static inline void bcma_set_drvdata(struct bcma_device *core, void *drvdata)
2476 +{
2477 + core->drvdata = drvdata;
2478 +}
2479 +
2480 +struct bcma_driver {
2481 + const char *name;
2482 + const struct bcma_device_id *id_table;
2483 +
2484 + int (*probe)(struct bcma_device *dev);
2485 + void (*remove)(struct bcma_device *dev);
2486 + int (*suspend)(struct bcma_device *dev);
2487 + int (*resume)(struct bcma_device *dev);
2488 + void (*shutdown)(struct bcma_device *dev);
2489 +
2490 + struct device_driver drv;
2491 +};
2492 +extern
2493 +int __bcma_driver_register(struct bcma_driver *drv, struct module *owner);
2494 +#define bcma_driver_register(drv) \
2495 + __bcma_driver_register(drv, THIS_MODULE)
2496 +
2497 +extern void bcma_driver_unregister(struct bcma_driver *drv);
2498 +
2499 +/* Set a fallback SPROM.
2500 + * See kdoc at the function definition for complete documentation. */
2501 +extern int bcma_arch_register_fallback_sprom(
2502 + int (*sprom_callback)(struct bcma_bus *bus,
2503 + struct ssb_sprom *out));
2504 +
2505 +struct bcma_bus {
2506 + /* The MMIO area. */
2507 + void __iomem *mmio;
2508 +
2509 + const struct bcma_host_ops *ops;
2510 +
2511 + enum bcma_hosttype hosttype;
2512 + union {
2513 + /* Pointer to the PCI bus (only for BCMA_HOSTTYPE_PCI) */
2514 + struct pci_dev *host_pci;
2515 + /* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
2516 + struct sdio_func *host_sdio;
2517 + };
2518 +
2519 + struct bcma_chipinfo chipinfo;
2520 +
2521 + struct bcma_device *mapped_core;
2522 + struct list_head cores;
2523 + u8 nr_cores;
2524 + u8 init_done:1;
2525 + u8 num;
2526 +
2527 + struct bcma_drv_cc drv_cc;
2528 + struct bcma_drv_pci drv_pci;
2529 + struct bcma_drv_mips drv_mips;
2530 +
2531 + /* We decided to share SPROM struct with SSB as long as we do not need
2532 + * any hacks for BCMA. This simplifies drivers code. */
2533 + struct ssb_sprom sprom;
2534 +};
2535 +
2536 +static inline u32 bcma_read8(struct bcma_device *core, u16 offset)
2537 +{
2538 + return core->bus->ops->read8(core, offset);
2539 +}
2540 +static inline u32 bcma_read16(struct bcma_device *core, u16 offset)
2541 +{
2542 + return core->bus->ops->read16(core, offset);
2543 +}
2544 +static inline u32 bcma_read32(struct bcma_device *core, u16 offset)
2545 +{
2546 + return core->bus->ops->read32(core, offset);
2547 +}
2548 +static inline
2549 +void bcma_write8(struct bcma_device *core, u16 offset, u32 value)
2550 +{
2551 + core->bus->ops->write8(core, offset, value);
2552 +}
2553 +static inline
2554 +void bcma_write16(struct bcma_device *core, u16 offset, u32 value)
2555 +{
2556 + core->bus->ops->write16(core, offset, value);
2557 +}
2558 +static inline
2559 +void bcma_write32(struct bcma_device *core, u16 offset, u32 value)
2560 +{
2561 + core->bus->ops->write32(core, offset, value);
2562 +}
2563 +#ifdef CONFIG_BCMA_BLOCKIO
2564 +static inline void bcma_block_read(struct bcma_device *core, void *buffer,
2565 + size_t count, u16 offset, u8 reg_width)
2566 +{
2567 + core->bus->ops->block_read(core, buffer, count, offset, reg_width);
2568 +}
2569 +static inline void bcma_block_write(struct bcma_device *core,
2570 + const void *buffer, size_t count,
2571 + u16 offset, u8 reg_width)
2572 +{
2573 + core->bus->ops->block_write(core, buffer, count, offset, reg_width);
2574 +}
2575 +#endif
2576 +static inline u32 bcma_aread32(struct bcma_device *core, u16 offset)
2577 +{
2578 + return core->bus->ops->aread32(core, offset);
2579 +}
2580 +static inline
2581 +void bcma_awrite32(struct bcma_device *core, u16 offset, u32 value)
2582 +{
2583 + core->bus->ops->awrite32(core, offset, value);
2584 +}
2585 +
2586 +static inline void bcma_mask32(struct bcma_device *cc, u16 offset, u32 mask)
2587 +{
2588 + bcma_write32(cc, offset, bcma_read32(cc, offset) & mask);
2589 +}
2590 +static inline void bcma_set32(struct bcma_device *cc, u16 offset, u32 set)
2591 +{
2592 + bcma_write32(cc, offset, bcma_read32(cc, offset) | set);
2593 +}
2594 +static inline void bcma_maskset32(struct bcma_device *cc,
2595 + u16 offset, u32 mask, u32 set)
2596 +{
2597 + bcma_write32(cc, offset, (bcma_read32(cc, offset) & mask) | set);
2598 +}
2599 +static inline void bcma_mask16(struct bcma_device *cc, u16 offset, u16 mask)
2600 +{
2601 + bcma_write16(cc, offset, bcma_read16(cc, offset) & mask);
2602 +}
2603 +static inline void bcma_set16(struct bcma_device *cc, u16 offset, u16 set)
2604 +{
2605 + bcma_write16(cc, offset, bcma_read16(cc, offset) | set);
2606 +}
2607 +static inline void bcma_maskset16(struct bcma_device *cc,
2608 + u16 offset, u16 mask, u16 set)
2609 +{
2610 + bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
2611 +}
2612 +
2613 +extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
2614 +extern bool bcma_core_is_enabled(struct bcma_device *core);
2615 +extern void bcma_core_disable(struct bcma_device *core, u32 flags);
2616 +extern int bcma_core_enable(struct bcma_device *core, u32 flags);
2617 +extern void bcma_core_set_clockmode(struct bcma_device *core,
2618 + enum bcma_clkmode clkmode);
2619 +extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
2620 + bool on);
2621 +#define BCMA_DMA_TRANSLATION_MASK 0xC0000000
2622 +#define BCMA_DMA_TRANSLATION_NONE 0x00000000
2623 +#define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
2624 +#define BCMA_DMA_TRANSLATION_DMA64_CMT 0x80000000 /* Client Mode Translation for 64-bit DMA */
2625 +extern u32 bcma_core_dma_translation(struct bcma_device *core);
2626 +
2627 +#endif /* LINUX_BCMA_H_ */
2628 --- /dev/null
2629 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
2630 @@ -0,0 +1,415 @@
2631 +#ifndef LINUX_BCMA_DRIVER_CC_H_
2632 +#define LINUX_BCMA_DRIVER_CC_H_
2633 +
2634 +/** ChipCommon core registers. **/
2635 +#define BCMA_CC_ID 0x0000
2636 +#define BCMA_CC_ID_ID 0x0000FFFF
2637 +#define BCMA_CC_ID_ID_SHIFT 0
2638 +#define BCMA_CC_ID_REV 0x000F0000
2639 +#define BCMA_CC_ID_REV_SHIFT 16
2640 +#define BCMA_CC_ID_PKG 0x00F00000
2641 +#define BCMA_CC_ID_PKG_SHIFT 20
2642 +#define BCMA_CC_ID_NRCORES 0x0F000000
2643 +#define BCMA_CC_ID_NRCORES_SHIFT 24
2644 +#define BCMA_CC_ID_TYPE 0xF0000000
2645 +#define BCMA_CC_ID_TYPE_SHIFT 28
2646 +#define BCMA_CC_CAP 0x0004 /* Capabilities */
2647 +#define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
2648 +#define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
2649 +#define BCMA_CC_CAP_UARTCLK 0x00000018 /* UART clock select */
2650 +#define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
2651 +#define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
2652 +#define BCMA_CC_CAP_EXTBUS 0x000000C0 /* External buses present */
2653 +#define BCMA_CC_CAP_FLASHT 0x00000700 /* Flash Type */
2654 +#define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
2655 +#define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
2656 +#define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
2657 +#define BCMA_CC_FLASHT_NFLASH 0x00000200
2658 +#define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
2659 +#define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
2660 +#define BCMA_PLLTYPE_NONE 0x00000000
2661 +#define BCMA_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */
2662 +#define BCMA_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */
2663 +#define BCMA_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */
2664 +#define BCMA_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */
2665 +#define BCMA_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */
2666 +#define BCMA_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */
2667 +#define BCMA_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */
2668 +#define BCMA_CC_CAP_PCTL 0x00040000 /* Power Control */
2669 +#define BCMA_CC_CAP_OTPS 0x00380000 /* OTP size */
2670 +#define BCMA_CC_CAP_OTPS_SHIFT 19
2671 +#define BCMA_CC_CAP_OTPS_BASE 5
2672 +#define BCMA_CC_CAP_JTAGM 0x00400000 /* JTAG master present */
2673 +#define BCMA_CC_CAP_BROM 0x00800000 /* Internal boot ROM active */
2674 +#define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
2675 +#define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
2676 +#define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
2677 +#define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
2678 +#define BCMA_CC_CORECTL 0x0008
2679 +#define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
2680 +#define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
2681 +#define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
2682 +#define BCMA_CC_BIST 0x000C
2683 +#define BCMA_CC_OTPS 0x0010 /* OTP status */
2684 +#define BCMA_CC_OTPS_PROGFAIL 0x80000000
2685 +#define BCMA_CC_OTPS_PROTECT 0x00000007
2686 +#define BCMA_CC_OTPS_HW_PROTECT 0x00000001
2687 +#define BCMA_CC_OTPS_SW_PROTECT 0x00000002
2688 +#define BCMA_CC_OTPS_CID_PROTECT 0x00000004
2689 +#define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */
2690 +#define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8
2691 +#define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */
2692 +#define BCMA_CC_OTPC 0x0014 /* OTP control */
2693 +#define BCMA_CC_OTPC_RECWAIT 0xFF000000
2694 +#define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
2695 +#define BCMA_CC_OTPC_PRW_SHIFT 8
2696 +#define BCMA_CC_OTPC_MAXFAIL 0x00000038
2697 +#define BCMA_CC_OTPC_VSEL 0x00000006
2698 +#define BCMA_CC_OTPC_SELVL 0x00000001
2699 +#define BCMA_CC_OTPP 0x0018 /* OTP prog */
2700 +#define BCMA_CC_OTPP_COL 0x000000FF
2701 +#define BCMA_CC_OTPP_ROW 0x0000FF00
2702 +#define BCMA_CC_OTPP_ROW_SHIFT 8
2703 +#define BCMA_CC_OTPP_READERR 0x10000000
2704 +#define BCMA_CC_OTPP_VALUE 0x20000000
2705 +#define BCMA_CC_OTPP_READ 0x40000000
2706 +#define BCMA_CC_OTPP_START 0x80000000
2707 +#define BCMA_CC_OTPP_BUSY 0x80000000
2708 +#define BCMA_CC_OTPL 0x001C /* OTP layout */
2709 +#define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
2710 +#define BCMA_CC_IRQSTAT 0x0020
2711 +#define BCMA_CC_IRQMASK 0x0024
2712 +#define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
2713 +#define BCMA_CC_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
2714 +#define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
2715 +#define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
2716 +#define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
2717 +#define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
2718 +#define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
2719 +#define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
2720 +#define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
2721 +#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
2722 +#define BCMA_CC_JCMD_START 0x80000000
2723 +#define BCMA_CC_JCMD_BUSY 0x80000000
2724 +#define BCMA_CC_JCMD_PAUSE 0x40000000
2725 +#define BCMA_CC_JCMD0_ACC_MASK 0x0000F000
2726 +#define BCMA_CC_JCMD0_ACC_IRDR 0x00000000
2727 +#define BCMA_CC_JCMD0_ACC_DR 0x00001000
2728 +#define BCMA_CC_JCMD0_ACC_IR 0x00002000
2729 +#define BCMA_CC_JCMD0_ACC_RESET 0x00003000
2730 +#define BCMA_CC_JCMD0_ACC_IRPDR 0x00004000
2731 +#define BCMA_CC_JCMD0_ACC_PDR 0x00005000
2732 +#define BCMA_CC_JCMD0_IRW_MASK 0x00000F00
2733 +#define BCMA_CC_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
2734 +#define BCMA_CC_JCMD_ACC_IRDR 0x00000000
2735 +#define BCMA_CC_JCMD_ACC_DR 0x00010000
2736 +#define BCMA_CC_JCMD_ACC_IR 0x00020000
2737 +#define BCMA_CC_JCMD_ACC_RESET 0x00030000
2738 +#define BCMA_CC_JCMD_ACC_IRPDR 0x00040000
2739 +#define BCMA_CC_JCMD_ACC_PDR 0x00050000
2740 +#define BCMA_CC_JCMD_IRW_MASK 0x00001F00
2741 +#define BCMA_CC_JCMD_IRW_SHIFT 8
2742 +#define BCMA_CC_JCMD_DRW_MASK 0x0000003F
2743 +#define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */
2744 +#define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */
2745 +#define BCMA_CC_JCTL 0x003C /* Rev >= 10 only */
2746 +#define BCMA_CC_JCTL_FORCE_CLK 4 /* Force clock */
2747 +#define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
2748 +#define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
2749 +#define BCMA_CC_FLASHCTL 0x0040
2750 +#define BCMA_CC_FLASHCTL_START 0x80000000
2751 +#define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
2752 +#define BCMA_CC_FLASHADDR 0x0044
2753 +#define BCMA_CC_FLASHDATA 0x0048
2754 +#define BCMA_CC_BCAST_ADDR 0x0050
2755 +#define BCMA_CC_BCAST_DATA 0x0054
2756 +#define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
2757 +#define BCMA_CC_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
2758 +#define BCMA_CC_GPIOIN 0x0060
2759 +#define BCMA_CC_GPIOOUT 0x0064
2760 +#define BCMA_CC_GPIOOUTEN 0x0068
2761 +#define BCMA_CC_GPIOCTL 0x006C
2762 +#define BCMA_CC_GPIOPOL 0x0070
2763 +#define BCMA_CC_GPIOIRQ 0x0074
2764 +#define BCMA_CC_WATCHDOG 0x0080
2765 +#define BCMA_CC_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
2766 +#define BCMA_CC_GPIOTIMER_OFFTIME 0x0000FFFF
2767 +#define BCMA_CC_GPIOTIMER_OFFTIME_SHIFT 0
2768 +#define BCMA_CC_GPIOTIMER_ONTIME 0xFFFF0000
2769 +#define BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16
2770 +#define BCMA_CC_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
2771 +#define BCMA_CC_CLOCK_N 0x0090
2772 +#define BCMA_CC_CLOCK_SB 0x0094
2773 +#define BCMA_CC_CLOCK_PCI 0x0098
2774 +#define BCMA_CC_CLOCK_M2 0x009C
2775 +#define BCMA_CC_CLOCK_MIPS 0x00A0
2776 +#define BCMA_CC_CLKDIV 0x00A4 /* Rev >= 3 only */
2777 +#define BCMA_CC_CLKDIV_SFLASH 0x0F000000
2778 +#define BCMA_CC_CLKDIV_SFLASH_SHIFT 24
2779 +#define BCMA_CC_CLKDIV_OTP 0x000F0000
2780 +#define BCMA_CC_CLKDIV_OTP_SHIFT 16
2781 +#define BCMA_CC_CLKDIV_JTAG 0x00000F00
2782 +#define BCMA_CC_CLKDIV_JTAG_SHIFT 8
2783 +#define BCMA_CC_CLKDIV_UART 0x000000FF
2784 +#define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
2785 +#define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
2786 +#define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
2787 +#define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
2788 +#define BCMA_CC_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */
2789 +#define BCMA_CC_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */
2790 +#define BCMA_CC_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
2791 +#define BCMA_CC_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */
2792 +#define BCMA_CC_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
2793 +#define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
2794 +#define BCMA_CC_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
2795 +#define BCMA_CC_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
2796 +#define BCMA_CC_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
2797 +#define BCMA_CC_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
2798 +#define BCMA_CC_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
2799 +#define BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT 16
2800 +#define BCMA_CC_SYSCLKCTL 0x00C0 /* Rev >= 3 only */
2801 +#define BCMA_CC_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */
2802 +#define BCMA_CC_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */
2803 +#define BCMA_CC_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */
2804 +#define BCMA_CC_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */
2805 +#define BCMA_CC_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */
2806 +#define BCMA_CC_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
2807 +#define BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16
2808 +#define BCMA_CC_CLKSTSTR 0x00C4 /* Rev >= 3 only */
2809 +#define BCMA_CC_EROM 0x00FC
2810 +#define BCMA_CC_PCMCIA_CFG 0x0100
2811 +#define BCMA_CC_PCMCIA_MEMWAIT 0x0104
2812 +#define BCMA_CC_PCMCIA_ATTRWAIT 0x0108
2813 +#define BCMA_CC_PCMCIA_IOWAIT 0x010C
2814 +#define BCMA_CC_IDE_CFG 0x0110
2815 +#define BCMA_CC_IDE_MEMWAIT 0x0114
2816 +#define BCMA_CC_IDE_ATTRWAIT 0x0118
2817 +#define BCMA_CC_IDE_IOWAIT 0x011C
2818 +#define BCMA_CC_PROG_CFG 0x0120
2819 +#define BCMA_CC_PROG_WAITCNT 0x0124
2820 +#define BCMA_CC_FLASH_CFG 0x0128
2821 +#define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
2822 +#define BCMA_CC_FLASH_WAITCNT 0x012C
2823 +#define BCMA_CC_SROM_CONTROL 0x0190
2824 +#define BCMA_CC_SROM_CONTROL_START 0x80000000
2825 +#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
2826 +#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
2827 +#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
2828 +#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
2829 +#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
2830 +#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
2831 +#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
2832 +#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
2833 +#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
2834 +#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
2835 +#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
2836 +#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
2837 +#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
2838 +#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
2839 +/* 0x1E0 is defined as shared BCMA_CLKCTLST */
2840 +#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
2841 +#define BCMA_CC_UART0_DATA 0x0300
2842 +#define BCMA_CC_UART0_IMR 0x0304
2843 +#define BCMA_CC_UART0_FCR 0x0308
2844 +#define BCMA_CC_UART0_LCR 0x030C
2845 +#define BCMA_CC_UART0_MCR 0x0310
2846 +#define BCMA_CC_UART0_LSR 0x0314
2847 +#define BCMA_CC_UART0_MSR 0x0318
2848 +#define BCMA_CC_UART0_SCRATCH 0x031C
2849 +#define BCMA_CC_UART1_DATA 0x0400
2850 +#define BCMA_CC_UART1_IMR 0x0404
2851 +#define BCMA_CC_UART1_FCR 0x0408
2852 +#define BCMA_CC_UART1_LCR 0x040C
2853 +#define BCMA_CC_UART1_MCR 0x0410
2854 +#define BCMA_CC_UART1_LSR 0x0414
2855 +#define BCMA_CC_UART1_MSR 0x0418
2856 +#define BCMA_CC_UART1_SCRATCH 0x041C
2857 +/* PMU registers (rev >= 20) */
2858 +#define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
2859 +#define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
2860 +#define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
2861 +#define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
2862 +#define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
2863 +#define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
2864 +#define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
2865 +#define BCMA_CC_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
2866 +#define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2
2867 +#define BCMA_CC_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
2868 +#define BCMA_CC_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
2869 +#define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
2870 +#define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
2871 +#define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
2872 +#define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
2873 +#define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
2874 +#define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
2875 +#define BCMA_CC_PMU_STAT_HAVEHT 0x00000004 /* HT available */
2876 +#define BCMA_CC_PMU_STAT_RESINIT 0x00000003 /* Res init */
2877 +#define BCMA_CC_PMU_RES_STAT 0x060C /* PMU res status */
2878 +#define BCMA_CC_PMU_RES_PEND 0x0610 /* PMU res pending */
2879 +#define BCMA_CC_PMU_TIMER 0x0614 /* PMU timer */
2880 +#define BCMA_CC_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
2881 +#define BCMA_CC_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
2882 +#define BCMA_CC_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
2883 +#define BCMA_CC_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
2884 +#define BCMA_CC_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
2885 +#define BCMA_CC_PMU_RES_TIMER 0x062C /* PMU res timer */
2886 +#define BCMA_CC_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
2887 +#define BCMA_CC_PMU_WATCHDOG 0x0634 /* PMU watchdog */
2888 +#define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
2889 +#define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
2890 +#define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
2891 +#define BCMA_CC_CHIPCTL_ADDR 0x0650
2892 +#define BCMA_CC_CHIPCTL_DATA 0x0654
2893 +#define BCMA_CC_REGCTL_ADDR 0x0658
2894 +#define BCMA_CC_REGCTL_DATA 0x065C
2895 +#define BCMA_CC_PLLCTL_ADDR 0x0660
2896 +#define BCMA_CC_PLLCTL_DATA 0x0664
2897 +#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
2898 +
2899 +/* Divider allocation in 4716/47162/5356 */
2900 +#define BCMA_CC_PMU5_MAINPLL_CPU 1
2901 +#define BCMA_CC_PMU5_MAINPLL_MEM 2
2902 +#define BCMA_CC_PMU5_MAINPLL_SSB 3
2903 +
2904 +/* PLL usage in 4716/47162 */
2905 +#define BCMA_CC_PMU4716_MAINPLL_PLL0 12
2906 +
2907 +/* PLL usage in 5356/5357 */
2908 +#define BCMA_CC_PMU5356_MAINPLL_PLL0 0
2909 +#define BCMA_CC_PMU5357_MAINPLL_PLL0 0
2910 +
2911 +/* 4706 PMU */
2912 +#define BCMA_CC_PMU4706_MAINPLL_PLL0 0
2913 +
2914 +/* ALP clock on pre-PMU chips */
2915 +#define BCMA_CC_PMU_ALP_CLOCK 20000000
2916 +/* HT clock for systems with PMU-enabled chipcommon */
2917 +#define BCMA_CC_PMU_HT_CLOCK 80000000
2918 +
2919 +/* PMU rev 5 (& 6) */
2920 +#define BCMA_CC_PPL_P1P2_OFF 0
2921 +#define BCMA_CC_PPL_P1_MASK 0x0f000000
2922 +#define BCMA_CC_PPL_P1_SHIFT 24
2923 +#define BCMA_CC_PPL_P2_MASK 0x00f00000
2924 +#define BCMA_CC_PPL_P2_SHIFT 20
2925 +#define BCMA_CC_PPL_M14_OFF 1
2926 +#define BCMA_CC_PPL_MDIV_MASK 0x000000ff
2927 +#define BCMA_CC_PPL_MDIV_WIDTH 8
2928 +#define BCMA_CC_PPL_NM5_OFF 2
2929 +#define BCMA_CC_PPL_NDIV_MASK 0xfff00000
2930 +#define BCMA_CC_PPL_NDIV_SHIFT 20
2931 +#define BCMA_CC_PPL_FMAB_OFF 3
2932 +#define BCMA_CC_PPL_MRAT_MASK 0xf0000000
2933 +#define BCMA_CC_PPL_MRAT_SHIFT 28
2934 +#define BCMA_CC_PPL_ABRAT_MASK 0x08000000
2935 +#define BCMA_CC_PPL_ABRAT_SHIFT 27
2936 +#define BCMA_CC_PPL_FDIV_MASK 0x07ffffff
2937 +#define BCMA_CC_PPL_PLLCTL_OFF 4
2938 +#define BCMA_CC_PPL_PCHI_OFF 5
2939 +#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
2940 +
2941 +/* BCM4331 ChipControl numbers. */
2942 +#define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
2943 +#define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
2944 +#define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */
2945 +#define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */
2946 +#define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */
2947 +#define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */
2948 +#define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */
2949 +#define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout */
2950 +#define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */
2951 +#define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
2952 +#define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
2953 +#define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
2954 +#define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
2955 +#define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
2956 +
2957 +/* Data for the PMU, if available.
2958 + * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
2959 + */
2960 +struct bcma_chipcommon_pmu {
2961 + u8 rev; /* PMU revision */
2962 + u32 crystalfreq; /* The active crystal frequency (in kHz) */
2963 +};
2964 +
2965 +#ifdef CONFIG_BCMA_DRIVER_MIPS
2966 +struct bcma_pflash {
2967 + u8 buswidth;
2968 + u32 window;
2969 + u32 window_size;
2970 +};
2971 +
2972 +struct bcma_serial_port {
2973 + void *regs;
2974 + unsigned long clockspeed;
2975 + unsigned int irq;
2976 + unsigned int baud_base;
2977 + unsigned int reg_shift;
2978 +};
2979 +#endif /* CONFIG_BCMA_DRIVER_MIPS */
2980 +
2981 +struct bcma_drv_cc {
2982 + struct bcma_device *core;
2983 + u32 status;
2984 + u32 capabilities;
2985 + u32 capabilities_ext;
2986 + u8 setup_done:1;
2987 + /* Fast Powerup Delay constant */
2988 + u16 fast_pwrup_delay;
2989 + struct bcma_chipcommon_pmu pmu;
2990 +#ifdef CONFIG_BCMA_DRIVER_MIPS
2991 + struct bcma_pflash pflash;
2992 +
2993 + int nr_serial_ports;
2994 + struct bcma_serial_port serial_ports[4];
2995 +#endif /* CONFIG_BCMA_DRIVER_MIPS */
2996 +};
2997 +
2998 +/* Register access */
2999 +#define bcma_cc_read32(cc, offset) \
3000 + bcma_read32((cc)->core, offset)
3001 +#define bcma_cc_write32(cc, offset, val) \
3002 + bcma_write32((cc)->core, offset, val)
3003 +
3004 +#define bcma_cc_mask32(cc, offset, mask) \
3005 + bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask))
3006 +#define bcma_cc_set32(cc, offset, set) \
3007 + bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set))
3008 +#define bcma_cc_maskset32(cc, offset, mask, set) \
3009 + bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
3010 +
3011 +extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
3012 +
3013 +extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
3014 +extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
3015 +
3016 +void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
3017 +
3018 +extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
3019 + u32 ticks);
3020 +
3021 +void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
3022 +
3023 +u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
3024 +
3025 +/* Chipcommon GPIO pin access. */
3026 +u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask);
3027 +u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value);
3028 +u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value);
3029 +u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
3030 +u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
3031 +u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
3032 +
3033 +/* PMU support */
3034 +extern void bcma_pmu_init(struct bcma_drv_cc *cc);
3035 +
3036 +extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
3037 + u32 value);
3038 +extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset,
3039 + u32 mask, u32 set);
3040 +extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
3041 + u32 offset, u32 mask, u32 set);
3042 +extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
3043 + u32 offset, u32 mask, u32 set);
3044 +
3045 +#endif /* LINUX_BCMA_DRIVER_CC_H_ */
3046 --- /dev/null
3047 +++ b/include/linux/bcma/bcma_driver_pci.h
3048 @@ -0,0 +1,214 @@
3049 +#ifndef LINUX_BCMA_DRIVER_PCI_H_
3050 +#define LINUX_BCMA_DRIVER_PCI_H_
3051 +
3052 +#include <linux/types.h>
3053 +
3054 +struct pci_dev;
3055 +
3056 +/** PCI core registers. **/
3057 +#define BCMA_CORE_PCI_CTL 0x0000 /* PCI Control */
3058 +#define BCMA_CORE_PCI_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
3059 +#define BCMA_CORE_PCI_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */
3060 +#define BCMA_CORE_PCI_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
3061 +#define BCMA_CORE_PCI_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */
3062 +#define BCMA_CORE_PCI_ARBCTL 0x0010 /* PCI Arbiter Control */
3063 +#define BCMA_CORE_PCI_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */
3064 +#define BCMA_CORE_PCI_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */
3065 +#define BCMA_CORE_PCI_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus */
3066 +#define BCMA_CORE_PCI_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */
3067 +#define BCMA_CORE_PCI_ARBCTL_PARKID_4710 0x00000002 /* 4710 */
3068 +#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT0 0x00000004 /* External requestor 0 */
3069 +#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT1 0x00000006 /* External requestor 1 */
3070 +#define BCMA_CORE_PCI_ISTAT 0x0020 /* Interrupt status */
3071 +#define BCMA_CORE_PCI_ISTAT_INTA 0x00000001 /* PCI INTA# */
3072 +#define BCMA_CORE_PCI_ISTAT_INTB 0x00000002 /* PCI INTB# */
3073 +#define BCMA_CORE_PCI_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */
3074 +#define BCMA_CORE_PCI_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */
3075 +#define BCMA_CORE_PCI_ISTAT_PME 0x00000010 /* PCI PME# */
3076 +#define BCMA_CORE_PCI_IMASK 0x0024 /* Interrupt mask */
3077 +#define BCMA_CORE_PCI_IMASK_INTA 0x00000001 /* PCI INTA# */
3078 +#define BCMA_CORE_PCI_IMASK_INTB 0x00000002 /* PCI INTB# */
3079 +#define BCMA_CORE_PCI_IMASK_SERR 0x00000004 /* PCI SERR# */
3080 +#define BCMA_CORE_PCI_IMASK_PERR 0x00000008 /* PCI PERR# */
3081 +#define BCMA_CORE_PCI_IMASK_PME 0x00000010 /* PCI PME# */
3082 +#define BCMA_CORE_PCI_MBOX 0x0028 /* Backplane to PCI Mailbox */
3083 +#define BCMA_CORE_PCI_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */
3084 +#define BCMA_CORE_PCI_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */
3085 +#define BCMA_CORE_PCI_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */
3086 +#define BCMA_CORE_PCI_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */
3087 +#define BCMA_CORE_PCI_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */
3088 +#define BCMA_CORE_PCI_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */
3089 +#define BCMA_CORE_PCI_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */
3090 +#define BCMA_CORE_PCI_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */
3091 +#define BCMA_CORE_PCI_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */
3092 +#define BCMA_CORE_PCI_BCAST_ADDR_MASK 0x000000FF
3093 +#define BCMA_CORE_PCI_BCAST_DATA 0x0054 /* Backplane Broadcast Data */
3094 +#define BCMA_CORE_PCI_GPIO_IN 0x0060 /* rev >= 2 only */
3095 +#define BCMA_CORE_PCI_GPIO_OUT 0x0064 /* rev >= 2 only */
3096 +#define BCMA_CORE_PCI_GPIO_ENABLE 0x0068 /* rev >= 2 only */
3097 +#define BCMA_CORE_PCI_GPIO_CTL 0x006C /* rev >= 2 only */
3098 +#define BCMA_CORE_PCI_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */
3099 +#define BCMA_CORE_PCI_SBTOPCI0_MASK 0xFC000000
3100 +#define BCMA_CORE_PCI_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */
3101 +#define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
3102 +#define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
3103 +#define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
3104 +#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
3105 +#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
3106 +#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */
3107 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
3108 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2
3109 +#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
3110 +#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
3111 +#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */
3112 +#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */
3113 +#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */
3114 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
3115 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
3116 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
3117 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
3118 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
3119 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
3120 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
3121 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
3122 +#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */
3123 +#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */
3124 +#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */
3125 +#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
3126 +#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
3127 +#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
3128 +#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
3129 +#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
3130 +#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */
3131 +#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */
3132 +#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */
3133 +#define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
3134 +#define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
3135 +#define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
3136 +#define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
3137 +#define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
3138 +
3139 +/* SBtoPCIx */
3140 +#define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
3141 +#define BCMA_CORE_PCI_SBTOPCI_IO 0x00000001
3142 +#define BCMA_CORE_PCI_SBTOPCI_CFG0 0x00000002
3143 +#define BCMA_CORE_PCI_SBTOPCI_CFG1 0x00000003
3144 +#define BCMA_CORE_PCI_SBTOPCI_PREF 0x00000004 /* Prefetch enable */
3145 +#define BCMA_CORE_PCI_SBTOPCI_BURST 0x00000008 /* Burst enable */
3146 +#define BCMA_CORE_PCI_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */
3147 +#define BCMA_CORE_PCI_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */
3148 +#define BCMA_CORE_PCI_SBTOPCI_RC_READ 0x00000000 /* Memory read */
3149 +#define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
3150 +#define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
3151 +
3152 +/* PCIE protocol PHY diagnostic registers */
3153 +#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */
3154 +#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */
3155 +#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */
3156 +#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
3157 +#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
3158 +#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
3159 +#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
3160 +#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */
3161 +#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */
3162 +#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */
3163 +#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
3164 +#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
3165 +#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */
3166 +#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
3167 +#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
3168 +#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
3169 +#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
3170 +
3171 +/* PCIE protocol DLLP diagnostic registers */
3172 +#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */
3173 +#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */
3174 +#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */
3175 +#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)
3176 +#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
3177 +#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
3178 +#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
3179 +#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
3180 +#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
3181 +#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */
3182 +#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
3183 +#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
3184 +#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
3185 +#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
3186 +#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
3187 +#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
3188 +#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
3189 +#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
3190 +#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */
3191 +#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
3192 +#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */
3193 +#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */
3194 +#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
3195 +
3196 +/* SERDES RX registers */
3197 +#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */
3198 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
3199 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
3200 +#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */
3201 +#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */
3202 +#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */
3203 +
3204 +/* SERDES PLL registers */
3205 +#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */
3206 +#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
3207 +
3208 +/* PCIcore specific boardflags */
3209 +#define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
3210 +
3211 +/* PCIE Config space accessing MACROS */
3212 +#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */
3213 +#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */
3214 +#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */
3215 +#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */
3216 +
3217 +#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */
3218 +#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */
3219 +#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
3220 +#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
3221 +
3222 +/* PCIE Root Capability Register bits (Host mode only) */
3223 +#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
3224 +
3225 +struct bcma_drv_pci;
3226 +
3227 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
3228 +struct bcma_drv_pci_host {
3229 + struct bcma_drv_pci *pdev;
3230 +
3231 + u32 host_cfg_addr;
3232 + spinlock_t cfgspace_lock;
3233 +
3234 + struct pci_controller pci_controller;
3235 + struct pci_ops pci_ops;
3236 + struct resource mem_resource;
3237 + struct resource io_resource;
3238 +};
3239 +#endif
3240 +
3241 +struct bcma_drv_pci {
3242 + struct bcma_device *core;
3243 + u8 setup_done:1;
3244 + u8 hostmode:1;
3245 +
3246 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
3247 + struct bcma_drv_pci_host *host_controller;
3248 +#endif
3249 +};
3250 +
3251 +/* Register access */
3252 +#define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
3253 +#define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
3254 +
3255 +extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc);
3256 +extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
3257 + struct bcma_device *core, bool enable);
3258 +
3259 +extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
3260 +extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
3261 +
3262 +#endif /* LINUX_BCMA_DRIVER_PCI_H_ */
3263 --- /dev/null
3264 +++ b/include/linux/bcma/bcma_regs.h
3265 @@ -0,0 +1,86 @@
3266 +#ifndef LINUX_BCMA_REGS_H_
3267 +#define LINUX_BCMA_REGS_H_
3268 +
3269 +/* Some single registers are shared between many cores */
3270 +/* BCMA_CLKCTLST: ChipCommon (rev >= 20), PCIe, 80211 */
3271 +#define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
3272 +#define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
3273 +#define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
3274 +#define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
3275 +#define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
3276 +#define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
3277 +#define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
3278 +#define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
3279 +#define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
3280 +#define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
3281 +#define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
3282 +#define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
3283 +#define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
3284 +/* Is there any BCM4328 on BCMA bus? */
3285 +#define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
3286 +#define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
3287 +
3288 +/* Agent registers (common for every core) */
3289 +#define BCMA_IOCTL 0x0408 /* IO control */
3290 +#define BCMA_IOCTL_CLK 0x0001
3291 +#define BCMA_IOCTL_FGC 0x0002
3292 +#define BCMA_IOCTL_CORE_BITS 0x3FFC
3293 +#define BCMA_IOCTL_PME_EN 0x4000
3294 +#define BCMA_IOCTL_BIST_EN 0x8000
3295 +#define BCMA_IOST 0x0500 /* IO status */
3296 +#define BCMA_IOST_CORE_BITS 0x0FFF
3297 +#define BCMA_IOST_DMA64 0x1000
3298 +#define BCMA_IOST_GATED_CLK 0x2000
3299 +#define BCMA_IOST_BIST_ERROR 0x4000
3300 +#define BCMA_IOST_BIST_DONE 0x8000
3301 +#define BCMA_RESET_CTL 0x0800
3302 +#define BCMA_RESET_CTL_RESET 0x0001
3303 +
3304 +/* BCMA PCI config space registers. */
3305 +#define BCMA_PCI_PMCSR 0x44
3306 +#define BCMA_PCI_PE 0x100
3307 +#define BCMA_PCI_BAR0_WIN 0x80 /* Backplane address space 0 */
3308 +#define BCMA_PCI_BAR1_WIN 0x84 /* Backplane address space 1 */
3309 +#define BCMA_PCI_SPROMCTL 0x88 /* SPROM control */
3310 +#define BCMA_PCI_SPROMCTL_WE 0x10 /* SPROM write enable */
3311 +#define BCMA_PCI_BAR1_CONTROL 0x8c /* Address space 1 burst control */
3312 +#define BCMA_PCI_IRQS 0x90 /* PCI interrupts */
3313 +#define BCMA_PCI_IRQMASK 0x94 /* PCI IRQ control and mask (pcirev >= 6 only) */
3314 +#define BCMA_PCI_BACKPLANE_IRQS 0x98 /* Backplane Interrupts */
3315 +#define BCMA_PCI_BAR0_WIN2 0xAC
3316 +#define BCMA_PCI_GPIO_IN 0xB0 /* GPIO Input (pcirev >= 3 only) */
3317 +#define BCMA_PCI_GPIO_OUT 0xB4 /* GPIO Output (pcirev >= 3 only) */
3318 +#define BCMA_PCI_GPIO_OUT_ENABLE 0xB8 /* GPIO Output Enable/Disable (pcirev >= 3 only) */
3319 +#define BCMA_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
3320 +#define BCMA_PCI_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
3321 +#define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
3322 +#define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
3323 +
3324 +/* SiliconBackplane Address Map.
3325 + * All regions may not exist on all chips.
3326 + */
3327 +#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */
3328 +#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
3329 +#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024)
3330 +#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
3331 +#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
3332 +#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */
3333 +
3334 +
3335 +#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
3336 +#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */
3337 +#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
3338 +#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2
3339 + * (2 ZettaBytes), low 32 bits
3340 + */
3341 +#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2
3342 + * (2 ZettaBytes), high 32 bits
3343 + */
3344 +
3345 +#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
3346 +#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
3347 +#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2
3348 + * (2 ZettaBytes), high 32 bits
3349 + */
3350 +
3351 +#endif /* LINUX_BCMA_REGS_H_ */
3352 --- a/include/linux/mod_devicetable.h
3353 +++ b/include/linux/mod_devicetable.h
3354 @@ -382,6 +382,23 @@ struct ssb_device_id {
3355 #define SSB_ANY_ID 0xFFFF
3356 #define SSB_ANY_REV 0xFF
3357
3358 +/* Broadcom's specific AMBA core, see drivers/bcma/ */
3359 +struct bcma_device_id {
3360 + __u16 manuf;
3361 + __u16 id;
3362 + __u8 rev;
3363 + __u8 class;
3364 +};
3365 +#define BCMA_CORE(_manuf, _id, _rev, _class) \
3366 + { .manuf = _manuf, .id = _id, .rev = _rev, .class = _class, }
3367 +#define BCMA_CORETABLE_END \
3368 + { 0, },
3369 +
3370 +#define BCMA_ANY_MANUF 0xFFFF
3371 +#define BCMA_ANY_ID 0xFFFF
3372 +#define BCMA_ANY_REV 0xFF
3373 +#define BCMA_ANY_CLASS 0xFF
3374 +
3375 struct virtio_device_id {
3376 __u32 device;
3377 __u32 vendor;
3378 --- a/scripts/mod/file2alias.c
3379 +++ b/scripts/mod/file2alias.c
3380 @@ -633,6 +633,24 @@ static int do_ssb_entry(const char *file
3381 return 1;
3382 }
3383
3384 +/* Looks like: bcma:mNidNrevNclN. */
3385 +static int do_bcma_entry(const char *filename,
3386 + struct bcma_device_id *id, char *alias)
3387 +{
3388 + id->manuf = TO_NATIVE(id->manuf);
3389 + id->id = TO_NATIVE(id->id);
3390 + id->rev = TO_NATIVE(id->rev);
3391 + id->class = TO_NATIVE(id->class);
3392 +
3393 + strcpy(alias, "bcma:");
3394 + ADD(alias, "m", id->manuf != BCMA_ANY_MANUF, id->manuf);
3395 + ADD(alias, "id", id->id != BCMA_ANY_ID, id->id);
3396 + ADD(alias, "rev", id->rev != BCMA_ANY_REV, id->rev);
3397 + ADD(alias, "cl", id->class != BCMA_ANY_CLASS, id->class);
3398 + add_wildcard(alias);
3399 + return 1;
3400 +}
3401 +
3402 /* Looks like: virtio:dNvN */
3403 static int do_virtio_entry(const char *filename, struct virtio_device_id *id,
3404 char *alias)
3405 @@ -854,6 +872,10 @@ void handle_moddevtable(struct module *m
3406 do_table(symval, sym->st_size,
3407 sizeof(struct ssb_device_id), "ssb",
3408 do_ssb_entry, mod);
3409 + else if (sym_is(symname, "__mod_bcma_device_table"))
3410 + do_table(symval, sym->st_size,
3411 + sizeof(struct bcma_device_id), "bcma",
3412 + do_bcma_entry, mod);
3413 else if (sym_is(symname, "__mod_virtio_device_table"))
3414 do_table(symval, sym->st_size,
3415 sizeof(struct virtio_device_id), "virtio",
3416 --- /dev/null
3417 +++ b/drivers/bcma/sprom.c
3418 @@ -0,0 +1,450 @@
3419 +/*
3420 + * Broadcom specific AMBA
3421 + * SPROM reading
3422 + *
3423 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
3424 + *
3425 + * Licensed under the GNU/GPL. See COPYING for details.
3426 + */
3427 +
3428 +#include "bcma_private.h"
3429 +
3430 +#include <linux/bcma/bcma.h>
3431 +#include <linux/bcma/bcma_regs.h>
3432 +#include <linux/pci.h>
3433 +#include <linux/io.h>
3434 +#include <linux/dma-mapping.h>
3435 +#include <linux/slab.h>
3436 +
3437 +static int(*get_fallback_sprom)(struct bcma_bus *dev, struct ssb_sprom *out);
3438 +
3439 +/**
3440 + * bcma_arch_register_fallback_sprom - Registers a method providing a
3441 + * fallback SPROM if no SPROM is found.
3442 + *
3443 + * @sprom_callback: The callback function.
3444 + *
3445 + * With this function the architecture implementation may register a
3446 + * callback handler which fills the SPROM data structure. The fallback is
3447 + * used for PCI based BCMA devices, where no valid SPROM can be found
3448 + * in the shadow registers and to provide the SPROM for SoCs where BCMA is
3449 + * to controll the system bus.
3450 + *
3451 + * This function is useful for weird architectures that have a half-assed
3452 + * BCMA device hardwired to their PCI bus.
3453 + *
3454 + * This function is available for architecture code, only. So it is not
3455 + * exported.
3456 + */
3457 +int bcma_arch_register_fallback_sprom(int (*sprom_callback)(struct bcma_bus *bus,
3458 + struct ssb_sprom *out))
3459 +{
3460 + if (get_fallback_sprom)
3461 + return -EEXIST;
3462 + get_fallback_sprom = sprom_callback;
3463 +
3464 + return 0;
3465 +}
3466 +
3467 +static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus,
3468 + struct ssb_sprom *out)
3469 +{
3470 + int err;
3471 +
3472 + if (!get_fallback_sprom) {
3473 + err = -ENOENT;
3474 + goto fail;
3475 + }
3476 +
3477 + err = get_fallback_sprom(bus, out);
3478 + if (err)
3479 + goto fail;
3480 +
3481 + pr_debug("Using SPROM revision %d provided by"
3482 + " platform.\n", bus->sprom.revision);
3483 + return 0;
3484 +fail:
3485 + pr_warning("Using fallback SPROM failed (err %d)\n", err);
3486 + return err;
3487 +}
3488 +
3489 +/**************************************************
3490 + * R/W ops.
3491 + **************************************************/
3492 +
3493 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
3494 +{
3495 + int i;
3496 + for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
3497 + sprom[i] = bcma_read16(bus->drv_cc.core,
3498 + offset + (i * 2));
3499 +}
3500 +
3501 +/**************************************************
3502 + * Validation.
3503 + **************************************************/
3504 +
3505 +static inline u8 bcma_crc8(u8 crc, u8 data)
3506 +{
3507 + /* Polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 */
3508 + static const u8 t[] = {
3509 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
3510 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
3511 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
3512 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
3513 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
3514 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
3515 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
3516 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
3517 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
3518 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
3519 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
3520 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
3521 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
3522 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
3523 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
3524 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
3525 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
3526 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
3527 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
3528 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
3529 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
3530 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
3531 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
3532 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
3533 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
3534 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
3535 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
3536 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
3537 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
3538 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
3539 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
3540 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
3541 + };
3542 + return t[crc ^ data];
3543 +}
3544 +
3545 +static u8 bcma_sprom_crc(const u16 *sprom)
3546 +{
3547 + int word;
3548 + u8 crc = 0xFF;
3549 +
3550 + for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
3551 + crc = bcma_crc8(crc, sprom[word] & 0x00FF);
3552 + crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
3553 + }
3554 + crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
3555 + crc ^= 0xFF;
3556 +
3557 + return crc;
3558 +}
3559 +
3560 +static int bcma_sprom_check_crc(const u16 *sprom)
3561 +{
3562 + u8 crc;
3563 + u8 expected_crc;
3564 + u16 tmp;
3565 +
3566 + crc = bcma_sprom_crc(sprom);
3567 + tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
3568 + expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
3569 + if (crc != expected_crc)
3570 + return -EPROTO;
3571 +
3572 + return 0;
3573 +}
3574 +
3575 +static int bcma_sprom_valid(const u16 *sprom)
3576 +{
3577 + u16 revision;
3578 + int err;
3579 +
3580 + err = bcma_sprom_check_crc(sprom);
3581 + if (err)
3582 + return err;
3583 +
3584 + revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
3585 + if (revision != 8 && revision != 9) {
3586 + pr_err("Unsupported SPROM revision: %d\n", revision);
3587 + return -ENOENT;
3588 + }
3589 +
3590 + return 0;
3591 +}
3592 +
3593 +/**************************************************
3594 + * SPROM extraction.
3595 + **************************************************/
3596 +
3597 +#define SPOFF(offset) ((offset) / sizeof(u16))
3598 +
3599 +#define SPEX(_field, _offset, _mask, _shift) \
3600 + bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
3601 +
3602 +static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
3603 +{
3604 + u16 v, o;
3605 + int i;
3606 + u16 pwr_info_offset[] = {
3607 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
3608 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
3609 + };
3610 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
3611 + ARRAY_SIZE(bus->sprom.core_pwr_info));
3612 +
3613 + bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
3614 + SSB_SPROM_REVISION_REV;
3615 +
3616 + for (i = 0; i < 3; i++) {
3617 + v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
3618 + *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
3619 + }
3620 +
3621 + SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
3622 +
3623 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
3624 + SSB_SPROM4_TXPID2G0_SHIFT);
3625 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G1,
3626 + SSB_SPROM4_TXPID2G1_SHIFT);
3627 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G2,
3628 + SSB_SPROM4_TXPID2G2_SHIFT);
3629 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G3,
3630 + SSB_SPROM4_TXPID2G3_SHIFT);
3631 +
3632 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL0,
3633 + SSB_SPROM4_TXPID5GL0_SHIFT);
3634 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL1,
3635 + SSB_SPROM4_TXPID5GL1_SHIFT);
3636 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL2,
3637 + SSB_SPROM4_TXPID5GL2_SHIFT);
3638 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL3,
3639 + SSB_SPROM4_TXPID5GL3_SHIFT);
3640 +
3641 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G0,
3642 + SSB_SPROM4_TXPID5G0_SHIFT);
3643 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G1,
3644 + SSB_SPROM4_TXPID5G1_SHIFT);
3645 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G2,
3646 + SSB_SPROM4_TXPID5G2_SHIFT);
3647 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G3,
3648 + SSB_SPROM4_TXPID5G3_SHIFT);
3649 +
3650 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH0,
3651 + SSB_SPROM4_TXPID5GH0_SHIFT);
3652 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH1,
3653 + SSB_SPROM4_TXPID5GH1_SHIFT);
3654 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH2,
3655 + SSB_SPROM4_TXPID5GH2_SHIFT);
3656 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH3,
3657 + SSB_SPROM4_TXPID5GH3_SHIFT);
3658 +
3659 + SPEX(boardflags_lo, SSB_SPROM8_BFLLO, ~0, 0);
3660 + SPEX(boardflags_hi, SSB_SPROM8_BFLHI, ~0, 0);
3661 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, ~0, 0);
3662 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, ~0, 0);
3663 +
3664 + SPEX(country_code, SSB_SPROM8_CCODE, ~0, 0);
3665 +
3666 + /* Extract cores power info info */
3667 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
3668 + o = pwr_info_offset[i];
3669 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
3670 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
3671 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
3672 + SSB_SPROM8_2G_MAXP, 0);
3673 +
3674 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
3675 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
3676 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
3677 +
3678 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
3679 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
3680 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
3681 + SSB_SPROM8_5G_MAXP, 0);
3682 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
3683 + SSB_SPROM8_5GH_MAXP, 0);
3684 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
3685 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
3686 +
3687 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
3688 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
3689 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
3690 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
3691 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
3692 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
3693 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
3694 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
3695 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
3696 + }
3697 +
3698 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TSSIPOS,
3699 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
3700 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_EXTPA_GAIN,
3701 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
3702 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_PDET_RANGE,
3703 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
3704 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TR_ISO,
3705 + SSB_SROM8_FEM_TR_ISO_SHIFT);
3706 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_ANTSWLUT,
3707 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
3708 +
3709 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TSSIPOS,
3710 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
3711 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_EXTPA_GAIN,
3712 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
3713 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_PDET_RANGE,
3714 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
3715 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TR_ISO,
3716 + SSB_SROM8_FEM_TR_ISO_SHIFT);
3717 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_ANTSWLUT,
3718 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
3719 +}
3720 +
3721 +/*
3722 + * Indicates the presence of external SPROM.
3723 + */
3724 +static bool bcma_sprom_ext_available(struct bcma_bus *bus)
3725 +{
3726 + u32 chip_status;
3727 + u32 srom_control;
3728 + u32 present_mask;
3729 +
3730 + if (bus->drv_cc.core->id.rev >= 31) {
3731 + if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
3732 + return false;
3733 +
3734 + srom_control = bcma_read32(bus->drv_cc.core,
3735 + BCMA_CC_SROM_CONTROL);
3736 + return srom_control & BCMA_CC_SROM_CONTROL_PRESENT;
3737 + }
3738 +
3739 + /* older chipcommon revisions use chip status register */
3740 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
3741 + switch (bus->chipinfo.id) {
3742 + case 0x4313:
3743 + present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT;
3744 + break;
3745 +
3746 + case 0x4331:
3747 + present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT;
3748 + break;
3749 +
3750 + default:
3751 + return true;
3752 + }
3753 +
3754 + return chip_status & present_mask;
3755 +}
3756 +
3757 +/*
3758 + * Indicates that on-chip OTP memory is present and enabled.
3759 + */
3760 +static bool bcma_sprom_onchip_available(struct bcma_bus *bus)
3761 +{
3762 + u32 chip_status;
3763 + u32 otpsize = 0;
3764 + bool present;
3765 +
3766 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
3767 + switch (bus->chipinfo.id) {
3768 + case 0x4313:
3769 + present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT;
3770 + break;
3771 +
3772 + case 0x4331:
3773 + present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
3774 + break;
3775 +
3776 + case 43224:
3777 + case 43225:
3778 + /* for these chips OTP is always available */
3779 + present = true;
3780 + break;
3781 +
3782 + default:
3783 + present = false;
3784 + break;
3785 + }
3786 +
3787 + if (present) {
3788 + otpsize = bus->drv_cc.capabilities & BCMA_CC_CAP_OTPS;
3789 + otpsize >>= BCMA_CC_CAP_OTPS_SHIFT;
3790 + }
3791 +
3792 + return otpsize != 0;
3793 +}
3794 +
3795 +/*
3796 + * Verify OTP is filled and determine the byte
3797 + * offset where SPROM data is located.
3798 + *
3799 + * On error, returns 0; byte offset otherwise.
3800 + */
3801 +static int bcma_sprom_onchip_offset(struct bcma_bus *bus)
3802 +{
3803 + struct bcma_device *cc = bus->drv_cc.core;
3804 + u32 offset;
3805 +
3806 + /* verify OTP status */
3807 + if ((bcma_read32(cc, BCMA_CC_OTPS) & BCMA_CC_OTPS_GU_PROG_HW) == 0)
3808 + return 0;
3809 +
3810 + /* obtain bit offset from otplayout register */
3811 + offset = (bcma_read32(cc, BCMA_CC_OTPL) & BCMA_CC_OTPL_GURGN_OFFSET);
3812 + return BCMA_CC_SPROM + (offset >> 3);
3813 +}
3814 +
3815 +int bcma_sprom_get(struct bcma_bus *bus)
3816 +{
3817 + u16 offset = BCMA_CC_SPROM;
3818 + u16 *sprom;
3819 + int err = 0;
3820 +
3821 + if (!bus->drv_cc.core)
3822 + return -EOPNOTSUPP;
3823 +
3824 + if (!bcma_sprom_ext_available(bus)) {
3825 + /*
3826 + * External SPROM takes precedence so check
3827 + * on-chip OTP only when no external SPROM
3828 + * is present.
3829 + */
3830 + if (bcma_sprom_onchip_available(bus)) {
3831 + /* determine offset */
3832 + offset = bcma_sprom_onchip_offset(bus);
3833 + }
3834 + if (!offset) {
3835 + /*
3836 + * Maybe there is no SPROM on the device?
3837 + * Now we ask the arch code if there is some sprom
3838 + * available for this device in some other storage.
3839 + */
3840 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
3841 + return err;
3842 + }
3843 + }
3844 +
3845 + sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
3846 + GFP_KERNEL);
3847 + if (!sprom)
3848 + return -ENOMEM;
3849 +
3850 + if (bus->chipinfo.id == 0x4331)
3851 + bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
3852 +
3853 + pr_debug("SPROM offset 0x%x\n", offset);
3854 + bcma_sprom_read(bus, offset, sprom);
3855 +
3856 + if (bus->chipinfo.id == 0x4331)
3857 + bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
3858 +
3859 + err = bcma_sprom_valid(sprom);
3860 + if (err)
3861 + goto out;
3862 +
3863 + bcma_sprom_extract_r8(bus, sprom);
3864 +
3865 +out:
3866 + kfree(sprom);
3867 + return err;
3868 +}
3869 --- /dev/null
3870 +++ b/drivers/bcma/driver_pci_host.c
3871 @@ -0,0 +1,589 @@
3872 +/*
3873 + * Broadcom specific AMBA
3874 + * PCI Core in hostmode
3875 + *
3876 + * Copyright 2005 - 2011, Broadcom Corporation
3877 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
3878 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
3879 + *
3880 + * Licensed under the GNU/GPL. See COPYING for details.
3881 + */
3882 +
3883 +#include "bcma_private.h"
3884 +#include <linux/pci.h>
3885 +#include <linux/export.h>
3886 +#include <linux/bcma/bcma.h>
3887 +#include <asm/paccess.h>
3888 +
3889 +/* Probe a 32bit value on the bus and catch bus exceptions.
3890 + * Returns nonzero on a bus exception.
3891 + * This is MIPS specific */
3892 +#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
3893 +
3894 +/* Assume one-hot slot wiring */
3895 +#define BCMA_PCI_SLOT_MAX 16
3896 +#define PCI_CONFIG_SPACE_SIZE 256
3897 +
3898 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
3899 +{
3900 + struct bcma_bus *bus = pc->core->bus;
3901 + u16 chipid_top;
3902 + u32 tmp;
3903 +
3904 + chipid_top = (bus->chipinfo.id & 0xFF00);
3905 + if (chipid_top != 0x4700 &&
3906 + chipid_top != 0x5300)
3907 + return false;
3908 +
3909 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
3910 + pr_info("This PCI core is disabled and not working\n");
3911 + return false;
3912 + }
3913 +
3914 + bcma_core_enable(pc->core, 0);
3915 +
3916 + return !mips_busprobe32(tmp, pc->core->io_addr);
3917 +}
3918 +
3919 +static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
3920 +{
3921 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
3922 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
3923 + return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
3924 +}
3925 +
3926 +static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
3927 + u32 data)
3928 +{
3929 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
3930 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
3931 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
3932 +}
3933 +
3934 +static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
3935 + unsigned int func, unsigned int off)
3936 +{
3937 + u32 addr = 0;
3938 +
3939 + /* Issue config commands only when the data link is up (atleast
3940 + * one external pcie device is present).
3941 + */
3942 + if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
3943 + & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
3944 + goto out;
3945 +
3946 + /* Type 0 transaction */
3947 + /* Slide the PCI window to the appropriate slot */
3948 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
3949 + /* Calculate the address */
3950 + addr = pc->host_controller->host_cfg_addr;
3951 + addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
3952 + addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
3953 + addr |= (off & ~3);
3954 +
3955 +out:
3956 + return addr;
3957 +}
3958 +
3959 +static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
3960 + unsigned int func, unsigned int off,
3961 + void *buf, int len)
3962 +{
3963 + int err = -EINVAL;
3964 + u32 addr, val;
3965 + void __iomem *mmio = 0;
3966 +
3967 + WARN_ON(!pc->hostmode);
3968 + if (unlikely(len != 1 && len != 2 && len != 4))
3969 + goto out;
3970 + if (dev == 0) {
3971 + /* we support only two functions on device 0 */
3972 + if (func > 1)
3973 + return -EINVAL;
3974 +
3975 + /* accesses to config registers with offsets >= 256
3976 + * requires indirect access.
3977 + */
3978 + if (off >= PCI_CONFIG_SPACE_SIZE) {
3979 + addr = (func << 12);
3980 + addr |= (off & 0x0FFF);
3981 + val = bcma_pcie_read_config(pc, addr);
3982 + } else {
3983 + addr = BCMA_CORE_PCI_PCICFG0;
3984 + addr |= (func << 8);
3985 + addr |= (off & 0xfc);
3986 + val = pcicore_read32(pc, addr);
3987 + }
3988 + } else {
3989 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
3990 + if (unlikely(!addr))
3991 + goto out;
3992 + err = -ENOMEM;
3993 + mmio = ioremap_nocache(addr, len);
3994 + if (!mmio)
3995 + goto out;
3996 +
3997 + if (mips_busprobe32(val, mmio)) {
3998 + val = 0xffffffff;
3999 + goto unmap;
4000 + }
4001 +
4002 + val = readl(mmio);
4003 + }
4004 + val >>= (8 * (off & 3));
4005 +
4006 + switch (len) {
4007 + case 1:
4008 + *((u8 *)buf) = (u8)val;
4009 + break;
4010 + case 2:
4011 + *((u16 *)buf) = (u16)val;
4012 + break;
4013 + case 4:
4014 + *((u32 *)buf) = (u32)val;
4015 + break;
4016 + }
4017 + err = 0;
4018 +unmap:
4019 + if (mmio)
4020 + iounmap(mmio);
4021 +out:
4022 + return err;
4023 +}
4024 +
4025 +static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
4026 + unsigned int func, unsigned int off,
4027 + const void *buf, int len)
4028 +{
4029 + int err = -EINVAL;
4030 + u32 addr = 0, val = 0;
4031 + void __iomem *mmio = 0;
4032 + u16 chipid = pc->core->bus->chipinfo.id;
4033 +
4034 + WARN_ON(!pc->hostmode);
4035 + if (unlikely(len != 1 && len != 2 && len != 4))
4036 + goto out;
4037 + if (dev == 0) {
4038 + /* accesses to config registers with offsets >= 256
4039 + * requires indirect access.
4040 + */
4041 + if (off < PCI_CONFIG_SPACE_SIZE) {
4042 + addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
4043 + addr |= (func << 8);
4044 + addr |= (off & 0xfc);
4045 + mmio = ioremap_nocache(addr, len);
4046 + if (!mmio)
4047 + goto out;
4048 + }
4049 + } else {
4050 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
4051 + if (unlikely(!addr))
4052 + goto out;
4053 + err = -ENOMEM;
4054 + mmio = ioremap_nocache(addr, len);
4055 + if (!mmio)
4056 + goto out;
4057 +
4058 + if (mips_busprobe32(val, mmio)) {
4059 + val = 0xffffffff;
4060 + goto unmap;
4061 + }
4062 + }
4063 +
4064 + switch (len) {
4065 + case 1:
4066 + val = readl(mmio);
4067 + val &= ~(0xFF << (8 * (off & 3)));
4068 + val |= *((const u8 *)buf) << (8 * (off & 3));
4069 + break;
4070 + case 2:
4071 + val = readl(mmio);
4072 + val &= ~(0xFFFF << (8 * (off & 3)));
4073 + val |= *((const u16 *)buf) << (8 * (off & 3));
4074 + break;
4075 + case 4:
4076 + val = *((const u32 *)buf);
4077 + break;
4078 + }
4079 + if (dev == 0 && !addr) {
4080 + /* accesses to config registers with offsets >= 256
4081 + * requires indirect access.
4082 + */
4083 + addr = (func << 12);
4084 + addr |= (off & 0x0FFF);
4085 + bcma_pcie_write_config(pc, addr, val);
4086 + } else {
4087 + writel(val, mmio);
4088 +
4089 + if (chipid == 0x4716 || chipid == 0x4748)
4090 + readl(mmio);
4091 + }
4092 +
4093 + err = 0;
4094 +unmap:
4095 + if (mmio)
4096 + iounmap(mmio);
4097 +out:
4098 + return err;
4099 +}
4100 +
4101 +static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
4102 + unsigned int devfn,
4103 + int reg, int size, u32 *val)
4104 +{
4105 + unsigned long flags;
4106 + int err;
4107 + struct bcma_drv_pci *pc;
4108 + struct bcma_drv_pci_host *pc_host;
4109 +
4110 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
4111 + pc = pc_host->pdev;
4112 +
4113 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
4114 + err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
4115 + PCI_FUNC(devfn), reg, val, size);
4116 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
4117 +
4118 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
4119 +}
4120 +
4121 +static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
4122 + unsigned int devfn,
4123 + int reg, int size, u32 val)
4124 +{
4125 + unsigned long flags;
4126 + int err;
4127 + struct bcma_drv_pci *pc;
4128 + struct bcma_drv_pci_host *pc_host;
4129 +
4130 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
4131 + pc = pc_host->pdev;
4132 +
4133 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
4134 + err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
4135 + PCI_FUNC(devfn), reg, &val, size);
4136 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
4137 +
4138 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
4139 +}
4140 +
4141 +/* return cap_offset if requested capability exists in the PCI config space */
4142 +static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc,
4143 + unsigned int dev,
4144 + unsigned int func, u8 req_cap_id,
4145 + unsigned char *buf, u32 *buflen)
4146 +{
4147 + u8 cap_id;
4148 + u8 cap_ptr = 0;
4149 + u32 bufsize;
4150 + u8 byte_val;
4151 +
4152 + /* check for Header type 0 */
4153 + bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
4154 + sizeof(u8));
4155 + if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
4156 + return cap_ptr;
4157 +
4158 + /* check if the capability pointer field exists */
4159 + bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
4160 + sizeof(u8));
4161 + if (!(byte_val & PCI_STATUS_CAP_LIST))
4162 + return cap_ptr;
4163 +
4164 + /* check if the capability pointer is 0x00 */
4165 + bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
4166 + sizeof(u8));
4167 + if (cap_ptr == 0x00)
4168 + return cap_ptr;
4169 +
4170 + /* loop thr'u the capability list and see if the requested capabilty
4171 + * exists */
4172 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
4173 + while (cap_id != req_cap_id) {
4174 + bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
4175 + sizeof(u8));
4176 + if (cap_ptr == 0x00)
4177 + return cap_ptr;
4178 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
4179 + sizeof(u8));
4180 + }
4181 +
4182 + /* found the caller requested capability */
4183 + if ((buf != NULL) && (buflen != NULL)) {
4184 + u8 cap_data;
4185 +
4186 + bufsize = *buflen;
4187 + if (!bufsize)
4188 + return cap_ptr;
4189 +
4190 + *buflen = 0;
4191 +
4192 + /* copy the cpability data excluding cap ID and next ptr */
4193 + cap_data = cap_ptr + 2;
4194 + if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE)
4195 + bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
4196 + *buflen = bufsize;
4197 + while (bufsize--) {
4198 + bcma_extpci_read_config(pc, dev, func, cap_data, buf,
4199 + sizeof(u8));
4200 + cap_data++;
4201 + buf++;
4202 + }
4203 + }
4204 +
4205 + return cap_ptr;
4206 +}
4207 +
4208 +/* If the root port is capable of returning Config Request
4209 + * Retry Status (CRS) Completion Status to software then
4210 + * enable the feature.
4211 + */
4212 +static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
4213 +{
4214 + u8 cap_ptr, root_ctrl, root_cap, dev;
4215 + u16 val16;
4216 + int i;
4217 +
4218 + cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
4219 + NULL);
4220 + root_cap = cap_ptr + PCI_EXP_RTCAP;
4221 + bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
4222 + if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
4223 + /* Enable CRS software visibility */
4224 + root_ctrl = cap_ptr + PCI_EXP_RTCTL;
4225 + val16 = PCI_EXP_RTCTL_CRSSVE;
4226 + bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
4227 + sizeof(u16));
4228 +
4229 + /* Initiate a configuration request to read the vendor id
4230 + * field of the device function's config space header after
4231 + * 100 ms wait time from the end of Reset. If the device is
4232 + * not done with its internal initialization, it must at
4233 + * least return a completion TLP, with a completion status
4234 + * of "Configuration Request Retry Status (CRS)". The root
4235 + * complex must complete the request to the host by returning
4236 + * a read-data value of 0001h for the Vendor ID field and
4237 + * all 1s for any additional bytes included in the request.
4238 + * Poll using the config reads for max wait time of 1 sec or
4239 + * until we receive the successful completion status. Repeat
4240 + * the procedure for all the devices.
4241 + */
4242 + for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
4243 + for (i = 0; i < 100000; i++) {
4244 + bcma_extpci_read_config(pc, dev, 0,
4245 + PCI_VENDOR_ID, &val16,
4246 + sizeof(val16));
4247 + if (val16 != 0x1)
4248 + break;
4249 + udelay(10);
4250 + }
4251 + if (val16 == 0x1)
4252 + pr_err("PCI: Broken device in slot %d\n", dev);
4253 + }
4254 + }
4255 +}
4256 +
4257 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
4258 +{
4259 + struct bcma_bus *bus = pc->core->bus;
4260 + struct bcma_drv_pci_host *pc_host;
4261 + u32 tmp;
4262 + u32 pci_membase_1G;
4263 + unsigned long io_map_base;
4264 +
4265 + pr_info("PCIEcore in host mode found\n");
4266 +
4267 + pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
4268 + if (!pc_host) {
4269 + pr_err("can not allocate memory");
4270 + return;
4271 + }
4272 +
4273 + pc->host_controller = pc_host;
4274 + pc_host->pci_controller.io_resource = &pc_host->io_resource;
4275 + pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
4276 + pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
4277 + pc_host->pdev = pc;
4278 +
4279 + pci_membase_1G = BCMA_SOC_PCI_DMA;
4280 + pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
4281 +
4282 + pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
4283 + pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
4284 +
4285 + pc_host->mem_resource.name = "BCMA PCIcore external memory",
4286 + pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
4287 + pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
4288 + pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
4289 +
4290 + pc_host->io_resource.name = "BCMA PCIcore external I/O",
4291 + pc_host->io_resource.start = 0x100;
4292 + pc_host->io_resource.end = 0x7FF;
4293 + pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
4294 +
4295 + /* Reset RC */
4296 + udelay(3000);
4297 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
4298 + udelay(1000);
4299 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
4300 + BCMA_CORE_PCI_CTL_RST_OE);
4301 +
4302 + /* 64 MB I/O access window. On 4716, use
4303 + * sbtopcie0 to access the device registers. We
4304 + * can't use address match 2 (1 GB window) region
4305 + * as mips can't generate 64-bit address on the
4306 + * backplane.
4307 + */
4308 + if (bus->chipinfo.id == 0x4716 || bus->chipinfo.id == 0x4748) {
4309 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
4310 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
4311 + BCMA_SOC_PCI_MEM_SZ - 1;
4312 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
4313 + BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
4314 + } else if (bus->chipinfo.id == 0x5300) {
4315 + tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
4316 + tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
4317 + tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
4318 + if (pc->core->core_unit == 0) {
4319 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
4320 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
4321 + BCMA_SOC_PCI_MEM_SZ - 1;
4322 + pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
4323 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
4324 + tmp | BCMA_SOC_PCI_MEM);
4325 + } else if (pc->core->core_unit == 1) {
4326 + pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
4327 + pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
4328 + BCMA_SOC_PCI_MEM_SZ - 1;
4329 + pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
4330 + pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
4331 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
4332 + tmp | BCMA_SOC_PCI1_MEM);
4333 + }
4334 + } else
4335 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
4336 + BCMA_CORE_PCI_SBTOPCI_IO);
4337 +
4338 + /* 64 MB configuration access window */
4339 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
4340 +
4341 + /* 1 GB memory access window */
4342 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
4343 + BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
4344 +
4345 +
4346 + /* As per PCI Express Base Spec 1.1 we need to wait for
4347 + * at least 100 ms from the end of a reset (cold/warm/hot)
4348 + * before issuing configuration requests to PCI Express
4349 + * devices.
4350 + */
4351 + udelay(100000);
4352 +
4353 + bcma_core_pci_enable_crs(pc);
4354 +
4355 + /* Enable PCI bridge BAR0 memory & master access */
4356 + tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
4357 + bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
4358 +
4359 + /* Enable PCI interrupts */
4360 + pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
4361 +
4362 + /* Ok, ready to run, register it to the system.
4363 + * The following needs change, if we want to port hostmode
4364 + * to non-MIPS platform. */
4365 + io_map_base = (unsigned long)ioremap_nocache(BCMA_SOC_PCI_MEM,
4366 + 0x04000000);
4367 + pc_host->pci_controller.io_map_base = io_map_base;
4368 + set_io_port_base(pc_host->pci_controller.io_map_base);
4369 + /* Give some time to the PCI controller to configure itself with the new
4370 + * values. Not waiting at this point causes crashes of the machine. */
4371 + mdelay(10);
4372 + register_pci_controller(&pc_host->pci_controller);
4373 + return;
4374 +}
4375 +
4376 +/* Early PCI fixup for a device on the PCI-core bridge. */
4377 +static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
4378 +{
4379 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
4380 + /* This is not a device on the PCI-core bridge. */
4381 + return;
4382 + }
4383 + if (PCI_SLOT(dev->devfn) != 0)
4384 + return;
4385 +
4386 + pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
4387 +
4388 + /* Enable PCI bridge bus mastering and memory space */
4389 + pci_set_master(dev);
4390 + if (pcibios_enable_device(dev, ~0) < 0) {
4391 + pr_err("PCI: BCMA bridge enable failed\n");
4392 + return;
4393 + }
4394 +
4395 + /* Enable PCI bridge BAR1 prefetch and burst */
4396 + pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
4397 +}
4398 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
4399 +
4400 +/* Early PCI fixup for all PCI-cores to set the correct memory address. */
4401 +static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
4402 +{
4403 + struct resource *res;
4404 + int pos;
4405 +
4406 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
4407 + /* This is not a device on the PCI-core bridge. */
4408 + return;
4409 + }
4410 + if (PCI_SLOT(dev->devfn) == 0)
4411 + return;
4412 +
4413 + pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
4414 +
4415 + for (pos = 0; pos < 6; pos++) {
4416 + res = &dev->resource[pos];
4417 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
4418 + pci_assign_resource(dev, pos);
4419 + }
4420 +}
4421 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
4422 +
4423 +/* This function is called when doing a pci_enable_device().
4424 + * We must first check if the device is a device on the PCI-core bridge. */
4425 +int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
4426 +{
4427 + struct bcma_drv_pci_host *pc_host;
4428 +
4429 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
4430 + /* This is not a device on the PCI-core bridge. */
4431 + return -ENODEV;
4432 + }
4433 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
4434 + pci_ops);
4435 +
4436 + pr_info("PCI: Fixing up device %s\n", pci_name(dev));
4437 +
4438 + /* Fix up interrupt lines */
4439 + dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
4440 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
4441 +
4442 + return 0;
4443 +}
4444 +EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
4445 +
4446 +/* PCI device IRQ mapping. */
4447 +int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
4448 +{
4449 + struct bcma_drv_pci_host *pc_host;
4450 +
4451 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
4452 + /* This is not a device on the PCI-core bridge. */
4453 + return -ENODEV;
4454 + }
4455 +
4456 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
4457 + pci_ops);
4458 + return bcma_core_mips_irq(pc_host->pdev->core) + 2;
4459 +}
4460 +EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
4461 --- /dev/null
4462 +++ b/drivers/bcma/driver_mips.c
4463 @@ -0,0 +1,256 @@
4464 +/*
4465 + * Broadcom specific AMBA
4466 + * Broadcom MIPS32 74K core driver
4467 + *
4468 + * Copyright 2009, Broadcom Corporation
4469 + * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
4470 + * Copyright 2010, Bernhard Loos <bernhardloos@googlemail.com>
4471 + * Copyright 2011, Hauke Mehrtens <hauke@hauke-m.de>
4472 + *
4473 + * Licensed under the GNU/GPL. See COPYING for details.
4474 + */
4475 +
4476 +#include "bcma_private.h"
4477 +
4478 +#include <linux/bcma/bcma.h>
4479 +
4480 +#include <linux/serial.h>
4481 +#include <linux/serial_core.h>
4482 +#include <linux/serial_reg.h>
4483 +#include <linux/time.h>
4484 +
4485 +/* The 47162a0 hangs when reading MIPS DMP registers registers */
4486 +static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
4487 +{
4488 + return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
4489 + dev->id.id == BCMA_CORE_MIPS_74K;
4490 +}
4491 +
4492 +/* The 5357b0 hangs when reading USB20H DMP registers */
4493 +static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
4494 +{
4495 + return (dev->bus->chipinfo.id == 0x5357 ||
4496 + dev->bus->chipinfo.id == 0x4749) &&
4497 + dev->bus->chipinfo.pkg == 11 &&
4498 + dev->id.id == BCMA_CORE_USB20_HOST;
4499 +}
4500 +
4501 +static inline u32 mips_read32(struct bcma_drv_mips *mcore,
4502 + u16 offset)
4503 +{
4504 + return bcma_read32(mcore->core, offset);
4505 +}
4506 +
4507 +static inline void mips_write32(struct bcma_drv_mips *mcore,
4508 + u16 offset,
4509 + u32 value)
4510 +{
4511 + bcma_write32(mcore->core, offset, value);
4512 +}
4513 +
4514 +static const u32 ipsflag_irq_mask[] = {
4515 + 0,
4516 + BCMA_MIPS_IPSFLAG_IRQ1,
4517 + BCMA_MIPS_IPSFLAG_IRQ2,
4518 + BCMA_MIPS_IPSFLAG_IRQ3,
4519 + BCMA_MIPS_IPSFLAG_IRQ4,
4520 +};
4521 +
4522 +static const u32 ipsflag_irq_shift[] = {
4523 + 0,
4524 + BCMA_MIPS_IPSFLAG_IRQ1_SHIFT,
4525 + BCMA_MIPS_IPSFLAG_IRQ2_SHIFT,
4526 + BCMA_MIPS_IPSFLAG_IRQ3_SHIFT,
4527 + BCMA_MIPS_IPSFLAG_IRQ4_SHIFT,
4528 +};
4529 +
4530 +static u32 bcma_core_mips_irqflag(struct bcma_device *dev)
4531 +{
4532 + u32 flag;
4533 +
4534 + if (bcma_core_mips_bcm47162a0_quirk(dev))
4535 + return dev->core_index;
4536 + if (bcma_core_mips_bcm5357b0_quirk(dev))
4537 + return dev->core_index;
4538 + flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
4539 +
4540 + return flag & 0x1F;
4541 +}
4542 +
4543 +/* Get the MIPS IRQ assignment for a specified device.
4544 + * If unassigned, 0 is returned.
4545 + */
4546 +unsigned int bcma_core_mips_irq(struct bcma_device *dev)
4547 +{
4548 + struct bcma_device *mdev = dev->bus->drv_mips.core;
4549 + u32 irqflag;
4550 + unsigned int irq;
4551 +
4552 + irqflag = bcma_core_mips_irqflag(dev);
4553 +
4554 + for (irq = 1; irq <= 4; irq++)
4555 + if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
4556 + (1 << irqflag))
4557 + return irq;
4558 +
4559 + return 0;
4560 +}
4561 +EXPORT_SYMBOL(bcma_core_mips_irq);
4562 +
4563 +static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
4564 +{
4565 + unsigned int oldirq = bcma_core_mips_irq(dev);
4566 + struct bcma_bus *bus = dev->bus;
4567 + struct bcma_device *mdev = bus->drv_mips.core;
4568 + u32 irqflag;
4569 +
4570 + irqflag = bcma_core_mips_irqflag(dev);
4571 + BUG_ON(oldirq == 6);
4572 +
4573 + dev->irq = irq + 2;
4574 +
4575 + /* clear the old irq */
4576 + if (oldirq == 0)
4577 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
4578 + bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
4579 + ~(1 << irqflag));
4580 + else
4581 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
4582 +
4583 + /* assign the new one */
4584 + if (irq == 0) {
4585 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
4586 + bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
4587 + (1 << irqflag));
4588 + } else {
4589 + u32 oldirqflag = bcma_read32(mdev,
4590 + BCMA_MIPS_MIPS74K_INTMASK(irq));
4591 + if (oldirqflag) {
4592 + struct bcma_device *core;
4593 +
4594 + /* backplane irq line is in use, find out who uses
4595 + * it and set user to irq 0
4596 + */
4597 + list_for_each_entry_reverse(core, &bus->cores, list) {
4598 + if ((1 << bcma_core_mips_irqflag(core)) ==
4599 + oldirqflag) {
4600 + bcma_core_mips_set_irq(core, 0);
4601 + break;
4602 + }
4603 + }
4604 + }
4605 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq),
4606 + 1 << irqflag);
4607 + }
4608 +
4609 + pr_info("set_irq: core 0x%04x, irq %d => %d\n",
4610 + dev->id.id, oldirq + 2, irq + 2);
4611 +}
4612 +
4613 +static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
4614 +{
4615 + int i;
4616 + static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
4617 + printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
4618 + for (i = 0; i <= 6; i++)
4619 + printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
4620 + printk("\n");
4621 +}
4622 +
4623 +static void bcma_core_mips_dump_irq(struct bcma_bus *bus)
4624 +{
4625 + struct bcma_device *core;
4626 +
4627 + list_for_each_entry_reverse(core, &bus->cores, list) {
4628 + bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
4629 + }
4630 +}
4631 +
4632 +u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
4633 +{
4634 + struct bcma_bus *bus = mcore->core->bus;
4635 +
4636 + if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
4637 + return bcma_pmu_get_clockcpu(&bus->drv_cc);
4638 +
4639 + pr_err("No PMU available, need this to get the cpu clock\n");
4640 + return 0;
4641 +}
4642 +EXPORT_SYMBOL(bcma_cpu_clock);
4643 +
4644 +static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
4645 +{
4646 + struct bcma_bus *bus = mcore->core->bus;
4647 +
4648 + switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
4649 + case BCMA_CC_FLASHT_STSER:
4650 + case BCMA_CC_FLASHT_ATSER:
4651 + pr_err("Serial flash not supported.\n");
4652 + break;
4653 + case BCMA_CC_FLASHT_PARA:
4654 + pr_info("found parallel flash.\n");
4655 + bus->drv_cc.pflash.window = 0x1c000000;
4656 + bus->drv_cc.pflash.window_size = 0x02000000;
4657 +
4658 + if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
4659 + BCMA_CC_FLASH_CFG_DS) == 0)
4660 + bus->drv_cc.pflash.buswidth = 1;
4661 + else
4662 + bus->drv_cc.pflash.buswidth = 2;
4663 + break;
4664 + default:
4665 + pr_err("flash not supported.\n");
4666 + }
4667 +}
4668 +
4669 +void bcma_core_mips_init(struct bcma_drv_mips *mcore)
4670 +{
4671 + struct bcma_bus *bus;
4672 + struct bcma_device *core;
4673 + bus = mcore->core->bus;
4674 +
4675 + pr_info("Initializing MIPS core...\n");
4676 +
4677 + if (!mcore->setup_done)
4678 + mcore->assigned_irqs = 1;
4679 +
4680 + /* Assign IRQs to all cores on the bus */
4681 + list_for_each_entry_reverse(core, &bus->cores, list) {
4682 + int mips_irq;
4683 + if (core->irq)
4684 + continue;
4685 +
4686 + mips_irq = bcma_core_mips_irq(core);
4687 + if (mips_irq > 4)
4688 + core->irq = 0;
4689 + else
4690 + core->irq = mips_irq + 2;
4691 + if (core->irq > 5)
4692 + continue;
4693 + switch (core->id.id) {
4694 + case BCMA_CORE_PCI:
4695 + case BCMA_CORE_PCIE:
4696 + case BCMA_CORE_ETHERNET:
4697 + case BCMA_CORE_ETHERNET_GBIT:
4698 + case BCMA_CORE_MAC_GBIT:
4699 + case BCMA_CORE_80211:
4700 + case BCMA_CORE_USB20_HOST:
4701 + /* These devices get their own IRQ line if available,
4702 + * the rest goes on IRQ0
4703 + */
4704 + if (mcore->assigned_irqs <= 4)
4705 + bcma_core_mips_set_irq(core,
4706 + mcore->assigned_irqs++);
4707 + break;
4708 + }
4709 + }
4710 + pr_info("IRQ reconfiguration done\n");
4711 + bcma_core_mips_dump_irq(bus);
4712 +
4713 + if (mcore->setup_done)
4714 + return;
4715 +
4716 + bcma_chipco_serial_init(&bus->drv_cc);
4717 + bcma_core_mips_flash_detect(mcore);
4718 + mcore->setup_done = true;
4719 +}
4720 --- /dev/null
4721 +++ b/drivers/bcma/host_soc.c
4722 @@ -0,0 +1,183 @@
4723 +/*
4724 + * Broadcom specific AMBA
4725 + * System on Chip (SoC) Host
4726 + *
4727 + * Licensed under the GNU/GPL. See COPYING for details.
4728 + */
4729 +
4730 +#include "bcma_private.h"
4731 +#include "scan.h"
4732 +#include <linux/bcma/bcma.h>
4733 +#include <linux/bcma/bcma_soc.h>
4734 +
4735 +static u8 bcma_host_soc_read8(struct bcma_device *core, u16 offset)
4736 +{
4737 + return readb(core->io_addr + offset);
4738 +}
4739 +
4740 +static u16 bcma_host_soc_read16(struct bcma_device *core, u16 offset)
4741 +{
4742 + return readw(core->io_addr + offset);
4743 +}
4744 +
4745 +static u32 bcma_host_soc_read32(struct bcma_device *core, u16 offset)
4746 +{
4747 + return readl(core->io_addr + offset);
4748 +}
4749 +
4750 +static void bcma_host_soc_write8(struct bcma_device *core, u16 offset,
4751 + u8 value)
4752 +{
4753 + writeb(value, core->io_addr + offset);
4754 +}
4755 +
4756 +static void bcma_host_soc_write16(struct bcma_device *core, u16 offset,
4757 + u16 value)
4758 +{
4759 + writew(value, core->io_addr + offset);
4760 +}
4761 +
4762 +static void bcma_host_soc_write32(struct bcma_device *core, u16 offset,
4763 + u32 value)
4764 +{
4765 + writel(value, core->io_addr + offset);
4766 +}
4767 +
4768 +#ifdef CONFIG_BCMA_BLOCKIO
4769 +static void bcma_host_soc_block_read(struct bcma_device *core, void *buffer,
4770 + size_t count, u16 offset, u8 reg_width)
4771 +{
4772 + void __iomem *addr = core->io_addr + offset;
4773 +
4774 + switch (reg_width) {
4775 + case sizeof(u8): {
4776 + u8 *buf = buffer;
4777 +
4778 + while (count) {
4779 + *buf = __raw_readb(addr);
4780 + buf++;
4781 + count--;
4782 + }
4783 + break;
4784 + }
4785 + case sizeof(u16): {
4786 + __le16 *buf = buffer;
4787 +
4788 + WARN_ON(count & 1);
4789 + while (count) {
4790 + *buf = (__force __le16)__raw_readw(addr);
4791 + buf++;
4792 + count -= 2;
4793 + }
4794 + break;
4795 + }
4796 + case sizeof(u32): {
4797 + __le32 *buf = buffer;
4798 +
4799 + WARN_ON(count & 3);
4800 + while (count) {
4801 + *buf = (__force __le32)__raw_readl(addr);
4802 + buf++;
4803 + count -= 4;
4804 + }
4805 + break;
4806 + }
4807 + default:
4808 + WARN_ON(1);
4809 + }
4810 +}
4811 +
4812 +static void bcma_host_soc_block_write(struct bcma_device *core,
4813 + const void *buffer,
4814 + size_t count, u16 offset, u8 reg_width)
4815 +{
4816 + void __iomem *addr = core->io_addr + offset;
4817 +
4818 + switch (reg_width) {
4819 + case sizeof(u8): {
4820 + const u8 *buf = buffer;
4821 +
4822 + while (count) {
4823 + __raw_writeb(*buf, addr);
4824 + buf++;
4825 + count--;
4826 + }
4827 + break;
4828 + }
4829 + case sizeof(u16): {
4830 + const __le16 *buf = buffer;
4831 +
4832 + WARN_ON(count & 1);
4833 + while (count) {
4834 + __raw_writew((__force u16)(*buf), addr);
4835 + buf++;
4836 + count -= 2;
4837 + }
4838 + break;
4839 + }
4840 + case sizeof(u32): {
4841 + const __le32 *buf = buffer;
4842 +
4843 + WARN_ON(count & 3);
4844 + while (count) {
4845 + __raw_writel((__force u32)(*buf), addr);
4846 + buf++;
4847 + count -= 4;
4848 + }
4849 + break;
4850 + }
4851 + default:
4852 + WARN_ON(1);
4853 + }
4854 +}
4855 +#endif /* CONFIG_BCMA_BLOCKIO */
4856 +
4857 +static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
4858 +{
4859 + return readl(core->io_wrap + offset);
4860 +}
4861 +
4862 +static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
4863 + u32 value)
4864 +{
4865 + writel(value, core->io_wrap + offset);
4866 +}
4867 +
4868 +const struct bcma_host_ops bcma_host_soc_ops = {
4869 + .read8 = bcma_host_soc_read8,
4870 + .read16 = bcma_host_soc_read16,
4871 + .read32 = bcma_host_soc_read32,
4872 + .write8 = bcma_host_soc_write8,
4873 + .write16 = bcma_host_soc_write16,
4874 + .write32 = bcma_host_soc_write32,
4875 +#ifdef CONFIG_BCMA_BLOCKIO
4876 + .block_read = bcma_host_soc_block_read,
4877 + .block_write = bcma_host_soc_block_write,
4878 +#endif
4879 + .aread32 = bcma_host_soc_aread32,
4880 + .awrite32 = bcma_host_soc_awrite32,
4881 +};
4882 +
4883 +int __init bcma_host_soc_register(struct bcma_soc *soc)
4884 +{
4885 + struct bcma_bus *bus = &soc->bus;
4886 + int err;
4887 +
4888 + /* iomap only first core. We have to read some register on this core
4889 + * to scan the bus.
4890 + */
4891 + bus->mmio = ioremap_nocache(BCMA_ADDR_BASE, BCMA_CORE_SIZE * 1);
4892 + if (!bus->mmio)
4893 + return -ENOMEM;
4894 +
4895 + /* Host specific */
4896 + bus->hosttype = BCMA_HOSTTYPE_SOC;
4897 + bus->ops = &bcma_host_soc_ops;
4898 +
4899 + /* Register */
4900 + err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
4901 + if (err)
4902 + iounmap(bus->mmio);
4903 +
4904 + return err;
4905 +}
4906 --- /dev/null
4907 +++ b/include/linux/bcma/bcma_driver_mips.h
4908 @@ -0,0 +1,51 @@
4909 +#ifndef LINUX_BCMA_DRIVER_MIPS_H_
4910 +#define LINUX_BCMA_DRIVER_MIPS_H_
4911 +
4912 +#define BCMA_MIPS_IPSFLAG 0x0F08
4913 +/* which sbflags get routed to mips interrupt 1 */
4914 +#define BCMA_MIPS_IPSFLAG_IRQ1 0x0000003F
4915 +#define BCMA_MIPS_IPSFLAG_IRQ1_SHIFT 0
4916 +/* which sbflags get routed to mips interrupt 2 */
4917 +#define BCMA_MIPS_IPSFLAG_IRQ2 0x00003F00
4918 +#define BCMA_MIPS_IPSFLAG_IRQ2_SHIFT 8
4919 +/* which sbflags get routed to mips interrupt 3 */
4920 +#define BCMA_MIPS_IPSFLAG_IRQ3 0x003F0000
4921 +#define BCMA_MIPS_IPSFLAG_IRQ3_SHIFT 16
4922 +/* which sbflags get routed to mips interrupt 4 */
4923 +#define BCMA_MIPS_IPSFLAG_IRQ4 0x3F000000
4924 +#define BCMA_MIPS_IPSFLAG_IRQ4_SHIFT 24
4925 +
4926 +/* MIPS 74K core registers */
4927 +#define BCMA_MIPS_MIPS74K_CORECTL 0x0000
4928 +#define BCMA_MIPS_MIPS74K_EXCEPTBASE 0x0004
4929 +#define BCMA_MIPS_MIPS74K_BIST 0x000C
4930 +#define BCMA_MIPS_MIPS74K_INTMASK_INT0 0x0014
4931 +#define BCMA_MIPS_MIPS74K_INTMASK(int) \
4932 + ((int) * 4 + BCMA_MIPS_MIPS74K_INTMASK_INT0)
4933 +#define BCMA_MIPS_MIPS74K_NMIMASK 0x002C
4934 +#define BCMA_MIPS_MIPS74K_GPIOSEL 0x0040
4935 +#define BCMA_MIPS_MIPS74K_GPIOOUT 0x0044
4936 +#define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
4937 +#define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
4938 +
4939 +#define BCMA_MIPS_OOBSELOUTA30 0x100
4940 +
4941 +struct bcma_device;
4942 +
4943 +struct bcma_drv_mips {
4944 + struct bcma_device *core;
4945 + u8 setup_done:1;
4946 + unsigned int assigned_irqs;
4947 +};
4948 +
4949 +#ifdef CONFIG_BCMA_DRIVER_MIPS
4950 +extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
4951 +#else
4952 +static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
4953 +#endif
4954 +
4955 +extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
4956 +
4957 +extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
4958 +
4959 +#endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
4960 --- /dev/null
4961 +++ b/include/linux/bcma/bcma_soc.h
4962 @@ -0,0 +1,16 @@
4963 +#ifndef LINUX_BCMA_SOC_H_
4964 +#define LINUX_BCMA_SOC_H_
4965 +
4966 +#include <linux/bcma/bcma.h>
4967 +
4968 +struct bcma_soc {
4969 + struct bcma_bus bus;
4970 + struct bcma_device core_cc;
4971 + struct bcma_device core_mips;
4972 +};
4973 +
4974 +int __init bcma_host_soc_register(struct bcma_soc *soc);
4975 +
4976 +int bcma_bus_register(struct bcma_bus *bus);
4977 +
4978 +#endif /* LINUX_BCMA_SOC_H_ */
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