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[kernel] sched_connmark depends on NF_CONNTRACK_MARK (#8976, #9423)
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-2.6.32 / 975-ssb_update.patch
1 --- a/drivers/ssb/driver_chipcommon.c
2 +++ b/drivers/ssb/driver_chipcommon.c
3 @@ -209,6 +209,24 @@ static void chipco_powercontrol_init(str
4 }
5 }
6
7 +/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
8 +static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
9 +{
10 + struct ssb_bus *bus = cc->dev->bus;
11 +
12 + switch (bus->chip_id) {
13 + case 0x4312:
14 + case 0x4322:
15 + case 0x4328:
16 + return 7000;
17 + case 0x4325:
18 + /* TODO: */
19 + default:
20 + return 15000;
21 + }
22 +}
23 +
24 +/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
25 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
26 {
27 struct ssb_bus *bus = cc->dev->bus;
28 @@ -218,6 +236,12 @@ static void calc_fast_powerup_delay(stru
29
30 if (bus->bustype != SSB_BUSTYPE_PCI)
31 return;
32 +
33 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
34 + cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
35 + return;
36 + }
37 +
38 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
39 return;
40
41 @@ -373,6 +397,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
42 {
43 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
44 }
45 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
46
47 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
48 {
49 --- a/drivers/ssb/driver_chipcommon_pmu.c
50 +++ b/drivers/ssb/driver_chipcommon_pmu.c
51 @@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
52 case 0x5354:
53 ssb_pmu0_pllinit_r0(cc, crystalfreq);
54 break;
55 + case 0x4322:
56 + if (cc->pmu.rev == 2) {
57 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
58 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
59 + }
60 + break;
61 default:
62 ssb_printk(KERN_ERR PFX
63 "ERROR: PLL init unknown for device %04X\n",
64 @@ -417,6 +423,7 @@ static void ssb_pmu_resources_init(struc
65
66 switch (bus->chip_id) {
67 case 0x4312:
68 + case 0x4322:
69 /* We keep the default settings:
70 * min_msk = 0xCBB
71 * max_msk = 0x7FFFF
72 @@ -495,9 +502,9 @@ static void ssb_pmu_resources_init(struc
73 chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
74 }
75
76 +/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */
77 void ssb_pmu_init(struct ssb_chipcommon *cc)
78 {
79 - struct ssb_bus *bus = cc->dev->bus;
80 u32 pmucap;
81
82 if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
83 @@ -509,15 +516,12 @@ void ssb_pmu_init(struct ssb_chipcommon
84 ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
85 cc->pmu.rev, pmucap);
86
87 - if (cc->pmu.rev >= 1) {
88 - if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
89 - chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
90 - ~SSB_CHIPCO_PMU_CTL_NOILPONW);
91 - } else {
92 - chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
93 - SSB_CHIPCO_PMU_CTL_NOILPONW);
94 - }
95 - }
96 + if (cc->pmu.rev == 1)
97 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
98 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
99 + else
100 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
101 + SSB_CHIPCO_PMU_CTL_NOILPONW);
102 ssb_pmu_pll_init(cc);
103 ssb_pmu_resources_init(cc);
104 }
105 --- a/drivers/ssb/driver_gige.c
106 +++ b/drivers/ssb/driver_gige.c
107 @@ -12,6 +12,7 @@
108 #include <linux/ssb/ssb_driver_gige.h>
109 #include <linux/pci.h>
110 #include <linux/pci_regs.h>
111 +#include <linux/slab.h>
112
113
114 /*
115 --- a/drivers/ssb/driver_mipscore.c
116 +++ b/drivers/ssb/driver_mipscore.c
117 @@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
118 set_irq(dev, irq++);
119 }
120 break;
121 - /* fallthrough */
122 case SSB_DEV_PCI:
123 case SSB_DEV_ETHERNET:
124 case SSB_DEV_ETHERNET_GBIT:
125 @@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
126 set_irq(dev, irq++);
127 break;
128 }
129 + /* fallthrough */
130 + case SSB_DEV_EXTIF:
131 + set_irq(dev, 0);
132 + break;
133 }
134 }
135 ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
136 --- a/drivers/ssb/driver_pcicore.c
137 +++ b/drivers/ssb/driver_pcicore.c
138 @@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
139 .pci_ops = &ssb_pcicore_pciops,
140 .io_resource = &ssb_pcicore_io_resource,
141 .mem_resource = &ssb_pcicore_mem_resource,
142 - .mem_offset = 0x24000000,
143 };
144
145 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
146 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
147 -
148 /* This function is called when doing a pci_enable_device().
149 * We must first check if the device is a device on the PCI-core bridge. */
150 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
151 {
152 - struct resource *res;
153 - int pos, size;
154 - u32 *base;
155 -
156 if (d->bus->ops != &ssb_pcicore_pciops) {
157 /* This is not a device on the PCI-core bridge. */
158 return -ENODEV;
159 @@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
160 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
161 pci_name(d));
162
163 - /* Fix up resource bases */
164 - for (pos = 0; pos < 6; pos++) {
165 - res = &d->resource[pos];
166 - if (res->flags & IORESOURCE_IO)
167 - base = &ssb_pcicore_pcibus_iobase;
168 - else
169 - base = &ssb_pcicore_pcibus_membase;
170 - res->flags |= IORESOURCE_PCI_FIXED;
171 - if (res->end) {
172 - size = res->end - res->start + 1;
173 - if (*base & (size - 1))
174 - *base = (*base + size) & ~(size - 1);
175 - res->start = *base;
176 - res->end = res->start + size - 1;
177 - *base += size;
178 - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
179 - }
180 - /* Fix up PCI bridge BAR0 only */
181 - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
182 - break;
183 - }
184 /* Fix up interrupt lines */
185 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
186 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
187 @@ -551,13 +522,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc
188 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
189
190 /* Enable interrupts for this device. */
191 - if (bus->host_pci &&
192 - ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
193 + if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
194 u32 coremask;
195
196 /* Calculate the "coremask" for the device. */
197 coremask = (1 << dev->core_index);
198
199 + SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
200 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
201 if (err)
202 goto out;
203 --- a/drivers/ssb/main.c
204 +++ b/drivers/ssb/main.c
205 @@ -18,6 +18,7 @@
206 #include <linux/dma-mapping.h>
207 #include <linux/pci.h>
208 #include <linux/mmc/sdio_func.h>
209 +#include <linux/slab.h>
210
211 #include <pcmcia/cs_types.h>
212 #include <pcmcia/cs.h>
213 @@ -140,6 +141,19 @@ static void ssb_device_put(struct ssb_de
214 put_device(dev->dev);
215 }
216
217 +static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
218 +{
219 + if (drv)
220 + get_driver(&drv->drv);
221 + return drv;
222 +}
223 +
224 +static inline void ssb_driver_put(struct ssb_driver *drv)
225 +{
226 + if (drv)
227 + put_driver(&drv->drv);
228 +}
229 +
230 static int ssb_device_resume(struct device *dev)
231 {
232 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
233 @@ -210,90 +224,81 @@ int ssb_bus_suspend(struct ssb_bus *bus)
234 EXPORT_SYMBOL(ssb_bus_suspend);
235
236 #ifdef CONFIG_SSB_SPROM
237 -int ssb_devices_freeze(struct ssb_bus *bus)
238 +/** ssb_devices_freeze - Freeze all devices on the bus.
239 + *
240 + * After freezing no device driver will be handling a device
241 + * on this bus anymore. ssb_devices_thaw() must be called after
242 + * a successful freeze to reactivate the devices.
243 + *
244 + * @bus: The bus.
245 + * @ctx: Context structure. Pass this to ssb_devices_thaw().
246 + */
247 +int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
248 {
249 - struct ssb_device *dev;
250 - struct ssb_driver *drv;
251 - int err = 0;
252 - int i;
253 - pm_message_t state = PMSG_FREEZE;
254 + struct ssb_device *sdev;
255 + struct ssb_driver *sdrv;
256 + unsigned int i;
257 +
258 + memset(ctx, 0, sizeof(*ctx));
259 + ctx->bus = bus;
260 + SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
261
262 - /* First check that we are capable to freeze all devices. */
263 for (i = 0; i < bus->nr_devices; i++) {
264 - dev = &(bus->devices[i]);
265 - if (!dev->dev ||
266 - !dev->dev->driver ||
267 - !device_is_registered(dev->dev))
268 - continue;
269 - drv = drv_to_ssb_drv(dev->dev->driver);
270 - if (!drv)
271 + sdev = ssb_device_get(&bus->devices[i]);
272 +
273 + if (!sdev->dev || !sdev->dev->driver ||
274 + !device_is_registered(sdev->dev)) {
275 + ssb_device_put(sdev);
276 continue;
277 - if (!drv->suspend) {
278 - /* Nope, can't suspend this one. */
279 - return -EOPNOTSUPP;
280 }
281 - }
282 - /* Now suspend all devices */
283 - for (i = 0; i < bus->nr_devices; i++) {
284 - dev = &(bus->devices[i]);
285 - if (!dev->dev ||
286 - !dev->dev->driver ||
287 - !device_is_registered(dev->dev))
288 - continue;
289 - drv = drv_to_ssb_drv(dev->dev->driver);
290 - if (!drv)
291 + sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
292 + if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
293 + ssb_device_put(sdev);
294 continue;
295 - err = drv->suspend(dev, state);
296 - if (err) {
297 - ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
298 - dev_name(dev->dev));
299 - goto err_unwind;
300 }
301 + sdrv->remove(sdev);
302 + ctx->device_frozen[i] = 1;
303 }
304
305 return 0;
306 -err_unwind:
307 - for (i--; i >= 0; i--) {
308 - dev = &(bus->devices[i]);
309 - if (!dev->dev ||
310 - !dev->dev->driver ||
311 - !device_is_registered(dev->dev))
312 - continue;
313 - drv = drv_to_ssb_drv(dev->dev->driver);
314 - if (!drv)
315 - continue;
316 - if (drv->resume)
317 - drv->resume(dev);
318 - }
319 - return err;
320 }
321
322 -int ssb_devices_thaw(struct ssb_bus *bus)
323 +/** ssb_devices_thaw - Unfreeze all devices on the bus.
324 + *
325 + * This will re-attach the device drivers and re-init the devices.
326 + *
327 + * @ctx: The context structure from ssb_devices_freeze()
328 + */
329 +int ssb_devices_thaw(struct ssb_freeze_context *ctx)
330 {
331 - struct ssb_device *dev;
332 - struct ssb_driver *drv;
333 - int err;
334 - int i;
335 + struct ssb_bus *bus = ctx->bus;
336 + struct ssb_device *sdev;
337 + struct ssb_driver *sdrv;
338 + unsigned int i;
339 + int err, result = 0;
340
341 for (i = 0; i < bus->nr_devices; i++) {
342 - dev = &(bus->devices[i]);
343 - if (!dev->dev ||
344 - !dev->dev->driver ||
345 - !device_is_registered(dev->dev))
346 + if (!ctx->device_frozen[i])
347 continue;
348 - drv = drv_to_ssb_drv(dev->dev->driver);
349 - if (!drv)
350 + sdev = &bus->devices[i];
351 +
352 + if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
353 continue;
354 - if (SSB_WARN_ON(!drv->resume))
355 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
356 + if (SSB_WARN_ON(!sdrv || !sdrv->probe))
357 continue;
358 - err = drv->resume(dev);
359 +
360 + err = sdrv->probe(sdev, &sdev->id);
361 if (err) {
362 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
363 - dev_name(dev->dev));
364 + dev_name(sdev->dev));
365 + result = err;
366 }
367 + ssb_driver_put(sdrv);
368 + ssb_device_put(sdev);
369 }
370
371 - return 0;
372 + return result;
373 }
374 #endif /* CONFIG_SSB_SPROM */
375
376 @@ -380,6 +385,35 @@ static int ssb_device_uevent(struct devi
377 ssb_dev->id.revision);
378 }
379
380 +#define ssb_config_attr(attrib, field, format_string) \
381 +static ssize_t \
382 +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
383 +{ \
384 + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
385 +}
386 +
387 +ssb_config_attr(core_num, core_index, "%u\n")
388 +ssb_config_attr(coreid, id.coreid, "0x%04x\n")
389 +ssb_config_attr(vendor, id.vendor, "0x%04x\n")
390 +ssb_config_attr(revision, id.revision, "%u\n")
391 +ssb_config_attr(irq, irq, "%u\n")
392 +static ssize_t
393 +name_show(struct device *dev, struct device_attribute *attr, char *buf)
394 +{
395 + return sprintf(buf, "%s\n",
396 + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
397 +}
398 +
399 +static struct device_attribute ssb_device_attrs[] = {
400 + __ATTR_RO(name),
401 + __ATTR_RO(core_num),
402 + __ATTR_RO(coreid),
403 + __ATTR_RO(vendor),
404 + __ATTR_RO(revision),
405 + __ATTR_RO(irq),
406 + __ATTR_NULL,
407 +};
408 +
409 static struct bus_type ssb_bustype = {
410 .name = "ssb",
411 .match = ssb_bus_match,
412 @@ -389,6 +423,7 @@ static struct bus_type ssb_bustype = {
413 .suspend = ssb_device_suspend,
414 .resume = ssb_device_resume,
415 .uevent = ssb_device_uevent,
416 + .dev_attrs = ssb_device_attrs,
417 };
418
419 static void ssb_buses_lock(void)
420 @@ -481,6 +516,7 @@ static int ssb_devices_register(struct s
421 #ifdef CONFIG_SSB_PCIHOST
422 sdev->irq = bus->host_pci->irq;
423 dev->parent = &bus->host_pci->dev;
424 + sdev->dma_dev = dev->parent;
425 #endif
426 break;
427 case SSB_BUSTYPE_PCMCIA:
428 @@ -490,13 +526,13 @@ static int ssb_devices_register(struct s
429 #endif
430 break;
431 case SSB_BUSTYPE_SDIO:
432 -#ifdef CONFIG_SSB_SDIO
433 - sdev->irq = bus->host_sdio->dev.irq;
434 +#ifdef CONFIG_SSB_SDIOHOST
435 dev->parent = &bus->host_sdio->dev;
436 #endif
437 break;
438 case SSB_BUSTYPE_SSB:
439 dev->dma_mask = &dev->coherent_dma_mask;
440 + sdev->dma_dev = dev;
441 break;
442 }
443
444 @@ -830,6 +866,9 @@ int ssb_bus_pcibus_register(struct ssb_b
445 if (!err) {
446 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
447 "PCI device %s\n", dev_name(&host_pci->dev));
448 + } else {
449 + ssb_printk(KERN_ERR PFX "Failed to register PCI version"
450 + " of SSB with error %d\n", err);
451 }
452
453 return err;
454 @@ -1155,10 +1194,10 @@ void ssb_device_enable(struct ssb_device
455 }
456 EXPORT_SYMBOL(ssb_device_enable);
457
458 -/* Wait for a bit in a register to get set or unset.
459 +/* Wait for bitmask in a register to get set or cleared.
460 * timeout is in units of ten-microseconds */
461 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
462 - int timeout, int set)
463 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
464 + int timeout, int set)
465 {
466 int i;
467 u32 val;
468 @@ -1166,7 +1205,7 @@ static int ssb_wait_bit(struct ssb_devic
469 for (i = 0; i < timeout; i++) {
470 val = ssb_read32(dev, reg);
471 if (set) {
472 - if (val & bitmask)
473 + if ((val & bitmask) == bitmask)
474 return 0;
475 } else {
476 if (!(val & bitmask))
477 @@ -1183,20 +1222,38 @@ static int ssb_wait_bit(struct ssb_devic
478
479 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
480 {
481 - u32 reject;
482 + u32 reject, val;
483
484 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
485 return;
486
487 reject = ssb_tmslow_reject_bitmask(dev);
488 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
489 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
490 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
491 - ssb_write32(dev, SSB_TMSLOW,
492 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
493 - reject | SSB_TMSLOW_RESET |
494 - core_specific_flags);
495 - ssb_flush_tmslow(dev);
496 +
497 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
498 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
499 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
500 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
501 +
502 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
503 + val = ssb_read32(dev, SSB_IMSTATE);
504 + val |= SSB_IMSTATE_REJECT;
505 + ssb_write32(dev, SSB_IMSTATE, val);
506 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
507 + 0);
508 + }
509 +
510 + ssb_write32(dev, SSB_TMSLOW,
511 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
512 + reject | SSB_TMSLOW_RESET |
513 + core_specific_flags);
514 + ssb_flush_tmslow(dev);
515 +
516 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
517 + val = ssb_read32(dev, SSB_IMSTATE);
518 + val &= ~SSB_IMSTATE_REJECT;
519 + ssb_write32(dev, SSB_IMSTATE, val);
520 + }
521 + }
522
523 ssb_write32(dev, SSB_TMSLOW,
524 reject | SSB_TMSLOW_RESET |
525 --- a/drivers/ssb/pci.c
526 +++ b/drivers/ssb/pci.c
527 @@ -17,6 +17,7 @@
528
529 #include <linux/ssb/ssb.h>
530 #include <linux/ssb/ssb_regs.h>
531 +#include <linux/slab.h>
532 #include <linux/pci.h>
533 #include <linux/delay.h>
534
535 @@ -167,7 +168,7 @@ err_pci:
536 }
537
538 /* Get the word-offset for a SSB_SPROM_XXX define. */
539 -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE1) / sizeof(u16))
540 +#define SPOFF(offset) ((offset) / sizeof(u16))
541 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
542 #define SPEX16(_outvar, _offset, _mask, _shift) \
543 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
544 @@ -405,6 +406,46 @@ static void sprom_extract_r123(struct ss
545 out->antenna_gain.ghz5.a3 = gain;
546 }
547
548 +/* Revs 4 5 and 8 have partially shared layout */
549 +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
550 +{
551 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
552 + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
553 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
554 + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
555 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
556 + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
557 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
558 + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
559 +
560 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
561 + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
562 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
563 + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
564 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
565 + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
566 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
567 + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
568 +
569 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
570 + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
571 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
572 + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
573 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
574 + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
575 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
576 + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
577 +
578 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
579 + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
580 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
581 + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
582 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
583 + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
584 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
585 + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
586 +}
587 +
588 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
589 {
590 int i;
591 @@ -427,10 +468,14 @@ static void sprom_extract_r45(struct ssb
592 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
593 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
594 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
595 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
596 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
597 } else {
598 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
599 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
600 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
601 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
602 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
603 }
604 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
605 SSB_SPROM4_ANTAVAIL_A_SHIFT);
606 @@ -470,6 +515,8 @@ static void sprom_extract_r45(struct ssb
607 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
608 sizeof(out->antenna_gain.ghz5));
609
610 + sprom_extract_r458(out, in);
611 +
612 /* TODO - get remaining rev 4 stuff needed */
613 }
614
615 @@ -560,6 +607,8 @@ static void sprom_extract_r8(struct ssb_
616 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
617 sizeof(out->antenna_gain.ghz5));
618
619 + sprom_extract_r458(out, in);
620 +
621 /* TODO - get remaining rev 8 stuff needed */
622 }
623
624 @@ -572,37 +621,34 @@ static int sprom_extract(struct ssb_bus
625 ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
626 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
627 memset(out->et1mac, 0xFF, 6);
628 +
629 if ((bus->chip_id & 0xFF00) == 0x4400) {
630 /* Workaround: The BCM44XX chip has a stupid revision
631 * number stored in the SPROM.
632 * Always extract r1. */
633 out->revision = 1;
634 + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
635 + }
636 +
637 + switch (out->revision) {
638 + case 1:
639 + case 2:
640 + case 3:
641 sprom_extract_r123(out, in);
642 - } else if (bus->chip_id == 0x4321) {
643 - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
644 - out->revision = 4;
645 + break;
646 + case 4:
647 + case 5:
648 sprom_extract_r45(out, in);
649 - } else {
650 - switch (out->revision) {
651 - case 1:
652 - case 2:
653 - case 3:
654 - sprom_extract_r123(out, in);
655 - break;
656 - case 4:
657 - case 5:
658 - sprom_extract_r45(out, in);
659 - break;
660 - case 8:
661 - sprom_extract_r8(out, in);
662 - break;
663 - default:
664 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
665 - " revision %d detected. Will extract"
666 - " v1\n", out->revision);
667 - out->revision = 1;
668 - sprom_extract_r123(out, in);
669 - }
670 + break;
671 + case 8:
672 + sprom_extract_r8(out, in);
673 + break;
674 + default:
675 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
676 + " revision %d detected. Will extract"
677 + " v1\n", out->revision);
678 + out->revision = 1;
679 + sprom_extract_r123(out, in);
680 }
681
682 if (out->boardflags_lo == 0xFFFF)
683 @@ -617,7 +663,7 @@ static int ssb_pci_sprom_get(struct ssb_
684 struct ssb_sprom *sprom)
685 {
686 const struct ssb_sprom *fallback;
687 - int err = -ENOMEM;
688 + int err;
689 u16 *buf;
690
691 if (!ssb_is_sprom_available(bus)) {
692 @@ -644,7 +690,7 @@ static int ssb_pci_sprom_get(struct ssb_
693
694 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
695 if (!buf)
696 - goto out;
697 + return -ENOMEM;
698 bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
699 sprom_do_read(bus, buf);
700 err = sprom_check_crc(buf, bus->sprom_size);
701 @@ -654,7 +700,7 @@ static int ssb_pci_sprom_get(struct ssb_
702 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
703 GFP_KERNEL);
704 if (!buf)
705 - goto out;
706 + return -ENOMEM;
707 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
708 sprom_do_read(bus, buf);
709 err = sprom_check_crc(buf, bus->sprom_size);
710 @@ -676,7 +722,6 @@ static int ssb_pci_sprom_get(struct ssb_
711
712 out_free:
713 kfree(buf);
714 -out:
715 return err;
716 }
717
718 --- a/drivers/ssb/pcihost_wrapper.c
719 +++ b/drivers/ssb/pcihost_wrapper.c
720 @@ -12,6 +12,7 @@
721 */
722
723 #include <linux/pci.h>
724 +#include <linux/slab.h>
725 #include <linux/ssb/ssb.h>
726
727
728 @@ -58,6 +59,7 @@ static int ssb_pcihost_probe(struct pci_
729 struct ssb_bus *ssb;
730 int err = -ENOMEM;
731 const char *name;
732 + u32 val;
733
734 ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
735 if (!ssb)
736 @@ -73,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
737 goto err_pci_disable;
738 pci_set_master(dev);
739
740 + /* Disable the RETRY_TIMEOUT register (0x41) to keep
741 + * PCI Tx retries from interfering with C3 CPU state */
742 + pci_read_config_dword(dev, 0x40, &val);
743 + if ((val & 0x0000ff00) != 0)
744 + pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
745 +
746 err = ssb_bus_pcibus_register(ssb, dev);
747 if (err)
748 goto err_pci_release_regions;
749 --- a/drivers/ssb/pcmcia.c
750 +++ b/drivers/ssb/pcmcia.c
751 @@ -617,136 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co
752 } \
753 } while (0)
754
755 -int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
756 - struct ssb_init_invariants *iv)
757 +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
758 + tuple_t *tuple,
759 + void *priv)
760 {
761 - tuple_t tuple;
762 - int res;
763 - unsigned char buf[32];
764 + struct ssb_sprom *sprom = priv;
765 +
766 + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
767 + return -EINVAL;
768 + if (tuple->TupleDataLen != ETH_ALEN + 2)
769 + return -EINVAL;
770 + if (tuple->TupleData[1] != ETH_ALEN)
771 + return -EINVAL;
772 + memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
773 + return 0;
774 +};
775 +
776 +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
777 + tuple_t *tuple,
778 + void *priv)
779 +{
780 + struct ssb_init_invariants *iv = priv;
781 struct ssb_sprom *sprom = &iv->sprom;
782 struct ssb_boardinfo *bi = &iv->boardinfo;
783 const char *error_description;
784
785 + GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
786 + switch (tuple->TupleData[0]) {
787 + case SSB_PCMCIA_CIS_ID:
788 + GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
789 + (tuple->TupleDataLen != 7),
790 + "id tpl size");
791 + bi->vendor = tuple->TupleData[1] |
792 + ((u16)tuple->TupleData[2] << 8);
793 + break;
794 + case SSB_PCMCIA_CIS_BOARDREV:
795 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
796 + "boardrev tpl size");
797 + sprom->board_rev = tuple->TupleData[1];
798 + break;
799 + case SSB_PCMCIA_CIS_PA:
800 + GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
801 + (tuple->TupleDataLen != 10),
802 + "pa tpl size");
803 + sprom->pa0b0 = tuple->TupleData[1] |
804 + ((u16)tuple->TupleData[2] << 8);
805 + sprom->pa0b1 = tuple->TupleData[3] |
806 + ((u16)tuple->TupleData[4] << 8);
807 + sprom->pa0b2 = tuple->TupleData[5] |
808 + ((u16)tuple->TupleData[6] << 8);
809 + sprom->itssi_a = tuple->TupleData[7];
810 + sprom->itssi_bg = tuple->TupleData[7];
811 + sprom->maxpwr_a = tuple->TupleData[8];
812 + sprom->maxpwr_bg = tuple->TupleData[8];
813 + break;
814 + case SSB_PCMCIA_CIS_OEMNAME:
815 + /* We ignore this. */
816 + break;
817 + case SSB_PCMCIA_CIS_CCODE:
818 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
819 + "ccode tpl size");
820 + sprom->country_code = tuple->TupleData[1];
821 + break;
822 + case SSB_PCMCIA_CIS_ANTENNA:
823 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
824 + "ant tpl size");
825 + sprom->ant_available_a = tuple->TupleData[1];
826 + sprom->ant_available_bg = tuple->TupleData[1];
827 + break;
828 + case SSB_PCMCIA_CIS_ANTGAIN:
829 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
830 + "antg tpl size");
831 + sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
832 + sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
833 + sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
834 + sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
835 + sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
836 + sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
837 + sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
838 + sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
839 + break;
840 + case SSB_PCMCIA_CIS_BFLAGS:
841 + GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
842 + (tuple->TupleDataLen != 5),
843 + "bfl tpl size");
844 + sprom->boardflags_lo = tuple->TupleData[1] |
845 + ((u16)tuple->TupleData[2] << 8);
846 + break;
847 + case SSB_PCMCIA_CIS_LEDS:
848 + GOTO_ERROR_ON(tuple->TupleDataLen != 5,
849 + "leds tpl size");
850 + sprom->gpio0 = tuple->TupleData[1];
851 + sprom->gpio1 = tuple->TupleData[2];
852 + sprom->gpio2 = tuple->TupleData[3];
853 + sprom->gpio3 = tuple->TupleData[4];
854 + break;
855 + }
856 + return -ENOSPC; /* continue with next entry */
857 +
858 +error:
859 + ssb_printk(KERN_ERR PFX
860 + "PCMCIA: Failed to fetch device invariants: %s\n",
861 + error_description);
862 + return -ENODEV;
863 +}
864 +
865 +
866 +int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
867 + struct ssb_init_invariants *iv)
868 +{
869 + struct ssb_sprom *sprom = &iv->sprom;
870 + int res;
871 +
872 memset(sprom, 0xFF, sizeof(*sprom));
873 sprom->revision = 1;
874 sprom->boardflags_lo = 0;
875 sprom->boardflags_hi = 0;
876
877 /* First fetch the MAC address. */
878 - memset(&tuple, 0, sizeof(tuple));
879 - tuple.DesiredTuple = CISTPL_FUNCE;
880 - tuple.TupleData = buf;
881 - tuple.TupleDataMax = sizeof(buf);
882 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
883 - GOTO_ERROR_ON(res != 0, "MAC first tpl");
884 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
885 - GOTO_ERROR_ON(res != 0, "MAC first tpl data");
886 - while (1) {
887 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
888 - if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
889 - break;
890 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
891 - GOTO_ERROR_ON(res != 0, "MAC next tpl");
892 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
893 - GOTO_ERROR_ON(res != 0, "MAC next tpl data");
894 + res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
895 + ssb_pcmcia_get_mac, sprom);
896 + if (res != 0) {
897 + ssb_printk(KERN_ERR PFX
898 + "PCMCIA: Failed to fetch MAC address\n");
899 + return -ENODEV;
900 }
901 - GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
902 - memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
903
904 /* Fetch the vendor specific tuples. */
905 - memset(&tuple, 0, sizeof(tuple));
906 - tuple.DesiredTuple = SSB_PCMCIA_CIS;
907 - tuple.TupleData = buf;
908 - tuple.TupleDataMax = sizeof(buf);
909 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
910 - GOTO_ERROR_ON(res != 0, "VEN first tpl");
911 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
912 - GOTO_ERROR_ON(res != 0, "VEN first tpl data");
913 - while (1) {
914 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
915 - switch (tuple.TupleData[0]) {
916 - case SSB_PCMCIA_CIS_ID:
917 - GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
918 - (tuple.TupleDataLen != 7),
919 - "id tpl size");
920 - bi->vendor = tuple.TupleData[1] |
921 - ((u16)tuple.TupleData[2] << 8);
922 - break;
923 - case SSB_PCMCIA_CIS_BOARDREV:
924 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
925 - "boardrev tpl size");
926 - sprom->board_rev = tuple.TupleData[1];
927 - break;
928 - case SSB_PCMCIA_CIS_PA:
929 - GOTO_ERROR_ON((tuple.TupleDataLen != 9) &&
930 - (tuple.TupleDataLen != 10),
931 - "pa tpl size");
932 - sprom->pa0b0 = tuple.TupleData[1] |
933 - ((u16)tuple.TupleData[2] << 8);
934 - sprom->pa0b1 = tuple.TupleData[3] |
935 - ((u16)tuple.TupleData[4] << 8);
936 - sprom->pa0b2 = tuple.TupleData[5] |
937 - ((u16)tuple.TupleData[6] << 8);
938 - sprom->itssi_a = tuple.TupleData[7];
939 - sprom->itssi_bg = tuple.TupleData[7];
940 - sprom->maxpwr_a = tuple.TupleData[8];
941 - sprom->maxpwr_bg = tuple.TupleData[8];
942 - break;
943 - case SSB_PCMCIA_CIS_OEMNAME:
944 - /* We ignore this. */
945 - break;
946 - case SSB_PCMCIA_CIS_CCODE:
947 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
948 - "ccode tpl size");
949 - sprom->country_code = tuple.TupleData[1];
950 - break;
951 - case SSB_PCMCIA_CIS_ANTENNA:
952 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
953 - "ant tpl size");
954 - sprom->ant_available_a = tuple.TupleData[1];
955 - sprom->ant_available_bg = tuple.TupleData[1];
956 - break;
957 - case SSB_PCMCIA_CIS_ANTGAIN:
958 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
959 - "antg tpl size");
960 - sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
961 - sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
962 - sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
963 - sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
964 - sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
965 - sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
966 - sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
967 - sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
968 - break;
969 - case SSB_PCMCIA_CIS_BFLAGS:
970 - GOTO_ERROR_ON((tuple.TupleDataLen != 3) &&
971 - (tuple.TupleDataLen != 5),
972 - "bfl tpl size");
973 - sprom->boardflags_lo = tuple.TupleData[1] |
974 - ((u16)tuple.TupleData[2] << 8);
975 - break;
976 - case SSB_PCMCIA_CIS_LEDS:
977 - GOTO_ERROR_ON(tuple.TupleDataLen != 5,
978 - "leds tpl size");
979 - sprom->gpio0 = tuple.TupleData[1];
980 - sprom->gpio1 = tuple.TupleData[2];
981 - sprom->gpio2 = tuple.TupleData[3];
982 - sprom->gpio3 = tuple.TupleData[4];
983 - break;
984 - }
985 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
986 - if (res == -ENOSPC)
987 - break;
988 - GOTO_ERROR_ON(res != 0, "VEN next tpl");
989 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
990 - GOTO_ERROR_ON(res != 0, "VEN next tpl data");
991 - }
992 + res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
993 + ssb_pcmcia_do_get_invariants, iv);
994 + if ((res == 0) || (res == -ENOSPC))
995 + return 0;
996
997 - return 0;
998 -error:
999 ssb_printk(KERN_ERR PFX
1000 - "PCMCIA: Failed to fetch device invariants: %s\n",
1001 - error_description);
1002 + "PCMCIA: Failed to fetch device invariants\n");
1003 return -ENODEV;
1004 }
1005
1006 --- a/drivers/ssb/scan.c
1007 +++ b/drivers/ssb/scan.c
1008 @@ -354,7 +354,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1009 dev->bus = bus;
1010 dev->ops = bus->ops;
1011
1012 - ssb_dprintk(KERN_INFO PFX
1013 + printk(KERN_DEBUG PFX
1014 "Core %d found: %s "
1015 "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
1016 i, ssb_core_name(dev->id.coreid),
1017 @@ -422,6 +422,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
1018 bus->pcicore.dev = dev;
1019 #endif /* CONFIG_SSB_DRIVER_PCICORE */
1020 break;
1021 + case SSB_DEV_ETHERNET:
1022 + if (bus->bustype == SSB_BUSTYPE_PCI) {
1023 + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
1024 + (bus->host_pci->device & 0xFF00) == 0x4300) {
1025 + /* This is a dangling ethernet core on a
1026 + * wireless device. Ignore it. */
1027 + continue;
1028 + }
1029 + }
1030 + break;
1031 default:
1032 break;
1033 }
1034 --- a/drivers/ssb/sprom.c
1035 +++ b/drivers/ssb/sprom.c
1036 @@ -14,6 +14,7 @@
1037 #include "ssb_private.h"
1038
1039 #include <linux/ctype.h>
1040 +#include <linux/slab.h>
1041
1042
1043 static const struct ssb_sprom *fallback_sprom;
1044 @@ -102,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1045 u16 *sprom;
1046 int res = 0, err = -ENOMEM;
1047 size_t sprom_size_words = bus->sprom_size;
1048 + struct ssb_freeze_context freeze;
1049
1050 sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
1051 if (!sprom)
1052 @@ -123,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1053 err = -ERESTARTSYS;
1054 if (mutex_lock_interruptible(&bus->sprom_mutex))
1055 goto out_kfree;
1056 - err = ssb_devices_freeze(bus);
1057 - if (err == -EOPNOTSUPP) {
1058 - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
1059 - "No suspend support. Is CONFIG_PM enabled?\n");
1060 - goto out_unlock;
1061 - }
1062 + err = ssb_devices_freeze(bus, &freeze);
1063 if (err) {
1064 ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
1065 goto out_unlock;
1066 }
1067 res = sprom_write(bus, sprom);
1068 - err = ssb_devices_thaw(bus);
1069 + err = ssb_devices_thaw(&freeze);
1070 if (err)
1071 ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
1072 out_unlock:
1073 --- a/drivers/ssb/ssb_private.h
1074 +++ b/drivers/ssb/ssb_private.h
1075 @@ -176,19 +176,27 @@ extern const struct ssb_sprom *ssb_get_f
1076
1077 /* core.c */
1078 extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
1079 -extern int ssb_devices_freeze(struct ssb_bus *bus);
1080 -extern int ssb_devices_thaw(struct ssb_bus *bus);
1081 extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
1082 int ssb_for_each_bus_call(unsigned long data,
1083 int (*func)(struct ssb_bus *bus, unsigned long data));
1084 extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
1085
1086 +struct ssb_freeze_context {
1087 + /* Pointer to the bus */
1088 + struct ssb_bus *bus;
1089 + /* Boolean list to indicate whether a device is frozen on this bus. */
1090 + bool device_frozen[SSB_MAX_NR_CORES];
1091 +};
1092 +extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
1093 +extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
1094 +
1095 +
1096
1097 /* b43_pci_bridge.c */
1098 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
1099 extern int __init b43_pci_ssb_bridge_init(void);
1100 extern void __exit b43_pci_ssb_bridge_exit(void);
1101 -#else /* CONFIG_SSB_B43_PCI_BRIDGR */
1102 +#else /* CONFIG_SSB_B43_PCI_BRIDGE */
1103 static inline int b43_pci_ssb_bridge_init(void)
1104 {
1105 return 0;
1106 @@ -196,6 +204,6 @@ static inline int b43_pci_ssb_bridge_ini
1107 static inline void b43_pci_ssb_bridge_exit(void)
1108 {
1109 }
1110 -#endif /* CONFIG_SSB_PCIHOST */
1111 +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
1112
1113 #endif /* LINUX_SSB_PRIVATE_H_ */
1114 --- a/include/linux/ssb/ssb.h
1115 +++ b/include/linux/ssb/ssb.h
1116 @@ -55,6 +55,10 @@ struct ssb_sprom {
1117 u8 tri5gl; /* 5.2GHz TX isolation */
1118 u8 tri5g; /* 5.3GHz TX isolation */
1119 u8 tri5gh; /* 5.8GHz TX isolation */
1120 + u8 txpid2g[4]; /* 2GHz TX power index */
1121 + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
1122 + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
1123 + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
1124 u8 rxpo2g; /* 2GHz RX power offset */
1125 u8 rxpo5g; /* 5GHz RX power offset */
1126 u8 rssisav2g; /* 2GHz RSSI params */
1127 @@ -167,7 +171,7 @@ struct ssb_device {
1128 * is an optimization. */
1129 const struct ssb_bus_ops *ops;
1130
1131 - struct device *dev;
1132 + struct device *dev, *dma_dev;
1133
1134 struct ssb_bus *bus;
1135 struct ssb_device_id id;
1136 @@ -269,7 +273,8 @@ struct ssb_bus {
1137
1138 const struct ssb_bus_ops *ops;
1139
1140 - /* The core in the basic address register window. (PCI bus only) */
1141 + /* The core currently mapped into the MMIO window.
1142 + * Not valid on all host-buses. So don't use outside of SSB. */
1143 struct ssb_device *mapped_device;
1144 union {
1145 /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
1146 @@ -281,14 +286,17 @@ struct ssb_bus {
1147 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
1148 spinlock_t bar_lock;
1149
1150 - /* The bus this backplane is running on. */
1151 + /* The host-bus this backplane is running on. */
1152 enum ssb_bustype bustype;
1153 - /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
1154 - struct pci_dev *host_pci;
1155 - /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
1156 - struct pcmcia_device *host_pcmcia;
1157 - /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
1158 - struct sdio_func *host_sdio;
1159 + /* Pointers to the host-bus. Check bustype before using any of these pointers. */
1160 + union {
1161 + /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
1162 + struct pci_dev *host_pci;
1163 + /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
1164 + struct pcmcia_device *host_pcmcia;
1165 + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
1166 + struct sdio_func *host_sdio;
1167 + };
1168
1169 /* See enum ssb_quirks */
1170 unsigned int quirks;
1171 --- a/include/linux/ssb/ssb_regs.h
1172 +++ b/include/linux/ssb/ssb_regs.h
1173 @@ -85,6 +85,8 @@
1174 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
1175 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
1176 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
1177 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
1178 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
1179 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
1180 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
1181 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
1182 @@ -172,25 +174,25 @@
1183 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
1184 #define SSB_SPROM_BASE1 0x1000
1185 #define SSB_SPROM_BASE31 0x0800
1186 -#define SSB_SPROM_REVISION 0x107E
1187 +#define SSB_SPROM_REVISION 0x007E
1188 #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
1189 #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
1190 #define SSB_SPROM_REVISION_CRC_SHIFT 8
1191
1192 /* SPROM Revision 1 */
1193 -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
1194 -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
1195 -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
1196 -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
1197 -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
1198 -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
1199 -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
1200 +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
1201 +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
1202 +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
1203 +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
1204 +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
1205 +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
1206 +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
1207 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
1208 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
1209 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
1210 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
1211 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
1212 -#define SSB_SPROM1_BINF 0x105C /* Board info */
1213 +#define SSB_SPROM1_BINF 0x005C /* Board info */
1214 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
1215 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
1216 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
1217 @@ -198,63 +200,63 @@
1218 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
1219 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
1220 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
1221 -#define SSB_SPROM1_PA0B0 0x105E
1222 -#define SSB_SPROM1_PA0B1 0x1060
1223 -#define SSB_SPROM1_PA0B2 0x1062
1224 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
1225 +#define SSB_SPROM1_PA0B0 0x005E
1226 +#define SSB_SPROM1_PA0B1 0x0060
1227 +#define SSB_SPROM1_PA0B2 0x0062
1228 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
1229 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
1230 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
1231 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
1232 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
1233 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
1234 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
1235 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
1236 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
1237 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
1238 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
1239 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
1240 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
1241 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
1242 -#define SSB_SPROM1_PA1B0 0x106A
1243 -#define SSB_SPROM1_PA1B1 0x106C
1244 -#define SSB_SPROM1_PA1B2 0x106E
1245 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
1246 +#define SSB_SPROM1_PA1B0 0x006A
1247 +#define SSB_SPROM1_PA1B1 0x006C
1248 +#define SSB_SPROM1_PA1B2 0x006E
1249 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
1250 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
1251 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
1252 #define SSB_SPROM1_ITSSI_A_SHIFT 8
1253 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
1254 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
1255 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
1256 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
1257 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
1258 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
1259 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
1260 #define SSB_SPROM1_AGAIN_A_SHIFT 8
1261
1262 /* SPROM Revision 2 (inherits from rev 1) */
1263 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
1264 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
1265 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
1266 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
1267 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
1268 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
1269 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
1270 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
1271 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
1272 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
1273 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
1274 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
1275 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
1276 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
1277 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
1278 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
1279 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
1280 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
1281 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
1282 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
1283 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
1284 #define SSB_SPROM2_OPO_VALUE 0x00FF
1285 #define SSB_SPROM2_OPO_UNUSED 0xFF00
1286 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
1287 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
1288
1289 /* SPROM Revision 3 (inherits most data from rev 2) */
1290 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
1291 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
1292 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
1293 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
1294 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
1295 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
1296 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
1297 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
1298 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
1299 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
1300 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
1301 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
1302 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
1303 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
1304 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
1305 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
1306 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
1307 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
1308 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
1309 @@ -265,100 +267,144 @@
1310 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
1311
1312 /* SPROM Revision 4 */
1313 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
1314 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
1315 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
1316 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
1317 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
1318 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
1319 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
1320 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
1321 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
1322 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
1323 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
1324 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
1325 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
1326 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
1327 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
1328 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
1329 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
1330 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
1331 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
1332 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
1333 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
1334 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
1335 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
1336 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
1337 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
1338 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
1339 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
1340 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
1341 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
1342 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
1343 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
1344 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
1345 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
1346 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
1347 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
1348 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
1349 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
1350 #define SSB_SPROM4_AGAIN0_SHIFT 0
1351 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
1352 #define SSB_SPROM4_AGAIN1_SHIFT 8
1353 -#define SSB_SPROM4_AGAIN23 0x1060
1354 +#define SSB_SPROM4_AGAIN23 0x0060
1355 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
1356 #define SSB_SPROM4_AGAIN2_SHIFT 0
1357 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
1358 #define SSB_SPROM4_AGAIN3_SHIFT 8
1359 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
1360 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
1361 +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
1362 +#define SSB_SPROM4_TXPID2G0 0x00FF
1363 +#define SSB_SPROM4_TXPID2G0_SHIFT 0
1364 +#define SSB_SPROM4_TXPID2G1 0xFF00
1365 +#define SSB_SPROM4_TXPID2G1_SHIFT 8
1366 +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
1367 +#define SSB_SPROM4_TXPID2G2 0x00FF
1368 +#define SSB_SPROM4_TXPID2G2_SHIFT 0
1369 +#define SSB_SPROM4_TXPID2G3 0xFF00
1370 +#define SSB_SPROM4_TXPID2G3_SHIFT 8
1371 +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
1372 +#define SSB_SPROM4_TXPID5G0 0x00FF
1373 +#define SSB_SPROM4_TXPID5G0_SHIFT 0
1374 +#define SSB_SPROM4_TXPID5G1 0xFF00
1375 +#define SSB_SPROM4_TXPID5G1_SHIFT 8
1376 +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
1377 +#define SSB_SPROM4_TXPID5G2 0x00FF
1378 +#define SSB_SPROM4_TXPID5G2_SHIFT 0
1379 +#define SSB_SPROM4_TXPID5G3 0xFF00
1380 +#define SSB_SPROM4_TXPID5G3_SHIFT 8
1381 +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
1382 +#define SSB_SPROM4_TXPID5GL0 0x00FF
1383 +#define SSB_SPROM4_TXPID5GL0_SHIFT 0
1384 +#define SSB_SPROM4_TXPID5GL1 0xFF00
1385 +#define SSB_SPROM4_TXPID5GL1_SHIFT 8
1386 +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
1387 +#define SSB_SPROM4_TXPID5GL2 0x00FF
1388 +#define SSB_SPROM4_TXPID5GL2_SHIFT 0
1389 +#define SSB_SPROM4_TXPID5GL3 0xFF00
1390 +#define SSB_SPROM4_TXPID5GL3_SHIFT 8
1391 +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
1392 +#define SSB_SPROM4_TXPID5GH0 0x00FF
1393 +#define SSB_SPROM4_TXPID5GH0_SHIFT 0
1394 +#define SSB_SPROM4_TXPID5GH1 0xFF00
1395 +#define SSB_SPROM4_TXPID5GH1_SHIFT 8
1396 +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
1397 +#define SSB_SPROM4_TXPID5GH2 0x00FF
1398 +#define SSB_SPROM4_TXPID5GH2_SHIFT 0
1399 +#define SSB_SPROM4_TXPID5GH3 0xFF00
1400 +#define SSB_SPROM4_TXPID5GH3_SHIFT 8
1401 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
1402 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
1403 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1404 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
1405 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
1406 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
1407 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
1408 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
1409 #define SSB_SPROM4_ITSSI_A_SHIFT 8
1410 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
1411 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
1412 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
1413 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
1414 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
1415 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
1416 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
1417 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
1418 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
1419 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
1420 -#define SSB_SPROM4_PA0B2 0x1086
1421 -#define SSB_SPROM4_PA1B0 0x108E
1422 -#define SSB_SPROM4_PA1B1 0x1090
1423 -#define SSB_SPROM4_PA1B2 0x1092
1424 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
1425 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
1426 +#define SSB_SPROM4_PA0B2 0x0086
1427 +#define SSB_SPROM4_PA1B0 0x008E
1428 +#define SSB_SPROM4_PA1B1 0x0090
1429 +#define SSB_SPROM4_PA1B2 0x0092
1430
1431 /* SPROM Revision 5 (inherits most data from rev 4) */
1432 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
1433 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
1434 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
1435 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
1436 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
1437 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
1438 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
1439 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
1440 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
1441 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
1442 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
1443 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
1444 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
1445 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
1446 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
1447 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
1448 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
1449 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
1450 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
1451 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
1452
1453 /* SPROM Revision 8 */
1454 -#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
1455 -#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
1456 -#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
1457 -#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
1458 -#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
1459 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
1460 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
1461 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
1462 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1463 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1464 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1465 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
1466 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
1467 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
1468 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
1469 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
1470 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
1471 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
1472 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
1473 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
1474 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
1475 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
1476 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
1477 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
1478 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
1479 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1480 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1481 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
1482 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
1483 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1484 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1485 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1486 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
1487 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
1488 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
1489 #define SSB_SPROM8_AGAIN0_SHIFT 0
1490 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
1491 #define SSB_SPROM8_AGAIN1_SHIFT 8
1492 -#define SSB_SPROM8_AGAIN23 0x10A0
1493 +#define SSB_SPROM8_AGAIN23 0x00A0
1494 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
1495 #define SSB_SPROM8_AGAIN2_SHIFT 0
1496 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
1497 #define SSB_SPROM8_AGAIN3_SHIFT 8
1498 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
1499 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
1500 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
1501 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
1502 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
1503 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1504 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1505 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
1506 -#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
1507 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
1508 #define SSB_SPROM8_RSSISMF2G 0x000F
1509 #define SSB_SPROM8_RSSISMC2G 0x00F0
1510 #define SSB_SPROM8_RSSISMC2G_SHIFT 4
1511 @@ -366,7 +412,7 @@
1512 #define SSB_SPROM8_RSSISAV2G_SHIFT 8
1513 #define SSB_SPROM8_BXA2G 0x1800
1514 #define SSB_SPROM8_BXA2G_SHIFT 11
1515 -#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
1516 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
1517 #define SSB_SPROM8_RSSISMF5G 0x000F
1518 #define SSB_SPROM8_RSSISMC5G 0x00F0
1519 #define SSB_SPROM8_RSSISMC5G_SHIFT 4
1520 @@ -374,47 +420,47 @@
1521 #define SSB_SPROM8_RSSISAV5G_SHIFT 8
1522 #define SSB_SPROM8_BXA5G 0x1800
1523 #define SSB_SPROM8_BXA5G_SHIFT 11
1524 -#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
1525 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
1526 #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
1527 #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
1528 #define SSB_SPROM8_TRI5G_SHIFT 8
1529 -#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
1530 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
1531 #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
1532 #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
1533 #define SSB_SPROM8_TRI5GH_SHIFT 8
1534 -#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
1535 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
1536 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
1537 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
1538 #define SSB_SPROM8_RXPO5G_SHIFT 8
1539 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
1540 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
1541 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1542 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1543 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
1544 -#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
1545 -#define SSB_SPROM8_PA0B1 0x10C4
1546 -#define SSB_SPROM8_PA0B2 0x10C6
1547 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
1548 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
1549 +#define SSB_SPROM8_PA0B1 0x00C4
1550 +#define SSB_SPROM8_PA0B2 0x00C6
1551 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
1552 #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
1553 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
1554 #define SSB_SPROM8_ITSSI_A_SHIFT 8
1555 -#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
1556 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
1557 #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
1558 #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
1559 #define SSB_SPROM8_MAXP_AL_SHIFT 8
1560 -#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
1561 -#define SSB_SPROM8_PA1B1 0x10CE
1562 -#define SSB_SPROM8_PA1B2 0x10D0
1563 -#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
1564 -#define SSB_SPROM8_PA1LOB1 0x10D4
1565 -#define SSB_SPROM8_PA1LOB2 0x10D6
1566 -#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
1567 -#define SSB_SPROM8_PA1HIB1 0x10DA
1568 -#define SSB_SPROM8_PA1HIB2 0x10DC
1569 -#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
1570 -#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
1571 -#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
1572 -#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
1573 -#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
1574 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
1575 +#define SSB_SPROM8_PA1B1 0x00CE
1576 +#define SSB_SPROM8_PA1B2 0x00D0
1577 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
1578 +#define SSB_SPROM8_PA1LOB1 0x00D4
1579 +#define SSB_SPROM8_PA1LOB2 0x00D6
1580 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
1581 +#define SSB_SPROM8_PA1HIB1 0x00DA
1582 +#define SSB_SPROM8_PA1HIB2 0x00DC
1583 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
1584 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
1585 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
1586 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1587 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
1588
1589 /* Values for SSB_SPROM1_BINF_CCODE */
1590 enum {
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