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[openwrt/svn-archive/archive.git] / target / linux / generic / patches-2.6.37 / 020-ssb_update.patch
1 --- a/drivers/ssb/main.c
2 +++ b/drivers/ssb/main.c
3 @@ -3,7 +3,7 @@
4 * Subsystem core
5 *
6 * Copyright 2005, Broadcom Corporation
7 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
9 *
10 * Licensed under the GNU/GPL. See COPYING for details.
11 */
12 @@ -12,6 +12,7 @@
13
14 #include <linux/delay.h>
15 #include <linux/io.h>
16 +#include <linux/module.h>
17 #include <linux/ssb/ssb.h>
18 #include <linux/ssb/ssb_regs.h>
19 #include <linux/ssb/ssb_driver_gige.h>
20 @@ -139,19 +140,6 @@ static void ssb_device_put(struct ssb_de
21 put_device(dev->dev);
22 }
23
24 -static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
25 -{
26 - if (drv)
27 - get_driver(&drv->drv);
28 - return drv;
29 -}
30 -
31 -static inline void ssb_driver_put(struct ssb_driver *drv)
32 -{
33 - if (drv)
34 - put_driver(&drv->drv);
35 -}
36 -
37 static int ssb_device_resume(struct device *dev)
38 {
39 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
40 @@ -249,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
41 ssb_device_put(sdev);
42 continue;
43 }
44 - sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
45 - if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
46 - ssb_device_put(sdev);
47 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
48 + if (SSB_WARN_ON(!sdrv->remove))
49 continue;
50 - }
51 sdrv->remove(sdev);
52 ctx->device_frozen[i] = 1;
53 }
54 @@ -292,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
55 dev_name(sdev->dev));
56 result = err;
57 }
58 - ssb_driver_put(sdrv);
59 ssb_device_put(sdev);
60 }
61
62 @@ -383,6 +368,35 @@ static int ssb_device_uevent(struct devi
63 ssb_dev->id.revision);
64 }
65
66 +#define ssb_config_attr(attrib, field, format_string) \
67 +static ssize_t \
68 +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
69 +{ \
70 + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
71 +}
72 +
73 +ssb_config_attr(core_num, core_index, "%u\n")
74 +ssb_config_attr(coreid, id.coreid, "0x%04x\n")
75 +ssb_config_attr(vendor, id.vendor, "0x%04x\n")
76 +ssb_config_attr(revision, id.revision, "%u\n")
77 +ssb_config_attr(irq, irq, "%u\n")
78 +static ssize_t
79 +name_show(struct device *dev, struct device_attribute *attr, char *buf)
80 +{
81 + return sprintf(buf, "%s\n",
82 + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
83 +}
84 +
85 +static struct device_attribute ssb_device_attrs[] = {
86 + __ATTR_RO(name),
87 + __ATTR_RO(core_num),
88 + __ATTR_RO(coreid),
89 + __ATTR_RO(vendor),
90 + __ATTR_RO(revision),
91 + __ATTR_RO(irq),
92 + __ATTR_NULL,
93 +};
94 +
95 static struct bus_type ssb_bustype = {
96 .name = "ssb",
97 .match = ssb_bus_match,
98 @@ -392,6 +406,7 @@ static struct bus_type ssb_bustype = {
99 .suspend = ssb_device_suspend,
100 .resume = ssb_device_resume,
101 .uevent = ssb_device_uevent,
102 + .dev_attrs = ssb_device_attrs,
103 };
104
105 static void ssb_buses_lock(void)
106 @@ -527,7 +542,7 @@ error:
107 }
108
109 /* Needs ssb_buses_lock() */
110 -static int ssb_attach_queued_buses(void)
111 +static int __devinit ssb_attach_queued_buses(void)
112 {
113 struct ssb_bus *bus, *n;
114 int err = 0;
115 @@ -738,9 +753,9 @@ out:
116 return err;
117 }
118
119 -static int ssb_bus_register(struct ssb_bus *bus,
120 - ssb_invariants_func_t get_invariants,
121 - unsigned long baseaddr)
122 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
123 + ssb_invariants_func_t get_invariants,
124 + unsigned long baseaddr)
125 {
126 int err;
127
128 @@ -821,8 +836,8 @@ err_disable_xtal:
129 }
130
131 #ifdef CONFIG_SSB_PCIHOST
132 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
133 - struct pci_dev *host_pci)
134 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
135 + struct pci_dev *host_pci)
136 {
137 int err;
138
139 @@ -845,9 +860,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
140 #endif /* CONFIG_SSB_PCIHOST */
141
142 #ifdef CONFIG_SSB_PCMCIAHOST
143 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
144 - struct pcmcia_device *pcmcia_dev,
145 - unsigned long baseaddr)
146 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
147 + struct pcmcia_device *pcmcia_dev,
148 + unsigned long baseaddr)
149 {
150 int err;
151
152 @@ -867,8 +882,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
153 #endif /* CONFIG_SSB_PCMCIAHOST */
154
155 #ifdef CONFIG_SSB_SDIOHOST
156 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
157 - unsigned int quirks)
158 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
159 + struct sdio_func *func,
160 + unsigned int quirks)
161 {
162 int err;
163
164 @@ -888,9 +904,9 @@ int ssb_bus_sdiobus_register(struct ssb_
165 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
166 #endif /* CONFIG_SSB_PCMCIAHOST */
167
168 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
169 - unsigned long baseaddr,
170 - ssb_invariants_func_t get_invariants)
171 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
172 + unsigned long baseaddr,
173 + ssb_invariants_func_t get_invariants)
174 {
175 int err;
176
177 @@ -971,8 +987,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
178 switch (plltype) {
179 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
180 if (m & SSB_CHIPCO_CLK_T6_MMASK)
181 - return SSB_CHIPCO_CLK_T6_M0;
182 - return SSB_CHIPCO_CLK_T6_M1;
183 + return SSB_CHIPCO_CLK_T6_M1;
184 + return SSB_CHIPCO_CLK_T6_M0;
185 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
186 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
187 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
188 @@ -1062,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
189 u32 plltype;
190 u32 clkctl_n, clkctl_m;
191
192 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
193 + return ssb_pmu_get_controlclock(&bus->chipco);
194 +
195 if (ssb_extif_available(&bus->extif))
196 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
197 &clkctl_n, &clkctl_m);
198 @@ -1087,23 +1106,22 @@ static u32 ssb_tmslow_reject_bitmask(str
199 {
200 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
201
202 - /* The REJECT bit changed position in TMSLOW between
203 - * Backplane revisions. */
204 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
205 switch (rev) {
206 case SSB_IDLOW_SSBREV_22:
207 - return SSB_TMSLOW_REJECT_22;
208 + case SSB_IDLOW_SSBREV_24:
209 + case SSB_IDLOW_SSBREV_26:
210 + return SSB_TMSLOW_REJECT;
211 case SSB_IDLOW_SSBREV_23:
212 return SSB_TMSLOW_REJECT_23;
213 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
214 - case SSB_IDLOW_SSBREV_25: /* same here */
215 - case SSB_IDLOW_SSBREV_26: /* same here */
216 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
217 case SSB_IDLOW_SSBREV_27: /* same here */
218 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
219 + return SSB_TMSLOW_REJECT; /* this is a guess */
220 default:
221 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
222 WARN_ON(1);
223 }
224 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
225 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
226 }
227
228 int ssb_device_is_enabled(struct ssb_device *dev)
229 @@ -1162,10 +1180,10 @@ void ssb_device_enable(struct ssb_device
230 }
231 EXPORT_SYMBOL(ssb_device_enable);
232
233 -/* Wait for a bit in a register to get set or unset.
234 +/* Wait for bitmask in a register to get set or cleared.
235 * timeout is in units of ten-microseconds */
236 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
237 - int timeout, int set)
238 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
239 + int timeout, int set)
240 {
241 int i;
242 u32 val;
243 @@ -1173,7 +1191,7 @@ static int ssb_wait_bit(struct ssb_devic
244 for (i = 0; i < timeout; i++) {
245 val = ssb_read32(dev, reg);
246 if (set) {
247 - if (val & bitmask)
248 + if ((val & bitmask) == bitmask)
249 return 0;
250 } else {
251 if (!(val & bitmask))
252 @@ -1190,20 +1208,38 @@ static int ssb_wait_bit(struct ssb_devic
253
254 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
255 {
256 - u32 reject;
257 + u32 reject, val;
258
259 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
260 return;
261
262 reject = ssb_tmslow_reject_bitmask(dev);
263 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
264 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
265 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
266 - ssb_write32(dev, SSB_TMSLOW,
267 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
268 - reject | SSB_TMSLOW_RESET |
269 - core_specific_flags);
270 - ssb_flush_tmslow(dev);
271 +
272 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
273 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
274 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
275 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
276 +
277 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
278 + val = ssb_read32(dev, SSB_IMSTATE);
279 + val |= SSB_IMSTATE_REJECT;
280 + ssb_write32(dev, SSB_IMSTATE, val);
281 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
282 + 0);
283 + }
284 +
285 + ssb_write32(dev, SSB_TMSLOW,
286 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
287 + reject | SSB_TMSLOW_RESET |
288 + core_specific_flags);
289 + ssb_flush_tmslow(dev);
290 +
291 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
292 + val = ssb_read32(dev, SSB_IMSTATE);
293 + val &= ~SSB_IMSTATE_REJECT;
294 + ssb_write32(dev, SSB_IMSTATE, val);
295 + }
296 + }
297
298 ssb_write32(dev, SSB_TMSLOW,
299 reject | SSB_TMSLOW_RESET |
300 @@ -1212,13 +1248,34 @@ void ssb_device_disable(struct ssb_devic
301 }
302 EXPORT_SYMBOL(ssb_device_disable);
303
304 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
305 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
306 +{
307 + u16 chip_id = dev->bus->chip_id;
308 +
309 + if (dev->id.coreid == SSB_DEV_80211) {
310 + return (chip_id == 0x4322 || chip_id == 43221 ||
311 + chip_id == 43231 || chip_id == 43222);
312 + }
313 +
314 + return 0;
315 +}
316 +
317 u32 ssb_dma_translation(struct ssb_device *dev)
318 {
319 switch (dev->bus->bustype) {
320 case SSB_BUSTYPE_SSB:
321 return 0;
322 case SSB_BUSTYPE_PCI:
323 - return SSB_PCI_DMA;
324 + if (pci_is_pcie(dev->bus->host_pci) &&
325 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
326 + return SSB_PCIE_DMA_H32;
327 + } else {
328 + if (ssb_dma_translation_special_bit(dev))
329 + return SSB_PCIE_DMA_H32;
330 + else
331 + return SSB_PCI_DMA;
332 + }
333 default:
334 __ssb_dma_not_implemented(dev);
335 }
336 @@ -1261,20 +1318,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
337
338 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
339 {
340 - struct ssb_chipcommon *cc;
341 int err;
342 enum ssb_clkmode mode;
343
344 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
345 if (err)
346 goto error;
347 - cc = &bus->chipco;
348 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
349 - ssb_chipco_set_clockmode(cc, mode);
350
351 #ifdef CONFIG_SSB_DEBUG
352 bus->powered_up = 1;
353 #endif
354 +
355 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
356 + ssb_chipco_set_clockmode(&bus->chipco, mode);
357 +
358 return 0;
359 error:
360 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
361 @@ -1282,6 +1339,37 @@ error:
362 }
363 EXPORT_SYMBOL(ssb_bus_powerup);
364
365 +static void ssb_broadcast_value(struct ssb_device *dev,
366 + u32 address, u32 data)
367 +{
368 +#ifdef CONFIG_SSB_DRIVER_PCICORE
369 + /* This is used for both, PCI and ChipCommon core, so be careful. */
370 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
371 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
372 +#endif
373 +
374 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
375 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
376 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
377 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
378 +}
379 +
380 +void ssb_commit_settings(struct ssb_bus *bus)
381 +{
382 + struct ssb_device *dev;
383 +
384 +#ifdef CONFIG_SSB_DRIVER_PCICORE
385 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
386 +#else
387 + dev = bus->chipco.dev;
388 +#endif
389 + if (WARN_ON(!dev))
390 + return;
391 + /* This forces an update of the cached registers. */
392 + ssb_broadcast_value(dev, 0xFD8, 0);
393 +}
394 +EXPORT_SYMBOL(ssb_commit_settings);
395 +
396 u32 ssb_admatch_base(u32 adm)
397 {
398 u32 base = 0;
399 --- a/drivers/ssb/pci.c
400 +++ b/drivers/ssb/pci.c
401 @@ -1,7 +1,7 @@
402 /*
403 * Sonics Silicon Backplane PCI-Hostbus related functions.
404 *
405 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
406 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
407 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
408 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
409 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
410 @@ -331,7 +331,6 @@ static void sprom_extract_r123(struct ss
411 {
412 int i;
413 u16 v;
414 - s8 gain;
415 u16 loc[3];
416
417 if (out->revision == 3) /* rev 3 moved MAC */
418 @@ -390,20 +389,52 @@ static void sprom_extract_r123(struct ss
419 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
420
421 /* Extract the antenna gain values. */
422 - gain = r123_extract_antgain(out->revision, in,
423 - SSB_SPROM1_AGAIN_BG,
424 - SSB_SPROM1_AGAIN_BG_SHIFT);
425 - out->antenna_gain.ghz24.a0 = gain;
426 - out->antenna_gain.ghz24.a1 = gain;
427 - out->antenna_gain.ghz24.a2 = gain;
428 - out->antenna_gain.ghz24.a3 = gain;
429 - gain = r123_extract_antgain(out->revision, in,
430 - SSB_SPROM1_AGAIN_A,
431 - SSB_SPROM1_AGAIN_A_SHIFT);
432 - out->antenna_gain.ghz5.a0 = gain;
433 - out->antenna_gain.ghz5.a1 = gain;
434 - out->antenna_gain.ghz5.a2 = gain;
435 - out->antenna_gain.ghz5.a3 = gain;
436 + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
437 + SSB_SPROM1_AGAIN_BG,
438 + SSB_SPROM1_AGAIN_BG_SHIFT);
439 + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
440 + SSB_SPROM1_AGAIN_A,
441 + SSB_SPROM1_AGAIN_A_SHIFT);
442 +}
443 +
444 +/* Revs 4 5 and 8 have partially shared layout */
445 +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
446 +{
447 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
448 + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
449 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
450 + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
451 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
452 + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
453 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
454 + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
455 +
456 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
457 + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
458 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
459 + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
460 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
461 + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
462 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
463 + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
464 +
465 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
466 + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
467 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
468 + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
469 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
470 + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
471 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
472 + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
473 +
474 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
475 + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
476 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
477 + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
478 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
479 + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
480 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
481 + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
482 }
483
484 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
485 @@ -428,10 +459,14 @@ static void sprom_extract_r45(struct ssb
486 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
487 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
488 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
489 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
490 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
491 } else {
492 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
493 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
494 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
495 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
496 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
497 }
498 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
499 SSB_SPROM4_ANTAVAIL_A_SHIFT);
500 @@ -460,16 +495,16 @@ static void sprom_extract_r45(struct ssb
501 }
502
503 /* Extract the antenna gain values. */
504 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
505 + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
506 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
507 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
508 + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
509 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
510 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
511 + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
512 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
513 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
514 + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
515 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
516 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
517 - sizeof(out->antenna_gain.ghz5));
518 +
519 + sprom_extract_r458(out, in);
520
521 /* TODO - get remaining rev 4 stuff needed */
522 }
523 @@ -477,7 +512,13 @@ static void sprom_extract_r45(struct ssb
524 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
525 {
526 int i;
527 - u16 v;
528 + u16 v, o;
529 + u16 pwr_info_offset[] = {
530 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
531 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
532 + };
533 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
534 + ARRAY_SIZE(out->core_pwr_info));
535
536 /* extract the MAC address */
537 for (i = 0; i < 3; i++) {
538 @@ -550,16 +591,71 @@ static void sprom_extract_r8(struct ssb_
539 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
540
541 /* Extract the antenna gain values. */
542 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
543 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
544 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
545 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
546 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
547 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
548 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
549 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
550 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
551 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
552 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
553 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
554 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
555 - sizeof(out->antenna_gain.ghz5));
556 +
557 + /* Extract cores power info info */
558 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
559 + o = pwr_info_offset[i];
560 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
561 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
562 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
563 + SSB_SPROM8_2G_MAXP, 0);
564 +
565 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
566 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
567 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
568 +
569 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
570 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
571 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
572 + SSB_SPROM8_5G_MAXP, 0);
573 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
574 + SSB_SPROM8_5GH_MAXP, 0);
575 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
576 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
577 +
578 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
579 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
580 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
581 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
582 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
583 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
584 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
585 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
586 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
587 + }
588 +
589 + /* Extract FEM info */
590 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
591 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
592 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
593 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
594 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
595 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
596 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
597 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
598 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
599 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
600 +
601 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
602 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
603 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
604 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
605 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
606 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
607 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
608 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
609 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
610 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
611 +
612 + sprom_extract_r458(out, in);
613
614 /* TODO - get remaining rev 8 stuff needed */
615 }
616 @@ -573,37 +669,34 @@ static int sprom_extract(struct ssb_bus
617 ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
618 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
619 memset(out->et1mac, 0xFF, 6);
620 +
621 if ((bus->chip_id & 0xFF00) == 0x4400) {
622 /* Workaround: The BCM44XX chip has a stupid revision
623 * number stored in the SPROM.
624 * Always extract r1. */
625 out->revision = 1;
626 + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
627 + }
628 +
629 + switch (out->revision) {
630 + case 1:
631 + case 2:
632 + case 3:
633 sprom_extract_r123(out, in);
634 - } else if (bus->chip_id == 0x4321) {
635 - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
636 - out->revision = 4;
637 + break;
638 + case 4:
639 + case 5:
640 sprom_extract_r45(out, in);
641 - } else {
642 - switch (out->revision) {
643 - case 1:
644 - case 2:
645 - case 3:
646 - sprom_extract_r123(out, in);
647 - break;
648 - case 4:
649 - case 5:
650 - sprom_extract_r45(out, in);
651 - break;
652 - case 8:
653 - sprom_extract_r8(out, in);
654 - break;
655 - default:
656 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
657 - " revision %d detected. Will extract"
658 - " v1\n", out->revision);
659 - out->revision = 1;
660 - sprom_extract_r123(out, in);
661 - }
662 + break;
663 + case 8:
664 + sprom_extract_r8(out, in);
665 + break;
666 + default:
667 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
668 + " revision %d detected. Will extract"
669 + " v1\n", out->revision);
670 + out->revision = 1;
671 + sprom_extract_r123(out, in);
672 }
673
674 if (out->boardflags_lo == 0xFFFF)
675 @@ -617,15 +710,14 @@ static int sprom_extract(struct ssb_bus
676 static int ssb_pci_sprom_get(struct ssb_bus *bus,
677 struct ssb_sprom *sprom)
678 {
679 - const struct ssb_sprom *fallback;
680 - int err = -ENOMEM;
681 + int err;
682 u16 *buf;
683
684 if (!ssb_is_sprom_available(bus)) {
685 ssb_printk(KERN_ERR PFX "No SPROM available!\n");
686 return -ENODEV;
687 }
688 - if (bus->chipco.dev) { /* can be unavailible! */
689 + if (bus->chipco.dev) { /* can be unavailable! */
690 /*
691 * get SPROM offset: SSB_SPROM_BASE1 except for
692 * chipcommon rev >= 31 or chip ID is 0x4312 and
693 @@ -645,7 +737,7 @@ static int ssb_pci_sprom_get(struct ssb_
694
695 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
696 if (!buf)
697 - goto out;
698 + return -ENOMEM;
699 bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
700 sprom_do_read(bus, buf);
701 err = sprom_check_crc(buf, bus->sprom_size);
702 @@ -655,17 +747,24 @@ static int ssb_pci_sprom_get(struct ssb_
703 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
704 GFP_KERNEL);
705 if (!buf)
706 - goto out;
707 + return -ENOMEM;
708 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
709 sprom_do_read(bus, buf);
710 err = sprom_check_crc(buf, bus->sprom_size);
711 if (err) {
712 /* All CRC attempts failed.
713 * Maybe there is no SPROM on the device?
714 - * If we have a fallback, use that. */
715 - fallback = ssb_get_fallback_sprom();
716 - if (fallback) {
717 - memcpy(sprom, fallback, sizeof(*sprom));
718 + * Now we ask the arch code if there is some sprom
719 + * available for this device in some other storage */
720 + err = ssb_fill_sprom_with_fallback(bus, sprom);
721 + if (err) {
722 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
723 + " fallback SPROM failed (err %d)\n",
724 + err);
725 + } else {
726 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
727 + " revision %d provided by"
728 + " platform.\n", sprom->revision);
729 err = 0;
730 goto out_free;
731 }
732 @@ -677,19 +776,15 @@ static int ssb_pci_sprom_get(struct ssb_
733
734 out_free:
735 kfree(buf);
736 -out:
737 return err;
738 }
739
740 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
741 struct ssb_boardinfo *bi)
742 {
743 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
744 - &bi->vendor);
745 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
746 - &bi->type);
747 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
748 - &bi->rev);
749 + bi->vendor = bus->host_pci->subsystem_vendor;
750 + bi->type = bus->host_pci->subsystem_device;
751 + bi->rev = bus->host_pci->revision;
752 }
753
754 int ssb_pci_get_invariants(struct ssb_bus *bus,
755 --- a/drivers/ssb/pcihost_wrapper.c
756 +++ b/drivers/ssb/pcihost_wrapper.c
757 @@ -6,7 +6,7 @@
758 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
759 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
760 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
761 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
762 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
763 *
764 * Licensed under the GNU/GPL. See COPYING for details.
765 */
766 @@ -53,12 +53,13 @@ static int ssb_pcihost_resume(struct pci
767 # define ssb_pcihost_resume NULL
768 #endif /* CONFIG_PM */
769
770 -static int ssb_pcihost_probe(struct pci_dev *dev,
771 - const struct pci_device_id *id)
772 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
773 + const struct pci_device_id *id)
774 {
775 struct ssb_bus *ssb;
776 int err = -ENOMEM;
777 const char *name;
778 + u32 val;
779
780 ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
781 if (!ssb)
782 @@ -74,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
783 goto err_pci_disable;
784 pci_set_master(dev);
785
786 + /* Disable the RETRY_TIMEOUT register (0x41) to keep
787 + * PCI Tx retries from interfering with C3 CPU state */
788 + pci_read_config_dword(dev, 0x40, &val);
789 + if ((val & 0x0000ff00) != 0)
790 + pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
791 +
792 err = ssb_bus_pcibus_register(ssb, dev);
793 if (err)
794 goto err_pci_release_regions;
795 @@ -103,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
796 pci_set_drvdata(dev, NULL);
797 }
798
799 -int ssb_pcihost_register(struct pci_driver *driver)
800 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
801 {
802 driver->probe = ssb_pcihost_probe;
803 driver->remove = ssb_pcihost_remove;
804 --- a/drivers/ssb/scan.c
805 +++ b/drivers/ssb/scan.c
806 @@ -2,7 +2,7 @@
807 * Sonics Silicon Backplane
808 * Bus scanning
809 *
810 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
811 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
812 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
813 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
814 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
815 @@ -258,7 +258,10 @@ static int we_support_multiple_80211_cor
816 #ifdef CONFIG_SSB_PCIHOST
817 if (bus->bustype == SSB_BUSTYPE_PCI) {
818 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
819 - bus->host_pci->device == 0x4324)
820 + ((bus->host_pci->device == 0x4313) ||
821 + (bus->host_pci->device == 0x431A) ||
822 + (bus->host_pci->device == 0x4321) ||
823 + (bus->host_pci->device == 0x4324)))
824 return 1;
825 }
826 #endif /* CONFIG_SSB_PCIHOST */
827 @@ -307,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
828 } else {
829 if (bus->bustype == SSB_BUSTYPE_PCI) {
830 bus->chip_id = pcidev_to_chipid(bus->host_pci);
831 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
832 - &bus->chip_rev);
833 + bus->chip_rev = bus->host_pci->revision;
834 bus->chip_package = 0;
835 } else {
836 bus->chip_id = 0x4710;
837 @@ -316,6 +318,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
838 bus->chip_package = 0;
839 }
840 }
841 + ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
842 + "package 0x%02X\n", bus->chip_id, bus->chip_rev,
843 + bus->chip_package);
844 if (!bus->nr_devices)
845 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
846 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
847 @@ -405,10 +410,10 @@ int ssb_bus_scan(struct ssb_bus *bus,
848 /* Ignore PCI cores on PCI-E cards.
849 * Ignore PCI-E cores on PCI cards. */
850 if (dev->id.coreid == SSB_DEV_PCI) {
851 - if (bus->host_pci->is_pcie)
852 + if (pci_is_pcie(bus->host_pci))
853 continue;
854 } else {
855 - if (!bus->host_pci->is_pcie)
856 + if (!pci_is_pcie(bus->host_pci))
857 continue;
858 }
859 }
860 @@ -420,6 +425,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
861 bus->pcicore.dev = dev;
862 #endif /* CONFIG_SSB_DRIVER_PCICORE */
863 break;
864 + case SSB_DEV_ETHERNET:
865 + if (bus->bustype == SSB_BUSTYPE_PCI) {
866 + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
867 + (bus->host_pci->device & 0xFF00) == 0x4300) {
868 + /* This is a dangling ethernet core on a
869 + * wireless device. Ignore it. */
870 + continue;
871 + }
872 + }
873 + break;
874 default:
875 break;
876 }
877 --- a/include/linux/ssb/ssb.h
878 +++ b/include/linux/ssb/ssb.h
879 @@ -16,6 +16,12 @@ struct pcmcia_device;
880 struct ssb_bus;
881 struct ssb_driver;
882
883 +struct ssb_sprom_core_pwr_info {
884 + u8 itssi_2g, itssi_5g;
885 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
886 + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
887 +};
888 +
889 struct ssb_sprom {
890 u8 revision;
891 u8 il0mac[6]; /* MAC address for 802.11b/g */
892 @@ -25,8 +31,13 @@ struct ssb_sprom {
893 u8 et1phyaddr; /* MII address for enet1 */
894 u8 et0mdcport; /* MDIO for enet0 */
895 u8 et1mdcport; /* MDIO for enet1 */
896 - u8 board_rev; /* Board revision number from SPROM. */
897 + u16 board_rev; /* Board revision number from SPROM. */
898 + u16 board_num; /* Board number from SPROM. */
899 + u16 board_type; /* Board type from SPROM. */
900 u8 country_code; /* Country Code */
901 + char alpha2[2]; /* Country Code as two chars like EU or US */
902 + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
903 + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
904 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
905 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
906 u16 pa0b0;
907 @@ -45,18 +56,22 @@ struct ssb_sprom {
908 u8 gpio1; /* GPIO pin 1 */
909 u8 gpio2; /* GPIO pin 2 */
910 u8 gpio3; /* GPIO pin 3 */
911 - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
912 - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
913 - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
914 - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
915 + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
916 + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
917 + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
918 + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
919 u8 itssi_a; /* Idle TSSI Target for A-PHY */
920 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
921 u8 tri2g; /* 2.4GHz TX isolation */
922 u8 tri5gl; /* 5.2GHz TX isolation */
923 u8 tri5g; /* 5.3GHz TX isolation */
924 u8 tri5gh; /* 5.8GHz TX isolation */
925 - u8 rxpo2g; /* 2GHz RX power offset */
926 - u8 rxpo5g; /* 5GHz RX power offset */
927 + u8 txpid2g[4]; /* 2GHz TX power index */
928 + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
929 + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
930 + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
931 + s8 rxpo2g; /* 2GHz RX power offset */
932 + s8 rxpo5g; /* 5GHz RX power offset */
933 u8 rssisav2g; /* 2GHz RSSI params */
934 u8 rssismc2g;
935 u8 rssismf2g;
936 @@ -76,26 +91,104 @@ struct ssb_sprom {
937 u16 boardflags2_hi; /* Board flags (bits 48-63) */
938 /* TODO store board flags in a single u64 */
939
940 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
941 +
942 /* Antenna gain values for up to 4 antennas
943 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
944 * loss in the connectors is bigger than the gain. */
945 struct {
946 - struct {
947 - s8 a0, a1, a2, a3;
948 - } ghz24; /* 2.4GHz band */
949 - struct {
950 - s8 a0, a1, a2, a3;
951 - } ghz5; /* 5GHz band */
952 + s8 a0, a1, a2, a3;
953 } antenna_gain;
954
955 - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
956 + struct {
957 + struct {
958 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
959 + } ghz2;
960 + struct {
961 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
962 + } ghz5;
963 + } fem;
964 +
965 + u16 mcs2gpo[8];
966 + u16 mcs5gpo[8];
967 + u16 mcs5glpo[8];
968 + u16 mcs5ghpo[8];
969 + u8 opo;
970 +
971 + u8 rxgainerr2ga[3];
972 + u8 rxgainerr5gla[3];
973 + u8 rxgainerr5gma[3];
974 + u8 rxgainerr5gha[3];
975 + u8 rxgainerr5gua[3];
976 +
977 + u8 noiselvl2ga[3];
978 + u8 noiselvl5gla[3];
979 + u8 noiselvl5gma[3];
980 + u8 noiselvl5gha[3];
981 + u8 noiselvl5gua[3];
982 +
983 + u8 regrev;
984 + u8 txchain;
985 + u8 rxchain;
986 + u8 antswitch;
987 + u16 cddpo;
988 + u16 stbcpo;
989 + u16 bw40po;
990 + u16 bwduppo;
991 +
992 + u8 tempthresh;
993 + u8 tempoffset;
994 + u16 rawtempsense;
995 + u8 measpower;
996 + u8 tempsense_slope;
997 + u8 tempcorrx;
998 + u8 tempsense_option;
999 + u8 freqoffset_corr;
1000 + u8 iqcal_swp_dis;
1001 + u8 hw_iqcal_en;
1002 + u8 elna2g;
1003 + u8 elna5g;
1004 + u8 phycal_tempdelta;
1005 + u8 temps_period;
1006 + u8 temps_hysteresis;
1007 + u8 measpower1;
1008 + u8 measpower2;
1009 + u8 pcieingress_war;
1010 +
1011 + /* power per rate from sromrev 9 */
1012 + u16 cckbw202gpo;
1013 + u16 cckbw20ul2gpo;
1014 + u32 legofdmbw202gpo;
1015 + u32 legofdmbw20ul2gpo;
1016 + u32 legofdmbw205glpo;
1017 + u32 legofdmbw20ul5glpo;
1018 + u32 legofdmbw205gmpo;
1019 + u32 legofdmbw20ul5gmpo;
1020 + u32 legofdmbw205ghpo;
1021 + u32 legofdmbw20ul5ghpo;
1022 + u32 mcsbw202gpo;
1023 + u32 mcsbw20ul2gpo;
1024 + u32 mcsbw402gpo;
1025 + u32 mcsbw205glpo;
1026 + u32 mcsbw20ul5glpo;
1027 + u32 mcsbw405glpo;
1028 + u32 mcsbw205gmpo;
1029 + u32 mcsbw20ul5gmpo;
1030 + u32 mcsbw405gmpo;
1031 + u32 mcsbw205ghpo;
1032 + u32 mcsbw20ul5ghpo;
1033 + u32 mcsbw405ghpo;
1034 + u16 mcs32po;
1035 + u16 legofdm40duppo;
1036 + u8 sar2g;
1037 + u8 sar5g;
1038 };
1039
1040 /* Information about the PCB the circuitry is soldered on. */
1041 struct ssb_boardinfo {
1042 u16 vendor;
1043 u16 type;
1044 - u16 rev;
1045 + u8 rev;
1046 };
1047
1048
1049 @@ -225,10 +318,9 @@ struct ssb_driver {
1050 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
1051
1052 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
1053 -static inline int ssb_driver_register(struct ssb_driver *drv)
1054 -{
1055 - return __ssb_driver_register(drv, THIS_MODULE);
1056 -}
1057 +#define ssb_driver_register(drv) \
1058 + __ssb_driver_register(drv, THIS_MODULE)
1059 +
1060 extern void ssb_driver_unregister(struct ssb_driver *drv);
1061
1062
1063 @@ -304,7 +396,7 @@ struct ssb_bus {
1064
1065 /* ID information about the Chip. */
1066 u16 chip_id;
1067 - u16 chip_rev;
1068 + u8 chip_rev;
1069 u16 sprom_offset;
1070 u16 sprom_size; /* number of words in sprom */
1071 u8 chip_package;
1072 @@ -400,7 +492,9 @@ extern bool ssb_is_sprom_available(struc
1073
1074 /* Set a fallback SPROM.
1075 * See kdoc at the function definition for complete documentation. */
1076 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
1077 +extern int ssb_arch_register_fallback_sprom(
1078 + int (*sprom_callback)(struct ssb_bus *bus,
1079 + struct ssb_sprom *out));
1080
1081 /* Suspend a SSB bus.
1082 * Call this from the parent bus suspend routine. */
1083 @@ -514,6 +608,7 @@ extern int ssb_bus_may_powerdown(struct
1084 * Otherwise static always-on powercontrol will be used. */
1085 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
1086
1087 +extern void ssb_commit_settings(struct ssb_bus *bus);
1088
1089 /* Various helper functions */
1090 extern u32 ssb_admatch_base(u32 adm);
1091 --- a/include/linux/ssb/ssb_regs.h
1092 +++ b/include/linux/ssb/ssb_regs.h
1093 @@ -85,6 +85,8 @@
1094 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
1095 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
1096 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
1097 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
1098 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
1099 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
1100 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
1101 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
1102 @@ -95,9 +97,8 @@
1103 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
1104 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
1105 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
1106 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
1107 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
1108 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
1109 -#define SSB_TMSLOW_PHYCLK 0x00000010 /* MAC PHY Clock Control Enable */
1110 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
1111 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
1112 #define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */
1113 @@ -268,6 +269,8 @@
1114 /* SPROM Revision 4 */
1115 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
1116 #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
1117 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
1118 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
1119 #define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
1120 #define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
1121 #define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
1122 @@ -299,6 +302,46 @@
1123 #define SSB_SPROM4_AGAIN2_SHIFT 0
1124 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
1125 #define SSB_SPROM4_AGAIN3_SHIFT 8
1126 +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
1127 +#define SSB_SPROM4_TXPID2G0 0x00FF
1128 +#define SSB_SPROM4_TXPID2G0_SHIFT 0
1129 +#define SSB_SPROM4_TXPID2G1 0xFF00
1130 +#define SSB_SPROM4_TXPID2G1_SHIFT 8
1131 +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
1132 +#define SSB_SPROM4_TXPID2G2 0x00FF
1133 +#define SSB_SPROM4_TXPID2G2_SHIFT 0
1134 +#define SSB_SPROM4_TXPID2G3 0xFF00
1135 +#define SSB_SPROM4_TXPID2G3_SHIFT 8
1136 +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
1137 +#define SSB_SPROM4_TXPID5G0 0x00FF
1138 +#define SSB_SPROM4_TXPID5G0_SHIFT 0
1139 +#define SSB_SPROM4_TXPID5G1 0xFF00
1140 +#define SSB_SPROM4_TXPID5G1_SHIFT 8
1141 +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
1142 +#define SSB_SPROM4_TXPID5G2 0x00FF
1143 +#define SSB_SPROM4_TXPID5G2_SHIFT 0
1144 +#define SSB_SPROM4_TXPID5G3 0xFF00
1145 +#define SSB_SPROM4_TXPID5G3_SHIFT 8
1146 +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
1147 +#define SSB_SPROM4_TXPID5GL0 0x00FF
1148 +#define SSB_SPROM4_TXPID5GL0_SHIFT 0
1149 +#define SSB_SPROM4_TXPID5GL1 0xFF00
1150 +#define SSB_SPROM4_TXPID5GL1_SHIFT 8
1151 +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
1152 +#define SSB_SPROM4_TXPID5GL2 0x00FF
1153 +#define SSB_SPROM4_TXPID5GL2_SHIFT 0
1154 +#define SSB_SPROM4_TXPID5GL3 0xFF00
1155 +#define SSB_SPROM4_TXPID5GL3_SHIFT 8
1156 +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
1157 +#define SSB_SPROM4_TXPID5GH0 0x00FF
1158 +#define SSB_SPROM4_TXPID5GH0_SHIFT 0
1159 +#define SSB_SPROM4_TXPID5GH1 0xFF00
1160 +#define SSB_SPROM4_TXPID5GH1_SHIFT 8
1161 +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
1162 +#define SSB_SPROM4_TXPID5GH2 0x00FF
1163 +#define SSB_SPROM4_TXPID5GH2_SHIFT 0
1164 +#define SSB_SPROM4_TXPID5GH3 0xFF00
1165 +#define SSB_SPROM4_TXPID5GH3_SHIFT 8
1166 #define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
1167 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
1168 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1169 @@ -318,6 +361,8 @@
1170 #define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
1171 #define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
1172 #define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
1173 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
1174 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
1175 #define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
1176 #define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
1177 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
1178 @@ -387,6 +432,56 @@
1179 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
1180 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
1181 #define SSB_SPROM8_RXPO5G_SHIFT 8
1182 +#define SSB_SPROM8_FEM2G 0x00AE
1183 +#define SSB_SPROM8_FEM5G 0x00B0
1184 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
1185 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
1186 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
1187 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
1188 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
1189 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
1190 +#define SSB_SROM8_FEM_TR_ISO 0x0700
1191 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
1192 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
1193 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
1194 +#define SSB_SPROM8_THERMAL 0x00B2
1195 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
1196 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
1197 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
1198 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
1199 +
1200 +/* There are 4 blocks with power info sharing the same layout */
1201 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
1202 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
1203 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
1204 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
1205 +
1206 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
1207 +#define SSB_SPROM8_2G_MAXP 0x00FF
1208 +#define SSB_SPROM8_2G_ITSSI 0xFF00
1209 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
1210 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
1211 +#define SSB_SROM8_2G_PA_1 0x04
1212 +#define SSB_SROM8_2G_PA_2 0x06
1213 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
1214 +#define SSB_SPROM8_5G_MAXP 0x00FF
1215 +#define SSB_SPROM8_5G_ITSSI 0xFF00
1216 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
1217 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
1218 +#define SSB_SPROM8_5GH_MAXP 0x00FF
1219 +#define SSB_SPROM8_5GL_MAXP 0xFF00
1220 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
1221 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
1222 +#define SSB_SROM8_5G_PA_1 0x0E
1223 +#define SSB_SROM8_5G_PA_2 0x10
1224 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
1225 +#define SSB_SROM8_5GL_PA_1 0x14
1226 +#define SSB_SROM8_5GL_PA_2 0x16
1227 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
1228 +#define SSB_SROM8_5GH_PA_1 0x1A
1229 +#define SSB_SROM8_5GH_PA_2 0x1C
1230 +
1231 +/* TODO: Make it deprecated */
1232 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
1233 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1234 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1235 @@ -411,12 +506,53 @@
1236 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
1237 #define SSB_SPROM8_PA1HIB1 0x00DA
1238 #define SSB_SPROM8_PA1HIB2 0x00DC
1239 +
1240 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
1241 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
1242 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
1243 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1244 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
1245
1246 +/* Values for boardflags_lo read from SPROM */
1247 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
1248 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
1249 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
1250 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
1251 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
1252 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
1253 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
1254 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
1255 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
1256 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
1257 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
1258 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
1259 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
1260 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
1261 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
1262 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
1263 +
1264 +/* Values for boardflags_hi read from SPROM */
1265 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
1266 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
1267 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
1268 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
1269 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
1270 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
1271 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
1272 +
1273 +/* Values for boardflags2_lo read from SPROM */
1274 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
1275 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
1276 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
1277 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
1278 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
1279 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
1280 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
1281 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
1282 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
1283 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
1284 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
1285 +
1286 /* Values for SSB_SPROM1_BINF_CCODE */
1287 enum {
1288 SSB_SPROM1CCODE_WORLD = 0,
1289 --- a/drivers/ssb/driver_chipcommon.c
1290 +++ b/drivers/ssb/driver_chipcommon.c
1291 @@ -3,7 +3,7 @@
1292 * Broadcom ChipCommon core driver
1293 *
1294 * Copyright 2005, Broadcom Corporation
1295 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1296 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1297 *
1298 * Licensed under the GNU/GPL. See COPYING for details.
1299 */
1300 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
1301 if (!ccdev)
1302 return;
1303 bus = ccdev->bus;
1304 +
1305 + /* We support SLOW only on 6..9 */
1306 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
1307 + mode = SSB_CLKMODE_DYNAMIC;
1308 +
1309 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
1310 + return; /* PMU controls clockmode, separated function needed */
1311 + SSB_WARN_ON(ccdev->id.revision >= 20);
1312 +
1313 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1314 if (ccdev->id.revision < 6)
1315 return;
1316 - /* chipcommon cores rev10 are a whole new ball game */
1317 +
1318 + /* ChipCommon cores rev10+ need testing */
1319 if (ccdev->id.revision >= 10)
1320 return;
1321 +
1322 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
1323 return;
1324
1325 switch (mode) {
1326 - case SSB_CLKMODE_SLOW:
1327 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
1328 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1329 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1330 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1331 break;
1332 case SSB_CLKMODE_FAST:
1333 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
1334 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1335 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1336 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
1337 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1338 + if (ccdev->id.revision < 10) {
1339 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
1340 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1341 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1342 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
1343 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1344 + } else {
1345 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
1346 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
1347 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
1348 + /* udelay(150); TODO: not available in early init */
1349 + }
1350 break;
1351 case SSB_CLKMODE_DYNAMIC:
1352 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1353 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1354 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
1355 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1356 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
1357 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1358 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1359 -
1360 - /* for dynamic control, we have to release our xtal_pu "force on" */
1361 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
1362 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
1363 + if (ccdev->id.revision < 10) {
1364 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1365 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1366 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
1367 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1368 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
1369 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
1370 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1371 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1372 +
1373 + /* For dynamic control, we have to release our xtal_pu
1374 + * "force on" */
1375 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
1376 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
1377 + } else {
1378 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
1379 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
1380 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
1381 + }
1382 break;
1383 default:
1384 SSB_WARN_ON(1);
1385 @@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
1386 if (cc->dev->id.revision >= 11)
1387 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
1388 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
1389 +
1390 + if (cc->dev->id.revision >= 20) {
1391 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
1392 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
1393 + }
1394 +
1395 ssb_pmu_init(cc);
1396 chipco_powercontrol_init(cc);
1397 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
1398 --- a/drivers/ssb/driver_chipcommon_pmu.c
1399 +++ b/drivers/ssb/driver_chipcommon_pmu.c
1400 @@ -2,7 +2,7 @@
1401 * Sonics Silicon Backplane
1402 * Broadcom ChipCommon Power Management Unit driver
1403 *
1404 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
1405 + * Copyright 2009, Michael Buesch <m@bues.ch>
1406 * Copyright 2007, Broadcom Corporation
1407 *
1408 * Licensed under the GNU/GPL. See COPYING for details.
1409 @@ -12,6 +12,9 @@
1410 #include <linux/ssb/ssb_regs.h>
1411 #include <linux/ssb/ssb_driver_chipcommon.h>
1412 #include <linux/delay.h>
1413 +#ifdef CONFIG_BCM47XX
1414 +#include <asm/mach-bcm47xx/nvram.h>
1415 +#endif
1416
1417 #include "ssb_private.h"
1418
1419 @@ -91,10 +94,6 @@ static void ssb_pmu0_pllinit_r0(struct s
1420 u32 pmuctl, tmp, pllctl;
1421 unsigned int i;
1422
1423 - if ((bus->chip_id == 0x5354) && !crystalfreq) {
1424 - /* The 5354 crystal freq is 25MHz */
1425 - crystalfreq = 25000;
1426 - }
1427 if (crystalfreq)
1428 e = pmu0_plltab_find_entry(crystalfreq);
1429 if (!e)
1430 @@ -320,7 +319,11 @@ static void ssb_pmu_pll_init(struct ssb_
1431 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
1432
1433 if (bus->bustype == SSB_BUSTYPE_SSB) {
1434 - /* TODO: The user may override the crystal frequency. */
1435 +#ifdef CONFIG_BCM47XX
1436 + char buf[20];
1437 + if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
1438 + crystalfreq = simple_strtoul(buf, NULL, 0);
1439 +#endif
1440 }
1441
1442 switch (bus->chip_id) {
1443 @@ -329,7 +332,11 @@ static void ssb_pmu_pll_init(struct ssb_
1444 ssb_pmu1_pllinit_r0(cc, crystalfreq);
1445 break;
1446 case 0x4328:
1447 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
1448 + break;
1449 case 0x5354:
1450 + if (crystalfreq == 0)
1451 + crystalfreq = 25000;
1452 ssb_pmu0_pllinit_r0(cc, crystalfreq);
1453 break;
1454 case 0x4322:
1455 @@ -417,12 +424,14 @@ static void ssb_pmu_resources_init(struc
1456 u32 min_msk = 0, max_msk = 0;
1457 unsigned int i;
1458 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
1459 - unsigned int updown_tab_size;
1460 + unsigned int updown_tab_size = 0;
1461 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
1462 - unsigned int depend_tab_size;
1463 + unsigned int depend_tab_size = 0;
1464
1465 switch (bus->chip_id) {
1466 case 0x4312:
1467 + min_msk = 0xCBB;
1468 + break;
1469 case 0x4322:
1470 /* We keep the default settings:
1471 * min_msk = 0xCBB
1472 @@ -604,3 +613,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
1473
1474 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
1475 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
1476 +
1477 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
1478 +{
1479 + struct ssb_bus *bus = cc->dev->bus;
1480 +
1481 + switch (bus->chip_id) {
1482 + case 0x5354:
1483 + /* 5354 chip uses a non programmable PLL of frequency 240MHz */
1484 + return 240000000;
1485 + default:
1486 + ssb_printk(KERN_ERR PFX
1487 + "ERROR: PMU cpu clock unknown for device %04X\n",
1488 + bus->chip_id);
1489 + return 0;
1490 + }
1491 +}
1492 +
1493 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
1494 +{
1495 + struct ssb_bus *bus = cc->dev->bus;
1496 +
1497 + switch (bus->chip_id) {
1498 + case 0x5354:
1499 + return 120000000;
1500 + default:
1501 + ssb_printk(KERN_ERR PFX
1502 + "ERROR: PMU controlclock unknown for device %04X\n",
1503 + bus->chip_id);
1504 + return 0;
1505 + }
1506 +}
1507 --- a/drivers/ssb/driver_gige.c
1508 +++ b/drivers/ssb/driver_gige.c
1509 @@ -3,7 +3,7 @@
1510 * Broadcom Gigabit Ethernet core driver
1511 *
1512 * Copyright 2008, Broadcom Corporation
1513 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
1514 + * Copyright 2008, Michael Buesch <m@bues.ch>
1515 *
1516 * Licensed under the GNU/GPL. See COPYING for details.
1517 */
1518 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
1519 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
1520 }
1521
1522 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
1523 - int reg, int size, u32 *val)
1524 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
1525 + unsigned int devfn, int reg,
1526 + int size, u32 *val)
1527 {
1528 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
1529 unsigned long flags;
1530 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
1531 return PCIBIOS_SUCCESSFUL;
1532 }
1533
1534 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
1535 - int reg, int size, u32 val)
1536 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
1537 + unsigned int devfn, int reg,
1538 + int size, u32 val)
1539 {
1540 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
1541 unsigned long flags;
1542 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
1543 return PCIBIOS_SUCCESSFUL;
1544 }
1545
1546 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
1547 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
1548 + const struct ssb_device_id *id)
1549 {
1550 struct ssb_gige *dev;
1551 u32 base, tmslow, tmshigh;
1552 --- a/drivers/ssb/driver_pcicore.c
1553 +++ b/drivers/ssb/driver_pcicore.c
1554 @@ -3,7 +3,7 @@
1555 * Broadcom PCI-core driver
1556 *
1557 * Copyright 2005, Broadcom Corporation
1558 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1559 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1560 *
1561 * Licensed under the GNU/GPL. See COPYING for details.
1562 */
1563 @@ -15,6 +15,11 @@
1564
1565 #include "ssb_private.h"
1566
1567 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
1568 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
1569 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
1570 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1571 + u8 address, u16 data);
1572
1573 static inline
1574 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
1575 @@ -69,7 +74,7 @@ static u32 get_cfgspace_addr(struct ssb_
1576 u32 tmp;
1577
1578 /* We do only have one cardbus device behind the bridge. */
1579 - if (pc->cardbusmode && (dev >= 1))
1580 + if (pc->cardbusmode && (dev > 1))
1581 goto out;
1582
1583 if (bus == 0) {
1584 @@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
1585 return ssb_mips_irq(extpci_core->dev) + 2;
1586 }
1587
1588 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
1589 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
1590 {
1591 u32 val;
1592
1593 @@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
1594 register_pci_controller(&ssb_pcicore_controller);
1595 }
1596
1597 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
1598 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
1599 {
1600 struct ssb_bus *bus = pc->dev->bus;
1601 u16 chipid_top;
1602 @@ -403,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
1603 }
1604 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
1605
1606 +/**************************************************
1607 + * Workarounds.
1608 + **************************************************/
1609 +
1610 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
1611 +{
1612 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
1613 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
1614 + tmp &= ~0xF000;
1615 + tmp |= (pc->dev->core_index << 12);
1616 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
1617 + }
1618 +}
1619 +
1620 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
1621 +{
1622 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
1623 +}
1624 +
1625 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
1626 +{
1627 + const u8 serdes_pll_device = 0x1D;
1628 + const u8 serdes_rx_device = 0x1F;
1629 + u16 tmp;
1630 +
1631 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
1632 + ssb_pcicore_polarity_workaround(pc));
1633 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
1634 + if (tmp & 0x4000)
1635 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
1636 +}
1637 +
1638 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
1639 +{
1640 + struct ssb_device *pdev = pc->dev;
1641 + struct ssb_bus *bus = pdev->bus;
1642 + u32 tmp;
1643 +
1644 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1645 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
1646 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
1647 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1648 +
1649 + if (pdev->id.revision < 5) {
1650 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
1651 + tmp &= ~SSB_IMCFGLO_SERTO;
1652 + tmp |= 2;
1653 + tmp &= ~SSB_IMCFGLO_REQTO;
1654 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1655 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
1656 + ssb_commit_settings(bus);
1657 + } else if (pdev->id.revision >= 11) {
1658 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1659 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
1660 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1661 + }
1662 +}
1663 +
1664 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
1665 +{
1666 + u32 tmp;
1667 + u8 rev = pc->dev->id.revision;
1668 +
1669 + if (rev == 0 || rev == 1) {
1670 + /* TLP Workaround register. */
1671 + tmp = ssb_pcie_read(pc, 0x4);
1672 + tmp |= 0x8;
1673 + ssb_pcie_write(pc, 0x4, tmp);
1674 + }
1675 + if (rev == 1) {
1676 + /* DLLP Link Control register. */
1677 + tmp = ssb_pcie_read(pc, 0x100);
1678 + tmp |= 0x40;
1679 + ssb_pcie_write(pc, 0x100, tmp);
1680 + }
1681 +
1682 + if (rev == 0) {
1683 + const u8 serdes_rx_device = 0x1F;
1684 +
1685 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1686 + 2 /* Timer */, 0x8128);
1687 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1688 + 6 /* CDR */, 0x0100);
1689 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1690 + 7 /* CDR BW */, 0x1466);
1691 + } else if (rev == 3 || rev == 4 || rev == 5) {
1692 + /* TODO: DLLP Power Management Threshold */
1693 + ssb_pcicore_serdes_workaround(pc);
1694 + /* TODO: ASPM */
1695 + } else if (rev == 7) {
1696 + /* TODO: No PLL down */
1697 + }
1698 +
1699 + if (rev >= 6) {
1700 + /* Miscellaneous Configuration Fixup */
1701 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
1702 + if (!(tmp & 0x8000))
1703 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
1704 + tmp | 0x8000);
1705 + }
1706 +}
1707
1708 /**************************************************
1709 * Generic and Clientmode operation code.
1710 **************************************************/
1711
1712 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
1713 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
1714 {
1715 + struct ssb_device *pdev = pc->dev;
1716 + struct ssb_bus *bus = pdev->bus;
1717 +
1718 + if (bus->bustype == SSB_BUSTYPE_PCI)
1719 + ssb_pcicore_fix_sprom_core_index(pc);
1720 +
1721 /* Disable PCI interrupts. */
1722 - ssb_write32(pc->dev, SSB_INTVEC, 0);
1723 + ssb_write32(pdev, SSB_INTVEC, 0);
1724 +
1725 + /* Additional PCIe always once-executed workarounds */
1726 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
1727 + ssb_pcicore_serdes_workaround(pc);
1728 + /* TODO: ASPM */
1729 + /* TODO: Clock Request Update */
1730 + }
1731 }
1732
1733 -void ssb_pcicore_init(struct ssb_pcicore *pc)
1734 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
1735 {
1736 struct ssb_device *dev = pc->dev;
1737 - struct ssb_bus *bus;
1738
1739 if (!dev)
1740 return;
1741 - bus = dev->bus;
1742 if (!ssb_device_is_enabled(dev))
1743 ssb_device_enable(dev, 0);
1744
1745 @@ -446,11 +563,35 @@ static void ssb_pcie_write(struct ssb_pc
1746 pcicore_write32(pc, 0x134, data);
1747 }
1748
1749 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1750 - u8 address, u16 data)
1751 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
1752 +{
1753 + const u16 mdio_control = 0x128;
1754 + const u16 mdio_data = 0x12C;
1755 + u32 v;
1756 + int i;
1757 +
1758 + v = (1 << 30); /* Start of Transaction */
1759 + v |= (1 << 28); /* Write Transaction */
1760 + v |= (1 << 17); /* Turnaround */
1761 + v |= (0x1F << 18);
1762 + v |= (phy << 4);
1763 + pcicore_write32(pc, mdio_data, v);
1764 +
1765 + udelay(10);
1766 + for (i = 0; i < 200; i++) {
1767 + v = pcicore_read32(pc, mdio_control);
1768 + if (v & 0x100 /* Trans complete */)
1769 + break;
1770 + msleep(1);
1771 + }
1772 +}
1773 +
1774 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
1775 {
1776 const u16 mdio_control = 0x128;
1777 const u16 mdio_data = 0x12C;
1778 + int max_retries = 10;
1779 + u16 ret = 0;
1780 u32 v;
1781 int i;
1782
1783 @@ -458,46 +599,68 @@ static void ssb_pcie_mdio_write(struct s
1784 v |= 0x2; /* MDIO Clock Divisor */
1785 pcicore_write32(pc, mdio_control, v);
1786
1787 + if (pc->dev->id.revision >= 10) {
1788 + max_retries = 200;
1789 + ssb_pcie_mdio_set_phy(pc, device);
1790 + }
1791 +
1792 v = (1 << 30); /* Start of Transaction */
1793 - v |= (1 << 28); /* Write Transaction */
1794 + v |= (1 << 29); /* Read Transaction */
1795 v |= (1 << 17); /* Turnaround */
1796 - v |= (u32)device << 22;
1797 + if (pc->dev->id.revision < 10)
1798 + v |= (u32)device << 22;
1799 v |= (u32)address << 18;
1800 - v |= data;
1801 pcicore_write32(pc, mdio_data, v);
1802 /* Wait for the device to complete the transaction */
1803 udelay(10);
1804 - for (i = 0; i < 10; i++) {
1805 + for (i = 0; i < max_retries; i++) {
1806 v = pcicore_read32(pc, mdio_control);
1807 - if (v & 0x100 /* Trans complete */)
1808 + if (v & 0x100 /* Trans complete */) {
1809 + udelay(10);
1810 + ret = pcicore_read32(pc, mdio_data);
1811 break;
1812 + }
1813 msleep(1);
1814 }
1815 pcicore_write32(pc, mdio_control, 0);
1816 + return ret;
1817 }
1818
1819 -static void ssb_broadcast_value(struct ssb_device *dev,
1820 - u32 address, u32 data)
1821 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1822 + u8 address, u16 data)
1823 {
1824 - /* This is used for both, PCI and ChipCommon core, so be careful. */
1825 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1826 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1827 + const u16 mdio_control = 0x128;
1828 + const u16 mdio_data = 0x12C;
1829 + int max_retries = 10;
1830 + u32 v;
1831 + int i;
1832
1833 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
1834 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
1835 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
1836 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
1837 -}
1838 + v = 0x80; /* Enable Preamble Sequence */
1839 + v |= 0x2; /* MDIO Clock Divisor */
1840 + pcicore_write32(pc, mdio_control, v);
1841
1842 -static void ssb_commit_settings(struct ssb_bus *bus)
1843 -{
1844 - struct ssb_device *dev;
1845 + if (pc->dev->id.revision >= 10) {
1846 + max_retries = 200;
1847 + ssb_pcie_mdio_set_phy(pc, device);
1848 + }
1849
1850 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1851 - if (WARN_ON(!dev))
1852 - return;
1853 - /* This forces an update of the cached registers. */
1854 - ssb_broadcast_value(dev, 0xFD8, 0);
1855 + v = (1 << 30); /* Start of Transaction */
1856 + v |= (1 << 28); /* Write Transaction */
1857 + v |= (1 << 17); /* Turnaround */
1858 + if (pc->dev->id.revision < 10)
1859 + v |= (u32)device << 22;
1860 + v |= (u32)address << 18;
1861 + v |= data;
1862 + pcicore_write32(pc, mdio_data, v);
1863 + /* Wait for the device to complete the transaction */
1864 + udelay(10);
1865 + for (i = 0; i < max_retries; i++) {
1866 + v = pcicore_read32(pc, mdio_control);
1867 + if (v & 0x100 /* Trans complete */)
1868 + break;
1869 + msleep(1);
1870 + }
1871 + pcicore_write32(pc, mdio_control, 0);
1872 }
1873
1874 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
1875 @@ -550,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
1876 if (pc->setup_done)
1877 goto out;
1878 if (pdev->id.coreid == SSB_DEV_PCI) {
1879 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1880 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
1881 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
1882 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1883 -
1884 - if (pdev->id.revision < 5) {
1885 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
1886 - tmp &= ~SSB_IMCFGLO_SERTO;
1887 - tmp |= 2;
1888 - tmp &= ~SSB_IMCFGLO_REQTO;
1889 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1890 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
1891 - ssb_commit_settings(bus);
1892 - } else if (pdev->id.revision >= 11) {
1893 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1894 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
1895 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1896 - }
1897 + ssb_pcicore_pci_setup_workarounds(pc);
1898 } else {
1899 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
1900 - //TODO: Better make defines for all these magic PCIE values.
1901 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
1902 - /* TLP Workaround register. */
1903 - tmp = ssb_pcie_read(pc, 0x4);
1904 - tmp |= 0x8;
1905 - ssb_pcie_write(pc, 0x4, tmp);
1906 - }
1907 - if (pdev->id.revision == 0) {
1908 - const u8 serdes_rx_device = 0x1F;
1909 -
1910 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1911 - 2 /* Timer */, 0x8128);
1912 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1913 - 6 /* CDR */, 0x0100);
1914 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1915 - 7 /* CDR BW */, 0x1466);
1916 - } else if (pdev->id.revision == 1) {
1917 - /* DLLP Link Control register. */
1918 - tmp = ssb_pcie_read(pc, 0x100);
1919 - tmp |= 0x40;
1920 - ssb_pcie_write(pc, 0x100, tmp);
1921 - }
1922 + ssb_pcicore_pcie_setup_workarounds(pc);
1923 }
1924 pc->setup_done = 1;
1925 out:
1926 --- a/drivers/ssb/sprom.c
1927 +++ b/drivers/ssb/sprom.c
1928 @@ -2,7 +2,7 @@
1929 * Sonics Silicon Backplane
1930 * Common SPROM support routines
1931 *
1932 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
1933 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
1934 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1935 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1936 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1937 @@ -17,7 +17,7 @@
1938 #include <linux/slab.h>
1939
1940
1941 -static const struct ssb_sprom *fallback_sprom;
1942 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
1943
1944
1945 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
1946 @@ -145,36 +145,43 @@ out:
1947 }
1948
1949 /**
1950 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
1951 + * ssb_arch_register_fallback_sprom - Registers a method providing a
1952 + * fallback SPROM if no SPROM is found.
1953 *
1954 - * @sprom: The SPROM data structure to register.
1955 + * @sprom_callback: The callback function.
1956 *
1957 - * With this function the architecture implementation may register a fallback
1958 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
1959 - * where no valid SPROM can be found in the shadow registers.
1960 + * With this function the architecture implementation may register a
1961 + * callback handler which fills the SPROM data structure. The fallback is
1962 + * only used for PCI based SSB devices, where no valid SPROM can be found
1963 + * in the shadow registers.
1964 + *
1965 + * This function is useful for weird architectures that have a half-assed
1966 + * SSB device hardwired to their PCI bus.
1967 + *
1968 + * Note that it does only work with PCI attached SSB devices. PCMCIA
1969 + * devices currently don't use this fallback.
1970 + * Architectures must provide the SPROM for native SSB devices anyway, so
1971 + * the fallback also isn't used for native devices.
1972 *
1973 - * This function is useful for weird architectures that have a half-assed SSB device
1974 - * hardwired to their PCI bus.
1975 - *
1976 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
1977 - * don't use this fallback.
1978 - * Architectures must provide the SPROM for native SSB devices anyway,
1979 - * so the fallback also isn't used for native devices.
1980 - *
1981 - * This function is available for architecture code, only. So it is not exported.
1982 + * This function is available for architecture code, only. So it is not
1983 + * exported.
1984 */
1985 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
1986 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
1987 + struct ssb_sprom *out))
1988 {
1989 - if (fallback_sprom)
1990 + if (get_fallback_sprom)
1991 return -EEXIST;
1992 - fallback_sprom = sprom;
1993 + get_fallback_sprom = sprom_callback;
1994
1995 return 0;
1996 }
1997
1998 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
1999 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
2000 {
2001 - return fallback_sprom;
2002 + if (!get_fallback_sprom)
2003 + return -ENOENT;
2004 +
2005 + return get_fallback_sprom(bus, out);
2006 }
2007
2008 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
2009 @@ -185,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_b
2010 /* this routine differs from specs as we do not access SPROM directly
2011 on PCMCIA */
2012 if (bus->bustype == SSB_BUSTYPE_PCI &&
2013 - bus->chipco.dev && /* can be unavailible! */
2014 + bus->chipco.dev && /* can be unavailable! */
2015 bus->chipco.dev->id.revision >= 31)
2016 return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
2017
2018 --- a/drivers/ssb/ssb_private.h
2019 +++ b/drivers/ssb/ssb_private.h
2020 @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_
2021 const char *buf, size_t count,
2022 int (*sprom_check_crc)(const u16 *sprom, size_t size),
2023 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
2024 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
2025 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
2026 + struct ssb_sprom *out);
2027
2028
2029 /* core.c */
2030 @@ -206,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
2031 }
2032 #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
2033
2034 +/* driver_chipcommon_pmu.c */
2035 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
2036 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
2037 +
2038 #endif /* LINUX_SSB_PRIVATE_H_ */
2039 --- a/include/linux/ssb/ssb_driver_chipcommon.h
2040 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
2041 @@ -8,7 +8,7 @@
2042 * gpio interface, extbus, and support for serial and parallel flashes.
2043 *
2044 * Copyright 2005, Broadcom Corporation
2045 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
2046 + * Copyright 2006, Michael Buesch <m@bues.ch>
2047 *
2048 * Licensed under the GPL version 2. See COPYING for details.
2049 */
2050 @@ -123,6 +123,8 @@
2051 #define SSB_CHIPCO_FLASHDATA 0x0048
2052 #define SSB_CHIPCO_BCAST_ADDR 0x0050
2053 #define SSB_CHIPCO_BCAST_DATA 0x0054
2054 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
2055 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
2056 #define SSB_CHIPCO_GPIOIN 0x0060
2057 #define SSB_CHIPCO_GPIOOUT 0x0064
2058 #define SSB_CHIPCO_GPIOOUTEN 0x0068
2059 @@ -131,6 +133,9 @@
2060 #define SSB_CHIPCO_GPIOIRQ 0x0074
2061 #define SSB_CHIPCO_WATCHDOG 0x0080
2062 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
2063 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
2064 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
2065 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
2066 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
2067 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
2068 #define SSB_CHIPCO_CLOCK_N 0x0090
2069 @@ -189,8 +194,10 @@
2070 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
2071 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
2072 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
2073 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
2074 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
2075 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
2076 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
2077 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
2078 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
2079 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
2080 #define SSB_CHIPCO_UART0_DATA 0x0300
2081 #define SSB_CHIPCO_UART0_IMR 0x0304
2082 --- a/drivers/ssb/b43_pci_bridge.c
2083 +++ b/drivers/ssb/b43_pci_bridge.c
2084 @@ -5,12 +5,13 @@
2085 * because of its small size we include it in the SSB core
2086 * instead of creating a standalone module.
2087 *
2088 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
2089 + * Copyright 2007 Michael Buesch <m@bues.ch>
2090 *
2091 * Licensed under the GNU/GPL. See COPYING for details.
2092 */
2093
2094 #include <linux/pci.h>
2095 +#include <linux/module.h>
2096 #include <linux/ssb/ssb.h>
2097
2098 #include "ssb_private.h"
2099 --- a/drivers/ssb/driver_extif.c
2100 +++ b/drivers/ssb/driver_extif.c
2101 @@ -3,7 +3,7 @@
2102 * Broadcom EXTIF core driver
2103 *
2104 * Copyright 2005, Broadcom Corporation
2105 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
2106 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
2107 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
2108 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
2109 *
2110 --- a/drivers/ssb/driver_mipscore.c
2111 +++ b/drivers/ssb/driver_mipscore.c
2112 @@ -3,7 +3,7 @@
2113 * Broadcom MIPS core driver
2114 *
2115 * Copyright 2005, Broadcom Corporation
2116 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
2117 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
2118 *
2119 * Licensed under the GNU/GPL. See COPYING for details.
2120 */
2121 @@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
2122 struct ssb_bus *bus = mcore->dev->bus;
2123 u32 pll_type, n, m, rate = 0;
2124
2125 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
2126 + return ssb_pmu_get_cpu_clock(&bus->chipco);
2127 +
2128 if (bus->extif.dev) {
2129 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
2130 } else if (bus->chipco.dev) {
2131 --- a/drivers/ssb/embedded.c
2132 +++ b/drivers/ssb/embedded.c
2133 @@ -3,7 +3,7 @@
2134 * Embedded systems support code
2135 *
2136 * Copyright 2005-2008, Broadcom Corporation
2137 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
2138 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
2139 *
2140 * Licensed under the GNU/GPL. See COPYING for details.
2141 */
2142 --- a/drivers/ssb/pcmcia.c
2143 +++ b/drivers/ssb/pcmcia.c
2144 @@ -3,7 +3,7 @@
2145 * PCMCIA-Hostbus related functions
2146 *
2147 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
2148 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
2149 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
2150 *
2151 * Licensed under the GNU/GPL. See COPYING for details.
2152 */
2153 @@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
2154 case SSB_PCMCIA_CIS_ANTGAIN:
2155 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2156 "antg tpl size");
2157 - sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
2158 - sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
2159 - sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
2160 - sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
2161 - sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
2162 - sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
2163 - sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
2164 - sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
2165 + sprom->antenna_gain.a0 = tuple->TupleData[1];
2166 + sprom->antenna_gain.a1 = tuple->TupleData[1];
2167 + sprom->antenna_gain.a2 = tuple->TupleData[1];
2168 + sprom->antenna_gain.a3 = tuple->TupleData[1];
2169 break;
2170 case SSB_PCMCIA_CIS_BFLAGS:
2171 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
2172 --- a/drivers/ssb/sdio.c
2173 +++ b/drivers/ssb/sdio.c
2174 @@ -6,7 +6,7 @@
2175 *
2176 * Based on drivers/ssb/pcmcia.c
2177 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
2178 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
2179 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
2180 *
2181 * Licensed under the GNU/GPL. See COPYING for details.
2182 *
2183 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
2184 case SSB_SDIO_CIS_ANTGAIN:
2185 GOTO_ERROR_ON(tuple->size != 2,
2186 "antg tpl size");
2187 - sprom->antenna_gain.ghz24.a0 = tuple->data[1];
2188 - sprom->antenna_gain.ghz24.a1 = tuple->data[1];
2189 - sprom->antenna_gain.ghz24.a2 = tuple->data[1];
2190 - sprom->antenna_gain.ghz24.a3 = tuple->data[1];
2191 - sprom->antenna_gain.ghz5.a0 = tuple->data[1];
2192 - sprom->antenna_gain.ghz5.a1 = tuple->data[1];
2193 - sprom->antenna_gain.ghz5.a2 = tuple->data[1];
2194 - sprom->antenna_gain.ghz5.a3 = tuple->data[1];
2195 + sprom->antenna_gain.a0 = tuple->data[1];
2196 + sprom->antenna_gain.a1 = tuple->data[1];
2197 + sprom->antenna_gain.a2 = tuple->data[1];
2198 + sprom->antenna_gain.a3 = tuple->data[1];
2199 break;
2200 case SSB_SDIO_CIS_BFLAGS:
2201 GOTO_ERROR_ON((tuple->size != 3) &&
2202 --- a/include/linux/ssb/ssb_driver_gige.h
2203 +++ b/include/linux/ssb/ssb_driver_gige.h
2204 @@ -2,6 +2,7 @@
2205 #define LINUX_SSB_DRIVER_GIGE_H_
2206
2207 #include <linux/ssb/ssb.h>
2208 +#include <linux/bug.h>
2209 #include <linux/pci.h>
2210 #include <linux/spinlock.h>
2211
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