projects / openwrt / svn-archive / archive.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
kernel: update bcma to the tag master-2014-09-26 (wireless-next)
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.10 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
4 config BCMA_HOST_PCI
5 bool "Support for BCMA on PCI-host bus"
6 depends on BCMA_HOST_PCI_POSSIBLE
7 + default y
8
9 config BCMA_DRIVER_PCI_HOSTMODE
10 bool "Driver for PCI core working in hostmode"
11 @@ -34,8 +35,14 @@ config BCMA_DRIVER_PCI_HOSTMODE
12 PCI core hostmode operation (external PCI bus).
13
14 config BCMA_HOST_SOC
15 - bool
16 - depends on BCMA_DRIVER_MIPS
17 + bool "Support for BCMA in a SoC"
18 + depends on BCMA
19 + help
20 + Host interface for a Broadcom AIX bus directly mapped into
21 + the memory. This only works with the Broadcom SoCs from the
22 + BCM47XX line.
23 +
24 + If unsure, say N
25
26 config BCMA_DRIVER_MIPS
27 bool "BCMA Broadcom MIPS core driver"
28 @@ -68,6 +75,7 @@ config BCMA_DRIVER_GMAC_CMN
29 config BCMA_DRIVER_GPIO
30 bool "BCMA GPIO driver"
31 depends on BCMA && GPIOLIB
32 + select IRQ_DOMAIN if BCMA_HOST_SOC
33 help
34 Driver to provide access to the GPIO pins of the bcma bus.
35
36 --- a/drivers/bcma/Makefile
37 +++ b/drivers/bcma/Makefile
38 @@ -1,8 +1,10 @@
39 bcma-y += main.o scan.o core.o sprom.o
40 bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
41 +bcma-y += driver_chipcommon_b.o
42 bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
43 bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
44 bcma-y += driver_pci.o
45 +bcma-y += driver_pcie2.o
46 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
47 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
48 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
49 --- a/drivers/bcma/bcma_private.h
50 +++ b/drivers/bcma/bcma_private.h
51 @@ -22,6 +22,8 @@
52 struct bcma_bus;
53
54 /* main.c */
55 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
56 + int timeout);
57 int bcma_bus_register(struct bcma_bus *bus);
58 void bcma_bus_unregister(struct bcma_bus *bus);
59 int __init bcma_bus_early_register(struct bcma_bus *bus,
60 @@ -31,8 +33,6 @@ int __init bcma_bus_early_register(struc
61 int bcma_bus_suspend(struct bcma_bus *bus);
62 int bcma_bus_resume(struct bcma_bus *bus);
63 #endif
64 -struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
65 - u8 unit);
66
67 /* scan.c */
68 int bcma_bus_scan(struct bcma_bus *bus);
69 @@ -50,6 +50,10 @@ void bcma_chipco_serial_init(struct bcma
70 extern struct platform_device bcma_pflash_dev;
71 #endif /* CONFIG_BCMA_DRIVER_MIPS */
72
73 +/* driver_chipcommon_b.c */
74 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
75 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb);
76 +
77 /* driver_chipcommon_pmu.c */
78 u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
79 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
80 --- a/drivers/bcma/core.c
81 +++ b/drivers/bcma/core.c
82 @@ -9,6 +9,25 @@
83 #include <linux/export.h>
84 #include <linux/bcma/bcma.h>
85
86 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
87 + u32 value, int timeout)
88 +{
89 + unsigned long deadline = jiffies + timeout;
90 + u32 val;
91 +
92 + do {
93 + val = bcma_aread32(core, reg);
94 + if ((val & mask) == value)
95 + return true;
96 + cpu_relax();
97 + udelay(10);
98 + } while (!time_after_eq(jiffies, deadline));
99 +
100 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
101 +
102 + return false;
103 +}
104 +
105 bool bcma_core_is_enabled(struct bcma_device *core)
106 {
107 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
108 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
109 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
110 return;
111
112 - bcma_awrite32(core, BCMA_IOCTL, flags);
113 - bcma_aread32(core, BCMA_IOCTL);
114 - udelay(10);
115 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
116
117 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
118 bcma_aread32(core, BCMA_RESET_CTL);
119 udelay(1);
120 +
121 + bcma_awrite32(core, BCMA_IOCTL, flags);
122 + bcma_aread32(core, BCMA_IOCTL);
123 + udelay(10);
124 }
125 EXPORT_SYMBOL_GPL(bcma_core_disable);
126
127 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
128 bcma_aread32(core, BCMA_IOCTL);
129
130 bcma_awrite32(core, BCMA_RESET_CTL, 0);
131 + bcma_aread32(core, BCMA_RESET_CTL);
132 udelay(1);
133
134 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
135 --- a/drivers/bcma/driver_chipcommon.c
136 +++ b/drivers/bcma/driver_chipcommon.c
137 @@ -140,8 +140,15 @@ void bcma_core_chipcommon_init(struct bc
138 bcma_core_chipcommon_early_init(cc);
139
140 if (cc->core->id.rev >= 20) {
141 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
142 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
143 + u32 pullup = 0, pulldown = 0;
144 +
145 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
146 + pullup = 0x402e0;
147 + pulldown = 0x20500;
148 + }
149 +
150 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
151 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
152 }
153
154 if (cc->capabilities & BCMA_CC_CAP_PMU)
155 --- a/drivers/bcma/driver_chipcommon_pmu.c
156 +++ b/drivers/bcma/driver_chipcommon_pmu.c
157 @@ -56,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
158 }
159 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
160
161 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
162 +{
163 + u32 ilp_ctl, alp_hz;
164 +
165 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
166 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
167 + return 0;
168 +
169 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
170 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
171 + usleep_range(1000, 2000);
172 +
173 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
174 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
175 +
176 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
177 +
178 + alp_hz = ilp_ctl * 32768 / 4;
179 + return (alp_hz + 50000) / 100000 * 100;
180 +}
181 +
182 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
183 +{
184 + struct bcma_bus *bus = cc->core->bus;
185 + u32 freq_tgt_target = 0, freq_tgt_current;
186 + u32 pll0, mask;
187 +
188 + switch (bus->chipinfo.id) {
189 + case BCMA_CHIP_ID_BCM43142:
190 + /* pmu2_xtaltab0_adfll_485 */
191 + switch (xtalfreq) {
192 + case 12000:
193 + freq_tgt_target = 0x50D52;
194 + break;
195 + case 20000:
196 + freq_tgt_target = 0x307FE;
197 + break;
198 + case 26000:
199 + freq_tgt_target = 0x254EA;
200 + break;
201 + case 37400:
202 + freq_tgt_target = 0x19EF8;
203 + break;
204 + case 52000:
205 + freq_tgt_target = 0x12A75;
206 + break;
207 + }
208 + break;
209 + }
210 +
211 + if (!freq_tgt_target) {
212 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
213 + xtalfreq);
214 + return;
215 + }
216 +
217 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
218 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
219 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
220 +
221 + if (freq_tgt_current == freq_tgt_target) {
222 + bcma_debug(bus, "Target TGT frequency already set\n");
223 + return;
224 + }
225 +
226 + /* Turn off PLL */
227 + switch (bus->chipinfo.id) {
228 + case BCMA_CHIP_ID_BCM43142:
229 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
230 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
231 +
232 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
233 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
234 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
235 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
236 + break;
237 + }
238 +
239 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
240 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
241 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
242 +
243 + /* Flush */
244 + if (cc->pmu.rev >= 2)
245 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
246 +
247 + /* TODO: Do we need to update OTP? */
248 +}
249 +
250 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
251 +{
252 + struct bcma_bus *bus = cc->core->bus;
253 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
254 +
255 + switch (bus->chipinfo.id) {
256 + case BCMA_CHIP_ID_BCM43142:
257 + if (xtalfreq == 0)
258 + xtalfreq = 20000;
259 + bcma_pmu2_pll_init0(cc, xtalfreq);
260 + break;
261 + }
262 +}
263 +
264 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
265 {
266 struct bcma_bus *bus = cc->core->bus;
267 @@ -66,6 +169,25 @@ static void bcma_pmu_resources_init(stru
268 min_msk = 0x200D;
269 max_msk = 0xFFFF;
270 break;
271 + case BCMA_CHIP_ID_BCM43142:
272 + min_msk = BCMA_RES_4314_LPLDO_PU |
273 + BCMA_RES_4314_PMU_SLEEP_DIS |
274 + BCMA_RES_4314_PMU_BG_PU |
275 + BCMA_RES_4314_CBUCK_LPOM_PU |
276 + BCMA_RES_4314_CBUCK_PFM_PU |
277 + BCMA_RES_4314_CLDO_PU |
278 + BCMA_RES_4314_LPLDO2_LVM |
279 + BCMA_RES_4314_WL_PMU_PU |
280 + BCMA_RES_4314_LDO3P3_PU |
281 + BCMA_RES_4314_OTP_PU |
282 + BCMA_RES_4314_WL_PWRSW_PU |
283 + BCMA_RES_4314_LQ_AVAIL |
284 + BCMA_RES_4314_LOGIC_RET |
285 + BCMA_RES_4314_MEM_SLEEP |
286 + BCMA_RES_4314_MACPHY_RET |
287 + BCMA_RES_4314_WL_CORE_READY;
288 + max_msk = 0x3FFFFFFF;
289 + break;
290 default:
291 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
292 bus->chipinfo.id);
293 @@ -165,6 +287,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
294 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
295 BCMA_CC_PMU_CTL_NOILPONW);
296
297 + bcma_pmu_pll_init(cc);
298 bcma_pmu_resources_init(cc);
299 bcma_pmu_workarounds(cc);
300 }
301 @@ -480,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct
302 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
303 break;
304
305 + case BCMA_CHIP_ID_BCM43131:
306 + case BCMA_CHIP_ID_BCM43217:
307 case BCMA_CHIP_ID_BCM43227:
308 case BCMA_CHIP_ID_BCM43228:
309 case BCMA_CHIP_ID_BCM43428:
310 --- a/drivers/bcma/driver_chipcommon_sflash.c
311 +++ b/drivers/bcma/driver_chipcommon_sflash.c
312 @@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e {
313 u16 numblocks;
314 };
315
316 -static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
317 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
318 { "M25P20", 0x11, 0x10000, 4, },
319 { "M25P40", 0x12, 0x10000, 8, },
320
321 @@ -38,10 +38,10 @@ static struct bcma_sflash_tbl_e bcma_sfl
322 { "M25P32", 0x15, 0x10000, 64, },
323 { "M25P64", 0x16, 0x10000, 128, },
324 { "M25FL128", 0x17, 0x10000, 256, },
325 - { 0 },
326 + { NULL },
327 };
328
329 -static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
330 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
331 { "SST25WF512", 1, 0x1000, 16, },
332 { "SST25VF512", 0x48, 0x1000, 16, },
333 { "SST25WF010", 2, 0x1000, 32, },
334 @@ -56,10 +56,10 @@ static struct bcma_sflash_tbl_e bcma_sfl
335 { "SST25VF016", 0x41, 0x1000, 512, },
336 { "SST25VF032", 0x4a, 0x1000, 1024, },
337 { "SST25VF064", 0x4b, 0x1000, 2048, },
338 - { 0 },
339 + { NULL },
340 };
341
342 -static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
343 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
344 { "AT45DB011", 0xc, 256, 512, },
345 { "AT45DB021", 0x14, 256, 1024, },
346 { "AT45DB041", 0x1c, 256, 2048, },
347 @@ -67,7 +67,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
348 { "AT45DB161", 0x2c, 512, 4096, },
349 { "AT45DB321", 0x34, 512, 8192, },
350 { "AT45DB642", 0x3c, 1024, 8192, },
351 - { 0 },
352 + { NULL },
353 };
354
355 static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
356 @@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc
357 {
358 struct bcma_bus *bus = cc->core->bus;
359 struct bcma_sflash *sflash = &cc->sflash;
360 - struct bcma_sflash_tbl_e *e;
361 + const struct bcma_sflash_tbl_e *e;
362 u32 id, id2;
363
364 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
365 --- a/drivers/bcma/driver_gpio.c
366 +++ b/drivers/bcma/driver_gpio.c
367 @@ -9,6 +9,9 @@
368 */
369
370 #include <linux/gpio.h>
371 +#include <linux/irq.h>
372 +#include <linux/interrupt.h>
373 +#include <linux/irqdomain.h>
374 #include <linux/export.h>
375 #include <linux/bcma/bcma.h>
376
377 @@ -73,19 +76,136 @@ static void bcma_gpio_free(struct gpio_c
378 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
379 }
380
381 +#if IS_BUILTIN(CONFIG_BCM47XX)
382 static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
383 {
384 struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
385
386 if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
387 - return bcma_core_irq(cc->core);
388 + return irq_find_mapping(cc->irq_domain, gpio);
389 else
390 return -EINVAL;
391 }
392
393 +static void bcma_gpio_irq_unmask(struct irq_data *d)
394 +{
395 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
396 + int gpio = irqd_to_hwirq(d);
397 + u32 val = bcma_chipco_gpio_in(cc, BIT(gpio));
398 +
399 + bcma_chipco_gpio_polarity(cc, BIT(gpio), val);
400 + bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio));
401 +}
402 +
403 +static void bcma_gpio_irq_mask(struct irq_data *d)
404 +{
405 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
406 + int gpio = irqd_to_hwirq(d);
407 +
408 + bcma_chipco_gpio_intmask(cc, BIT(gpio), 0);
409 +}
410 +
411 +static struct irq_chip bcma_gpio_irq_chip = {
412 + .name = "BCMA-GPIO",
413 + .irq_mask = bcma_gpio_irq_mask,
414 + .irq_unmask = bcma_gpio_irq_unmask,
415 +};
416 +
417 +static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id)
418 +{
419 + struct bcma_drv_cc *cc = dev_id;
420 + u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN);
421 + u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ);
422 + u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL);
423 + unsigned long irqs = (val ^ pol) & mask;
424 + int gpio;
425 +
426 + if (!irqs)
427 + return IRQ_NONE;
428 +
429 + for_each_set_bit(gpio, &irqs, cc->gpio.ngpio)
430 + generic_handle_irq(bcma_gpio_to_irq(&cc->gpio, gpio));
431 + bcma_chipco_gpio_polarity(cc, irqs, val & irqs);
432 +
433 + return IRQ_HANDLED;
434 +}
435 +
436 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
437 +{
438 + struct gpio_chip *chip = &cc->gpio;
439 + int gpio, hwirq, err;
440 +
441 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
442 + return 0;
443 +
444 + cc->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
445 + &irq_domain_simple_ops, cc);
446 + if (!cc->irq_domain) {
447 + err = -ENODEV;
448 + goto err_irq_domain;
449 + }
450 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
451 + int irq = irq_create_mapping(cc->irq_domain, gpio);
452 +
453 + irq_set_chip_data(irq, cc);
454 + irq_set_chip_and_handler(irq, &bcma_gpio_irq_chip,
455 + handle_simple_irq);
456 + }
457 +
458 + hwirq = bcma_core_irq(cc->core);
459 + err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
460 + cc);
461 + if (err)
462 + goto err_req_irq;
463 +
464 + bcma_chipco_gpio_intmask(cc, ~0, 0);
465 + bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);
466 +
467 + return 0;
468 +
469 +err_req_irq:
470 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
471 + int irq = irq_find_mapping(cc->irq_domain, gpio);
472 +
473 + irq_dispose_mapping(irq);
474 + }
475 + irq_domain_remove(cc->irq_domain);
476 +err_irq_domain:
477 + return err;
478 +}
479 +
480 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
481 +{
482 + struct gpio_chip *chip = &cc->gpio;
483 + int gpio;
484 +
485 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
486 + return;
487 +
488 + bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
489 + free_irq(bcma_core_irq(cc->core), cc);
490 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
491 + int irq = irq_find_mapping(cc->irq_domain, gpio);
492 +
493 + irq_dispose_mapping(irq);
494 + }
495 + irq_domain_remove(cc->irq_domain);
496 +}
497 +#else
498 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
499 +{
500 + return 0;
501 +}
502 +
503 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
504 +{
505 +}
506 +#endif
507 +
508 int bcma_gpio_init(struct bcma_drv_cc *cc)
509 {
510 struct gpio_chip *chip = &cc->gpio;
511 + int err;
512
513 chip->label = "bcma_gpio";
514 chip->owner = THIS_MODULE;
515 @@ -95,8 +215,18 @@ int bcma_gpio_init(struct bcma_drv_cc *c
516 chip->set = bcma_gpio_set_value;
517 chip->direction_input = bcma_gpio_direction_input;
518 chip->direction_output = bcma_gpio_direction_output;
519 +#if IS_BUILTIN(CONFIG_BCM47XX)
520 chip->to_irq = bcma_gpio_to_irq;
521 - chip->ngpio = 16;
522 +#endif
523 + switch (cc->core->bus->chipinfo.id) {
524 + case BCMA_CHIP_ID_BCM5357:
525 + case BCMA_CHIP_ID_BCM53572:
526 + chip->ngpio = 32;
527 + break;
528 + default:
529 + chip->ngpio = 16;
530 + }
531 +
532 /* There is just one SoC in one device and its GPIO addresses should be
533 * deterministic to address them more easily. The other buses could get
534 * a random base number. */
535 @@ -105,10 +235,21 @@ int bcma_gpio_init(struct bcma_drv_cc *c
536 else
537 chip->base = -1;
538
539 - return gpiochip_add(chip);
540 + err = bcma_gpio_irq_domain_init(cc);
541 + if (err)
542 + return err;
543 +
544 + err = gpiochip_add(chip);
545 + if (err) {
546 + bcma_gpio_irq_domain_exit(cc);
547 + return err;
548 + }
549 +
550 + return 0;
551 }
552
553 int bcma_gpio_unregister(struct bcma_drv_cc *cc)
554 {
555 + bcma_gpio_irq_domain_exit(cc);
556 return gpiochip_remove(&cc->gpio);
557 }
558 --- a/drivers/bcma/driver_pci.c
559 +++ b/drivers/bcma/driver_pci.c
560 @@ -31,7 +31,7 @@ static void bcma_pcie_write(struct bcma_
561 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
562 }
563
564 -static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
565 +static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
566 {
567 u32 v;
568 int i;
569 @@ -55,7 +55,7 @@ static void bcma_pcie_mdio_set_phy(struc
570 }
571 }
572
573 -static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
574 +static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
575 {
576 int max_retries = 10;
577 u16 ret = 0;
578 @@ -98,7 +98,7 @@ static u16 bcma_pcie_mdio_read(struct bc
579 return ret;
580 }
581
582 -static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
583 +static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
584 u8 address, u16 data)
585 {
586 int max_retries = 10;
587 @@ -137,6 +137,13 @@ static void bcma_pcie_mdio_write(struct
588 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
589 }
590
591 +static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
592 + u8 address, u16 data)
593 +{
594 + bcma_pcie_mdio_write(pc, device, address, data);
595 + return bcma_pcie_mdio_read(pc, device, address);
596 +}
597 +
598 /**************************************************
599 * Workarounds.
600 **************************************************/
601 @@ -229,6 +236,32 @@ void bcma_core_pci_init(struct bcma_drv_
602 bcma_core_pci_clientmode_init(pc);
603 }
604
605 +void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
606 +{
607 + struct bcma_drv_pci *pc;
608 + u16 data;
609 +
610 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
611 + return;
612 +
613 + pc = &bus->drv_pci[0];
614 +
615 + if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
616 + data = up ? 0x74 : 0x7C;
617 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
618 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
619 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
620 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
621 + } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
622 + data = up ? 0x75 : 0x7D;
623 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
624 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
625 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
626 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
627 + }
628 +}
629 +EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
630 +
631 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
632 bool enable)
633 {
634 @@ -262,7 +295,7 @@ out:
635 }
636 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
637
638 -void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
639 +static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
640 {
641 u32 w;
642
643 @@ -274,4 +307,29 @@ void bcma_core_pci_extend_L1timer(struct
644 bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
645 bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
646 }
647 -EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
648 +
649 +void bcma_core_pci_up(struct bcma_bus *bus)
650 +{
651 + struct bcma_drv_pci *pc;
652 +
653 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
654 + return;
655 +
656 + pc = &bus->drv_pci[0];
657 +
658 + bcma_core_pci_extend_L1timer(pc, true);
659 +}
660 +EXPORT_SYMBOL_GPL(bcma_core_pci_up);
661 +
662 +void bcma_core_pci_down(struct bcma_bus *bus)
663 +{
664 + struct bcma_drv_pci *pc;
665 +
666 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
667 + return;
668 +
669 + pc = &bus->drv_pci[0];
670 +
671 + bcma_core_pci_extend_L1timer(pc, false);
672 +}
673 +EXPORT_SYMBOL_GPL(bcma_core_pci_down);
674 --- a/drivers/bcma/driver_pci_host.c
675 +++ b/drivers/bcma/driver_pci_host.c
676 @@ -581,6 +581,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI
677 int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
678 {
679 struct bcma_drv_pci_host *pc_host;
680 + int readrq;
681
682 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
683 /* This is not a device on the PCI-core bridge. */
684 @@ -595,6 +596,11 @@ int bcma_core_pci_plat_dev_init(struct p
685 dev->irq = bcma_core_irq(pc_host->pdev->core);
686 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
687
688 + readrq = pcie_get_readrq(dev);
689 + if (readrq > 128) {
690 + pr_info("change PCIe max read request size from %i to 128\n", readrq);
691 + pcie_set_readrq(dev, 128);
692 + }
693 return 0;
694 }
695 EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
696 --- /dev/null
697 +++ b/drivers/bcma/driver_pcie2.c
698 @@ -0,0 +1,175 @@
699 +/*
700 + * Broadcom specific AMBA
701 + * PCIe Gen 2 Core
702 + *
703 + * Copyright 2014, Broadcom Corporation
704 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
705 + *
706 + * Licensed under the GNU/GPL. See COPYING for details.
707 + */
708 +
709 +#include "bcma_private.h"
710 +#include <linux/bcma/bcma.h>
711 +
712 +/**************************************************
713 + * R/W ops.
714 + **************************************************/
715 +
716 +#if 0
717 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
718 +{
719 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
720 + pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
721 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
722 +}
723 +#endif
724 +
725 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
726 + u32 val)
727 +{
728 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
729 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
730 +}
731 +
732 +/**************************************************
733 + * Init.
734 + **************************************************/
735 +
736 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
737 + bool enable)
738 +{
739 + u32 val;
740 +
741 + /* restore back to default */
742 + val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
743 + val |= PCIE2_CLKC_DLYPERST;
744 + val &= ~PCIE2_CLKC_DISSPROMLD;
745 + if (enable) {
746 + val &= ~PCIE2_CLKC_DLYPERST;
747 + val |= PCIE2_CLKC_DISSPROMLD;
748 + }
749 + pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
750 + /* flush */
751 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
752 +}
753 +
754 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
755 +{
756 + /* LTR0 */
757 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
758 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
759 + /* LTR1 */
760 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
761 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
762 + /* LTR2 */
763 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
764 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
765 +}
766 +
767 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
768 +{
769 + u8 core_rev = pcie2->core->id.rev;
770 + u32 devstsctr2;
771 +
772 + if (core_rev < 2 || core_rev == 10 || core_rev > 13)
773 + return;
774 +
775 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
776 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
777 + devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
778 + if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
779 + /* force the right LTR values */
780 + bcma_core_pcie2_set_ltr_vals(pcie2);
781 +
782 + /* TODO:
783 + si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
784 +
785 + /* enable the LTR */
786 + devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
787 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
788 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
789 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
790 +
791 + /* set the LTR state to be active */
792 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
793 + PCIE2_LTR_ACTIVE);
794 + usleep_range(1000, 2000);
795 +
796 + /* set the LTR state to be sleep */
797 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
798 + PCIE2_LTR_SLEEP);
799 + usleep_range(1000, 2000);
800 + }
801 +}
802 +
803 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
804 +{
805 + u8 core_rev = pcie2->core->id.rev;
806 + bool pciewar160, pciewar162;
807 +
808 + pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
809 + pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
810 + core_rev == 9 || core_rev == 11;
811 +
812 + if (!pciewar160 && !pciewar162)
813 + return;
814 +
815 +/* TODO */
816 +#if 0
817 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
818 + PCIE_DISABLE_L1CLK_GATING);
819 +#if 0
820 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
821 + PCIEGEN2_COE_PVT_TL_CTRL_0);
822 + pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
823 + ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
824 +#endif
825 +#endif
826 +}
827 +
828 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
829 +{
830 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
831 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
832 +}
833 +
834 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
835 +{
836 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
837 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
838 +}
839 +
840 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
841 +{
842 + struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
843 + u8 core_rev = pcie2->core->id.rev;
844 + u32 alp_khz, pm_value;
845 +
846 + if (core_rev <= 13) {
847 + alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
848 + pm_value = (1000000 * 2) / alp_khz;
849 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
850 + PCIE2_PVT_REG_PM_CLK_PERIOD);
851 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
852 + }
853 +}
854 +
855 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
856 +{
857 + struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
858 + u32 tmp;
859 +
860 + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
861 + if ((tmp & 0xe) >> 1 == 2)
862 + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
863 +
864 + /* TODO: Do we need pcie_reqsize? */
865 +
866 + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
867 + bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
868 + bcma_core_pcie2_hw_ltr_war(pcie2);
869 + pciedev_crwlpciegen2(pcie2);
870 + pciedev_reg_pm_clk_period(pcie2);
871 + pciedev_crwlpciegen2_180(pcie2);
872 + pciedev_crwlpciegen2_182(pcie2);
873 +}
874 --- a/drivers/bcma/host_pci.c
875 +++ b/drivers/bcma/host_pci.c
876 @@ -188,8 +188,11 @@ static int bcma_host_pci_probe(struct pc
877 pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
878
879 /* SSB needed additional powering up, do we have any AMBA PCI cards? */
880 - if (!pci_is_pcie(dev))
881 - bcma_err(bus, "PCI card detected, report problems.\n");
882 + if (!pci_is_pcie(dev)) {
883 + bcma_err(bus, "PCI card detected, they are not supported.\n");
884 + err = -ENXIO;
885 + goto err_pci_release_regions;
886 + }
887
888 /* Map MMIO */
889 err = -ENOMEM;
890 @@ -205,6 +208,9 @@ static int bcma_host_pci_probe(struct pc
891 bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
892 bus->boardinfo.type = bus->host_pci->subsystem_device;
893
894 + /* Initialize struct, detect chip */
895 + bcma_init_bus(bus);
896 +
897 /* Register */
898 err = bcma_bus_register(bus);
899 if (err)
900 @@ -235,7 +241,6 @@ static void bcma_host_pci_remove(struct
901 pci_release_regions(dev);
902 pci_disable_device(dev);
903 kfree(bus);
904 - pci_set_drvdata(dev, NULL);
905 }
906
907 #ifdef CONFIG_PM_SLEEP
908 @@ -267,15 +272,20 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
909
910 #endif /* CONFIG_PM_SLEEP */
911
912 -static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
913 +static const struct pci_device_id bcma_pci_bridge_tbl[] = {
914 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
915 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
916 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
917 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
918 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
919 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
920 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
921 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
922 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
923 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
924 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
925 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
926 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xA8DB */
927 { 0, },
928 };
929 MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
930 --- a/drivers/bcma/main.c
931 +++ b/drivers/bcma/main.c
932 @@ -69,28 +69,36 @@ static u16 bcma_cc_core_id(struct bcma_b
933 return BCMA_CORE_CHIPCOMMON;
934 }
935
936 -struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
937 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
938 + u8 unit)
939 {
940 struct bcma_device *core;
941
942 list_for_each_entry(core, &bus->cores, list) {
943 - if (core->id.id == coreid)
944 + if (core->id.id == coreid && core->core_unit == unit)
945 return core;
946 }
947 return NULL;
948 }
949 -EXPORT_SYMBOL_GPL(bcma_find_core);
950 +EXPORT_SYMBOL_GPL(bcma_find_core_unit);
951
952 -struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
953 - u8 unit)
954 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
955 + int timeout)
956 {
957 - struct bcma_device *core;
958 + unsigned long deadline = jiffies + timeout;
959 + u32 val;
960
961 - list_for_each_entry(core, &bus->cores, list) {
962 - if (core->id.id == coreid && core->core_unit == unit)
963 - return core;
964 - }
965 - return NULL;
966 + do {
967 + val = bcma_read32(core, reg);
968 + if ((val & mask) == value)
969 + return true;
970 + cpu_relax();
971 + udelay(10);
972 + } while (!time_after_eq(jiffies, deadline));
973 +
974 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
975 +
976 + return false;
977 }
978
979 static void bcma_release_core_dev(struct device *dev)
980 @@ -103,55 +111,78 @@ static void bcma_release_core_dev(struct
981 kfree(core);
982 }
983
984 -static int bcma_register_cores(struct bcma_bus *bus)
985 +static bool bcma_is_core_needed_early(u16 core_id)
986 +{
987 + switch (core_id) {
988 + case BCMA_CORE_NS_NAND:
989 + case BCMA_CORE_NS_QSPI:
990 + return true;
991 + }
992 +
993 + return false;
994 +}
995 +
996 +static void bcma_register_core(struct bcma_bus *bus, struct bcma_device *core)
997 +{
998 + int err;
999 +
1000 + core->dev.release = bcma_release_core_dev;
1001 + core->dev.bus = &bcma_bus_type;
1002 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index);
1003 +
1004 + switch (bus->hosttype) {
1005 + case BCMA_HOSTTYPE_PCI:
1006 + core->dev.parent = &bus->host_pci->dev;
1007 + core->dma_dev = &bus->host_pci->dev;
1008 + core->irq = bus->host_pci->irq;
1009 + break;
1010 + case BCMA_HOSTTYPE_SOC:
1011 + core->dev.dma_mask = &core->dev.coherent_dma_mask;
1012 + core->dma_dev = &core->dev;
1013 + break;
1014 + case BCMA_HOSTTYPE_SDIO:
1015 + break;
1016 + }
1017 +
1018 + err = device_register(&core->dev);
1019 + if (err) {
1020 + bcma_err(bus, "Could not register dev for core 0x%03X\n",
1021 + core->id.id);
1022 + put_device(&core->dev);
1023 + return;
1024 + }
1025 + core->dev_registered = true;
1026 +}
1027 +
1028 +static int bcma_register_devices(struct bcma_bus *bus)
1029 {
1030 struct bcma_device *core;
1031 - int err, dev_id = 0;
1032 + int err;
1033
1034 list_for_each_entry(core, &bus->cores, list) {
1035 /* We support that cores ourself */
1036 switch (core->id.id) {
1037 case BCMA_CORE_4706_CHIPCOMMON:
1038 case BCMA_CORE_CHIPCOMMON:
1039 + case BCMA_CORE_NS_CHIPCOMMON_B:
1040 case BCMA_CORE_PCI:
1041 case BCMA_CORE_PCIE:
1042 + case BCMA_CORE_PCIE2:
1043 case BCMA_CORE_MIPS_74K:
1044 case BCMA_CORE_4706_MAC_GBIT_COMMON:
1045 continue;
1046 }
1047
1048 + /* Early cores were already registered */
1049 + if (bcma_is_core_needed_early(core->id.id))
1050 + continue;
1051 +
1052 /* Only first GMAC core on BCM4706 is connected and working */
1053 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1054 core->core_unit > 0)
1055 continue;
1056
1057 - core->dev.release = bcma_release_core_dev;
1058 - core->dev.bus = &bcma_bus_type;
1059 - dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
1060 -
1061 - switch (bus->hosttype) {
1062 - case BCMA_HOSTTYPE_PCI:
1063 - core->dev.parent = &bus->host_pci->dev;
1064 - core->dma_dev = &bus->host_pci->dev;
1065 - core->irq = bus->host_pci->irq;
1066 - break;
1067 - case BCMA_HOSTTYPE_SOC:
1068 - core->dev.dma_mask = &core->dev.coherent_dma_mask;
1069 - core->dma_dev = &core->dev;
1070 - break;
1071 - case BCMA_HOSTTYPE_SDIO:
1072 - break;
1073 - }
1074 -
1075 - err = device_register(&core->dev);
1076 - if (err) {
1077 - bcma_err(bus,
1078 - "Could not register dev for core 0x%03X\n",
1079 - core->id.id);
1080 - continue;
1081 - }
1082 - core->dev_registered = true;
1083 - dev_id++;
1084 + bcma_register_core(bus, core);
1085 }
1086
1087 #ifdef CONFIG_BCMA_DRIVER_MIPS
1088 @@ -218,7 +249,7 @@ int bcma_bus_register(struct bcma_bus *b
1089 err = bcma_bus_scan(bus);
1090 if (err) {
1091 bcma_err(bus, "Failed to scan: %d\n", err);
1092 - return -1;
1093 + return err;
1094 }
1095
1096 /* Early init CC core */
1097 @@ -228,6 +259,12 @@ int bcma_bus_register(struct bcma_bus *b
1098 bcma_core_chipcommon_early_init(&bus->drv_cc);
1099 }
1100
1101 + /* Cores providing flash access go before SPROM init */
1102 + list_for_each_entry(core, &bus->cores, list) {
1103 + if (bcma_is_core_needed_early(core->id.id))
1104 + bcma_register_core(bus, core);
1105 + }
1106 +
1107 /* Try to get SPROM */
1108 err = bcma_sprom_get(bus);
1109 if (err == -ENOENT) {
1110 @@ -242,6 +279,13 @@ int bcma_bus_register(struct bcma_bus *b
1111 bcma_core_chipcommon_init(&bus->drv_cc);
1112 }
1113
1114 + /* Init CC core */
1115 + core = bcma_find_core(bus, BCMA_CORE_NS_CHIPCOMMON_B);
1116 + if (core) {
1117 + bus->drv_cc_b.core = core;
1118 + bcma_core_chipcommon_b_init(&bus->drv_cc_b);
1119 + }
1120 +
1121 /* Init MIPS core */
1122 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1123 if (core) {
1124 @@ -263,6 +307,13 @@ int bcma_bus_register(struct bcma_bus *b
1125 bcma_core_pci_init(&bus->drv_pci[1]);
1126 }
1127
1128 + /* Init PCIe Gen 2 core */
1129 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
1130 + if (core) {
1131 + bus->drv_pcie2.core = core;
1132 + bcma_core_pcie2_init(&bus->drv_pcie2);
1133 + }
1134 +
1135 /* Init GBIT MAC COMMON core */
1136 core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
1137 if (core) {
1138 @@ -271,7 +322,7 @@ int bcma_bus_register(struct bcma_bus *b
1139 }
1140
1141 /* Register found cores */
1142 - bcma_register_cores(bus);
1143 + bcma_register_devices(bus);
1144
1145 bcma_info(bus, "Bus registered\n");
1146
1147 @@ -289,6 +340,8 @@ void bcma_bus_unregister(struct bcma_bus
1148 else if (err)
1149 bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
1150
1151 + bcma_core_chipcommon_b_free(&bus->drv_cc_b);
1152 +
1153 cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1154 cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
1155 cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
1156 @@ -308,8 +361,6 @@ int __init bcma_bus_early_register(struc
1157 struct bcma_device *core;
1158 struct bcma_device_id match;
1159
1160 - bcma_init_bus(bus);
1161 -
1162 match.manuf = BCMA_MANUF_BCM;
1163 match.id = bcma_cc_core_id(bus);
1164 match.class = BCMA_CL_SIM;
1165 --- a/drivers/bcma/scan.c
1166 +++ b/drivers/bcma/scan.c
1167 @@ -32,6 +32,18 @@ static const struct bcma_device_id_name
1168 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
1169 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
1170 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
1171 + { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" },
1172 + { BCMA_CORE_NS_DMA, "DMA" },
1173 + { BCMA_CORE_NS_SDIO3, "SDIO3" },
1174 + { BCMA_CORE_NS_USB20, "USB 2.0" },
1175 + { BCMA_CORE_NS_USB30, "USB 3.0" },
1176 + { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" },
1177 + { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" },
1178 + { BCMA_CORE_NS_ROM, "ROM" },
1179 + { BCMA_CORE_NS_NAND, "NAND flash controller" },
1180 + { BCMA_CORE_NS_QSPI, "SPI flash controller" },
1181 + { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" },
1182 + { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
1183 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
1184 { BCMA_CORE_ALTA, "ALTA (I2S)" },
1185 { BCMA_CORE_INVALID, "Invalid" },
1186 @@ -201,7 +213,7 @@ static s32 bcma_erom_get_mst_port(struct
1187 return ent;
1188 }
1189
1190 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
1191 +static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
1192 u32 type, u8 port)
1193 {
1194 u32 addrl, addrh, sizel, sizeh = 0;
1195 @@ -213,7 +225,7 @@ static s32 bcma_erom_get_addr_desc(struc
1196 ((ent & SCAN_ADDR_TYPE) != type) ||
1197 (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
1198 bcma_erom_push_ent(eromptr);
1199 - return -EINVAL;
1200 + return (u32)-EINVAL;
1201 }
1202
1203 addrl = ent & SCAN_ADDR_ADDR;
1204 @@ -257,12 +269,14 @@ static struct bcma_device *bcma_find_cor
1205 return NULL;
1206 }
1207
1208 +#define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO)
1209 +
1210 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
1211 struct bcma_device_id *match, int core_num,
1212 struct bcma_device *core)
1213 {
1214 - s32 tmp;
1215 - u8 i, j;
1216 + u32 tmp;
1217 + u8 i, j, k;
1218 s32 cia, cib;
1219 u8 ports[2], wrappers[2];
1220
1221 @@ -300,6 +314,7 @@ static int bcma_get_next_core(struct bcm
1222 /* Some specific cores don't need wrappers */
1223 switch (core->id.id) {
1224 case BCMA_CORE_4706_MAC_GBIT_COMMON:
1225 + case BCMA_CORE_NS_CHIPCOMMON_B:
1226 /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
1227 break;
1228 default:
1229 @@ -339,11 +354,11 @@ static int bcma_get_next_core(struct bcm
1230 * the main register space for the core
1231 */
1232 tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
1233 - if (tmp <= 0) {
1234 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
1235 /* Try again to see if it is a bridge */
1236 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1237 SCAN_ADDR_TYPE_BRIDGE, 0);
1238 - if (tmp <= 0) {
1239 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
1240 return -EILSEQ;
1241 } else {
1242 bcma_info(bus, "Bridge found\n");
1243 @@ -353,18 +368,19 @@ static int bcma_get_next_core(struct bcm
1244 core->addr = tmp;
1245
1246 /* get & parse slave ports */
1247 + k = 0;
1248 for (i = 0; i < ports[1]; i++) {
1249 for (j = 0; ; j++) {
1250 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1251 SCAN_ADDR_TYPE_SLAVE, i);
1252 - if (tmp < 0) {
1253 + if (IS_ERR_VALUE_U32(tmp)) {
1254 /* no more entries for port _i_ */
1255 /* pr_debug("erom: slave port %d "
1256 * "has %d descriptors\n", i, j); */
1257 break;
1258 - } else {
1259 - if (i == 0 && j == 0)
1260 - core->addr1 = tmp;
1261 + } else if (k < ARRAY_SIZE(core->addr_s)) {
1262 + core->addr_s[k] = tmp;
1263 + k++;
1264 }
1265 }
1266 }
1267 @@ -374,7 +390,7 @@ static int bcma_get_next_core(struct bcm
1268 for (j = 0; ; j++) {
1269 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1270 SCAN_ADDR_TYPE_MWRAP, i);
1271 - if (tmp < 0) {
1272 + if (IS_ERR_VALUE_U32(tmp)) {
1273 /* no more entries for port _i_ */
1274 /* pr_debug("erom: master wrapper %d "
1275 * "has %d descriptors\n", i, j); */
1276 @@ -392,7 +408,7 @@ static int bcma_get_next_core(struct bcm
1277 for (j = 0; ; j++) {
1278 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1279 SCAN_ADDR_TYPE_SWRAP, i + hack);
1280 - if (tmp < 0) {
1281 + if (IS_ERR_VALUE_U32(tmp)) {
1282 /* no more entries for port _i_ */
1283 /* pr_debug("erom: master wrapper %d "
1284 * has %d descriptors\n", i, j); */
1285 @@ -407,10 +423,13 @@ static int bcma_get_next_core(struct bcm
1286 core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
1287 if (!core->io_addr)
1288 return -ENOMEM;
1289 - core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
1290 - if (!core->io_wrap) {
1291 - iounmap(core->io_addr);
1292 - return -ENOMEM;
1293 + if (core->wrap) {
1294 + core->io_wrap = ioremap_nocache(core->wrap,
1295 + BCMA_CORE_SIZE);
1296 + if (!core->io_wrap) {
1297 + iounmap(core->io_addr);
1298 + return -ENOMEM;
1299 + }
1300 }
1301 }
1302 return 0;
1303 @@ -420,9 +439,7 @@ void bcma_init_bus(struct bcma_bus *bus)
1304 {
1305 s32 tmp;
1306 struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
1307 -
1308 - if (bus->init_done)
1309 - return;
1310 + char chip_id[8];
1311
1312 INIT_LIST_HEAD(&bus->cores);
1313 bus->nr_cores = 0;
1314 @@ -433,10 +450,11 @@ void bcma_init_bus(struct bcma_bus *bus)
1315 chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
1316 chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
1317 chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
1318 - bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
1319 - chipinfo->id, chipinfo->rev, chipinfo->pkg);
1320
1321 - bus->init_done = true;
1322 + snprintf(chip_id, ARRAY_SIZE(chip_id),
1323 + (chipinfo->id > 0x9999) ? "%d" : "0x%04X", chipinfo->id);
1324 + bcma_info(bus, "Found chip with id %s, rev 0x%02X and package 0x%02X\n",
1325 + chip_id, chipinfo->rev, chipinfo->pkg);
1326 }
1327
1328 int bcma_bus_scan(struct bcma_bus *bus)
1329 @@ -446,8 +464,6 @@ int bcma_bus_scan(struct bcma_bus *bus)
1330
1331 int err, core_num = 0;
1332
1333 - bcma_init_bus(bus);
1334 -
1335 erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
1336 if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
1337 eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
1338 --- a/drivers/bcma/sprom.c
1339 +++ b/drivers/bcma/sprom.c
1340 @@ -72,12 +72,12 @@ fail:
1341 * R/W ops.
1342 **************************************************/
1343
1344 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
1345 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
1346 + size_t words)
1347 {
1348 int i;
1349 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
1350 - sprom[i] = bcma_read16(bus->drv_cc.core,
1351 - offset + (i * 2));
1352 + for (i = 0; i < words; i++)
1353 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
1354 }
1355
1356 /**************************************************
1357 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
1358 return t[crc ^ data];
1359 }
1360
1361 -static u8 bcma_sprom_crc(const u16 *sprom)
1362 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
1363 {
1364 int word;
1365 u8 crc = 0xFF;
1366
1367 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
1368 + for (word = 0; word < words - 1; word++) {
1369 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
1370 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
1371 }
1372 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
1373 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
1374 crc ^= 0xFF;
1375
1376 return crc;
1377 }
1378
1379 -static int bcma_sprom_check_crc(const u16 *sprom)
1380 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
1381 {
1382 u8 crc;
1383 u8 expected_crc;
1384 u16 tmp;
1385
1386 - crc = bcma_sprom_crc(sprom);
1387 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
1388 + crc = bcma_sprom_crc(sprom, words);
1389 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
1390 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
1391 if (crc != expected_crc)
1392 return -EPROTO;
1393 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
1394 return 0;
1395 }
1396
1397 -static int bcma_sprom_valid(const u16 *sprom)
1398 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
1399 + size_t words)
1400 {
1401 u16 revision;
1402 int err;
1403
1404 - err = bcma_sprom_check_crc(sprom);
1405 + err = bcma_sprom_check_crc(sprom, words);
1406 if (err)
1407 return err;
1408
1409 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
1410 - if (revision != 8 && revision != 9) {
1411 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
1412 + if (revision != 8 && revision != 9 && revision != 10) {
1413 pr_err("Unsupported SPROM revision: %d\n", revision);
1414 return -ENOENT;
1415 }
1416
1417 + bus->sprom.revision = revision;
1418 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
1419 +
1420 return 0;
1421 }
1422
1423 @@ -197,6 +201,23 @@ static int bcma_sprom_valid(const u16 *s
1424 SPEX(_field[7], _offset + 14, _mask, _shift); \
1425 } while (0)
1426
1427 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
1428 +{
1429 + u16 v;
1430 + u8 gain;
1431 +
1432 + v = in[SPOFF(offset)];
1433 + gain = (v & mask) >> shift;
1434 + if (gain == 0xFF) {
1435 + gain = 8; /* If unset use 2dBm */
1436 + } else {
1437 + /* Q5.2 Fractional part is stored in 0xC0 */
1438 + gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
1439 + }
1440 +
1441 + return (s8)gain;
1442 +}
1443 +
1444 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
1445 {
1446 u16 v, o;
1447 @@ -208,9 +229,6 @@ static void bcma_sprom_extract_r8(struct
1448 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1449 ARRAY_SIZE(bus->sprom.core_pwr_info));
1450
1451 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
1452 - SSB_SPROM_REVISION_REV;
1453 -
1454 for (i = 0; i < 3; i++) {
1455 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
1456 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
1457 @@ -380,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
1458 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
1459
1460 /* Extract the antenna gain values. */
1461 - SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
1462 - SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
1463 - SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
1464 - SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
1465 - SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
1466 - SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
1467 - SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
1468 - SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
1469 + bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
1470 + SSB_SPROM8_AGAIN01,
1471 + SSB_SPROM8_AGAIN0,
1472 + SSB_SPROM8_AGAIN0_SHIFT);
1473 + bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
1474 + SSB_SPROM8_AGAIN01,
1475 + SSB_SPROM8_AGAIN1,
1476 + SSB_SPROM8_AGAIN1_SHIFT);
1477 + bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
1478 + SSB_SPROM8_AGAIN23,
1479 + SSB_SPROM8_AGAIN2,
1480 + SSB_SPROM8_AGAIN2_SHIFT);
1481 + bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
1482 + SSB_SPROM8_AGAIN23,
1483 + SSB_SPROM8_AGAIN3,
1484 + SSB_SPROM8_AGAIN3_SHIFT);
1485
1486 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
1487 SSB_SPROM8_LEDDC_ON_SHIFT);
1488 @@ -502,12 +528,14 @@ static bool bcma_sprom_onchip_available(
1489 case BCMA_CHIP_ID_BCM4331:
1490 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
1491 break;
1492 -
1493 + case BCMA_CHIP_ID_BCM43142:
1494 case BCMA_CHIP_ID_BCM43224:
1495 case BCMA_CHIP_ID_BCM43225:
1496 /* for these chips OTP is always available */
1497 present = true;
1498 break;
1499 + case BCMA_CHIP_ID_BCM43131:
1500 + case BCMA_CHIP_ID_BCM43217:
1501 case BCMA_CHIP_ID_BCM43227:
1502 case BCMA_CHIP_ID_BCM43228:
1503 case BCMA_CHIP_ID_BCM43428:
1504 @@ -550,7 +578,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
1505 {
1506 u16 offset = BCMA_CC_SPROM;
1507 u16 *sprom;
1508 - int err = 0;
1509 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
1510 + SSB_SPROMSIZE_WORDS_R10, };
1511 + int i, err = 0;
1512
1513 if (!bus->drv_cc.core)
1514 return -EOPNOTSUPP;
1515 @@ -579,32 +609,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
1516 }
1517 }
1518
1519 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
1520 - GFP_KERNEL);
1521 - if (!sprom)
1522 - return -ENOMEM;
1523 -
1524 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
1525 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
1526 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
1527
1528 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
1529 - bcma_sprom_read(bus, offset, sprom);
1530 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
1531 + size_t words = sprom_sizes[i];
1532 +
1533 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
1534 + if (!sprom)
1535 + return -ENOMEM;
1536 +
1537 + bcma_sprom_read(bus, offset, sprom, words);
1538 + err = bcma_sprom_valid(bus, sprom, words);
1539 + if (!err)
1540 + break;
1541 +
1542 + kfree(sprom);
1543 + }
1544
1545 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
1546 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
1547 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
1548
1549 - err = bcma_sprom_valid(sprom);
1550 if (err) {
1551 - bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
1552 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
1553 err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
1554 - goto out;
1555 + } else {
1556 + bcma_sprom_extract_r8(bus, sprom);
1557 + kfree(sprom);
1558 }
1559
1560 - bcma_sprom_extract_r8(bus, sprom);
1561 -
1562 -out:
1563 - kfree(sprom);
1564 return err;
1565 }
1566 --- a/include/linux/bcma/bcma.h
1567 +++ b/include/linux/bcma/bcma.h
1568 @@ -6,6 +6,7 @@
1569
1570 #include <linux/bcma/bcma_driver_chipcommon.h>
1571 #include <linux/bcma/bcma_driver_pci.h>
1572 +#include <linux/bcma/bcma_driver_pcie2.h>
1573 #include <linux/bcma/bcma_driver_mips.h>
1574 #include <linux/bcma/bcma_driver_gmac_cmn.h>
1575 #include <linux/ssb/ssb.h> /* SPROM sharing */
1576 @@ -72,7 +73,19 @@ struct bcma_host_ops {
1577 /* Core-ID values. */
1578 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
1579 #define BCMA_CORE_4706_CHIPCOMMON 0x500
1580 +#define BCMA_CORE_NS_PCIEG2 0x501
1581 +#define BCMA_CORE_NS_DMA 0x502
1582 +#define BCMA_CORE_NS_SDIO3 0x503
1583 +#define BCMA_CORE_NS_USB20 0x504
1584 +#define BCMA_CORE_NS_USB30 0x505
1585 +#define BCMA_CORE_NS_A9JTAG 0x506
1586 +#define BCMA_CORE_NS_DDR23 0x507
1587 +#define BCMA_CORE_NS_ROM 0x508
1588 +#define BCMA_CORE_NS_NAND 0x509
1589 +#define BCMA_CORE_NS_QSPI 0x50A
1590 +#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
1591 #define BCMA_CORE_4706_SOC_RAM 0x50E
1592 +#define BCMA_CORE_ARMCA9 0x510
1593 #define BCMA_CORE_4706_MAC_GBIT 0x52D
1594 #define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
1595 #define BCMA_CORE_ALTA 0x534 /* I2S core */
1596 @@ -144,6 +157,10 @@ struct bcma_host_ops {
1597
1598 /* Chip IDs of PCIe devices */
1599 #define BCMA_CHIP_ID_BCM4313 0x4313
1600 +#define BCMA_CHIP_ID_BCM43142 43142
1601 +#define BCMA_CHIP_ID_BCM43131 43131
1602 +#define BCMA_CHIP_ID_BCM43217 43217
1603 +#define BCMA_CHIP_ID_BCM43222 43222
1604 #define BCMA_CHIP_ID_BCM43224 43224
1605 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
1606 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
1607 @@ -176,6 +193,11 @@ struct bcma_host_ops {
1608 #define BCMA_PKG_ID_BCM5357 11
1609 #define BCMA_CHIP_ID_BCM53572 53572
1610 #define BCMA_PKG_ID_BCM47188 9
1611 +#define BCMA_CHIP_ID_BCM4707 53010
1612 +#define BCMA_PKG_ID_BCM4707 1
1613 +#define BCMA_PKG_ID_BCM4708 2
1614 +#define BCMA_PKG_ID_BCM4709 0
1615 +#define BCMA_CHIP_ID_BCM53018 53018
1616
1617 /* Board types (on PCI usually equals to the subsystem dev id) */
1618 /* BCM4313 */
1619 @@ -245,7 +267,7 @@ struct bcma_device {
1620 u8 core_unit;
1621
1622 u32 addr;
1623 - u32 addr1;
1624 + u32 addr_s[8];
1625 u32 wrap;
1626
1627 void __iomem *io_addr;
1628 @@ -310,11 +332,12 @@ struct bcma_bus {
1629 struct bcma_device *mapped_core;
1630 struct list_head cores;
1631 u8 nr_cores;
1632 - u8 init_done:1;
1633 u8 num;
1634
1635 struct bcma_drv_cc drv_cc;
1636 + struct bcma_drv_cc_b drv_cc_b;
1637 struct bcma_drv_pci drv_pci[2];
1638 + struct bcma_drv_pcie2 drv_pcie2;
1639 struct bcma_drv_mips drv_mips;
1640 struct bcma_drv_gmac_cmn drv_gmac_cmn;
1641
1642 @@ -400,7 +423,14 @@ static inline void bcma_maskset16(struct
1643 bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
1644 }
1645
1646 -extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
1647 +extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1648 + u8 unit);
1649 +static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus,
1650 + u16 coreid)
1651 +{
1652 + return bcma_find_core_unit(bus, coreid, 0);
1653 +}
1654 +
1655 extern bool bcma_core_is_enabled(struct bcma_device *core);
1656 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
1657 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
1658 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1659 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1660 @@ -330,6 +330,8 @@
1661 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
1662 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
1663 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
1664 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
1665 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
1666 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
1667 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
1668 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
1669 @@ -355,6 +357,11 @@
1670 #define BCMA_CC_REGCTL_DATA 0x065C
1671 #define BCMA_CC_PLLCTL_ADDR 0x0660
1672 #define BCMA_CC_PLLCTL_DATA 0x0664
1673 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
1674 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
1675 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
1676 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
1677 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
1678 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
1679 /* NAND flash MLC controller registers (corerev >= 38) */
1680 #define BCMA_CC_NAND_REVISION 0x0C00
1681 @@ -435,6 +442,23 @@
1682 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
1683 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
1684
1685 +/* PMU rev 15 */
1686 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
1687 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
1688 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
1689 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
1690 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
1691 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
1692 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
1693 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
1694 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
1695 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
1696 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
1697 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
1698 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
1699 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
1700 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
1701 +
1702 /* ALP clock on pre-PMU chips */
1703 #define BCMA_CC_PMU_ALP_CLOCK 20000000
1704 /* HT clock for systems with PMU-enabled chipcommon */
1705 @@ -507,6 +531,37 @@
1706 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
1707 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
1708
1709 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
1710 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
1711 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
1712 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
1713 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
1714 +#define BCMA_RES_4314_CLDO_PU BIT(5)
1715 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
1716 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
1717 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
1718 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
1719 +#define BCMA_RES_4314_OTP_PU BIT(10)
1720 +#define BCMA_RES_4314_XTAL_PU BIT(11)
1721 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
1722 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
1723 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
1724 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
1725 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
1726 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
1727 +#define BCMA_RES_4314_ILP_REQ BIT(18)
1728 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
1729 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
1730 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
1731 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
1732 +#define BCMA_RES_4314_RADIO_PU BIT(23)
1733 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
1734 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
1735 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
1736 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
1737 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
1738 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
1739 +
1740 /* Data for the PMU, if available.
1741 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
1742 */
1743 @@ -585,9 +640,16 @@ struct bcma_drv_cc {
1744 spinlock_t gpio_lock;
1745 #ifdef CONFIG_BCMA_DRIVER_GPIO
1746 struct gpio_chip gpio;
1747 + struct irq_domain *irq_domain;
1748 #endif
1749 };
1750
1751 +struct bcma_drv_cc_b {
1752 + struct bcma_device *core;
1753 + u8 setup_done:1;
1754 + void __iomem *mii;
1755 +};
1756 +
1757 /* Register access */
1758 #define bcma_cc_read32(cc, offset) \
1759 bcma_read32((cc)->core, offset)
1760 @@ -643,4 +705,6 @@ extern void bcma_pmu_spuravoid_pllupdate
1761
1762 extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
1763
1764 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value);
1765 +
1766 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
1767 --- a/include/linux/bcma/bcma_driver_pci.h
1768 +++ b/include/linux/bcma/bcma_driver_pci.h
1769 @@ -181,10 +181,31 @@ struct pci_dev;
1770
1771 #define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
1772
1773 +#define BCMA_CORE_PCI_
1774 +
1775 +/* MDIO devices (SERDES modules) */
1776 +#define BCMA_CORE_PCI_MDIO_IEEE0 0x000
1777 +#define BCMA_CORE_PCI_MDIO_IEEE1 0x001
1778 +#define BCMA_CORE_PCI_MDIO_BLK0 0x800
1779 +#define BCMA_CORE_PCI_MDIO_BLK1 0x801
1780 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16
1781 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17
1782 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18
1783 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19
1784 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A
1785 +#define BCMA_CORE_PCI_MDIO_BLK2 0x802
1786 +#define BCMA_CORE_PCI_MDIO_BLK3 0x803
1787 +#define BCMA_CORE_PCI_MDIO_BLK4 0x804
1788 +#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */
1789 +#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820
1790 +#define BCMA_CORE_PCI_MDIO_SERDESID 0x831
1791 +#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840
1792 +
1793 /* PCIE Root Capability Register bits (Host mode only) */
1794 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
1795
1796 struct bcma_drv_pci;
1797 +struct bcma_bus;
1798
1799 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
1800 struct bcma_drv_pci_host {
1801 @@ -219,7 +240,9 @@ struct bcma_drv_pci {
1802 extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
1803 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
1804 struct bcma_device *core, bool enable);
1805 -extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
1806 +extern void bcma_core_pci_up(struct bcma_bus *bus);
1807 +extern void bcma_core_pci_down(struct bcma_bus *bus);
1808 +extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up);
1809
1810 extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
1811 extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
1812 --- /dev/null
1813 +++ b/include/linux/bcma/bcma_driver_pcie2.h
1814 @@ -0,0 +1,158 @@
1815 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
1816 +#define LINUX_BCMA_DRIVER_PCIE2_H_
1817 +
1818 +#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
1819 +#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
1820 +#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
1821 +#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
1822 +#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
1823 +#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
1824 +#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
1825 +#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
1826 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
1827 +#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
1828 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
1829 +#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
1830 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
1831 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
1832 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
1833 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
1834 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
1835 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
1836 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
1837 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
1838 +#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
1839 +#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
1840 +#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
1841 +#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
1842 +#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
1843 +#define BCMA_CORE_PCIE2_DATAINTF 0x0180
1844 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
1845 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
1846 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
1847 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
1848 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
1849 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
1850 +#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
1851 +#define PCIE2_LTR_ACTIVE 2
1852 +#define PCIE2_LTR_ACTIVE_IDLE 1
1853 +#define PCIE2_LTR_SLEEP 0
1854 +#define PCIE2_LTR_FINAL_MASK 0x300
1855 +#define PCIE2_LTR_FINAL_SHIFT 8
1856 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
1857 +#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
1858 +#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
1859 +#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
1860 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
1861 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
1862 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
1863 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
1864 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
1865 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
1866 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
1867 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
1868 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
1869 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
1870 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
1871 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
1872 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
1873 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
1874 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
1875 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
1876 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
1877 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
1878 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
1879 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
1880 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
1881 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
1882 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
1883 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
1884 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
1885 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
1886 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
1887 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
1888 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
1889 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
1890 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
1891 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
1892 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
1893 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
1894 +#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
1895 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
1896 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
1897 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
1898 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
1899 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
1900 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
1901 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
1902 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
1903 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
1904 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
1905 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
1906 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
1907 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
1908 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
1909 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
1910 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
1911 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
1912 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
1913 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
1914 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
1915 +#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
1916 +#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
1917 +#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
1918 +#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
1919 +#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
1920 +#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
1921 +#define BCMA_CORE_PCIE2_OARR0 0x0D20
1922 +#define BCMA_CORE_PCIE2_OARR1 0x0D28
1923 +#define BCMA_CORE_PCIE2_OARR2 0x0D30
1924 +#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
1925 +#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
1926 +#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
1927 +#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
1928 +#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
1929 +#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
1930 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
1931 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
1932 +#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
1933 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
1934 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
1935 +#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
1936 +#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
1937 +#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
1938 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
1939 +#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
1940 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
1941 +#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
1942 +#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
1943 +#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
1944 +#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
1945 +#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
1946 +
1947 +/* PCIE gen2 config regs */
1948 +#define PCIE2_INTSTATUS 0x090
1949 +#define PCIE2_INTMASK 0x094
1950 +#define PCIE2_SBMBX 0x098
1951 +
1952 +#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
1953 +
1954 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
1955 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
1956 +#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
1957 +
1958 +struct bcma_drv_pcie2 {
1959 + struct bcma_device *core;
1960 +};
1961 +
1962 +#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
1963 +#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
1964 +#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
1965 +#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
1966 +
1967 +#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
1968 +#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
1969 +
1970 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
1971 +
1972 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
1973 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1974 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1975 @@ -679,27 +679,6 @@ bool ai_clkctl_cc(struct si_pub *sih, en
1976 return mode == BCMA_CLKMODE_FAST;
1977 }
1978
1979 -void ai_pci_up(struct si_pub *sih)
1980 -{
1981 - struct si_info *sii;
1982 -
1983 - sii = container_of(sih, struct si_info, pub);
1984 -
1985 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1986 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
1987 -}
1988 -
1989 -/* Unconfigure and/or apply various WARs when going down */
1990 -void ai_pci_down(struct si_pub *sih)
1991 -{
1992 - struct si_info *sii;
1993 -
1994 - sii = container_of(sih, struct si_info, pub);
1995 -
1996 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1997 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
1998 -}
1999 -
2000 /* Enable BT-COEX & Ex-PA for 4313 */
2001 void ai_epa_4313war(struct si_pub *sih)
2002 {
2003 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
2004 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
2005 @@ -183,9 +183,6 @@ extern u16 ai_clkctl_fast_pwrup_delay(st
2006 extern bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
2007 extern bool ai_deviceremoved(struct si_pub *sih);
2008
2009 -extern void ai_pci_down(struct si_pub *sih);
2010 -extern void ai_pci_up(struct si_pub *sih);
2011 -
2012 /* Enable Ex-PA for 4313 */
2013 extern void ai_epa_4313war(struct si_pub *sih);
2014
2015 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
2016 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
2017 @@ -4667,7 +4667,7 @@ static int brcms_b_attach(struct brcms_c
2018 brcms_c_coredisable(wlc_hw);
2019
2020 /* Match driver "down" state */
2021 - ai_pci_down(wlc_hw->sih);
2022 + bcma_core_pci_down(wlc_hw->d11core->bus);
2023
2024 /* turn off pll and xtal to match driver "down" state */
2025 brcms_b_xtal(wlc_hw, OFF);
2026 @@ -5010,12 +5010,12 @@ static int brcms_b_up_prep(struct brcms_
2027 */
2028 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
2029 /* put SB PCI in down state again */
2030 - ai_pci_down(wlc_hw->sih);
2031 + bcma_core_pci_down(wlc_hw->d11core->bus);
2032 brcms_b_xtal(wlc_hw, OFF);
2033 return -ENOMEDIUM;
2034 }
2035
2036 - ai_pci_up(wlc_hw->sih);
2037 + bcma_core_pci_up(wlc_hw->d11core->bus);
2038
2039 /* reset the d11 core */
2040 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
2041 @@ -5212,7 +5212,7 @@ static int brcms_b_down_finish(struct br
2042
2043 /* turn off primary xtal and pll */
2044 if (!wlc_hw->noreset) {
2045 - ai_pci_down(wlc_hw->sih);
2046 + bcma_core_pci_down(wlc_hw->d11core->bus);
2047 brcms_b_xtal(wlc_hw, OFF);
2048 }
2049 }
2050 --- a/drivers/bcma/driver_mips.c
2051 +++ b/drivers/bcma/driver_mips.c
2052 @@ -21,6 +21,14 @@
2053 #include <linux/serial_reg.h>
2054 #include <linux/time.h>
2055
2056 +enum bcma_boot_dev {
2057 + BCMA_BOOT_DEV_UNK = 0,
2058 + BCMA_BOOT_DEV_ROM,
2059 + BCMA_BOOT_DEV_PARALLEL,
2060 + BCMA_BOOT_DEV_SERIAL,
2061 + BCMA_BOOT_DEV_NAND,
2062 +};
2063 +
2064 static const char * const part_probes[] = { "bcm47xxpart", NULL };
2065
2066 static struct physmap_flash_data bcma_pflash_data = {
2067 @@ -229,11 +237,51 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
2068 }
2069 EXPORT_SYMBOL(bcma_cpu_clock);
2070
2071 +static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
2072 +{
2073 + struct bcma_drv_cc *cc = &bus->drv_cc;
2074 + u8 cc_rev = cc->core->id.rev;
2075 +
2076 + if (cc_rev == 42) {
2077 + struct bcma_device *core;
2078 +
2079 + core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
2080 + if (core) {
2081 + switch (bcma_aread32(core, BCMA_IOST) &
2082 + BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
2083 + case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
2084 + return BCMA_BOOT_DEV_SERIAL;
2085 + case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
2086 + return BCMA_BOOT_DEV_NAND;
2087 + case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
2088 + default:
2089 + return BCMA_BOOT_DEV_ROM;
2090 + }
2091 + }
2092 + } else {
2093 + if (cc_rev == 38) {
2094 + if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
2095 + return BCMA_BOOT_DEV_NAND;
2096 + else if (cc->status & BIT(5))
2097 + return BCMA_BOOT_DEV_ROM;
2098 + }
2099 +
2100 + if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
2101 + BCMA_CC_FLASHT_PARA)
2102 + return BCMA_BOOT_DEV_PARALLEL;
2103 + else
2104 + return BCMA_BOOT_DEV_SERIAL;
2105 + }
2106 +
2107 + return BCMA_BOOT_DEV_SERIAL;
2108 +}
2109 +
2110 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
2111 {
2112 struct bcma_bus *bus = mcore->core->bus;
2113 struct bcma_drv_cc *cc = &bus->drv_cc;
2114 struct bcma_pflash *pflash = &cc->pflash;
2115 + enum bcma_boot_dev boot_dev;
2116
2117 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
2118 case BCMA_CC_FLASHT_STSER:
2119 @@ -269,6 +317,20 @@ static void bcma_core_mips_flash_detect(
2120 bcma_nflash_init(cc);
2121 }
2122 }
2123 +
2124 + /* Determine flash type this SoC boots from */
2125 + boot_dev = bcma_boot_dev(bus);
2126 + switch (boot_dev) {
2127 + case BCMA_BOOT_DEV_PARALLEL:
2128 + case BCMA_BOOT_DEV_SERIAL:
2129 + /* TODO: Init NVRAM using BCMA_SOC_FLASH2 window */
2130 + break;
2131 + case BCMA_BOOT_DEV_NAND:
2132 + /* TODO: Init NVRAM using BCMA_SOC_FLASH1 window */
2133 + break;
2134 + default:
2135 + break;
2136 + }
2137 }
2138
2139 void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
2140 --- a/drivers/bcma/host_soc.c
2141 +++ b/drivers/bcma/host_soc.c
2142 @@ -134,12 +134,16 @@ static void bcma_host_soc_block_write(st
2143
2144 static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
2145 {
2146 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
2147 + return ~0;
2148 return readl(core->io_wrap + offset);
2149 }
2150
2151 static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
2152 u32 value)
2153 {
2154 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
2155 + return;
2156 writel(value, core->io_wrap + offset);
2157 }
2158
2159 @@ -161,7 +165,6 @@ static const struct bcma_host_ops bcma_h
2160 int __init bcma_host_soc_register(struct bcma_soc *soc)
2161 {
2162 struct bcma_bus *bus = &soc->bus;
2163 - int err;
2164
2165 /* iomap only first core. We have to read some register on this core
2166 * to scan the bus.
2167 @@ -174,7 +177,18 @@ int __init bcma_host_soc_register(struct
2168 bus->hosttype = BCMA_HOSTTYPE_SOC;
2169 bus->ops = &bcma_host_soc_ops;
2170
2171 - /* Register */
2172 + /* Initialize struct, detect chip */
2173 + bcma_init_bus(bus);
2174 +
2175 + return 0;
2176 +}
2177 +
2178 +int __init bcma_host_soc_init(struct bcma_soc *soc)
2179 +{
2180 + struct bcma_bus *bus = &soc->bus;
2181 + int err;
2182 +
2183 + /* Scan bus and initialize it */
2184 err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
2185 if (err)
2186 iounmap(bus->mmio);
2187 --- a/include/linux/bcma/bcma_regs.h
2188 +++ b/include/linux/bcma/bcma_regs.h
2189 @@ -39,6 +39,11 @@
2190 #define BCMA_RESET_CTL_RESET 0x0001
2191 #define BCMA_RESET_ST 0x0804
2192
2193 +#define BCMA_NS_ROM_IOST_BOOT_DEV_MASK 0x0003
2194 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NOR 0x0000
2195 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NAND 0x0001
2196 +#define BCMA_NS_ROM_IOST_BOOT_DEV_ROM 0x0002
2197 +
2198 /* BCMA PCI config space registers. */
2199 #define BCMA_PCI_PMCSR 0x44
2200 #define BCMA_PCI_PE 0x100
2201 --- a/drivers/usb/host/bcma-hcd.c
2202 +++ b/drivers/usb/host/bcma-hcd.c
2203 @@ -238,7 +238,7 @@ static int bcma_hcd_probe(struct bcma_de
2204 bcma_hcd_init_chip(dev);
2205
2206 /* In AI chips EHCI is addrspace 0, OHCI is 1 */
2207 - ohci_addr = dev->addr1;
2208 + ohci_addr = dev->addr_s[0];
2209 if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749)
2210 && chipinfo->rev == 0)
2211 ohci_addr = 0x18009000;
2212 --- /dev/null
2213 +++ b/drivers/bcma/driver_chipcommon_b.c
2214 @@ -0,0 +1,61 @@
2215 +/*
2216 + * Broadcom specific AMBA
2217 + * ChipCommon B Unit driver
2218 + *
2219 + * Copyright 2014, Hauke Mehrtens <hauke@hauke-m.de>
2220 + *
2221 + * Licensed under the GNU/GPL. See COPYING for details.
2222 + */
2223 +
2224 +#include "bcma_private.h"
2225 +#include <linux/export.h>
2226 +#include <linux/bcma/bcma.h>
2227 +
2228 +static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
2229 + u32 value, int timeout)
2230 +{
2231 + unsigned long deadline = jiffies + timeout;
2232 + u32 val;
2233 +
2234 + do {
2235 + val = readl(addr);
2236 + if ((val & mask) == value)
2237 + return true;
2238 + cpu_relax();
2239 + udelay(10);
2240 + } while (!time_after_eq(jiffies, deadline));
2241 +
2242 + bcma_err(bus, "Timeout waiting for register %p\n", addr);
2243 +
2244 + return false;
2245 +}
2246 +
2247 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
2248 +{
2249 + struct bcma_bus *bus = ccb->core->bus;
2250 +
2251 + writel(offset, ccb->mii + 0x00);
2252 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
2253 + writel(value, ccb->mii + 0x04);
2254 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
2255 +}
2256 +EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
2257 +
2258 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb)
2259 +{
2260 + if (ccb->setup_done)
2261 + return 0;
2262 +
2263 + ccb->setup_done = 1;
2264 + ccb->mii = ioremap_nocache(ccb->core->addr_s[1], BCMA_CORE_SIZE);
2265 + if (!ccb->mii)
2266 + return -ENOMEM;
2267 +
2268 + return 0;
2269 +}
2270 +
2271 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb)
2272 +{
2273 + if (ccb->mii)
2274 + iounmap(ccb->mii);
2275 +}
2276 --- a/include/linux/bcma/bcma_soc.h
2277 +++ b/include/linux/bcma/bcma_soc.h
2278 @@ -10,6 +10,7 @@ struct bcma_soc {
2279 };
2280
2281 int __init bcma_host_soc_register(struct bcma_soc *soc);
2282 +int __init bcma_host_soc_init(struct bcma_soc *soc);
2283
2284 int bcma_bus_register(struct bcma_bus *bus);
2285
2286 --- a/arch/mips/bcm47xx/setup.c
2287 +++ b/arch/mips/bcm47xx/setup.c
2288 @@ -194,6 +194,10 @@ static void __init bcm47xx_register_bcma
2289
2290 err = bcma_host_soc_register(&bcm47xx_bus.bcma);
2291 if (err)
2292 + panic("Failed to register BCMA bus (err %d)", err);
2293 +
2294 + err = bcma_host_soc_init(&bcm47xx_bus.bcma);
2295 + if (err)
2296 panic("Failed to initialize BCMA bus (err %d)", err);
2297
2298 bcm47xx_fill_bcma_boardinfo(&bcm47xx_bus.bcma.bus.boardinfo, NULL);
OpenWrt SVN history