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kernel: bgmac: update backport patch
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.10 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
4 config BCMA_HOST_PCI
5 bool "Support for BCMA on PCI-host bus"
6 depends on BCMA_HOST_PCI_POSSIBLE
7 + default y
8
9 config BCMA_DRIVER_PCI_HOSTMODE
10 bool "Driver for PCI core working in hostmode"
11 @@ -34,8 +35,14 @@ config BCMA_DRIVER_PCI_HOSTMODE
12 PCI core hostmode operation (external PCI bus).
13
14 config BCMA_HOST_SOC
15 - bool
16 - depends on BCMA_DRIVER_MIPS
17 + bool "Support for BCMA in a SoC"
18 + depends on BCMA
19 + help
20 + Host interface for a Broadcom AIX bus directly mapped into
21 + the memory. This only works with the Broadcom SoCs from the
22 + BCM47XX line.
23 +
24 + If unsure, say N
25
26 config BCMA_DRIVER_MIPS
27 bool "BCMA Broadcom MIPS core driver"
28 --- a/drivers/bcma/bcma_private.h
29 +++ b/drivers/bcma/bcma_private.h
30 @@ -22,6 +22,8 @@
31 struct bcma_bus;
32
33 /* main.c */
34 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
35 + int timeout);
36 int bcma_bus_register(struct bcma_bus *bus);
37 void bcma_bus_unregister(struct bcma_bus *bus);
38 int __init bcma_bus_early_register(struct bcma_bus *bus,
39 --- a/drivers/bcma/core.c
40 +++ b/drivers/bcma/core.c
41 @@ -9,6 +9,25 @@
42 #include <linux/export.h>
43 #include <linux/bcma/bcma.h>
44
45 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
46 + u32 value, int timeout)
47 +{
48 + unsigned long deadline = jiffies + timeout;
49 + u32 val;
50 +
51 + do {
52 + val = bcma_aread32(core, reg);
53 + if ((val & mask) == value)
54 + return true;
55 + cpu_relax();
56 + udelay(10);
57 + } while (!time_after_eq(jiffies, deadline));
58 +
59 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
60 +
61 + return false;
62 +}
63 +
64 bool bcma_core_is_enabled(struct bcma_device *core)
65 {
66 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
67 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
68 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
69 return;
70
71 - bcma_awrite32(core, BCMA_IOCTL, flags);
72 - bcma_aread32(core, BCMA_IOCTL);
73 - udelay(10);
74 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
75
76 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
77 bcma_aread32(core, BCMA_RESET_CTL);
78 udelay(1);
79 +
80 + bcma_awrite32(core, BCMA_IOCTL, flags);
81 + bcma_aread32(core, BCMA_IOCTL);
82 + udelay(10);
83 }
84 EXPORT_SYMBOL_GPL(bcma_core_disable);
85
86 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
87 bcma_aread32(core, BCMA_IOCTL);
88
89 bcma_awrite32(core, BCMA_RESET_CTL, 0);
90 + bcma_aread32(core, BCMA_RESET_CTL);
91 udelay(1);
92
93 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
94 --- a/drivers/bcma/driver_chipcommon.c
95 +++ b/drivers/bcma/driver_chipcommon.c
96 @@ -140,8 +140,15 @@ void bcma_core_chipcommon_init(struct bc
97 bcma_core_chipcommon_early_init(cc);
98
99 if (cc->core->id.rev >= 20) {
100 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
101 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
102 + u32 pullup = 0, pulldown = 0;
103 +
104 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
105 + pullup = 0x402e0;
106 + pulldown = 0x20500;
107 + }
108 +
109 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
110 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
111 }
112
113 if (cc->capabilities & BCMA_CC_CAP_PMU)
114 --- a/drivers/bcma/driver_chipcommon_pmu.c
115 +++ b/drivers/bcma/driver_chipcommon_pmu.c
116 @@ -56,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
117 }
118 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
119
120 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
121 +{
122 + u32 ilp_ctl, alp_hz;
123 +
124 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
125 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
126 + return 0;
127 +
128 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
129 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
130 + usleep_range(1000, 2000);
131 +
132 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
133 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
134 +
135 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
136 +
137 + alp_hz = ilp_ctl * 32768 / 4;
138 + return (alp_hz + 50000) / 100000 * 100;
139 +}
140 +
141 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
142 +{
143 + struct bcma_bus *bus = cc->core->bus;
144 + u32 freq_tgt_target = 0, freq_tgt_current;
145 + u32 pll0, mask;
146 +
147 + switch (bus->chipinfo.id) {
148 + case BCMA_CHIP_ID_BCM43142:
149 + /* pmu2_xtaltab0_adfll_485 */
150 + switch (xtalfreq) {
151 + case 12000:
152 + freq_tgt_target = 0x50D52;
153 + break;
154 + case 20000:
155 + freq_tgt_target = 0x307FE;
156 + break;
157 + case 26000:
158 + freq_tgt_target = 0x254EA;
159 + break;
160 + case 37400:
161 + freq_tgt_target = 0x19EF8;
162 + break;
163 + case 52000:
164 + freq_tgt_target = 0x12A75;
165 + break;
166 + }
167 + break;
168 + }
169 +
170 + if (!freq_tgt_target) {
171 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
172 + xtalfreq);
173 + return;
174 + }
175 +
176 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
177 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
178 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
179 +
180 + if (freq_tgt_current == freq_tgt_target) {
181 + bcma_debug(bus, "Target TGT frequency already set\n");
182 + return;
183 + }
184 +
185 + /* Turn off PLL */
186 + switch (bus->chipinfo.id) {
187 + case BCMA_CHIP_ID_BCM43142:
188 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
189 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
190 +
191 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
192 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
193 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
194 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
195 + break;
196 + }
197 +
198 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
199 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
200 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
201 +
202 + /* Flush */
203 + if (cc->pmu.rev >= 2)
204 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
205 +
206 + /* TODO: Do we need to update OTP? */
207 +}
208 +
209 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
210 +{
211 + struct bcma_bus *bus = cc->core->bus;
212 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
213 +
214 + switch (bus->chipinfo.id) {
215 + case BCMA_CHIP_ID_BCM43142:
216 + if (xtalfreq == 0)
217 + xtalfreq = 20000;
218 + bcma_pmu2_pll_init0(cc, xtalfreq);
219 + break;
220 + }
221 +}
222 +
223 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
224 {
225 struct bcma_bus *bus = cc->core->bus;
226 @@ -66,6 +169,25 @@ static void bcma_pmu_resources_init(stru
227 min_msk = 0x200D;
228 max_msk = 0xFFFF;
229 break;
230 + case BCMA_CHIP_ID_BCM43142:
231 + min_msk = BCMA_RES_4314_LPLDO_PU |
232 + BCMA_RES_4314_PMU_SLEEP_DIS |
233 + BCMA_RES_4314_PMU_BG_PU |
234 + BCMA_RES_4314_CBUCK_LPOM_PU |
235 + BCMA_RES_4314_CBUCK_PFM_PU |
236 + BCMA_RES_4314_CLDO_PU |
237 + BCMA_RES_4314_LPLDO2_LVM |
238 + BCMA_RES_4314_WL_PMU_PU |
239 + BCMA_RES_4314_LDO3P3_PU |
240 + BCMA_RES_4314_OTP_PU |
241 + BCMA_RES_4314_WL_PWRSW_PU |
242 + BCMA_RES_4314_LQ_AVAIL |
243 + BCMA_RES_4314_LOGIC_RET |
244 + BCMA_RES_4314_MEM_SLEEP |
245 + BCMA_RES_4314_MACPHY_RET |
246 + BCMA_RES_4314_WL_CORE_READY;
247 + max_msk = 0x3FFFFFFF;
248 + break;
249 default:
250 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
251 bus->chipinfo.id);
252 @@ -165,6 +287,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
253 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
254 BCMA_CC_PMU_CTL_NOILPONW);
255
256 + bcma_pmu_pll_init(cc);
257 bcma_pmu_resources_init(cc);
258 bcma_pmu_workarounds(cc);
259 }
260 --- a/drivers/bcma/driver_chipcommon_sflash.c
261 +++ b/drivers/bcma/driver_chipcommon_sflash.c
262 @@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e {
263 u16 numblocks;
264 };
265
266 -static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
267 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
268 { "M25P20", 0x11, 0x10000, 4, },
269 { "M25P40", 0x12, 0x10000, 8, },
270
271 @@ -41,7 +41,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
272 { 0 },
273 };
274
275 -static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
276 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
277 { "SST25WF512", 1, 0x1000, 16, },
278 { "SST25VF512", 0x48, 0x1000, 16, },
279 { "SST25WF010", 2, 0x1000, 32, },
280 @@ -59,7 +59,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
281 { 0 },
282 };
283
284 -static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
285 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
286 { "AT45DB011", 0xc, 256, 512, },
287 { "AT45DB021", 0x14, 256, 1024, },
288 { "AT45DB041", 0x1c, 256, 2048, },
289 @@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc
290 {
291 struct bcma_bus *bus = cc->core->bus;
292 struct bcma_sflash *sflash = &cc->sflash;
293 - struct bcma_sflash_tbl_e *e;
294 + const struct bcma_sflash_tbl_e *e;
295 u32 id, id2;
296
297 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
298 --- a/drivers/bcma/host_pci.c
299 +++ b/drivers/bcma/host_pci.c
300 @@ -275,6 +275,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
301 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
302 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
303 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
304 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
305 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
306 { 0, },
307 };
308 --- a/drivers/bcma/main.c
309 +++ b/drivers/bcma/main.c
310 @@ -93,6 +93,25 @@ struct bcma_device *bcma_find_core_unit(
311 return NULL;
312 }
313
314 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
315 + int timeout)
316 +{
317 + unsigned long deadline = jiffies + timeout;
318 + u32 val;
319 +
320 + do {
321 + val = bcma_read32(core, reg);
322 + if ((val & mask) == value)
323 + return true;
324 + cpu_relax();
325 + udelay(10);
326 + } while (!time_after_eq(jiffies, deadline));
327 +
328 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
329 +
330 + return false;
331 +}
332 +
333 static void bcma_release_core_dev(struct device *dev)
334 {
335 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
336 @@ -218,7 +237,7 @@ int bcma_bus_register(struct bcma_bus *b
337 err = bcma_bus_scan(bus);
338 if (err) {
339 bcma_err(bus, "Failed to scan: %d\n", err);
340 - return -1;
341 + return err;
342 }
343
344 /* Early init CC core */
345 --- a/drivers/bcma/sprom.c
346 +++ b/drivers/bcma/sprom.c
347 @@ -72,12 +72,12 @@ fail:
348 * R/W ops.
349 **************************************************/
350
351 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
352 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
353 + size_t words)
354 {
355 int i;
356 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
357 - sprom[i] = bcma_read16(bus->drv_cc.core,
358 - offset + (i * 2));
359 + for (i = 0; i < words; i++)
360 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
361 }
362
363 /**************************************************
364 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
365 return t[crc ^ data];
366 }
367
368 -static u8 bcma_sprom_crc(const u16 *sprom)
369 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
370 {
371 int word;
372 u8 crc = 0xFF;
373
374 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
375 + for (word = 0; word < words - 1; word++) {
376 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
377 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
378 }
379 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
380 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
381 crc ^= 0xFF;
382
383 return crc;
384 }
385
386 -static int bcma_sprom_check_crc(const u16 *sprom)
387 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
388 {
389 u8 crc;
390 u8 expected_crc;
391 u16 tmp;
392
393 - crc = bcma_sprom_crc(sprom);
394 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
395 + crc = bcma_sprom_crc(sprom, words);
396 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
397 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
398 if (crc != expected_crc)
399 return -EPROTO;
400 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
401 return 0;
402 }
403
404 -static int bcma_sprom_valid(const u16 *sprom)
405 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
406 + size_t words)
407 {
408 u16 revision;
409 int err;
410
411 - err = bcma_sprom_check_crc(sprom);
412 + err = bcma_sprom_check_crc(sprom, words);
413 if (err)
414 return err;
415
416 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
417 - if (revision != 8 && revision != 9) {
418 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
419 + if (revision != 8 && revision != 9 && revision != 10) {
420 pr_err("Unsupported SPROM revision: %d\n", revision);
421 return -ENOENT;
422 }
423
424 + bus->sprom.revision = revision;
425 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
426 +
427 return 0;
428 }
429
430 @@ -208,9 +212,6 @@ static void bcma_sprom_extract_r8(struct
431 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
432 ARRAY_SIZE(bus->sprom.core_pwr_info));
433
434 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
435 - SSB_SPROM_REVISION_REV;
436 -
437 for (i = 0; i < 3; i++) {
438 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
439 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
440 @@ -502,7 +503,7 @@ static bool bcma_sprom_onchip_available(
441 case BCMA_CHIP_ID_BCM4331:
442 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
443 break;
444 -
445 + case BCMA_CHIP_ID_BCM43142:
446 case BCMA_CHIP_ID_BCM43224:
447 case BCMA_CHIP_ID_BCM43225:
448 /* for these chips OTP is always available */
449 @@ -550,7 +551,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
450 {
451 u16 offset = BCMA_CC_SPROM;
452 u16 *sprom;
453 - int err = 0;
454 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
455 + SSB_SPROMSIZE_WORDS_R10, };
456 + int i, err = 0;
457
458 if (!bus->drv_cc.core)
459 return -EOPNOTSUPP;
460 @@ -579,32 +582,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
461 }
462 }
463
464 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
465 - GFP_KERNEL);
466 - if (!sprom)
467 - return -ENOMEM;
468 -
469 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
470 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
471 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
472
473 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
474 - bcma_sprom_read(bus, offset, sprom);
475 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
476 + size_t words = sprom_sizes[i];
477 +
478 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
479 + if (!sprom)
480 + return -ENOMEM;
481 +
482 + bcma_sprom_read(bus, offset, sprom, words);
483 + err = bcma_sprom_valid(bus, sprom, words);
484 + if (!err)
485 + break;
486 +
487 + kfree(sprom);
488 + }
489
490 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
491 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
492 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
493
494 - err = bcma_sprom_valid(sprom);
495 if (err) {
496 - bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
497 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
498 err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
499 - goto out;
500 + } else {
501 + bcma_sprom_extract_r8(bus, sprom);
502 + kfree(sprom);
503 }
504
505 - bcma_sprom_extract_r8(bus, sprom);
506 -
507 -out:
508 - kfree(sprom);
509 return err;
510 }
511 --- a/include/linux/bcma/bcma.h
512 +++ b/include/linux/bcma/bcma.h
513 @@ -72,7 +72,19 @@ struct bcma_host_ops {
514 /* Core-ID values. */
515 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
516 #define BCMA_CORE_4706_CHIPCOMMON 0x500
517 +#define BCMA_CORE_PCIEG2 0x501
518 +#define BCMA_CORE_DMA 0x502
519 +#define BCMA_CORE_SDIO3 0x503
520 +#define BCMA_CORE_USB20 0x504
521 +#define BCMA_CORE_USB30 0x505
522 +#define BCMA_CORE_A9JTAG 0x506
523 +#define BCMA_CORE_DDR23 0x507
524 +#define BCMA_CORE_ROM 0x508
525 +#define BCMA_CORE_NAND 0x509
526 +#define BCMA_CORE_QSPI 0x50A
527 +#define BCMA_CORE_CHIPCOMMON_B 0x50B
528 #define BCMA_CORE_4706_SOC_RAM 0x50E
529 +#define BCMA_CORE_ARMCA9 0x510
530 #define BCMA_CORE_4706_MAC_GBIT 0x52D
531 #define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
532 #define BCMA_CORE_ALTA 0x534 /* I2S core */
533 @@ -144,6 +156,7 @@ struct bcma_host_ops {
534
535 /* Chip IDs of PCIe devices */
536 #define BCMA_CHIP_ID_BCM4313 0x4313
537 +#define BCMA_CHIP_ID_BCM43142 43142
538 #define BCMA_CHIP_ID_BCM43224 43224
539 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
540 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
541 @@ -176,6 +189,11 @@ struct bcma_host_ops {
542 #define BCMA_PKG_ID_BCM5357 11
543 #define BCMA_CHIP_ID_BCM53572 53572
544 #define BCMA_PKG_ID_BCM47188 9
545 +#define BCMA_CHIP_ID_BCM4707 53010
546 +#define BCMA_PKG_ID_BCM4707 1
547 +#define BCMA_PKG_ID_BCM4708 2
548 +#define BCMA_PKG_ID_BCM4709 0
549 +#define BCMA_CHIP_ID_BCM53018 53018
550
551 /* Board types (on PCI usually equals to the subsystem dev id) */
552 /* BCM4313 */
553 --- a/include/linux/bcma/bcma_driver_chipcommon.h
554 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
555 @@ -330,6 +330,8 @@
556 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
557 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
558 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
559 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
560 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
561 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
562 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
563 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
564 @@ -355,6 +357,11 @@
565 #define BCMA_CC_REGCTL_DATA 0x065C
566 #define BCMA_CC_PLLCTL_ADDR 0x0660
567 #define BCMA_CC_PLLCTL_DATA 0x0664
568 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
569 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
570 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
571 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
572 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
573 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
574 /* NAND flash MLC controller registers (corerev >= 38) */
575 #define BCMA_CC_NAND_REVISION 0x0C00
576 @@ -435,6 +442,23 @@
577 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
578 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
579
580 +/* PMU rev 15 */
581 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
582 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
583 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
584 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
585 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
586 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
587 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
588 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
589 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
590 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
591 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
592 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
593 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
594 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
595 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
596 +
597 /* ALP clock on pre-PMU chips */
598 #define BCMA_CC_PMU_ALP_CLOCK 20000000
599 /* HT clock for systems with PMU-enabled chipcommon */
600 @@ -507,6 +531,37 @@
601 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
602 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
603
604 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
605 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
606 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
607 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
608 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
609 +#define BCMA_RES_4314_CLDO_PU BIT(5)
610 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
611 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
612 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
613 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
614 +#define BCMA_RES_4314_OTP_PU BIT(10)
615 +#define BCMA_RES_4314_XTAL_PU BIT(11)
616 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
617 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
618 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
619 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
620 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
621 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
622 +#define BCMA_RES_4314_ILP_REQ BIT(18)
623 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
624 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
625 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
626 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
627 +#define BCMA_RES_4314_RADIO_PU BIT(23)
628 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
629 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
630 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
631 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
632 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
633 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
634 +
635 /* Data for the PMU, if available.
636 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
637 */
638 --- a/drivers/bcma/driver_pci.c
639 +++ b/drivers/bcma/driver_pci.c
640 @@ -31,7 +31,7 @@ static void bcma_pcie_write(struct bcma_
641 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
642 }
643
644 -static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
645 +static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
646 {
647 u32 v;
648 int i;
649 @@ -55,7 +55,7 @@ static void bcma_pcie_mdio_set_phy(struc
650 }
651 }
652
653 -static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
654 +static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
655 {
656 int max_retries = 10;
657 u16 ret = 0;
658 @@ -98,7 +98,7 @@ static u16 bcma_pcie_mdio_read(struct bc
659 return ret;
660 }
661
662 -static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
663 +static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
664 u8 address, u16 data)
665 {
666 int max_retries = 10;
667 @@ -137,6 +137,13 @@ static void bcma_pcie_mdio_write(struct
668 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
669 }
670
671 +static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
672 + u8 address, u16 data)
673 +{
674 + bcma_pcie_mdio_write(pc, device, address, data);
675 + return bcma_pcie_mdio_read(pc, device, address);
676 +}
677 +
678 /**************************************************
679 * Workarounds.
680 **************************************************/
681 @@ -229,6 +236,32 @@ void bcma_core_pci_init(struct bcma_drv_
682 bcma_core_pci_clientmode_init(pc);
683 }
684
685 +void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
686 +{
687 + struct bcma_drv_pci *pc;
688 + u16 data;
689 +
690 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
691 + return;
692 +
693 + pc = &bus->drv_pci[0];
694 +
695 + if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
696 + data = up ? 0x74 : 0x7C;
697 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
698 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
699 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
700 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
701 + } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
702 + data = up ? 0x75 : 0x7D;
703 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
704 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
705 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
706 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
707 + }
708 +}
709 +EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
710 +
711 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
712 bool enable)
713 {
714 @@ -262,7 +295,7 @@ out:
715 }
716 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
717
718 -void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
719 +static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
720 {
721 u32 w;
722
723 @@ -274,4 +307,29 @@ void bcma_core_pci_extend_L1timer(struct
724 bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
725 bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
726 }
727 -EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
728 +
729 +void bcma_core_pci_up(struct bcma_bus *bus)
730 +{
731 + struct bcma_drv_pci *pc;
732 +
733 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
734 + return;
735 +
736 + pc = &bus->drv_pci[0];
737 +
738 + bcma_core_pci_extend_L1timer(pc, true);
739 +}
740 +EXPORT_SYMBOL_GPL(bcma_core_pci_up);
741 +
742 +void bcma_core_pci_down(struct bcma_bus *bus)
743 +{
744 + struct bcma_drv_pci *pc;
745 +
746 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
747 + return;
748 +
749 + pc = &bus->drv_pci[0];
750 +
751 + bcma_core_pci_extend_L1timer(pc, false);
752 +}
753 +EXPORT_SYMBOL_GPL(bcma_core_pci_down);
754 --- a/drivers/bcma/driver_pci_host.c
755 +++ b/drivers/bcma/driver_pci_host.c
756 @@ -581,6 +581,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI
757 int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
758 {
759 struct bcma_drv_pci_host *pc_host;
760 + int readrq;
761
762 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
763 /* This is not a device on the PCI-core bridge. */
764 @@ -595,6 +596,11 @@ int bcma_core_pci_plat_dev_init(struct p
765 dev->irq = bcma_core_irq(pc_host->pdev->core);
766 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
767
768 + readrq = pcie_get_readrq(dev);
769 + if (readrq > 128) {
770 + pr_info("change PCIe max read request size from %i to 128\n", readrq);
771 + pcie_set_readrq(dev, 128);
772 + }
773 return 0;
774 }
775 EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
776 --- a/drivers/bcma/scan.c
777 +++ b/drivers/bcma/scan.c
778 @@ -32,6 +32,18 @@ static const struct bcma_device_id_name
779 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
780 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
781 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
782 + { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
783 + { BCMA_CORE_DMA, "DMA" },
784 + { BCMA_CORE_SDIO3, "SDIO3" },
785 + { BCMA_CORE_USB20, "USB 2.0" },
786 + { BCMA_CORE_USB30, "USB 3.0" },
787 + { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
788 + { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
789 + { BCMA_CORE_ROM, "ROM" },
790 + { BCMA_CORE_NAND, "NAND flash controller" },
791 + { BCMA_CORE_QSPI, "SPI flash controller" },
792 + { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
793 + { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
794 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
795 { BCMA_CORE_ALTA, "ALTA (I2S)" },
796 { BCMA_CORE_INVALID, "Invalid" },
797 @@ -201,7 +213,7 @@ static s32 bcma_erom_get_mst_port(struct
798 return ent;
799 }
800
801 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
802 +static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
803 u32 type, u8 port)
804 {
805 u32 addrl, addrh, sizel, sizeh = 0;
806 @@ -213,7 +225,7 @@ static s32 bcma_erom_get_addr_desc(struc
807 ((ent & SCAN_ADDR_TYPE) != type) ||
808 (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
809 bcma_erom_push_ent(eromptr);
810 - return -EINVAL;
811 + return (u32)-EINVAL;
812 }
813
814 addrl = ent & SCAN_ADDR_ADDR;
815 @@ -257,11 +269,13 @@ static struct bcma_device *bcma_find_cor
816 return NULL;
817 }
818
819 +#define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO)
820 +
821 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
822 struct bcma_device_id *match, int core_num,
823 struct bcma_device *core)
824 {
825 - s32 tmp;
826 + u32 tmp;
827 u8 i, j;
828 s32 cia, cib;
829 u8 ports[2], wrappers[2];
830 @@ -339,11 +353,11 @@ static int bcma_get_next_core(struct bcm
831 * the main register space for the core
832 */
833 tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
834 - if (tmp <= 0) {
835 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
836 /* Try again to see if it is a bridge */
837 tmp = bcma_erom_get_addr_desc(bus, eromptr,
838 SCAN_ADDR_TYPE_BRIDGE, 0);
839 - if (tmp <= 0) {
840 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
841 return -EILSEQ;
842 } else {
843 bcma_info(bus, "Bridge found\n");
844 @@ -357,7 +371,7 @@ static int bcma_get_next_core(struct bcm
845 for (j = 0; ; j++) {
846 tmp = bcma_erom_get_addr_desc(bus, eromptr,
847 SCAN_ADDR_TYPE_SLAVE, i);
848 - if (tmp < 0) {
849 + if (IS_ERR_VALUE_U32(tmp)) {
850 /* no more entries for port _i_ */
851 /* pr_debug("erom: slave port %d "
852 * "has %d descriptors\n", i, j); */
853 @@ -374,7 +388,7 @@ static int bcma_get_next_core(struct bcm
854 for (j = 0; ; j++) {
855 tmp = bcma_erom_get_addr_desc(bus, eromptr,
856 SCAN_ADDR_TYPE_MWRAP, i);
857 - if (tmp < 0) {
858 + if (IS_ERR_VALUE_U32(tmp)) {
859 /* no more entries for port _i_ */
860 /* pr_debug("erom: master wrapper %d "
861 * "has %d descriptors\n", i, j); */
862 @@ -392,7 +406,7 @@ static int bcma_get_next_core(struct bcm
863 for (j = 0; ; j++) {
864 tmp = bcma_erom_get_addr_desc(bus, eromptr,
865 SCAN_ADDR_TYPE_SWRAP, i + hack);
866 - if (tmp < 0) {
867 + if (IS_ERR_VALUE_U32(tmp)) {
868 /* no more entries for port _i_ */
869 /* pr_debug("erom: master wrapper %d "
870 * has %d descriptors\n", i, j); */
871 --- a/include/linux/bcma/bcma_driver_pci.h
872 +++ b/include/linux/bcma/bcma_driver_pci.h
873 @@ -181,10 +181,31 @@ struct pci_dev;
874
875 #define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
876
877 +#define BCMA_CORE_PCI_
878 +
879 +/* MDIO devices (SERDES modules) */
880 +#define BCMA_CORE_PCI_MDIO_IEEE0 0x000
881 +#define BCMA_CORE_PCI_MDIO_IEEE1 0x001
882 +#define BCMA_CORE_PCI_MDIO_BLK0 0x800
883 +#define BCMA_CORE_PCI_MDIO_BLK1 0x801
884 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16
885 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17
886 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18
887 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19
888 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A
889 +#define BCMA_CORE_PCI_MDIO_BLK2 0x802
890 +#define BCMA_CORE_PCI_MDIO_BLK3 0x803
891 +#define BCMA_CORE_PCI_MDIO_BLK4 0x804
892 +#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */
893 +#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820
894 +#define BCMA_CORE_PCI_MDIO_SERDESID 0x831
895 +#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840
896 +
897 /* PCIE Root Capability Register bits (Host mode only) */
898 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
899
900 struct bcma_drv_pci;
901 +struct bcma_bus;
902
903 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
904 struct bcma_drv_pci_host {
905 @@ -219,7 +240,9 @@ struct bcma_drv_pci {
906 extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
907 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
908 struct bcma_device *core, bool enable);
909 -extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
910 +extern void bcma_core_pci_up(struct bcma_bus *bus);
911 +extern void bcma_core_pci_down(struct bcma_bus *bus);
912 +extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up);
913
914 extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
915 extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
916 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
917 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
918 @@ -679,27 +679,6 @@ bool ai_clkctl_cc(struct si_pub *sih, en
919 return mode == BCMA_CLKMODE_FAST;
920 }
921
922 -void ai_pci_up(struct si_pub *sih)
923 -{
924 - struct si_info *sii;
925 -
926 - sii = container_of(sih, struct si_info, pub);
927 -
928 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
929 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
930 -}
931 -
932 -/* Unconfigure and/or apply various WARs when going down */
933 -void ai_pci_down(struct si_pub *sih)
934 -{
935 - struct si_info *sii;
936 -
937 - sii = container_of(sih, struct si_info, pub);
938 -
939 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
940 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
941 -}
942 -
943 /* Enable BT-COEX & Ex-PA for 4313 */
944 void ai_epa_4313war(struct si_pub *sih)
945 {
946 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
947 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
948 @@ -183,9 +183,6 @@ extern u16 ai_clkctl_fast_pwrup_delay(st
949 extern bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
950 extern bool ai_deviceremoved(struct si_pub *sih);
951
952 -extern void ai_pci_down(struct si_pub *sih);
953 -extern void ai_pci_up(struct si_pub *sih);
954 -
955 /* Enable Ex-PA for 4313 */
956 extern void ai_epa_4313war(struct si_pub *sih);
957
958 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
959 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
960 @@ -4667,7 +4667,7 @@ static int brcms_b_attach(struct brcms_c
961 brcms_c_coredisable(wlc_hw);
962
963 /* Match driver "down" state */
964 - ai_pci_down(wlc_hw->sih);
965 + bcma_core_pci_down(wlc_hw->d11core->bus);
966
967 /* turn off pll and xtal to match driver "down" state */
968 brcms_b_xtal(wlc_hw, OFF);
969 @@ -5010,12 +5010,12 @@ static int brcms_b_up_prep(struct brcms_
970 */
971 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
972 /* put SB PCI in down state again */
973 - ai_pci_down(wlc_hw->sih);
974 + bcma_core_pci_down(wlc_hw->d11core->bus);
975 brcms_b_xtal(wlc_hw, OFF);
976 return -ENOMEDIUM;
977 }
978
979 - ai_pci_up(wlc_hw->sih);
980 + bcma_core_pci_up(wlc_hw->d11core->bus);
981
982 /* reset the d11 core */
983 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
984 @@ -5212,7 +5212,7 @@ static int brcms_b_down_finish(struct br
985
986 /* turn off primary xtal and pll */
987 if (!wlc_hw->noreset) {
988 - ai_pci_down(wlc_hw->sih);
989 + bcma_core_pci_down(wlc_hw->d11core->bus);
990 brcms_b_xtal(wlc_hw, OFF);
991 }
992 }
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