target/linux/generic/patches-3.10/025-bcma_backport.patch

   1 diff --git a/drivers/bcma/Kconfig b/drivers/bcma/Kconfig
   2 index 8b4221c..380a200 100644
   3 --- a/drivers/bcma/Kconfig
   4 +++ b/drivers/bcma/Kconfig
   5 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
   6  config BCMA_HOST_PCI
   7         bool "Support for BCMA on PCI-host bus"
   8         depends on BCMA_HOST_PCI_POSSIBLE
   9 +       default y
  10
  11  config BCMA_DRIVER_PCI_HOSTMODE
  12         bool "Driver for PCI core working in hostmode"
  13 diff --git a/drivers/bcma/bcma_private.h b/drivers/bcma/bcma_private.h
  14 index 79595a0..0215f9a 100644
  15 --- a/drivers/bcma/bcma_private.h
  16 +++ b/drivers/bcma/bcma_private.h
  17 @@ -22,6 +22,8 @@
  18  struct bcma_bus;
  19
  20  /* main.c */
  21 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
  22 +                    int timeout);
  23  int bcma_bus_register(struct bcma_bus *bus);
  24  void bcma_bus_unregister(struct bcma_bus *bus);
  25  int __init bcma_bus_early_register(struct bcma_bus *bus,
  26 diff --git a/drivers/bcma/core.c b/drivers/bcma/core.c
  27 index 17b26ce..37a5ffe 100644
  28 --- a/drivers/bcma/core.c
  29 +++ b/drivers/bcma/core.c
  30 @@ -9,6 +9,25 @@
  31  #include <linux/export.h>
  32  #include <linux/bcma/bcma.h>
  33
  34 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
  35 +                                u32 value, int timeout)
  36 +{
  37 +       unsigned long deadline = jiffies + timeout;
  38 +       u32 val;
  39 +
  40 +       do {
  41 +               val = bcma_aread32(core, reg);
  42 +               if ((val & mask) == value)
  43 +                       return true;
  44 +               cpu_relax();
  45 +               udelay(10);
  46 +       } while (!time_after_eq(jiffies, deadline));
  47 +
  48 +       bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
  49 +
  50 +       return false;
  51 +}
  52 +
  53  bool bcma_core_is_enabled(struct bcma_device *core)
  54  {
  55         if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
  56 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_device *core, u32 flags)
  57         if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
  58                 return;
  59
  60 -       bcma_awrite32(core, BCMA_IOCTL, flags);
  61 -       bcma_aread32(core, BCMA_IOCTL);
  62 -       udelay(10);
  63 +       bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
  64
  65         bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
  66         bcma_aread32(core, BCMA_RESET_CTL);
  67         udelay(1);
  68 +
  69 +       bcma_awrite32(core, BCMA_IOCTL, flags);
  70 +       bcma_aread32(core, BCMA_IOCTL);
  71 +       udelay(10);
  72  }
  73  EXPORT_SYMBOL_GPL(bcma_core_disable);
  74
  75 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device *core, u32 flags)
  76         bcma_aread32(core, BCMA_IOCTL);
  77
  78         bcma_awrite32(core, BCMA_RESET_CTL, 0);
  79 +       bcma_aread32(core, BCMA_RESET_CTL);
  80         udelay(1);
  81
  82         bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
  83 diff --git a/drivers/bcma/driver_chipcommon.c b/drivers/bcma/driver_chipcommon.c
  84 index 036c674..b068f98 100644
  85 --- a/drivers/bcma/driver_chipcommon.c
  86 +++ b/drivers/bcma/driver_chipcommon.c
  87 @@ -140,8 +140,15 @@ void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
  88         bcma_core_chipcommon_early_init(cc);
  89
  90         if (cc->core->id.rev >= 20) {
  91 -               bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
  92 -               bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
  93 +               u32 pullup = 0, pulldown = 0;
  94 +
  95 +               if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
  96 +                       pullup = 0x402e0;
  97 +                       pulldown = 0x20500;
  98 +               }
  99 +
 100 +               bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
 101 +               bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
 102         }
 103
 104         if (cc->capabilities & BCMA_CC_CAP_PMU)
 105 diff --git a/drivers/bcma/driver_chipcommon_pmu.c b/drivers/bcma/driver_chipcommon_pmu.c
 106 index edca73a..5081a8c 100644
 107 --- a/drivers/bcma/driver_chipcommon_pmu.c
 108 +++ b/drivers/bcma/driver_chipcommon_pmu.c
 109 @@ -56,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
 110  }
 111  EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
 112
 113 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
 114 +{
 115 +       u32 ilp_ctl, alp_hz;
 116 +
 117 +       if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
 118 +             BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
 119 +               return 0;
 120 +
 121 +       bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
 122 +                       BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
 123 +       usleep_range(1000, 2000);
 124 +
 125 +       ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
 126 +       ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
 127 +
 128 +       bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
 129 +
 130 +       alp_hz = ilp_ctl * 32768 / 4;
 131 +       return (alp_hz + 50000) / 100000 * 100;
 132 +}
 133 +
 134 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
 135 +{
 136 +       struct bcma_bus *bus = cc->core->bus;
 137 +       u32 freq_tgt_target = 0, freq_tgt_current;
 138 +       u32 pll0, mask;
 139 +
 140 +       switch (bus->chipinfo.id) {
 141 +       case BCMA_CHIP_ID_BCM43142:
 142 +               /* pmu2_xtaltab0_adfll_485 */
 143 +               switch (xtalfreq) {
 144 +               case 12000:
 145 +                       freq_tgt_target = 0x50D52;
 146 +                       break;
 147 +               case 20000:
 148 +                       freq_tgt_target = 0x307FE;
 149 +                       break;
 150 +               case 26000:
 151 +                       freq_tgt_target = 0x254EA;
 152 +                       break;
 153 +               case 37400:
 154 +                       freq_tgt_target = 0x19EF8;
 155 +                       break;
 156 +               case 52000:
 157 +                       freq_tgt_target = 0x12A75;
 158 +                       break;
 159 +               }
 160 +               break;
 161 +       }
 162 +
 163 +       if (!freq_tgt_target) {
 164 +               bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
 165 +                        xtalfreq);
 166 +               return;
 167 +       }
 168 +
 169 +       pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
 170 +       freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
 171 +               BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
 172 +
 173 +       if (freq_tgt_current == freq_tgt_target) {
 174 +               bcma_debug(bus, "Target TGT frequency already set\n");
 175 +               return;
 176 +       }
 177 +
 178 +       /* Turn off PLL */
 179 +       switch (bus->chipinfo.id) {
 180 +       case BCMA_CHIP_ID_BCM43142:
 181 +               mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
 182 +                             BCMA_RES_4314_MACPHY_CLK_AVAIL);
 183 +
 184 +               bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
 185 +               bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
 186 +               bcma_wait_value(cc->core, BCMA_CLKCTLST,
 187 +                               BCMA_CLKCTLST_HAVEHT, 0, 20000);
 188 +               break;
 189 +       }
 190 +
 191 +       pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
 192 +       pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
 193 +       bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
 194 +
 195 +       /* Flush */
 196 +       if (cc->pmu.rev >= 2)
 197 +               bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
 198 +
 199 +       /* TODO: Do we need to update OTP? */
 200 +}
 201 +
 202 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
 203 +{
 204 +       struct bcma_bus *bus = cc->core->bus;
 205 +       u32 xtalfreq = bcma_pmu_xtalfreq(cc);
 206 +
 207 +       switch (bus->chipinfo.id) {
 208 +       case BCMA_CHIP_ID_BCM43142:
 209 +               if (xtalfreq == 0)
 210 +                       xtalfreq = 20000;
 211 +               bcma_pmu2_pll_init0(cc, xtalfreq);
 212 +               break;
 213 +       }
 214 +}
 215 +
 216  static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
 217  {
 218         struct bcma_bus *bus = cc->core->bus;
 219 @@ -66,6 +169,25 @@ static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
 220                 min_msk = 0x200D;
 221                 max_msk = 0xFFFF;
 222                 break;
 223 +       case BCMA_CHIP_ID_BCM43142:
 224 +               min_msk = BCMA_RES_4314_LPLDO_PU |
 225 +                         BCMA_RES_4314_PMU_SLEEP_DIS |
 226 +                         BCMA_RES_4314_PMU_BG_PU |
 227 +                         BCMA_RES_4314_CBUCK_LPOM_PU |
 228 +                         BCMA_RES_4314_CBUCK_PFM_PU |
 229 +                         BCMA_RES_4314_CLDO_PU |
 230 +                         BCMA_RES_4314_LPLDO2_LVM |
 231 +                         BCMA_RES_4314_WL_PMU_PU |
 232 +                         BCMA_RES_4314_LDO3P3_PU |
 233 +                         BCMA_RES_4314_OTP_PU |
 234 +                         BCMA_RES_4314_WL_PWRSW_PU |
 235 +                         BCMA_RES_4314_LQ_AVAIL |
 236 +                         BCMA_RES_4314_LOGIC_RET |
 237 +                         BCMA_RES_4314_MEM_SLEEP |
 238 +                         BCMA_RES_4314_MACPHY_RET |
 239 +                         BCMA_RES_4314_WL_CORE_READY;
 240 +               max_msk = 0x3FFFFFFF;
 241 +               break;
 242         default:
 243                 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
 244                            bus->chipinfo.id);
 245 @@ -165,6 +287,7 @@ void bcma_pmu_init(struct bcma_drv_cc *cc)
 246                 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
 247                              BCMA_CC_PMU_CTL_NOILPONW);
 248
 249 +       bcma_pmu_pll_init(cc);
 250         bcma_pmu_resources_init(cc);
 251         bcma_pmu_workarounds(cc);
 252  }
 253 diff --git a/drivers/bcma/driver_chipcommon_sflash.c b/drivers/bcma/driver_chipcommon_sflash.c
 254 index e6ed4fe..4d07cce 100644
 255 --- a/drivers/bcma/driver_chipcommon_sflash.c
 256 +++ b/drivers/bcma/driver_chipcommon_sflash.c
 257 @@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e {
 258         u16 numblocks;
 259  };
 260
 261 -static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
 262 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
 263         { "M25P20", 0x11, 0x10000, 4, },
 264         { "M25P40", 0x12, 0x10000, 8, },
 265
 266 @@ -41,7 +41,7 @@ static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
 267         { 0 },
 268  };
 269
 270 -static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
 271 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
 272         { "SST25WF512", 1, 0x1000, 16, },
 273         { "SST25VF512", 0x48, 0x1000, 16, },
 274         { "SST25WF010", 2, 0x1000, 32, },
 275 @@ -59,7 +59,7 @@ static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
 276         { 0 },
 277  };
 278
 279 -static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
 280 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
 281         { "AT45DB011", 0xc, 256, 512, },
 282         { "AT45DB021", 0x14, 256, 1024, },
 283         { "AT45DB041", 0x1c, 256, 2048, },
 284 @@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc *cc)
 285  {
 286         struct bcma_bus *bus = cc->core->bus;
 287         struct bcma_sflash *sflash = &cc->sflash;
 288 -       struct bcma_sflash_tbl_e *e;
 289 +       const struct bcma_sflash_tbl_e *e;
 290         u32 id, id2;
 291
 292         switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
 293 diff --git a/drivers/bcma/host_pci.c b/drivers/bcma/host_pci.c
 294 index fbf2759..a355e63 100644
 295 --- a/drivers/bcma/host_pci.c
 296 +++ b/drivers/bcma/host_pci.c
 297 @@ -275,6 +275,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
 298         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
 299         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
 300         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
 301 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
 302         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
 303         { 0, },
 304  };
 305 diff --git a/drivers/bcma/main.c b/drivers/bcma/main.c
 306 index f72f52b..0067422 100644
 307 --- a/drivers/bcma/main.c
 308 +++ b/drivers/bcma/main.c
 309 @@ -93,6 +93,25 @@ struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
 310         return NULL;
 311  }
 312
 313 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
 314 +                    int timeout)
 315 +{
 316 +       unsigned long deadline = jiffies + timeout;
 317 +       u32 val;
 318 +
 319 +       do {
 320 +               val = bcma_read32(core, reg);
 321 +               if ((val & mask) == value)
 322 +                       return true;
 323 +               cpu_relax();
 324 +               udelay(10);
 325 +       } while (!time_after_eq(jiffies, deadline));
 326 +
 327 +       bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
 328 +
 329 +       return false;
 330 +}
 331 +
 332  static void bcma_release_core_dev(struct device *dev)
 333  {
 334         struct bcma_device *core = container_of(dev, struct bcma_device, dev);
 335 diff --git a/drivers/bcma/sprom.c b/drivers/bcma/sprom.c
 336 index 8934298..72bf454 100644
 337 --- a/drivers/bcma/sprom.c
 338 +++ b/drivers/bcma/sprom.c
 339 @@ -72,12 +72,12 @@ fail:
 340   * R/W ops.
 341   **************************************************/
 342
 343 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
 344 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
 345 +                           size_t words)
 346  {
 347         int i;
 348 -       for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
 349 -               sprom[i] = bcma_read16(bus->drv_cc.core,
 350 -                                      offset + (i * 2));
 351 +       for (i = 0; i < words; i++)
 352 +               sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
 353  }
 354
 355  /**************************************************
 356 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 data)
 357         return t[crc ^ data];
 358  }
 359
 360 -static u8 bcma_sprom_crc(const u16 *sprom)
 361 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
 362  {
 363         int word;
 364         u8 crc = 0xFF;
 365
 366 -       for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
 367 +       for (word = 0; word < words - 1; word++) {
 368                 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
 369                 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
 370         }
 371 -       crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
 372 +       crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
 373         crc ^= 0xFF;
 374
 375         return crc;
 376  }
 377
 378 -static int bcma_sprom_check_crc(const u16 *sprom)
 379 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
 380  {
 381         u8 crc;
 382         u8 expected_crc;
 383         u16 tmp;
 384
 385 -       crc = bcma_sprom_crc(sprom);
 386 -       tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
 387 +       crc = bcma_sprom_crc(sprom, words);
 388 +       tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
 389         expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
 390         if (crc != expected_crc)
 391                 return -EPROTO;
 392 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u16 *sprom)
 393         return 0;
 394  }
 395
 396 -static int bcma_sprom_valid(const u16 *sprom)
 397 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
 398 +                           size_t words)
 399  {
 400         u16 revision;
 401         int err;
 402
 403 -       err = bcma_sprom_check_crc(sprom);
 404 +       err = bcma_sprom_check_crc(sprom, words);
 405         if (err)
 406                 return err;
 407
 408 -       revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
 409 -       if (revision != 8 && revision != 9) {
 410 +       revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
 411 +       if (revision != 8 && revision != 9 && revision != 10) {
 412                 pr_err("Unsupported SPROM revision: %d\n", revision);
 413                 return -ENOENT;
 414         }
 415
 416 +       bus->sprom.revision = revision;
 417 +       bcma_debug(bus, "Found SPROM revision %d\n", revision);
 418 +
 419         return 0;
 420  }
 421
 422 @@ -208,9 +212,6 @@ static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
 423         BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
 424                         ARRAY_SIZE(bus->sprom.core_pwr_info));
 425
 426 -       bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
 427 -               SSB_SPROM_REVISION_REV;
 428 -
 429         for (i = 0; i < 3; i++) {
 430                 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
 431                 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
 432 @@ -502,7 +503,7 @@ static bool bcma_sprom_onchip_available(struct bcma_bus *bus)
 433         case BCMA_CHIP_ID_BCM4331:
 434                 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
 435                 break;
 436 -
 437 +       case BCMA_CHIP_ID_BCM43142:
 438         case BCMA_CHIP_ID_BCM43224:
 439         case BCMA_CHIP_ID_BCM43225:
 440                 /* for these chips OTP is always available */
 441 @@ -550,7 +551,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
 442  {
 443         u16 offset = BCMA_CC_SPROM;
 444         u16 *sprom;
 445 -       int err = 0;
 446 +       size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
 447 +                                SSB_SPROMSIZE_WORDS_R10, };
 448 +       int i, err = 0;
 449
 450         if (!bus->drv_cc.core)
 451                 return -EOPNOTSUPP;
 452 @@ -579,32 +582,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
 453                 }
 454         }
 455
 456 -       sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
 457 -                       GFP_KERNEL);
 458 -       if (!sprom)
 459 -               return -ENOMEM;
 460 -
 461         if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
 462             bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
 463                 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
 464
 465         bcma_debug(bus, "SPROM offset 0x%x\n", offset);
 466 -       bcma_sprom_read(bus, offset, sprom);
 467 +       for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
 468 +               size_t words = sprom_sizes[i];
 469 +
 470 +               sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
 471 +               if (!sprom)
 472 +                       return -ENOMEM;
 473 +
 474 +               bcma_sprom_read(bus, offset, sprom, words);
 475 +               err = bcma_sprom_valid(bus, sprom, words);
 476 +               if (!err)
 477 +                       break;
 478 +
 479 +               kfree(sprom);
 480 +       }
 481
 482         if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
 483             bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
 484                 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
 485
 486 -       err = bcma_sprom_valid(sprom);
 487         if (err) {
 488 -               bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
 489 +               bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
 490                 err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
 491 -               goto out;
 492 +       } else {
 493 +               bcma_sprom_extract_r8(bus, sprom);
 494 +               kfree(sprom);
 495         }
 496
 497 -       bcma_sprom_extract_r8(bus, sprom);
 498 -
 499 -out:
 500 -       kfree(sprom);
 501         return err;
 502  }
 503 diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h
 504 index 2e34db8..622fc50 100644
 505 --- a/include/linux/bcma/bcma.h
 506 +++ b/include/linux/bcma/bcma.h
 507 @@ -144,6 +144,7 @@ struct bcma_host_ops {
 508
 509  /* Chip IDs of PCIe devices */
 510  #define BCMA_CHIP_ID_BCM4313   0x4313
 511 +#define BCMA_CHIP_ID_BCM43142  43142
 512  #define BCMA_CHIP_ID_BCM43224  43224
 513  #define  BCMA_PKG_ID_BCM43224_FAB_CSM  0x8
 514  #define  BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
 515 diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h
 516 index b8b09ea..c49e1a1 100644
 517 --- a/include/linux/bcma/bcma_driver_chipcommon.h
 518 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
 519 @@ -330,6 +330,8 @@
 520  #define BCMA_CC_PMU_CAP                        0x0604 /* PMU capabilities */
 521  #define  BCMA_CC_PMU_CAP_REVISION      0x000000FF /* Revision mask */
 522  #define BCMA_CC_PMU_STAT               0x0608 /* PMU status */
 523 +#define  BCMA_CC_PMU_STAT_EXT_LPO_AVAIL        0x00000100
 524 +#define  BCMA_CC_PMU_STAT_WDRESET      0x00000080
 525  #define  BCMA_CC_PMU_STAT_INTPEND      0x00000040 /* Interrupt pending */
 526  #define  BCMA_CC_PMU_STAT_SBCLKST      0x00000030 /* Backplane clock status? */
 527  #define  BCMA_CC_PMU_STAT_HAVEALP      0x00000008 /* ALP available */
 528 @@ -355,6 +357,11 @@
 529  #define BCMA_CC_REGCTL_DATA            0x065C
 530  #define BCMA_CC_PLLCTL_ADDR            0x0660
 531  #define BCMA_CC_PLLCTL_DATA            0x0664
 532 +#define BCMA_CC_PMU_STRAPOPT           0x0668 /* (corerev >= 28) */
 533 +#define BCMA_CC_PMU_XTAL_FREQ          0x066C /* (pmurev >= 10) */
 534 +#define  BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK     0x00001FFF
 535 +#define  BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK    0x80000000
 536 +#define  BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT   31
 537  #define BCMA_CC_SPROM                  0x0800 /* SPROM beginning */
 538  /* NAND flash MLC controller registers (corerev >= 38) */
 539  #define BCMA_CC_NAND_REVISION          0x0C00
 540 @@ -435,6 +442,23 @@
 541  #define  BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
 542  #define  BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT        0
 543
 544 +/* PMU rev 15 */
 545 +#define BCMA_CC_PMU15_PLL_PLLCTL0      0
 546 +#define  BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK     0x00000003
 547 +#define  BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT    0
 548 +#define  BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK    0x003FFFFC
 549 +#define  BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT   2
 550 +#define  BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK   0x00C00000
 551 +#define  BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT  22
 552 +#define  BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK     0x07000000
 553 +#define  BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT    24
 554 +#define  BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK   0x38000000
 555 +#define  BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT  27
 556 +#define  BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK    0x40000000
 557 +#define  BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT   30
 558 +#define  BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK   0x80000000
 559 +#define  BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT  31
 560 +
 561  /* ALP clock on pre-PMU chips */
 562  #define BCMA_CC_PMU_ALP_CLOCK          20000000
 563  /* HT clock for systems with PMU-enabled chipcommon */
 564 @@ -507,6 +531,37 @@
 565  #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE      BIT(18)
 566  #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE   BIT(19)
 567
 568 +#define BCMA_RES_4314_LPLDO_PU                 BIT(0)
 569 +#define BCMA_RES_4314_PMU_SLEEP_DIS            BIT(1)
 570 +#define BCMA_RES_4314_PMU_BG_PU                        BIT(2)
 571 +#define BCMA_RES_4314_CBUCK_LPOM_PU            BIT(3)
 572 +#define BCMA_RES_4314_CBUCK_PFM_PU             BIT(4)
 573 +#define BCMA_RES_4314_CLDO_PU                  BIT(5)
 574 +#define BCMA_RES_4314_LPLDO2_LVM               BIT(6)
 575 +#define BCMA_RES_4314_WL_PMU_PU                        BIT(7)
 576 +#define BCMA_RES_4314_LNLDO_PU                 BIT(8)
 577 +#define BCMA_RES_4314_LDO3P3_PU                        BIT(9)
 578 +#define BCMA_RES_4314_OTP_PU                   BIT(10)
 579 +#define BCMA_RES_4314_XTAL_PU                  BIT(11)
 580 +#define BCMA_RES_4314_WL_PWRSW_PU              BIT(12)
 581 +#define BCMA_RES_4314_LQ_AVAIL                 BIT(13)
 582 +#define BCMA_RES_4314_LOGIC_RET                        BIT(14)
 583 +#define BCMA_RES_4314_MEM_SLEEP                        BIT(15)
 584 +#define BCMA_RES_4314_MACPHY_RET               BIT(16)
 585 +#define BCMA_RES_4314_WL_CORE_READY            BIT(17)
 586 +#define BCMA_RES_4314_ILP_REQ                  BIT(18)
 587 +#define BCMA_RES_4314_ALP_AVAIL                        BIT(19)
 588 +#define BCMA_RES_4314_MISC_PWRSW_PU            BIT(20)
 589 +#define BCMA_RES_4314_SYNTH_PWRSW_PU           BIT(21)
 590 +#define BCMA_RES_4314_RX_PWRSW_PU              BIT(22)
 591 +#define BCMA_RES_4314_RADIO_PU                 BIT(23)
 592 +#define BCMA_RES_4314_VCO_LDO_PU               BIT(24)
 593 +#define BCMA_RES_4314_AFE_LDO_PU               BIT(25)
 594 +#define BCMA_RES_4314_RX_LDO_PU                        BIT(26)
 595 +#define BCMA_RES_4314_TX_LDO_PU                        BIT(27)
 596 +#define BCMA_RES_4314_HT_AVAIL                 BIT(28)
 597 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL         BIT(29)
 598 +
 599  /* Data for the PMU, if available.
 600   * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
 601   */