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301a97c55832c72ad4d0d896249dbd7174d0aafb
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.13 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -75,6 +75,7 @@ config BCMA_DRIVER_GMAC_CMN
4 config BCMA_DRIVER_GPIO
5 bool "BCMA GPIO driver"
6 depends on BCMA && GPIOLIB
7 + select IRQ_DOMAIN if BCMA_HOST_SOC
8 help
9 Driver to provide access to the GPIO pins of the bcma bus.
10
11 --- a/drivers/bcma/Makefile
12 +++ b/drivers/bcma/Makefile
13 @@ -3,6 +3,7 @@ bcma-y += driver_chipcommon.o driver
14 bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
15 bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
16 bcma-y += driver_pci.o
17 +bcma-y += driver_pcie2.o
18 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
19 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
20 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
21 --- a/drivers/bcma/bcma_private.h
22 +++ b/drivers/bcma/bcma_private.h
23 @@ -33,8 +33,6 @@ int __init bcma_bus_early_register(struc
24 int bcma_bus_suspend(struct bcma_bus *bus);
25 int bcma_bus_resume(struct bcma_bus *bus);
26 #endif
27 -struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
28 - u8 unit);
29
30 /* scan.c */
31 int bcma_bus_scan(struct bcma_bus *bus);
32 --- a/drivers/bcma/driver_chipcommon_pmu.c
33 +++ b/drivers/bcma/driver_chipcommon_pmu.c
34 @@ -603,6 +603,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
35 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
36 break;
37
38 + case BCMA_CHIP_ID_BCM43217:
39 case BCMA_CHIP_ID_BCM43227:
40 case BCMA_CHIP_ID_BCM43228:
41 case BCMA_CHIP_ID_BCM43428:
42 --- a/drivers/bcma/driver_chipcommon_sflash.c
43 +++ b/drivers/bcma/driver_chipcommon_sflash.c
44 @@ -38,7 +38,7 @@ static const struct bcma_sflash_tbl_e bc
45 { "M25P32", 0x15, 0x10000, 64, },
46 { "M25P64", 0x16, 0x10000, 128, },
47 { "M25FL128", 0x17, 0x10000, 256, },
48 - { 0 },
49 + { NULL },
50 };
51
52 static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
53 @@ -56,7 +56,7 @@ static const struct bcma_sflash_tbl_e bc
54 { "SST25VF016", 0x41, 0x1000, 512, },
55 { "SST25VF032", 0x4a, 0x1000, 1024, },
56 { "SST25VF064", 0x4b, 0x1000, 2048, },
57 - { 0 },
58 + { NULL },
59 };
60
61 static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
62 @@ -67,7 +67,7 @@ static const struct bcma_sflash_tbl_e bc
63 { "AT45DB161", 0x2c, 512, 4096, },
64 { "AT45DB321", 0x34, 512, 8192, },
65 { "AT45DB642", 0x3c, 1024, 8192, },
66 - { 0 },
67 + { NULL },
68 };
69
70 static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
71 --- a/drivers/bcma/driver_gpio.c
72 +++ b/drivers/bcma/driver_gpio.c
73 @@ -9,6 +9,9 @@
74 */
75
76 #include <linux/gpio.h>
77 +#include <linux/irq.h>
78 +#include <linux/interrupt.h>
79 +#include <linux/irqdomain.h>
80 #include <linux/export.h>
81 #include <linux/bcma/bcma.h>
82
83 @@ -73,19 +76,136 @@ static void bcma_gpio_free(struct gpio_c
84 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
85 }
86
87 +#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
88 static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
89 {
90 struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
91
92 if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
93 - return bcma_core_irq(cc->core);
94 + return irq_find_mapping(cc->irq_domain, gpio);
95 else
96 return -EINVAL;
97 }
98
99 +static void bcma_gpio_irq_unmask(struct irq_data *d)
100 +{
101 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
102 + int gpio = irqd_to_hwirq(d);
103 + u32 val = bcma_chipco_gpio_in(cc, BIT(gpio));
104 +
105 + bcma_chipco_gpio_polarity(cc, BIT(gpio), val);
106 + bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio));
107 +}
108 +
109 +static void bcma_gpio_irq_mask(struct irq_data *d)
110 +{
111 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
112 + int gpio = irqd_to_hwirq(d);
113 +
114 + bcma_chipco_gpio_intmask(cc, BIT(gpio), 0);
115 +}
116 +
117 +static struct irq_chip bcma_gpio_irq_chip = {
118 + .name = "BCMA-GPIO",
119 + .irq_mask = bcma_gpio_irq_mask,
120 + .irq_unmask = bcma_gpio_irq_unmask,
121 +};
122 +
123 +static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id)
124 +{
125 + struct bcma_drv_cc *cc = dev_id;
126 + u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN);
127 + u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ);
128 + u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL);
129 + unsigned long irqs = (val ^ pol) & mask;
130 + int gpio;
131 +
132 + if (!irqs)
133 + return IRQ_NONE;
134 +
135 + for_each_set_bit(gpio, &irqs, cc->gpio.ngpio)
136 + generic_handle_irq(bcma_gpio_to_irq(&cc->gpio, gpio));
137 + bcma_chipco_gpio_polarity(cc, irqs, val & irqs);
138 +
139 + return IRQ_HANDLED;
140 +}
141 +
142 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
143 +{
144 + struct gpio_chip *chip = &cc->gpio;
145 + int gpio, hwirq, err;
146 +
147 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
148 + return 0;
149 +
150 + cc->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
151 + &irq_domain_simple_ops, cc);
152 + if (!cc->irq_domain) {
153 + err = -ENODEV;
154 + goto err_irq_domain;
155 + }
156 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
157 + int irq = irq_create_mapping(cc->irq_domain, gpio);
158 +
159 + irq_set_chip_data(irq, cc);
160 + irq_set_chip_and_handler(irq, &bcma_gpio_irq_chip,
161 + handle_simple_irq);
162 + }
163 +
164 + hwirq = bcma_core_irq(cc->core);
165 + err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
166 + cc);
167 + if (err)
168 + goto err_req_irq;
169 +
170 + bcma_chipco_gpio_intmask(cc, ~0, 0);
171 + bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);
172 +
173 + return 0;
174 +
175 +err_req_irq:
176 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
177 + int irq = irq_find_mapping(cc->irq_domain, gpio);
178 +
179 + irq_dispose_mapping(irq);
180 + }
181 + irq_domain_remove(cc->irq_domain);
182 +err_irq_domain:
183 + return err;
184 +}
185 +
186 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
187 +{
188 + struct gpio_chip *chip = &cc->gpio;
189 + int gpio;
190 +
191 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
192 + return;
193 +
194 + bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
195 + free_irq(bcma_core_irq(cc->core), cc);
196 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
197 + int irq = irq_find_mapping(cc->irq_domain, gpio);
198 +
199 + irq_dispose_mapping(irq);
200 + }
201 + irq_domain_remove(cc->irq_domain);
202 +}
203 +#else
204 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
205 +{
206 + return 0;
207 +}
208 +
209 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
210 +{
211 +}
212 +#endif
213 +
214 int bcma_gpio_init(struct bcma_drv_cc *cc)
215 {
216 struct gpio_chip *chip = &cc->gpio;
217 + int err;
218
219 chip->label = "bcma_gpio";
220 chip->owner = THIS_MODULE;
221 @@ -95,8 +215,18 @@ int bcma_gpio_init(struct bcma_drv_cc *c
222 chip->set = bcma_gpio_set_value;
223 chip->direction_input = bcma_gpio_direction_input;
224 chip->direction_output = bcma_gpio_direction_output;
225 +#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
226 chip->to_irq = bcma_gpio_to_irq;
227 - chip->ngpio = 16;
228 +#endif
229 + switch (cc->core->bus->chipinfo.id) {
230 + case BCMA_CHIP_ID_BCM5357:
231 + case BCMA_CHIP_ID_BCM53572:
232 + chip->ngpio = 32;
233 + break;
234 + default:
235 + chip->ngpio = 16;
236 + }
237 +
238 /* There is just one SoC in one device and its GPIO addresses should be
239 * deterministic to address them more easily. The other buses could get
240 * a random base number. */
241 @@ -105,10 +235,21 @@ int bcma_gpio_init(struct bcma_drv_cc *c
242 else
243 chip->base = -1;
244
245 - return gpiochip_add(chip);
246 + err = bcma_gpio_irq_domain_init(cc);
247 + if (err)
248 + return err;
249 +
250 + err = gpiochip_add(chip);
251 + if (err) {
252 + bcma_gpio_irq_domain_exit(cc);
253 + return err;
254 + }
255 +
256 + return 0;
257 }
258
259 int bcma_gpio_unregister(struct bcma_drv_cc *cc)
260 {
261 + bcma_gpio_irq_domain_exit(cc);
262 return gpiochip_remove(&cc->gpio);
263 }
264 --- /dev/null
265 +++ b/drivers/bcma/driver_pcie2.c
266 @@ -0,0 +1,175 @@
267 +/*
268 + * Broadcom specific AMBA
269 + * PCIe Gen 2 Core
270 + *
271 + * Copyright 2014, Broadcom Corporation
272 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
273 + *
274 + * Licensed under the GNU/GPL. See COPYING for details.
275 + */
276 +
277 +#include "bcma_private.h"
278 +#include <linux/bcma/bcma.h>
279 +
280 +/**************************************************
281 + * R/W ops.
282 + **************************************************/
283 +
284 +#if 0
285 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
286 +{
287 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
288 + pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
289 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
290 +}
291 +#endif
292 +
293 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
294 + u32 val)
295 +{
296 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
297 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
298 +}
299 +
300 +/**************************************************
301 + * Init.
302 + **************************************************/
303 +
304 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
305 + bool enable)
306 +{
307 + u32 val;
308 +
309 + /* restore back to default */
310 + val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
311 + val |= PCIE2_CLKC_DLYPERST;
312 + val &= ~PCIE2_CLKC_DISSPROMLD;
313 + if (enable) {
314 + val &= ~PCIE2_CLKC_DLYPERST;
315 + val |= PCIE2_CLKC_DISSPROMLD;
316 + }
317 + pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
318 + /* flush */
319 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
320 +}
321 +
322 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
323 +{
324 + /* LTR0 */
325 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
326 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
327 + /* LTR1 */
328 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
329 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
330 + /* LTR2 */
331 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
332 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
333 +}
334 +
335 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
336 +{
337 + u8 core_rev = pcie2->core->id.rev;
338 + u32 devstsctr2;
339 +
340 + if (core_rev < 2 || core_rev == 10 || core_rev > 13)
341 + return;
342 +
343 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
344 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
345 + devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
346 + if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
347 + /* force the right LTR values */
348 + bcma_core_pcie2_set_ltr_vals(pcie2);
349 +
350 + /* TODO:
351 + si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
352 +
353 + /* enable the LTR */
354 + devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
355 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
356 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
357 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
358 +
359 + /* set the LTR state to be active */
360 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
361 + PCIE2_LTR_ACTIVE);
362 + usleep_range(1000, 2000);
363 +
364 + /* set the LTR state to be sleep */
365 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
366 + PCIE2_LTR_SLEEP);
367 + usleep_range(1000, 2000);
368 + }
369 +}
370 +
371 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
372 +{
373 + u8 core_rev = pcie2->core->id.rev;
374 + bool pciewar160, pciewar162;
375 +
376 + pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
377 + pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
378 + core_rev == 9 || core_rev == 11;
379 +
380 + if (!pciewar160 && !pciewar162)
381 + return;
382 +
383 +/* TODO */
384 +#if 0
385 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
386 + PCIE_DISABLE_L1CLK_GATING);
387 +#if 0
388 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
389 + PCIEGEN2_COE_PVT_TL_CTRL_0);
390 + pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
391 + ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
392 +#endif
393 +#endif
394 +}
395 +
396 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
397 +{
398 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
399 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
400 +}
401 +
402 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
403 +{
404 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
405 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
406 +}
407 +
408 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
409 +{
410 + struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
411 + u8 core_rev = pcie2->core->id.rev;
412 + u32 alp_khz, pm_value;
413 +
414 + if (core_rev <= 13) {
415 + alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
416 + pm_value = (1000000 * 2) / alp_khz;
417 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
418 + PCIE2_PVT_REG_PM_CLK_PERIOD);
419 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
420 + }
421 +}
422 +
423 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
424 +{
425 + struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
426 + u32 tmp;
427 +
428 + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
429 + if ((tmp & 0xe) >> 1 == 2)
430 + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
431 +
432 + /* TODO: Do we need pcie_reqsize? */
433 +
434 + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
435 + bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
436 + bcma_core_pcie2_hw_ltr_war(pcie2);
437 + pciedev_crwlpciegen2(pcie2);
438 + pciedev_reg_pm_clk_period(pcie2);
439 + pciedev_crwlpciegen2_180(pcie2);
440 + pciedev_crwlpciegen2_182(pcie2);
441 +}
442 --- a/drivers/bcma/host_pci.c
443 +++ b/drivers/bcma/host_pci.c
444 @@ -238,7 +238,6 @@ static void bcma_host_pci_remove(struct
445 pci_release_regions(dev);
446 pci_disable_device(dev);
447 kfree(bus);
448 - pci_set_drvdata(dev, NULL);
449 }
450
451 #ifdef CONFIG_PM_SLEEP
452 @@ -270,7 +269,7 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
453
454 #endif /* CONFIG_PM_SLEEP */
455
456 -static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
457 +static const struct pci_device_id bcma_pci_bridge_tbl[] = {
458 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
459 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
460 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
461 @@ -280,6 +279,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
462 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
463 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
464 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
465 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
466 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
467 { 0, },
468 };
469 --- a/drivers/bcma/main.c
470 +++ b/drivers/bcma/main.c
471 @@ -78,18 +78,6 @@ static u16 bcma_cc_core_id(struct bcma_b
472 return BCMA_CORE_CHIPCOMMON;
473 }
474
475 -struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
476 -{
477 - struct bcma_device *core;
478 -
479 - list_for_each_entry(core, &bus->cores, list) {
480 - if (core->id.id == coreid)
481 - return core;
482 - }
483 - return NULL;
484 -}
485 -EXPORT_SYMBOL_GPL(bcma_find_core);
486 -
487 struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
488 u8 unit)
489 {
490 @@ -101,6 +89,7 @@ struct bcma_device *bcma_find_core_unit(
491 }
492 return NULL;
493 }
494 +EXPORT_SYMBOL_GPL(bcma_find_core_unit);
495
496 bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
497 int timeout)
498 @@ -143,6 +132,7 @@ static int bcma_register_cores(struct bc
499 case BCMA_CORE_CHIPCOMMON:
500 case BCMA_CORE_PCI:
501 case BCMA_CORE_PCIE:
502 + case BCMA_CORE_PCIE2:
503 case BCMA_CORE_MIPS_74K:
504 case BCMA_CORE_4706_MAC_GBIT_COMMON:
505 continue;
506 @@ -176,6 +166,7 @@ static int bcma_register_cores(struct bc
507 bcma_err(bus,
508 "Could not register dev for core 0x%03X\n",
509 core->id.id);
510 + put_device(&core->dev);
511 continue;
512 }
513 core->dev_registered = true;
514 @@ -291,6 +282,13 @@ int bcma_bus_register(struct bcma_bus *b
515 bcma_core_pci_init(&bus->drv_pci[1]);
516 }
517
518 + /* Init PCIe Gen 2 core */
519 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
520 + if (core) {
521 + bus->drv_pcie2.core = core;
522 + bcma_core_pcie2_init(&bus->drv_pcie2);
523 + }
524 +
525 /* Init GBIT MAC COMMON core */
526 core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
527 if (core) {
528 --- a/drivers/bcma/sprom.c
529 +++ b/drivers/bcma/sprom.c
530 @@ -201,6 +201,23 @@ static int bcma_sprom_valid(struct bcma_
531 SPEX(_field[7], _offset + 14, _mask, _shift); \
532 } while (0)
533
534 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
535 +{
536 + u16 v;
537 + u8 gain;
538 +
539 + v = in[SPOFF(offset)];
540 + gain = (v & mask) >> shift;
541 + if (gain == 0xFF) {
542 + gain = 8; /* If unset use 2dBm */
543 + } else {
544 + /* Q5.2 Fractional part is stored in 0xC0 */
545 + gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
546 + }
547 +
548 + return (s8)gain;
549 +}
550 +
551 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
552 {
553 u16 v, o;
554 @@ -381,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
555 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
556
557 /* Extract the antenna gain values. */
558 - SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
559 - SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
560 - SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
561 - SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
562 - SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
563 - SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
564 - SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
565 - SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
566 + bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
567 + SSB_SPROM8_AGAIN01,
568 + SSB_SPROM8_AGAIN0,
569 + SSB_SPROM8_AGAIN0_SHIFT);
570 + bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
571 + SSB_SPROM8_AGAIN01,
572 + SSB_SPROM8_AGAIN1,
573 + SSB_SPROM8_AGAIN1_SHIFT);
574 + bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
575 + SSB_SPROM8_AGAIN23,
576 + SSB_SPROM8_AGAIN2,
577 + SSB_SPROM8_AGAIN2_SHIFT);
578 + bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
579 + SSB_SPROM8_AGAIN23,
580 + SSB_SPROM8_AGAIN3,
581 + SSB_SPROM8_AGAIN3_SHIFT);
582
583 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
584 SSB_SPROM8_LEDDC_ON_SHIFT);
585 @@ -509,6 +534,7 @@ static bool bcma_sprom_onchip_available(
586 /* for these chips OTP is always available */
587 present = true;
588 break;
589 + case BCMA_CHIP_ID_BCM43217:
590 case BCMA_CHIP_ID_BCM43227:
591 case BCMA_CHIP_ID_BCM43228:
592 case BCMA_CHIP_ID_BCM43428:
593 --- a/include/linux/bcma/bcma.h
594 +++ b/include/linux/bcma/bcma.h
595 @@ -6,6 +6,7 @@
596
597 #include <linux/bcma/bcma_driver_chipcommon.h>
598 #include <linux/bcma/bcma_driver_pci.h>
599 +#include <linux/bcma/bcma_driver_pcie2.h>
600 #include <linux/bcma/bcma_driver_mips.h>
601 #include <linux/bcma/bcma_driver_gmac_cmn.h>
602 #include <linux/ssb/ssb.h> /* SPROM sharing */
603 @@ -157,6 +158,8 @@ struct bcma_host_ops {
604 /* Chip IDs of PCIe devices */
605 #define BCMA_CHIP_ID_BCM4313 0x4313
606 #define BCMA_CHIP_ID_BCM43142 43142
607 +#define BCMA_CHIP_ID_BCM43217 43217
608 +#define BCMA_CHIP_ID_BCM43222 43222
609 #define BCMA_CHIP_ID_BCM43224 43224
610 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
611 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
612 @@ -333,6 +336,7 @@ struct bcma_bus {
613
614 struct bcma_drv_cc drv_cc;
615 struct bcma_drv_pci drv_pci[2];
616 + struct bcma_drv_pcie2 drv_pcie2;
617 struct bcma_drv_mips drv_mips;
618 struct bcma_drv_gmac_cmn drv_gmac_cmn;
619
620 @@ -418,7 +422,14 @@ static inline void bcma_maskset16(struct
621 bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
622 }
623
624 -extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
625 +extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
626 + u8 unit);
627 +static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus,
628 + u16 coreid)
629 +{
630 + return bcma_find_core_unit(bus, coreid, 0);
631 +}
632 +
633 extern bool bcma_core_is_enabled(struct bcma_device *core);
634 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
635 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
636 --- a/include/linux/bcma/bcma_driver_chipcommon.h
637 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
638 @@ -640,6 +640,7 @@ struct bcma_drv_cc {
639 spinlock_t gpio_lock;
640 #ifdef CONFIG_BCMA_DRIVER_GPIO
641 struct gpio_chip gpio;
642 + struct irq_domain *irq_domain;
643 #endif
644 };
645
646 --- /dev/null
647 +++ b/include/linux/bcma/bcma_driver_pcie2.h
648 @@ -0,0 +1,158 @@
649 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
650 +#define LINUX_BCMA_DRIVER_PCIE2_H_
651 +
652 +#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
653 +#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
654 +#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
655 +#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
656 +#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
657 +#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
658 +#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
659 +#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
660 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
661 +#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
662 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
663 +#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
664 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
665 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
666 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
667 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
668 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
669 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
670 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
671 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
672 +#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
673 +#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
674 +#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
675 +#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
676 +#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
677 +#define BCMA_CORE_PCIE2_DATAINTF 0x0180
678 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
679 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
680 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
681 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
682 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
683 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
684 +#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
685 +#define PCIE2_LTR_ACTIVE 2
686 +#define PCIE2_LTR_ACTIVE_IDLE 1
687 +#define PCIE2_LTR_SLEEP 0
688 +#define PCIE2_LTR_FINAL_MASK 0x300
689 +#define PCIE2_LTR_FINAL_SHIFT 8
690 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
691 +#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
692 +#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
693 +#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
694 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
695 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
696 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
697 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
698 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
699 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
700 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
701 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
702 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
703 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
704 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
705 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
706 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
707 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
708 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
709 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
710 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
711 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
712 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
713 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
714 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
715 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
716 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
717 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
718 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
719 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
720 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
721 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
722 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
723 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
724 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
725 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
726 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
727 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
728 +#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
729 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
730 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
731 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
732 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
733 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
734 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
735 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
736 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
737 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
738 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
739 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
740 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
741 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
742 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
743 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
744 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
745 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
746 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
747 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
748 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
749 +#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
750 +#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
751 +#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
752 +#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
753 +#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
754 +#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
755 +#define BCMA_CORE_PCIE2_OARR0 0x0D20
756 +#define BCMA_CORE_PCIE2_OARR1 0x0D28
757 +#define BCMA_CORE_PCIE2_OARR2 0x0D30
758 +#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
759 +#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
760 +#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
761 +#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
762 +#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
763 +#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
764 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
765 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
766 +#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
767 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
768 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
769 +#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
770 +#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
771 +#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
772 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
773 +#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
774 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
775 +#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
776 +#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
777 +#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
778 +#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
779 +#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
780 +
781 +/* PCIE gen2 config regs */
782 +#define PCIE2_INTSTATUS 0x090
783 +#define PCIE2_INTMASK 0x094
784 +#define PCIE2_SBMBX 0x098
785 +
786 +#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
787 +
788 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
789 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
790 +#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
791 +
792 +struct bcma_drv_pcie2 {
793 + struct bcma_device *core;
794 +};
795 +
796 +#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
797 +#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
798 +#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
799 +#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
800 +
801 +#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
802 +#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
803 +
804 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
805 +
806 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
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