target/linux/generic/patches-3.14/025-bcma_backport.patch

   1 --- a/drivers/bcma/Makefile
   2 +++ b/drivers/bcma/Makefile
   3 @@ -3,6 +3,7 @@ bcma-y                                  += driver_chipcommon.o driver
   4  bcma-$(CONFIG_BCMA_SFLASH)             += driver_chipcommon_sflash.o
   5  bcma-$(CONFIG_BCMA_NFLASH)             += driver_chipcommon_nflash.o
   6  bcma-y                                 += driver_pci.o
   7 +bcma-y                                 += driver_pcie2.o
   8  bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE)        += driver_pci_host.o
   9  bcma-$(CONFIG_BCMA_DRIVER_MIPS)                += driver_mips.o
  10  bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN)    += driver_gmac_cmn.o
  11 --- a/drivers/bcma/driver_chipcommon_pmu.c
  12 +++ b/drivers/bcma/driver_chipcommon_pmu.c
  13 @@ -603,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct
  14                 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
  15                 break;
  16
  17 +       case BCMA_CHIP_ID_BCM43131:
  18 +       case BCMA_CHIP_ID_BCM43217:
  19         case BCMA_CHIP_ID_BCM43227:
  20         case BCMA_CHIP_ID_BCM43228:
  21         case BCMA_CHIP_ID_BCM43428:
  22 --- a/drivers/bcma/driver_gpio.c
  23 +++ b/drivers/bcma/driver_gpio.c
  24 @@ -218,7 +218,15 @@ int bcma_gpio_init(struct bcma_drv_cc *c
  25  #if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
  26         chip->to_irq            = bcma_gpio_to_irq;
  27  #endif
  28 -       chip->ngpio             = 16;
  29 +       switch (cc->core->bus->chipinfo.id) {
  30 +       case BCMA_CHIP_ID_BCM5357:
  31 +       case BCMA_CHIP_ID_BCM53572:
  32 +               chip->ngpio     = 32;
  33 +               break;
  34 +       default:
  35 +               chip->ngpio     = 16;
  36 +       }
  37 +
  38         /* There is just one SoC in one device and its GPIO addresses should be
  39          * deterministic to address them more easily. The other buses could get
  40          * a random base number. */
  41 --- /dev/null
  42 +++ b/drivers/bcma/driver_pcie2.c
  43 @@ -0,0 +1,175 @@
  44 +/*
  45 + * Broadcom specific AMBA
  46 + * PCIe Gen 2 Core
  47 + *
  48 + * Copyright 2014, Broadcom Corporation
  49 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
  50 + *
  51 + * Licensed under the GNU/GPL. See COPYING for details.
  52 + */
  53 +
  54 +#include "bcma_private.h"
  55 +#include <linux/bcma/bcma.h>
  56 +
  57 +/**************************************************
  58 + * R/W ops.
  59 + **************************************************/
  60 +
  61 +#if 0
  62 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
  63 +{
  64 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
  65 +       pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
  66 +       return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
  67 +}
  68 +#endif
  69 +
  70 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
  71 +                                     u32 val)
  72 +{
  73 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
  74 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
  75 +}
  76 +
  77 +/**************************************************
  78 + * Init.
  79 + **************************************************/
  80 +
  81 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
  82 +                                               bool enable)
  83 +{
  84 +       u32 val;
  85 +
  86 +       /* restore back to default */
  87 +       val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
  88 +       val |= PCIE2_CLKC_DLYPERST;
  89 +       val &= ~PCIE2_CLKC_DISSPROMLD;
  90 +       if (enable) {
  91 +               val &= ~PCIE2_CLKC_DLYPERST;
  92 +               val |= PCIE2_CLKC_DISSPROMLD;
  93 +       }
  94 +       pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
  95 +       /* flush */
  96 +       return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
  97 +}
  98 +
  99 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
 100 +{
 101 +       /* LTR0 */
 102 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
 103 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
 104 +       /* LTR1 */
 105 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
 106 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
 107 +       /* LTR2 */
 108 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
 109 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
 110 +}
 111 +
 112 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
 113 +{
 114 +       u8 core_rev = pcie2->core->id.rev;
 115 +       u32 devstsctr2;
 116 +
 117 +       if (core_rev < 2 || core_rev == 10 || core_rev > 13)
 118 +               return;
 119 +
 120 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
 121 +                     PCIE2_CAP_DEVSTSCTRL2_OFFSET);
 122 +       devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
 123 +       if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
 124 +               /* force the right LTR values */
 125 +               bcma_core_pcie2_set_ltr_vals(pcie2);
 126 +
 127 +               /* TODO:
 128 +               si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
 129 +
 130 +               /* enable the LTR */
 131 +               devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
 132 +               pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
 133 +                             PCIE2_CAP_DEVSTSCTRL2_OFFSET);
 134 +               pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
 135 +
 136 +               /* set the LTR state to be active */
 137 +               pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
 138 +                             PCIE2_LTR_ACTIVE);
 139 +               usleep_range(1000, 2000);
 140 +
 141 +               /* set the LTR state to be sleep */
 142 +               pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
 143 +                             PCIE2_LTR_SLEEP);
 144 +               usleep_range(1000, 2000);
 145 +       }
 146 +}
 147 +
 148 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
 149 +{
 150 +       u8 core_rev = pcie2->core->id.rev;
 151 +       bool pciewar160, pciewar162;
 152 +
 153 +       pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
 154 +       pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
 155 +                    core_rev == 9 || core_rev == 11;
 156 +
 157 +       if (!pciewar160 && !pciewar162)
 158 +               return;
 159 +
 160 +/* TODO */
 161 +#if 0
 162 +       pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
 163 +                   PCIE_DISABLE_L1CLK_GATING);
 164 +#if 0
 165 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
 166 +                     PCIEGEN2_COE_PVT_TL_CTRL_0);
 167 +       pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
 168 +                    ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
 169 +#endif
 170 +#endif
 171 +}
 172 +
 173 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
 174 +{
 175 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
 176 +       pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
 177 +}
 178 +
 179 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
 180 +{
 181 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
 182 +       pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
 183 +}
 184 +
 185 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
 186 +{
 187 +       struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
 188 +       u8 core_rev = pcie2->core->id.rev;
 189 +       u32 alp_khz, pm_value;
 190 +
 191 +       if (core_rev <= 13) {
 192 +               alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
 193 +               pm_value = (1000000 * 2) / alp_khz;
 194 +               pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
 195 +                             PCIE2_PVT_REG_PM_CLK_PERIOD);
 196 +               pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
 197 +       }
 198 +}
 199 +
 200 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
 201 +{
 202 +       struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
 203 +       u32 tmp;
 204 +
 205 +       tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
 206 +       if ((tmp & 0xe) >> 1 == 2)
 207 +               bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
 208 +
 209 +       /* TODO: Do we need pcie_reqsize? */
 210 +
 211 +       if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
 212 +               bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
 213 +       bcma_core_pcie2_hw_ltr_war(pcie2);
 214 +       pciedev_crwlpciegen2(pcie2);
 215 +       pciedev_reg_pm_clk_period(pcie2);
 216 +       pciedev_crwlpciegen2_180(pcie2);
 217 +       pciedev_crwlpciegen2_182(pcie2);
 218 +}
 219 --- a/drivers/bcma/host_pci.c
 220 +++ b/drivers/bcma/host_pci.c
 221 @@ -279,6 +279,8 @@ static const struct pci_device_id bcma_p
 222         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
 223         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
 224         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
 225 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
 226 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
 227         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
 228         { 0, },
 229  };
 230 --- a/drivers/bcma/main.c
 231 +++ b/drivers/bcma/main.c
 232 @@ -132,6 +132,7 @@ static int bcma_register_cores(struct bc
 233                 case BCMA_CORE_CHIPCOMMON:
 234                 case BCMA_CORE_PCI:
 235                 case BCMA_CORE_PCIE:
 236 +               case BCMA_CORE_PCIE2:
 237                 case BCMA_CORE_MIPS_74K:
 238                 case BCMA_CORE_4706_MAC_GBIT_COMMON:
 239                         continue;
 240 @@ -281,6 +282,13 @@ int bcma_bus_register(struct bcma_bus *b
 241                 bcma_core_pci_init(&bus->drv_pci[1]);
 242         }
 243
 244 +       /* Init PCIe Gen 2 core */
 245 +       core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
 246 +       if (core) {
 247 +               bus->drv_pcie2.core = core;
 248 +               bcma_core_pcie2_init(&bus->drv_pcie2);
 249 +       }
 250 +
 251         /* Init GBIT MAC COMMON core */
 252         core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
 253         if (core) {
 254 --- a/drivers/bcma/sprom.c
 255 +++ b/drivers/bcma/sprom.c
 256 @@ -201,6 +201,23 @@ static int bcma_sprom_valid(struct bcma_
 257                 SPEX(_field[7], _offset + 14, _mask, _shift);   \
 258         } while (0)
 259
 260 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
 261 +{
 262 +       u16 v;
 263 +       u8 gain;
 264 +
 265 +       v = in[SPOFF(offset)];
 266 +       gain = (v & mask) >> shift;
 267 +       if (gain == 0xFF) {
 268 +               gain = 8; /* If unset use 2dBm */
 269 +       } else {
 270 +               /* Q5.2 Fractional part is stored in 0xC0 */
 271 +               gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
 272 +       }
 273 +
 274 +       return (s8)gain;
 275 +}
 276 +
 277  static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
 278  {
 279         u16 v, o;
 280 @@ -381,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
 281         SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
 282
 283         /* Extract the antenna gain values. */
 284 -       SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
 285 -            SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
 286 -       SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
 287 -            SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
 288 -       SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
 289 -            SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
 290 -       SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
 291 -            SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
 292 +       bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
 293 +                                                          SSB_SPROM8_AGAIN01,
 294 +                                                          SSB_SPROM8_AGAIN0,
 295 +                                                          SSB_SPROM8_AGAIN0_SHIFT);
 296 +       bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
 297 +                                                          SSB_SPROM8_AGAIN01,
 298 +                                                          SSB_SPROM8_AGAIN1,
 299 +                                                          SSB_SPROM8_AGAIN1_SHIFT);
 300 +       bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
 301 +                                                          SSB_SPROM8_AGAIN23,
 302 +                                                          SSB_SPROM8_AGAIN2,
 303 +                                                          SSB_SPROM8_AGAIN2_SHIFT);
 304 +       bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
 305 +                                                          SSB_SPROM8_AGAIN23,
 306 +                                                          SSB_SPROM8_AGAIN3,
 307 +                                                          SSB_SPROM8_AGAIN3_SHIFT);
 308
 309         SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
 310              SSB_SPROM8_LEDDC_ON_SHIFT);
 311 @@ -509,6 +534,8 @@ static bool bcma_sprom_onchip_available(
 312                 /* for these chips OTP is always available */
 313                 present = true;
 314                 break;
 315 +       case BCMA_CHIP_ID_BCM43131:
 316 +       case BCMA_CHIP_ID_BCM43217:
 317         case BCMA_CHIP_ID_BCM43227:
 318         case BCMA_CHIP_ID_BCM43228:
 319         case BCMA_CHIP_ID_BCM43428:
 320 --- a/include/linux/bcma/bcma.h
 321 +++ b/include/linux/bcma/bcma.h
 322 @@ -6,6 +6,7 @@
 323
 324  #include <linux/bcma/bcma_driver_chipcommon.h>
 325  #include <linux/bcma/bcma_driver_pci.h>
 326 +#include <linux/bcma/bcma_driver_pcie2.h>
 327  #include <linux/bcma/bcma_driver_mips.h>
 328  #include <linux/bcma/bcma_driver_gmac_cmn.h>
 329  #include <linux/ssb/ssb.h> /* SPROM sharing */
 330 @@ -157,6 +158,9 @@ struct bcma_host_ops {
 331  /* Chip IDs of PCIe devices */
 332  #define BCMA_CHIP_ID_BCM4313   0x4313
 333  #define BCMA_CHIP_ID_BCM43142  43142
 334 +#define BCMA_CHIP_ID_BCM43131  43131
 335 +#define BCMA_CHIP_ID_BCM43217  43217
 336 +#define BCMA_CHIP_ID_BCM43222  43222
 337  #define BCMA_CHIP_ID_BCM43224  43224
 338  #define  BCMA_PKG_ID_BCM43224_FAB_CSM  0x8
 339  #define  BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
 340 @@ -333,6 +337,7 @@ struct bcma_bus {
 341
 342         struct bcma_drv_cc drv_cc;
 343         struct bcma_drv_pci drv_pci[2];
 344 +       struct bcma_drv_pcie2 drv_pcie2;
 345         struct bcma_drv_mips drv_mips;
 346         struct bcma_drv_gmac_cmn drv_gmac_cmn;
 347
 348 --- /dev/null
 349 +++ b/include/linux/bcma/bcma_driver_pcie2.h
 350 @@ -0,0 +1,158 @@
 351 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
 352 +#define LINUX_BCMA_DRIVER_PCIE2_H_
 353 +
 354 +#define BCMA_CORE_PCIE2_CLK_CONTROL            0x0000
 355 +#define  PCIE2_CLKC_RST_OE                     0x0001 /* When set, drives PCI_RESET out to pin */
 356 +#define  PCIE2_CLKC_RST                                0x0002 /* Value driven out to pin */
 357 +#define  PCIE2_CLKC_SPERST                     0x0004 /* SurvivePeRst */
 358 +#define  PCIE2_CLKC_DISABLE_L1CLK_GATING       0x0010
 359 +#define  PCIE2_CLKC_DLYPERST                   0x0100 /* Delay PeRst to CoE Core */
 360 +#define  PCIE2_CLKC_DISSPROMLD                 0x0200 /* DisableSpromLoadOnPerst */
 361 +#define  PCIE2_CLKC_WAKE_MODE_L2               0x1000 /* Wake on L2 */
 362 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL          0x0004
 363 +#define BCMA_CORE_PCIE2_RC_PM_STATUS           0x0008
 364 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL          0x000C
 365 +#define BCMA_CORE_PCIE2_EP_PM_STATUS           0x0010
 366 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL         0x0014
 367 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS          0x0018
 368 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS         0x001C
 369 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS                0x0020
 370 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG          0x0100
 371 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG          0x0104
 372 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0                0x0108
 373 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0       0x010C
 374 +#define BCMA_CORE_PCIE2_CONFIGINDADDR          0x0120
 375 +#define BCMA_CORE_PCIE2_CONFIGINDDATA          0x0124
 376 +#define BCMA_CORE_PCIE2_MDIOCONTROL            0x0128
 377 +#define BCMA_CORE_PCIE2_MDIOWRDATA             0x012C
 378 +#define BCMA_CORE_PCIE2_MDIORDDATA             0x0130
 379 +#define BCMA_CORE_PCIE2_DATAINTF               0x0180
 380 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0         0x0188
 381 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0         0x018c
 382 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0          0x0190
 383 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0          0x0194
 384 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0          0x0198
 385 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0          0x019c
 386 +#define BCMA_CORE_PCIE2_LTR_STATE              0x01A0 /* Latency Tolerance Reporting */
 387 +#define  PCIE2_LTR_ACTIVE                      2
 388 +#define  PCIE2_LTR_ACTIVE_IDLE                 1
 389 +#define  PCIE2_LTR_SLEEP                       0
 390 +#define  PCIE2_LTR_FINAL_MASK                  0x300
 391 +#define  PCIE2_LTR_FINAL_SHIFT                 8
 392 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS         0x01A4
 393 +#define BCMA_CORE_PCIE2_PWR_INT_MASK           0x01A8
 394 +#define BCMA_CORE_PCIE2_CFG_ADDR               0x01F8
 395 +#define BCMA_CORE_PCIE2_CFG_DATA               0x01FC
 396 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE            0x0200
 397 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE           0x0204
 398 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN         0x0208
 399 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0          0x0210
 400 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1          0x0214
 401 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2          0x0218
 402 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3          0x021C
 403 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4          0x0220
 404 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5          0x0224
 405 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0           0x0250
 406 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0           0x0254
 407 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1           0x0258
 408 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1           0x025C
 409 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2           0x0260
 410 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2           0x0264
 411 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3           0x0268
 412 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3           0x026C
 413 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4           0x0270
 414 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4           0x0274
 415 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5           0x0278
 416 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5           0x027C
 417 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN         0x0330
 418 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR                0x0334
 419 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ            0x0340
 420 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN       0x0344
 421 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR      0x0348
 422 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0         0x0350
 423 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1         0x0354
 424 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2         0x0358
 425 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3         0x035C
 426 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0         0x0360
 427 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1         0x0364
 428 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0                0x0370
 429 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1                0x0374
 430 +#define BCMA_CORE_PCIE2_SPROM(wordoffset)      (0x0800 + ((wordoffset) * 2))
 431 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0          0x0C00
 432 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1          0x0C04
 433 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2          0x0C08
 434 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3          0x0C0C
 435 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4          0x0C10
 436 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5          0x0C14
 437 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6          0x0C18
 438 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7          0x0C1C
 439 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0          0x0C20
 440 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1          0x0C24
 441 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2          0x0C28
 442 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3          0x0C2C
 443 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4          0x0C30
 444 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5          0x0C34
 445 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6          0x0C38
 446 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7          0x0C3C
 447 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1            0x0C80
 448 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1            0x0C88
 449 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2            0x0CC0
 450 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2            0x0CC8
 451 +#define BCMA_CORE_PCIE2_IARR0_LOWER            0x0D00
 452 +#define BCMA_CORE_PCIE2_IARR0_UPPER            0x0D04
 453 +#define BCMA_CORE_PCIE2_IARR1_LOWER            0x0D08
 454 +#define BCMA_CORE_PCIE2_IARR1_UPPER            0x0D0C
 455 +#define BCMA_CORE_PCIE2_IARR2_LOWER            0x0D10
 456 +#define BCMA_CORE_PCIE2_IARR2_UPPER            0x0D14
 457 +#define BCMA_CORE_PCIE2_OARR0                  0x0D20
 458 +#define BCMA_CORE_PCIE2_OARR1                  0x0D28
 459 +#define BCMA_CORE_PCIE2_OARR2                  0x0D30
 460 +#define BCMA_CORE_PCIE2_OMAP0_LOWER            0x0D40
 461 +#define BCMA_CORE_PCIE2_OMAP0_UPPER            0x0D44
 462 +#define BCMA_CORE_PCIE2_OMAP1_LOWER            0x0D48
 463 +#define BCMA_CORE_PCIE2_OMAP1_UPPER            0x0D4C
 464 +#define BCMA_CORE_PCIE2_OMAP2_LOWER            0x0D50
 465 +#define BCMA_CORE_PCIE2_OMAP2_UPPER            0x0D54
 466 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE       0x0D58
 467 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE       0x0D5C
 468 +#define BCMA_CORE_PCIE2_MEM_CONTROL            0x0F00
 469 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0                0x0F04
 470 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1                0x0F08
 471 +#define BCMA_CORE_PCIE2_LINK_STATUS            0x0F0C
 472 +#define BCMA_CORE_PCIE2_STRAP_STATUS           0x0F10
 473 +#define BCMA_CORE_PCIE2_RESET_STATUS           0x0F14
 474 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN    0x0F18
 475 +#define BCMA_CORE_PCIE2_MISC_INTR_EN           0x0F1C
 476 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG           0x0F20
 477 +#define BCMA_CORE_PCIE2_MISC_CONFIG            0x0F24
 478 +#define BCMA_CORE_PCIE2_MISC_STATUS            0x0F28
 479 +#define BCMA_CORE_PCIE2_INTR_EN                        0x0F30
 480 +#define BCMA_CORE_PCIE2_INTR_CLEAR             0x0F34
 481 +#define BCMA_CORE_PCIE2_INTR_STATUS            0x0F38
 482 +
 483 +/* PCIE gen2 config regs */
 484 +#define PCIE2_INTSTATUS                                0x090
 485 +#define PCIE2_INTMASK                          0x094
 486 +#define PCIE2_SBMBX                            0x098
 487 +
 488 +#define PCIE2_PMCR_REFUP                       0x1814 /* Trefup time */
 489 +
 490 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET           0xD4
 491 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB          0x400
 492 +#define PCIE2_PVT_REG_PM_CLK_PERIOD            0x184c
 493 +
 494 +struct bcma_drv_pcie2 {
 495 +       struct bcma_device *core;
 496 +};
 497 +
 498 +#define pcie2_read16(pcie2, offset)            bcma_read16((pcie2)->core, offset)
 499 +#define pcie2_read32(pcie2, offset)            bcma_read32((pcie2)->core, offset)
 500 +#define pcie2_write16(pcie2, offset, val)      bcma_write16((pcie2)->core, offset, val)
 501 +#define pcie2_write32(pcie2, offset, val)      bcma_write32((pcie2)->core, offset, val)
 502 +
 503 +#define pcie2_set32(pcie2, offset, set)                bcma_set32((pcie2)->core, offset, set)
 504 +#define pcie2_mask32(pcie2, offset, mask)      bcma_mask32((pcie2)->core, offset, mask)
 505 +
 506 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
 507 +
 508 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */