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[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.14 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Makefile
2 +++ b/drivers/bcma/Makefile
3 @@ -1,8 +1,10 @@
4 bcma-y += main.o scan.o core.o sprom.o
5 bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
6 +bcma-y += driver_chipcommon_b.o
7 bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
8 bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
9 bcma-y += driver_pci.o
10 +bcma-y += driver_pcie2.o
11 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
12 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
13 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
14 --- a/drivers/bcma/driver_chipcommon_pmu.c
15 +++ b/drivers/bcma/driver_chipcommon_pmu.c
16 @@ -603,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct
17 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
18 break;
19
20 + case BCMA_CHIP_ID_BCM43131:
21 + case BCMA_CHIP_ID_BCM43217:
22 case BCMA_CHIP_ID_BCM43227:
23 case BCMA_CHIP_ID_BCM43228:
24 case BCMA_CHIP_ID_BCM43428:
25 --- a/drivers/bcma/driver_gpio.c
26 +++ b/drivers/bcma/driver_gpio.c
27 @@ -218,7 +218,15 @@ int bcma_gpio_init(struct bcma_drv_cc *c
28 #if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
29 chip->to_irq = bcma_gpio_to_irq;
30 #endif
31 - chip->ngpio = 16;
32 + switch (cc->core->bus->chipinfo.id) {
33 + case BCMA_CHIP_ID_BCM5357:
34 + case BCMA_CHIP_ID_BCM53572:
35 + chip->ngpio = 32;
36 + break;
37 + default:
38 + chip->ngpio = 16;
39 + }
40 +
41 /* There is just one SoC in one device and its GPIO addresses should be
42 * deterministic to address them more easily. The other buses could get
43 * a random base number. */
44 --- /dev/null
45 +++ b/drivers/bcma/driver_pcie2.c
46 @@ -0,0 +1,175 @@
47 +/*
48 + * Broadcom specific AMBA
49 + * PCIe Gen 2 Core
50 + *
51 + * Copyright 2014, Broadcom Corporation
52 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
53 + *
54 + * Licensed under the GNU/GPL. See COPYING for details.
55 + */
56 +
57 +#include "bcma_private.h"
58 +#include <linux/bcma/bcma.h>
59 +
60 +/**************************************************
61 + * R/W ops.
62 + **************************************************/
63 +
64 +#if 0
65 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
66 +{
67 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
68 + pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
69 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
70 +}
71 +#endif
72 +
73 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
74 + u32 val)
75 +{
76 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
77 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
78 +}
79 +
80 +/**************************************************
81 + * Init.
82 + **************************************************/
83 +
84 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
85 + bool enable)
86 +{
87 + u32 val;
88 +
89 + /* restore back to default */
90 + val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
91 + val |= PCIE2_CLKC_DLYPERST;
92 + val &= ~PCIE2_CLKC_DISSPROMLD;
93 + if (enable) {
94 + val &= ~PCIE2_CLKC_DLYPERST;
95 + val |= PCIE2_CLKC_DISSPROMLD;
96 + }
97 + pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
98 + /* flush */
99 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
100 +}
101 +
102 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
103 +{
104 + /* LTR0 */
105 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
106 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
107 + /* LTR1 */
108 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
109 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
110 + /* LTR2 */
111 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
112 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
113 +}
114 +
115 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
116 +{
117 + u8 core_rev = pcie2->core->id.rev;
118 + u32 devstsctr2;
119 +
120 + if (core_rev < 2 || core_rev == 10 || core_rev > 13)
121 + return;
122 +
123 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
124 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
125 + devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
126 + if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
127 + /* force the right LTR values */
128 + bcma_core_pcie2_set_ltr_vals(pcie2);
129 +
130 + /* TODO:
131 + si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
132 +
133 + /* enable the LTR */
134 + devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
135 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
136 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
137 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
138 +
139 + /* set the LTR state to be active */
140 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
141 + PCIE2_LTR_ACTIVE);
142 + usleep_range(1000, 2000);
143 +
144 + /* set the LTR state to be sleep */
145 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
146 + PCIE2_LTR_SLEEP);
147 + usleep_range(1000, 2000);
148 + }
149 +}
150 +
151 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
152 +{
153 + u8 core_rev = pcie2->core->id.rev;
154 + bool pciewar160, pciewar162;
155 +
156 + pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
157 + pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
158 + core_rev == 9 || core_rev == 11;
159 +
160 + if (!pciewar160 && !pciewar162)
161 + return;
162 +
163 +/* TODO */
164 +#if 0
165 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
166 + PCIE_DISABLE_L1CLK_GATING);
167 +#if 0
168 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
169 + PCIEGEN2_COE_PVT_TL_CTRL_0);
170 + pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
171 + ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
172 +#endif
173 +#endif
174 +}
175 +
176 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
177 +{
178 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
179 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
180 +}
181 +
182 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
183 +{
184 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
185 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
186 +}
187 +
188 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
189 +{
190 + struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
191 + u8 core_rev = pcie2->core->id.rev;
192 + u32 alp_khz, pm_value;
193 +
194 + if (core_rev <= 13) {
195 + alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
196 + pm_value = (1000000 * 2) / alp_khz;
197 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
198 + PCIE2_PVT_REG_PM_CLK_PERIOD);
199 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
200 + }
201 +}
202 +
203 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
204 +{
205 + struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
206 + u32 tmp;
207 +
208 + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
209 + if ((tmp & 0xe) >> 1 == 2)
210 + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
211 +
212 + /* TODO: Do we need pcie_reqsize? */
213 +
214 + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
215 + bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
216 + bcma_core_pcie2_hw_ltr_war(pcie2);
217 + pciedev_crwlpciegen2(pcie2);
218 + pciedev_reg_pm_clk_period(pcie2);
219 + pciedev_crwlpciegen2_180(pcie2);
220 + pciedev_crwlpciegen2_182(pcie2);
221 +}
222 --- a/drivers/bcma/host_pci.c
223 +++ b/drivers/bcma/host_pci.c
224 @@ -208,6 +208,9 @@ static int bcma_host_pci_probe(struct pc
225 bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
226 bus->boardinfo.type = bus->host_pci->subsystem_device;
227
228 + /* Initialize struct, detect chip */
229 + bcma_init_bus(bus);
230 +
231 /* Register */
232 err = bcma_bus_register(bus);
233 if (err)
234 @@ -279,7 +282,10 @@ static const struct pci_device_id bcma_p
235 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
236 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
237 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
238 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
239 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
240 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
241 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xA8DB */
242 { 0, },
243 };
244 MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
245 --- a/drivers/bcma/main.c
246 +++ b/drivers/bcma/main.c
247 @@ -120,56 +120,78 @@ static void bcma_release_core_dev(struct
248 kfree(core);
249 }
250
251 -static int bcma_register_cores(struct bcma_bus *bus)
252 +static bool bcma_is_core_needed_early(u16 core_id)
253 +{
254 + switch (core_id) {
255 + case BCMA_CORE_NS_NAND:
256 + case BCMA_CORE_NS_QSPI:
257 + return true;
258 + }
259 +
260 + return false;
261 +}
262 +
263 +static void bcma_register_core(struct bcma_bus *bus, struct bcma_device *core)
264 +{
265 + int err;
266 +
267 + core->dev.release = bcma_release_core_dev;
268 + core->dev.bus = &bcma_bus_type;
269 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index);
270 +
271 + switch (bus->hosttype) {
272 + case BCMA_HOSTTYPE_PCI:
273 + core->dev.parent = &bus->host_pci->dev;
274 + core->dma_dev = &bus->host_pci->dev;
275 + core->irq = bus->host_pci->irq;
276 + break;
277 + case BCMA_HOSTTYPE_SOC:
278 + core->dev.dma_mask = &core->dev.coherent_dma_mask;
279 + core->dma_dev = &core->dev;
280 + break;
281 + case BCMA_HOSTTYPE_SDIO:
282 + break;
283 + }
284 +
285 + err = device_register(&core->dev);
286 + if (err) {
287 + bcma_err(bus, "Could not register dev for core 0x%03X\n",
288 + core->id.id);
289 + put_device(&core->dev);
290 + return;
291 + }
292 + core->dev_registered = true;
293 +}
294 +
295 +static int bcma_register_devices(struct bcma_bus *bus)
296 {
297 struct bcma_device *core;
298 - int err, dev_id = 0;
299 + int err;
300
301 list_for_each_entry(core, &bus->cores, list) {
302 /* We support that cores ourself */
303 switch (core->id.id) {
304 case BCMA_CORE_4706_CHIPCOMMON:
305 case BCMA_CORE_CHIPCOMMON:
306 + case BCMA_CORE_NS_CHIPCOMMON_B:
307 case BCMA_CORE_PCI:
308 case BCMA_CORE_PCIE:
309 + case BCMA_CORE_PCIE2:
310 case BCMA_CORE_MIPS_74K:
311 case BCMA_CORE_4706_MAC_GBIT_COMMON:
312 continue;
313 }
314
315 + /* Early cores were already registered */
316 + if (bcma_is_core_needed_early(core->id.id))
317 + continue;
318 +
319 /* Only first GMAC core on BCM4706 is connected and working */
320 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
321 core->core_unit > 0)
322 continue;
323
324 - core->dev.release = bcma_release_core_dev;
325 - core->dev.bus = &bcma_bus_type;
326 - dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
327 -
328 - switch (bus->hosttype) {
329 - case BCMA_HOSTTYPE_PCI:
330 - core->dev.parent = &bus->host_pci->dev;
331 - core->dma_dev = &bus->host_pci->dev;
332 - core->irq = bus->host_pci->irq;
333 - break;
334 - case BCMA_HOSTTYPE_SOC:
335 - core->dev.dma_mask = &core->dev.coherent_dma_mask;
336 - core->dma_dev = &core->dev;
337 - break;
338 - case BCMA_HOSTTYPE_SDIO:
339 - break;
340 - }
341 -
342 - err = device_register(&core->dev);
343 - if (err) {
344 - bcma_err(bus,
345 - "Could not register dev for core 0x%03X\n",
346 - core->id.id);
347 - put_device(&core->dev);
348 - continue;
349 - }
350 - core->dev_registered = true;
351 - dev_id++;
352 + bcma_register_core(bus, core);
353 }
354
355 #ifdef CONFIG_BCMA_DRIVER_MIPS
356 @@ -246,6 +268,12 @@ int bcma_bus_register(struct bcma_bus *b
357 bcma_core_chipcommon_early_init(&bus->drv_cc);
358 }
359
360 + /* Cores providing flash access go before SPROM init */
361 + list_for_each_entry(core, &bus->cores, list) {
362 + if (bcma_is_core_needed_early(core->id.id))
363 + bcma_register_core(bus, core);
364 + }
365 +
366 /* Try to get SPROM */
367 err = bcma_sprom_get(bus);
368 if (err == -ENOENT) {
369 @@ -260,6 +288,13 @@ int bcma_bus_register(struct bcma_bus *b
370 bcma_core_chipcommon_init(&bus->drv_cc);
371 }
372
373 + /* Init CC core */
374 + core = bcma_find_core(bus, BCMA_CORE_NS_CHIPCOMMON_B);
375 + if (core) {
376 + bus->drv_cc_b.core = core;
377 + bcma_core_chipcommon_b_init(&bus->drv_cc_b);
378 + }
379 +
380 /* Init MIPS core */
381 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
382 if (core) {
383 @@ -281,6 +316,13 @@ int bcma_bus_register(struct bcma_bus *b
384 bcma_core_pci_init(&bus->drv_pci[1]);
385 }
386
387 + /* Init PCIe Gen 2 core */
388 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
389 + if (core) {
390 + bus->drv_pcie2.core = core;
391 + bcma_core_pcie2_init(&bus->drv_pcie2);
392 + }
393 +
394 /* Init GBIT MAC COMMON core */
395 core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
396 if (core) {
397 @@ -289,7 +331,7 @@ int bcma_bus_register(struct bcma_bus *b
398 }
399
400 /* Register found cores */
401 - bcma_register_cores(bus);
402 + bcma_register_devices(bus);
403
404 bcma_info(bus, "Bus registered\n");
405
406 @@ -307,6 +349,8 @@ void bcma_bus_unregister(struct bcma_bus
407 else if (err)
408 bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
409
410 + bcma_core_chipcommon_b_free(&bus->drv_cc_b);
411 +
412 cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
413 cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
414 cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
415 @@ -326,8 +370,6 @@ int __init bcma_bus_early_register(struc
416 struct bcma_device *core;
417 struct bcma_device_id match;
418
419 - bcma_init_bus(bus);
420 -
421 match.manuf = BCMA_MANUF_BCM;
422 match.id = bcma_cc_core_id(bus);
423 match.class = BCMA_CL_SIM;
424 --- a/drivers/bcma/sprom.c
425 +++ b/drivers/bcma/sprom.c
426 @@ -201,6 +201,23 @@ static int bcma_sprom_valid(struct bcma_
427 SPEX(_field[7], _offset + 14, _mask, _shift); \
428 } while (0)
429
430 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
431 +{
432 + u16 v;
433 + u8 gain;
434 +
435 + v = in[SPOFF(offset)];
436 + gain = (v & mask) >> shift;
437 + if (gain == 0xFF) {
438 + gain = 8; /* If unset use 2dBm */
439 + } else {
440 + /* Q5.2 Fractional part is stored in 0xC0 */
441 + gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
442 + }
443 +
444 + return (s8)gain;
445 +}
446 +
447 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
448 {
449 u16 v, o;
450 @@ -381,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
451 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
452
453 /* Extract the antenna gain values. */
454 - SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
455 - SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
456 - SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
457 - SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
458 - SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
459 - SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
460 - SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
461 - SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
462 + bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
463 + SSB_SPROM8_AGAIN01,
464 + SSB_SPROM8_AGAIN0,
465 + SSB_SPROM8_AGAIN0_SHIFT);
466 + bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
467 + SSB_SPROM8_AGAIN01,
468 + SSB_SPROM8_AGAIN1,
469 + SSB_SPROM8_AGAIN1_SHIFT);
470 + bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
471 + SSB_SPROM8_AGAIN23,
472 + SSB_SPROM8_AGAIN2,
473 + SSB_SPROM8_AGAIN2_SHIFT);
474 + bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
475 + SSB_SPROM8_AGAIN23,
476 + SSB_SPROM8_AGAIN3,
477 + SSB_SPROM8_AGAIN3_SHIFT);
478
479 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
480 SSB_SPROM8_LEDDC_ON_SHIFT);
481 @@ -509,6 +534,8 @@ static bool bcma_sprom_onchip_available(
482 /* for these chips OTP is always available */
483 present = true;
484 break;
485 + case BCMA_CHIP_ID_BCM43131:
486 + case BCMA_CHIP_ID_BCM43217:
487 case BCMA_CHIP_ID_BCM43227:
488 case BCMA_CHIP_ID_BCM43228:
489 case BCMA_CHIP_ID_BCM43428:
490 --- a/include/linux/bcma/bcma.h
491 +++ b/include/linux/bcma/bcma.h
492 @@ -6,6 +6,7 @@
493
494 #include <linux/bcma/bcma_driver_chipcommon.h>
495 #include <linux/bcma/bcma_driver_pci.h>
496 +#include <linux/bcma/bcma_driver_pcie2.h>
497 #include <linux/bcma/bcma_driver_mips.h>
498 #include <linux/bcma/bcma_driver_gmac_cmn.h>
499 #include <linux/ssb/ssb.h> /* SPROM sharing */
500 @@ -72,17 +73,17 @@ struct bcma_host_ops {
501 /* Core-ID values. */
502 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
503 #define BCMA_CORE_4706_CHIPCOMMON 0x500
504 -#define BCMA_CORE_PCIEG2 0x501
505 -#define BCMA_CORE_DMA 0x502
506 -#define BCMA_CORE_SDIO3 0x503
507 -#define BCMA_CORE_USB20 0x504
508 -#define BCMA_CORE_USB30 0x505
509 -#define BCMA_CORE_A9JTAG 0x506
510 -#define BCMA_CORE_DDR23 0x507
511 -#define BCMA_CORE_ROM 0x508
512 -#define BCMA_CORE_NAND 0x509
513 -#define BCMA_CORE_QSPI 0x50A
514 -#define BCMA_CORE_CHIPCOMMON_B 0x50B
515 +#define BCMA_CORE_NS_PCIEG2 0x501
516 +#define BCMA_CORE_NS_DMA 0x502
517 +#define BCMA_CORE_NS_SDIO3 0x503
518 +#define BCMA_CORE_NS_USB20 0x504
519 +#define BCMA_CORE_NS_USB30 0x505
520 +#define BCMA_CORE_NS_A9JTAG 0x506
521 +#define BCMA_CORE_NS_DDR23 0x507
522 +#define BCMA_CORE_NS_ROM 0x508
523 +#define BCMA_CORE_NS_NAND 0x509
524 +#define BCMA_CORE_NS_QSPI 0x50A
525 +#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
526 #define BCMA_CORE_4706_SOC_RAM 0x50E
527 #define BCMA_CORE_ARMCA9 0x510
528 #define BCMA_CORE_4706_MAC_GBIT 0x52D
529 @@ -157,6 +158,9 @@ struct bcma_host_ops {
530 /* Chip IDs of PCIe devices */
531 #define BCMA_CHIP_ID_BCM4313 0x4313
532 #define BCMA_CHIP_ID_BCM43142 43142
533 +#define BCMA_CHIP_ID_BCM43131 43131
534 +#define BCMA_CHIP_ID_BCM43217 43217
535 +#define BCMA_CHIP_ID_BCM43222 43222
536 #define BCMA_CHIP_ID_BCM43224 43224
537 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
538 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
539 @@ -263,7 +267,7 @@ struct bcma_device {
540 u8 core_unit;
541
542 u32 addr;
543 - u32 addr1;
544 + u32 addr_s[8];
545 u32 wrap;
546
547 void __iomem *io_addr;
548 @@ -328,11 +332,12 @@ struct bcma_bus {
549 struct bcma_device *mapped_core;
550 struct list_head cores;
551 u8 nr_cores;
552 - u8 init_done:1;
553 u8 num;
554
555 struct bcma_drv_cc drv_cc;
556 + struct bcma_drv_cc_b drv_cc_b;
557 struct bcma_drv_pci drv_pci[2];
558 + struct bcma_drv_pcie2 drv_pcie2;
559 struct bcma_drv_mips drv_mips;
560 struct bcma_drv_gmac_cmn drv_gmac_cmn;
561
562 --- /dev/null
563 +++ b/include/linux/bcma/bcma_driver_pcie2.h
564 @@ -0,0 +1,158 @@
565 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
566 +#define LINUX_BCMA_DRIVER_PCIE2_H_
567 +
568 +#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
569 +#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
570 +#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
571 +#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
572 +#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
573 +#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
574 +#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
575 +#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
576 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
577 +#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
578 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
579 +#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
580 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
581 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
582 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
583 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
584 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
585 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
586 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
587 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
588 +#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
589 +#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
590 +#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
591 +#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
592 +#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
593 +#define BCMA_CORE_PCIE2_DATAINTF 0x0180
594 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
595 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
596 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
597 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
598 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
599 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
600 +#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
601 +#define PCIE2_LTR_ACTIVE 2
602 +#define PCIE2_LTR_ACTIVE_IDLE 1
603 +#define PCIE2_LTR_SLEEP 0
604 +#define PCIE2_LTR_FINAL_MASK 0x300
605 +#define PCIE2_LTR_FINAL_SHIFT 8
606 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
607 +#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
608 +#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
609 +#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
610 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
611 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
612 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
613 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
614 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
615 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
616 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
617 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
618 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
619 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
620 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
621 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
622 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
623 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
624 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
625 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
626 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
627 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
628 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
629 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
630 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
631 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
632 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
633 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
634 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
635 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
636 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
637 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
638 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
639 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
640 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
641 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
642 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
643 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
644 +#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
645 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
646 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
647 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
648 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
649 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
650 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
651 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
652 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
653 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
654 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
655 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
656 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
657 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
658 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
659 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
660 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
661 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
662 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
663 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
664 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
665 +#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
666 +#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
667 +#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
668 +#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
669 +#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
670 +#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
671 +#define BCMA_CORE_PCIE2_OARR0 0x0D20
672 +#define BCMA_CORE_PCIE2_OARR1 0x0D28
673 +#define BCMA_CORE_PCIE2_OARR2 0x0D30
674 +#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
675 +#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
676 +#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
677 +#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
678 +#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
679 +#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
680 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
681 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
682 +#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
683 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
684 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
685 +#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
686 +#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
687 +#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
688 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
689 +#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
690 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
691 +#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
692 +#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
693 +#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
694 +#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
695 +#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
696 +
697 +/* PCIE gen2 config regs */
698 +#define PCIE2_INTSTATUS 0x090
699 +#define PCIE2_INTMASK 0x094
700 +#define PCIE2_SBMBX 0x098
701 +
702 +#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
703 +
704 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
705 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
706 +#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
707 +
708 +struct bcma_drv_pcie2 {
709 + struct bcma_device *core;
710 +};
711 +
712 +#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
713 +#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
714 +#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
715 +#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
716 +
717 +#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
718 +#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
719 +
720 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
721 +
722 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
723 --- a/drivers/bcma/scan.c
724 +++ b/drivers/bcma/scan.c
725 @@ -32,17 +32,17 @@ static const struct bcma_device_id_name
726 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
727 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
728 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
729 - { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
730 - { BCMA_CORE_DMA, "DMA" },
731 - { BCMA_CORE_SDIO3, "SDIO3" },
732 - { BCMA_CORE_USB20, "USB 2.0" },
733 - { BCMA_CORE_USB30, "USB 3.0" },
734 - { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
735 - { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
736 - { BCMA_CORE_ROM, "ROM" },
737 - { BCMA_CORE_NAND, "NAND flash controller" },
738 - { BCMA_CORE_QSPI, "SPI flash controller" },
739 - { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
740 + { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" },
741 + { BCMA_CORE_NS_DMA, "DMA" },
742 + { BCMA_CORE_NS_SDIO3, "SDIO3" },
743 + { BCMA_CORE_NS_USB20, "USB 2.0" },
744 + { BCMA_CORE_NS_USB30, "USB 3.0" },
745 + { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" },
746 + { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" },
747 + { BCMA_CORE_NS_ROM, "ROM" },
748 + { BCMA_CORE_NS_NAND, "NAND flash controller" },
749 + { BCMA_CORE_NS_QSPI, "SPI flash controller" },
750 + { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" },
751 { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
752 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
753 { BCMA_CORE_ALTA, "ALTA (I2S)" },
754 @@ -276,7 +276,7 @@ static int bcma_get_next_core(struct bcm
755 struct bcma_device *core)
756 {
757 u32 tmp;
758 - u8 i, j;
759 + u8 i, j, k;
760 s32 cia, cib;
761 u8 ports[2], wrappers[2];
762
763 @@ -314,6 +314,7 @@ static int bcma_get_next_core(struct bcm
764 /* Some specific cores don't need wrappers */
765 switch (core->id.id) {
766 case BCMA_CORE_4706_MAC_GBIT_COMMON:
767 + case BCMA_CORE_NS_CHIPCOMMON_B:
768 /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
769 break;
770 default:
771 @@ -367,6 +368,7 @@ static int bcma_get_next_core(struct bcm
772 core->addr = tmp;
773
774 /* get & parse slave ports */
775 + k = 0;
776 for (i = 0; i < ports[1]; i++) {
777 for (j = 0; ; j++) {
778 tmp = bcma_erom_get_addr_desc(bus, eromptr,
779 @@ -376,9 +378,9 @@ static int bcma_get_next_core(struct bcm
780 /* pr_debug("erom: slave port %d "
781 * "has %d descriptors\n", i, j); */
782 break;
783 - } else {
784 - if (i == 0 && j == 0)
785 - core->addr1 = tmp;
786 + } else if (k < ARRAY_SIZE(core->addr_s)) {
787 + core->addr_s[k] = tmp;
788 + k++;
789 }
790 }
791 }
792 @@ -421,10 +423,13 @@ static int bcma_get_next_core(struct bcm
793 core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
794 if (!core->io_addr)
795 return -ENOMEM;
796 - core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
797 - if (!core->io_wrap) {
798 - iounmap(core->io_addr);
799 - return -ENOMEM;
800 + if (core->wrap) {
801 + core->io_wrap = ioremap_nocache(core->wrap,
802 + BCMA_CORE_SIZE);
803 + if (!core->io_wrap) {
804 + iounmap(core->io_addr);
805 + return -ENOMEM;
806 + }
807 }
808 }
809 return 0;
810 @@ -435,9 +440,6 @@ void bcma_init_bus(struct bcma_bus *bus)
811 s32 tmp;
812 struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
813
814 - if (bus->init_done)
815 - return;
816 -
817 INIT_LIST_HEAD(&bus->cores);
818 bus->nr_cores = 0;
819
820 @@ -449,8 +451,6 @@ void bcma_init_bus(struct bcma_bus *bus)
821 chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
822 bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
823 chipinfo->id, chipinfo->rev, chipinfo->pkg);
824 -
825 - bus->init_done = true;
826 }
827
828 int bcma_bus_scan(struct bcma_bus *bus)
829 @@ -460,8 +460,6 @@ int bcma_bus_scan(struct bcma_bus *bus)
830
831 int err, core_num = 0;
832
833 - bcma_init_bus(bus);
834 -
835 erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
836 if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
837 eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
838 --- a/drivers/bcma/host_soc.c
839 +++ b/drivers/bcma/host_soc.c
840 @@ -134,12 +134,16 @@ static void bcma_host_soc_block_write(st
841
842 static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
843 {
844 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
845 + return ~0;
846 return readl(core->io_wrap + offset);
847 }
848
849 static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
850 u32 value)
851 {
852 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
853 + return;
854 writel(value, core->io_wrap + offset);
855 }
856
857 @@ -161,7 +165,6 @@ static const struct bcma_host_ops bcma_h
858 int __init bcma_host_soc_register(struct bcma_soc *soc)
859 {
860 struct bcma_bus *bus = &soc->bus;
861 - int err;
862
863 /* iomap only first core. We have to read some register on this core
864 * to scan the bus.
865 @@ -174,7 +177,18 @@ int __init bcma_host_soc_register(struct
866 bus->hosttype = BCMA_HOSTTYPE_SOC;
867 bus->ops = &bcma_host_soc_ops;
868
869 - /* Register */
870 + /* Initialize struct, detect chip */
871 + bcma_init_bus(bus);
872 +
873 + return 0;
874 +}
875 +
876 +int __init bcma_host_soc_init(struct bcma_soc *soc)
877 +{
878 + struct bcma_bus *bus = &soc->bus;
879 + int err;
880 +
881 + /* Scan bus and initialize it */
882 err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
883 if (err)
884 iounmap(bus->mmio);
885 --- a/drivers/bcma/driver_mips.c
886 +++ b/drivers/bcma/driver_mips.c
887 @@ -21,6 +21,14 @@
888 #include <linux/serial_reg.h>
889 #include <linux/time.h>
890
891 +enum bcma_boot_dev {
892 + BCMA_BOOT_DEV_UNK = 0,
893 + BCMA_BOOT_DEV_ROM,
894 + BCMA_BOOT_DEV_PARALLEL,
895 + BCMA_BOOT_DEV_SERIAL,
896 + BCMA_BOOT_DEV_NAND,
897 +};
898 +
899 static const char * const part_probes[] = { "bcm47xxpart", NULL };
900
901 static struct physmap_flash_data bcma_pflash_data = {
902 @@ -229,11 +237,51 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
903 }
904 EXPORT_SYMBOL(bcma_cpu_clock);
905
906 +static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
907 +{
908 + struct bcma_drv_cc *cc = &bus->drv_cc;
909 + u8 cc_rev = cc->core->id.rev;
910 +
911 + if (cc_rev == 42) {
912 + struct bcma_device *core;
913 +
914 + core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
915 + if (core) {
916 + switch (bcma_aread32(core, BCMA_IOST) &
917 + BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
918 + case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
919 + return BCMA_BOOT_DEV_SERIAL;
920 + case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
921 + return BCMA_BOOT_DEV_NAND;
922 + case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
923 + default:
924 + return BCMA_BOOT_DEV_ROM;
925 + }
926 + }
927 + } else {
928 + if (cc_rev == 38) {
929 + if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
930 + return BCMA_BOOT_DEV_NAND;
931 + else if (cc->status & BIT(5))
932 + return BCMA_BOOT_DEV_ROM;
933 + }
934 +
935 + if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
936 + BCMA_CC_FLASHT_PARA)
937 + return BCMA_BOOT_DEV_PARALLEL;
938 + else
939 + return BCMA_BOOT_DEV_SERIAL;
940 + }
941 +
942 + return BCMA_BOOT_DEV_SERIAL;
943 +}
944 +
945 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
946 {
947 struct bcma_bus *bus = mcore->core->bus;
948 struct bcma_drv_cc *cc = &bus->drv_cc;
949 struct bcma_pflash *pflash = &cc->pflash;
950 + enum bcma_boot_dev boot_dev;
951
952 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
953 case BCMA_CC_FLASHT_STSER:
954 @@ -269,6 +317,20 @@ static void bcma_core_mips_flash_detect(
955 bcma_nflash_init(cc);
956 }
957 }
958 +
959 + /* Determine flash type this SoC boots from */
960 + boot_dev = bcma_boot_dev(bus);
961 + switch (boot_dev) {
962 + case BCMA_BOOT_DEV_PARALLEL:
963 + case BCMA_BOOT_DEV_SERIAL:
964 + /* TODO: Init NVRAM using BCMA_SOC_FLASH2 window */
965 + break;
966 + case BCMA_BOOT_DEV_NAND:
967 + /* TODO: Init NVRAM using BCMA_SOC_FLASH1 window */
968 + break;
969 + default:
970 + break;
971 + }
972 }
973
974 void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
975 --- a/include/linux/bcma/bcma_regs.h
976 +++ b/include/linux/bcma/bcma_regs.h
977 @@ -39,6 +39,11 @@
978 #define BCMA_RESET_CTL_RESET 0x0001
979 #define BCMA_RESET_ST 0x0804
980
981 +#define BCMA_NS_ROM_IOST_BOOT_DEV_MASK 0x0003
982 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NOR 0x0000
983 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NAND 0x0001
984 +#define BCMA_NS_ROM_IOST_BOOT_DEV_ROM 0x0002
985 +
986 /* BCMA PCI config space registers. */
987 #define BCMA_PCI_PMCSR 0x44
988 #define BCMA_PCI_PE 0x100
989 --- a/drivers/usb/host/bcma-hcd.c
990 +++ b/drivers/usb/host/bcma-hcd.c
991 @@ -237,7 +237,7 @@ static int bcma_hcd_probe(struct bcma_de
992 bcma_hcd_init_chip(dev);
993
994 /* In AI chips EHCI is addrspace 0, OHCI is 1 */
995 - ohci_addr = dev->addr1;
996 + ohci_addr = dev->addr_s[0];
997 if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749)
998 && chipinfo->rev == 0)
999 ohci_addr = 0x18009000;
1000 --- a/drivers/bcma/bcma_private.h
1001 +++ b/drivers/bcma/bcma_private.h
1002 @@ -50,6 +50,10 @@ void bcma_chipco_serial_init(struct bcma
1003 extern struct platform_device bcma_pflash_dev;
1004 #endif /* CONFIG_BCMA_DRIVER_MIPS */
1005
1006 +/* driver_chipcommon_b.c */
1007 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
1008 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb);
1009 +
1010 /* driver_chipcommon_pmu.c */
1011 u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
1012 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
1013 --- /dev/null
1014 +++ b/drivers/bcma/driver_chipcommon_b.c
1015 @@ -0,0 +1,61 @@
1016 +/*
1017 + * Broadcom specific AMBA
1018 + * ChipCommon B Unit driver
1019 + *
1020 + * Copyright 2014, Hauke Mehrtens <hauke@hauke-m.de>
1021 + *
1022 + * Licensed under the GNU/GPL. See COPYING for details.
1023 + */
1024 +
1025 +#include "bcma_private.h"
1026 +#include <linux/export.h>
1027 +#include <linux/bcma/bcma.h>
1028 +
1029 +static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
1030 + u32 value, int timeout)
1031 +{
1032 + unsigned long deadline = jiffies + timeout;
1033 + u32 val;
1034 +
1035 + do {
1036 + val = readl(addr);
1037 + if ((val & mask) == value)
1038 + return true;
1039 + cpu_relax();
1040 + udelay(10);
1041 + } while (!time_after_eq(jiffies, deadline));
1042 +
1043 + bcma_err(bus, "Timeout waiting for register %p\n", addr);
1044 +
1045 + return false;
1046 +}
1047 +
1048 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
1049 +{
1050 + struct bcma_bus *bus = ccb->core->bus;
1051 +
1052 + writel(offset, ccb->mii + 0x00);
1053 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
1054 + writel(value, ccb->mii + 0x04);
1055 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
1056 +}
1057 +EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
1058 +
1059 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb)
1060 +{
1061 + if (ccb->setup_done)
1062 + return 0;
1063 +
1064 + ccb->setup_done = 1;
1065 + ccb->mii = ioremap_nocache(ccb->core->addr_s[1], BCMA_CORE_SIZE);
1066 + if (!ccb->mii)
1067 + return -ENOMEM;
1068 +
1069 + return 0;
1070 +}
1071 +
1072 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb)
1073 +{
1074 + if (ccb->mii)
1075 + iounmap(ccb->mii);
1076 +}
1077 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1078 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1079 @@ -644,6 +644,12 @@ struct bcma_drv_cc {
1080 #endif
1081 };
1082
1083 +struct bcma_drv_cc_b {
1084 + struct bcma_device *core;
1085 + u8 setup_done:1;
1086 + void __iomem *mii;
1087 +};
1088 +
1089 /* Register access */
1090 #define bcma_cc_read32(cc, offset) \
1091 bcma_read32((cc)->core, offset)
1092 @@ -699,4 +705,6 @@ extern void bcma_pmu_spuravoid_pllupdate
1093
1094 extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
1095
1096 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value);
1097 +
1098 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
1099 --- a/arch/mips/bcm47xx/setup.c
1100 +++ b/arch/mips/bcm47xx/setup.c
1101 @@ -202,6 +202,10 @@ static void __init bcm47xx_register_bcma
1102
1103 err = bcma_host_soc_register(&bcm47xx_bus.bcma);
1104 if (err)
1105 + panic("Failed to register BCMA bus (err %d)", err);
1106 +
1107 + err = bcma_host_soc_init(&bcm47xx_bus.bcma);
1108 + if (err)
1109 panic("Failed to initialize BCMA bus (err %d)", err);
1110
1111 bcm47xx_fill_bcma_boardinfo(&bcm47xx_bus.bcma.bus.boardinfo, NULL);
1112 --- a/include/linux/bcma/bcma_soc.h
1113 +++ b/include/linux/bcma/bcma_soc.h
1114 @@ -10,6 +10,7 @@ struct bcma_soc {
1115 };
1116
1117 int __init bcma_host_soc_register(struct bcma_soc *soc);
1118 +int __init bcma_host_soc_init(struct bcma_soc *soc);
1119
1120 int bcma_bus_register(struct bcma_bus *bus);
1121
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