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kernel: ssb/bcma: update to version from wireless-testing tag master-2012-05-16-2
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.3 / 020-ssb_update.patch
1 --- a/drivers/ssb/b43_pci_bridge.c
2 +++ b/drivers/ssb/b43_pci_bridge.c
3 @@ -29,6 +29,8 @@ static const struct pci_device_id b43_pc
4 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
5 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
6 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
7 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4322) },
8 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43222) },
9 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
10 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
11 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
12 --- a/drivers/ssb/driver_chipcommon_pmu.c
13 +++ b/drivers/ssb/driver_chipcommon_pmu.c
14 @@ -13,6 +13,9 @@
15 #include <linux/ssb/ssb_driver_chipcommon.h>
16 #include <linux/delay.h>
17 #include <linux/export.h>
18 +#ifdef CONFIG_BCM47XX
19 +#include <asm/mach-bcm47xx/nvram.h>
20 +#endif
21
22 #include "ssb_private.h"
23
24 @@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct s
25 u32 pmuctl, tmp, pllctl;
26 unsigned int i;
27
28 - if ((bus->chip_id == 0x5354) && !crystalfreq) {
29 - /* The 5354 crystal freq is 25MHz */
30 - crystalfreq = 25000;
31 - }
32 if (crystalfreq)
33 e = pmu0_plltab_find_entry(crystalfreq);
34 if (!e)
35 @@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_
36 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
37
38 if (bus->bustype == SSB_BUSTYPE_SSB) {
39 - /* TODO: The user may override the crystal frequency. */
40 +#ifdef CONFIG_BCM47XX
41 + char buf[20];
42 + if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
43 + crystalfreq = simple_strtoul(buf, NULL, 0);
44 +#endif
45 }
46
47 switch (bus->chip_id) {
48 @@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_
49 ssb_pmu1_pllinit_r0(cc, crystalfreq);
50 break;
51 case 0x4328:
52 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
53 + break;
54 case 0x5354:
55 + if (crystalfreq == 0)
56 + crystalfreq = 25000;
57 ssb_pmu0_pllinit_r0(cc, crystalfreq);
58 break;
59 case 0x4322:
60 @@ -607,3 +614,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
61
62 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
63 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
64 +
65 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
66 +{
67 + struct ssb_bus *bus = cc->dev->bus;
68 +
69 + switch (bus->chip_id) {
70 + case 0x5354:
71 + /* 5354 chip uses a non programmable PLL of frequency 240MHz */
72 + return 240000000;
73 + default:
74 + ssb_printk(KERN_ERR PFX
75 + "ERROR: PMU cpu clock unknown for device %04X\n",
76 + bus->chip_id);
77 + return 0;
78 + }
79 +}
80 +
81 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
82 +{
83 + struct ssb_bus *bus = cc->dev->bus;
84 +
85 + switch (bus->chip_id) {
86 + case 0x5354:
87 + return 120000000;
88 + default:
89 + ssb_printk(KERN_ERR PFX
90 + "ERROR: PMU controlclock unknown for device %04X\n",
91 + bus->chip_id);
92 + return 0;
93 + }
94 +}
95 --- a/drivers/ssb/driver_mipscore.c
96 +++ b/drivers/ssb/driver_mipscore.c
97 @@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
98 struct ssb_bus *bus = mcore->dev->bus;
99 u32 pll_type, n, m, rate = 0;
100
101 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
102 + return ssb_pmu_get_cpu_clock(&bus->chipco);
103 +
104 if (bus->extif.dev) {
105 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
106 } else if (bus->chipco.dev) {
107 --- a/drivers/ssb/main.c
108 +++ b/drivers/ssb/main.c
109 @@ -140,19 +140,6 @@ static void ssb_device_put(struct ssb_de
110 put_device(dev->dev);
111 }
112
113 -static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
114 -{
115 - if (drv)
116 - get_driver(&drv->drv);
117 - return drv;
118 -}
119 -
120 -static inline void ssb_driver_put(struct ssb_driver *drv)
121 -{
122 - if (drv)
123 - put_driver(&drv->drv);
124 -}
125 -
126 static int ssb_device_resume(struct device *dev)
127 {
128 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
129 @@ -250,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
130 ssb_device_put(sdev);
131 continue;
132 }
133 - sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
134 - if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
135 - ssb_device_put(sdev);
136 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
137 + if (SSB_WARN_ON(!sdrv->remove))
138 continue;
139 - }
140 sdrv->remove(sdev);
141 ctx->device_frozen[i] = 1;
142 }
143 @@ -293,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
144 dev_name(sdev->dev));
145 result = err;
146 }
147 - ssb_driver_put(sdrv);
148 ssb_device_put(sdev);
149 }
150
151 @@ -1094,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
152 u32 plltype;
153 u32 clkctl_n, clkctl_m;
154
155 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
156 + return ssb_pmu_get_controlclock(&bus->chipco);
157 +
158 if (ssb_extif_available(&bus->extif))
159 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
160 &clkctl_n, &clkctl_m);
161 --- a/drivers/ssb/pci.c
162 +++ b/drivers/ssb/pci.c
163 @@ -178,6 +178,18 @@ err_pci:
164 #define SPEX(_outvar, _offset, _mask, _shift) \
165 SPEX16(_outvar, _offset, _mask, _shift)
166
167 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
168 + do { \
169 + SPEX(_field[0], _offset + 0, _mask, _shift); \
170 + SPEX(_field[1], _offset + 2, _mask, _shift); \
171 + SPEX(_field[2], _offset + 4, _mask, _shift); \
172 + SPEX(_field[3], _offset + 6, _mask, _shift); \
173 + SPEX(_field[4], _offset + 8, _mask, _shift); \
174 + SPEX(_field[5], _offset + 10, _mask, _shift); \
175 + SPEX(_field[6], _offset + 12, _mask, _shift); \
176 + SPEX(_field[7], _offset + 14, _mask, _shift); \
177 + } while (0)
178 +
179
180 static inline u8 ssb_crc8(u8 crc, u8 data)
181 {
182 @@ -331,7 +343,6 @@ static void sprom_extract_r123(struct ss
183 {
184 int i;
185 u16 v;
186 - s8 gain;
187 u16 loc[3];
188
189 if (out->revision == 3) /* rev 3 moved MAC */
190 @@ -361,8 +372,9 @@ static void sprom_extract_r123(struct ss
191 SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
192 SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
193 SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
194 - SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
195 - SSB_SPROM1_BINF_CCODE_SHIFT);
196 + if (out->revision == 1)
197 + SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
198 + SSB_SPROM1_BINF_CCODE_SHIFT);
199 SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
200 SSB_SPROM1_BINF_ANTA_SHIFT);
201 SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
202 @@ -388,22 +400,16 @@ static void sprom_extract_r123(struct ss
203 SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
204 if (out->revision >= 2)
205 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
206 + SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
207 + SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
208
209 /* Extract the antenna gain values. */
210 - gain = r123_extract_antgain(out->revision, in,
211 - SSB_SPROM1_AGAIN_BG,
212 - SSB_SPROM1_AGAIN_BG_SHIFT);
213 - out->antenna_gain.ghz24.a0 = gain;
214 - out->antenna_gain.ghz24.a1 = gain;
215 - out->antenna_gain.ghz24.a2 = gain;
216 - out->antenna_gain.ghz24.a3 = gain;
217 - gain = r123_extract_antgain(out->revision, in,
218 - SSB_SPROM1_AGAIN_A,
219 - SSB_SPROM1_AGAIN_A_SHIFT);
220 - out->antenna_gain.ghz5.a0 = gain;
221 - out->antenna_gain.ghz5.a1 = gain;
222 - out->antenna_gain.ghz5.a2 = gain;
223 - out->antenna_gain.ghz5.a3 = gain;
224 + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
225 + SSB_SPROM1_AGAIN_BG,
226 + SSB_SPROM1_AGAIN_BG_SHIFT);
227 + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
228 + SSB_SPROM1_AGAIN_A,
229 + SSB_SPROM1_AGAIN_A_SHIFT);
230 }
231
232 /* Revs 4 5 and 8 have partially shared layout */
233 @@ -464,14 +470,17 @@ static void sprom_extract_r45(struct ssb
234 SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
235 SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
236 SSB_SPROM4_ETHPHY_ET1A_SHIFT);
237 + SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
238 if (out->revision == 4) {
239 - SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
240 + SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
241 + SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
242 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
243 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
244 SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
245 SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
246 } else {
247 - SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
248 + SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
249 + SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
250 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
251 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
252 SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
253 @@ -504,16 +513,14 @@ static void sprom_extract_r45(struct ssb
254 }
255
256 /* Extract the antenna gain values. */
257 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
258 + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
259 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
260 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
261 + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
262 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
263 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
264 + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
265 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
266 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
267 + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
268 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
269 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
270 - sizeof(out->antenna_gain.ghz5));
271
272 sprom_extract_r458(out, in);
273
274 @@ -523,14 +530,22 @@ static void sprom_extract_r45(struct ssb
275 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
276 {
277 int i;
278 - u16 v;
279 + u16 v, o;
280 + u16 pwr_info_offset[] = {
281 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
282 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
283 + };
284 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
285 + ARRAY_SIZE(out->core_pwr_info));
286
287 /* extract the MAC address */
288 for (i = 0; i < 3; i++) {
289 v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
290 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
291 }
292 - SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
293 + SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
294 + SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
295 + SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
296 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
297 SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
298 SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
299 @@ -596,16 +611,46 @@ static void sprom_extract_r8(struct ssb_
300 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
301
302 /* Extract the antenna gain values. */
303 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
304 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
305 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
306 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
307 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
308 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
309 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
310 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
311 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
312 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
313 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
314 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
315 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
316 - sizeof(out->antenna_gain.ghz5));
317 +
318 + /* Extract cores power info info */
319 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
320 + o = pwr_info_offset[i];
321 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
322 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
323 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
324 + SSB_SPROM8_2G_MAXP, 0);
325 +
326 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
327 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
328 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
329 +
330 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
331 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
332 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
333 + SSB_SPROM8_5G_MAXP, 0);
334 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
335 + SSB_SPROM8_5GH_MAXP, 0);
336 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
337 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
338 +
339 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
340 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
341 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
342 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
343 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
344 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
345 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
346 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
347 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
348 + }
349
350 /* Extract FEM info */
351 SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
352 @@ -630,6 +675,63 @@ static void sprom_extract_r8(struct ssb_
353 SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
354 SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
355
356 + SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
357 + SSB_SPROM8_LEDDC_ON_SHIFT);
358 + SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
359 + SSB_SPROM8_LEDDC_OFF_SHIFT);
360 +
361 + SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
362 + SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
363 + SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
364 + SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
365 + SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
366 + SSB_SPROM8_TXRXC_SWITCH_SHIFT);
367 +
368 + SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
369 +
370 + SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
371 + SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
372 + SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
373 + SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
374 +
375 + SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
376 + SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
377 + SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
378 + SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
379 + SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
380 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
381 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
382 + SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
383 + SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
384 + SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
385 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
386 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
387 + SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
388 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
389 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
390 + SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
391 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
392 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
393 + SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
394 + SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
395 +
396 + SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
397 + SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
398 + SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
399 + SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
400 +
401 + SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
402 + SSB_SPROM8_THERMAL_TRESH_SHIFT);
403 + SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
404 + SSB_SPROM8_THERMAL_OFFSET_SHIFT);
405 + SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
406 + SSB_SPROM8_TEMPDELTA_PHYCAL,
407 + SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
408 + SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
409 + SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
410 + SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
411 + SSB_SPROM8_TEMPDELTA_HYSTERESIS,
412 + SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
413 sprom_extract_r458(out, in);
414
415 /* TODO - get remaining rev 8 stuff needed */
416 @@ -759,7 +861,6 @@ static void ssb_pci_get_boardinfo(struct
417 {
418 bi->vendor = bus->host_pci->subsystem_vendor;
419 bi->type = bus->host_pci->subsystem_device;
420 - bi->rev = bus->host_pci->revision;
421 }
422
423 int ssb_pci_get_invariants(struct ssb_bus *bus,
424 --- a/drivers/ssb/pcmcia.c
425 +++ b/drivers/ssb/pcmcia.c
426 @@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
427 case SSB_PCMCIA_CIS_ANTGAIN:
428 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
429 "antg tpl size");
430 - sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
431 - sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
432 - sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
433 - sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
434 - sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
435 - sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
436 - sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
437 - sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
438 + sprom->antenna_gain.a0 = tuple->TupleData[1];
439 + sprom->antenna_gain.a1 = tuple->TupleData[1];
440 + sprom->antenna_gain.a2 = tuple->TupleData[1];
441 + sprom->antenna_gain.a3 = tuple->TupleData[1];
442 break;
443 case SSB_PCMCIA_CIS_BFLAGS:
444 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
445 --- a/drivers/ssb/scan.c
446 +++ b/drivers/ssb/scan.c
447 @@ -318,6 +318,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
448 bus->chip_package = 0;
449 }
450 }
451 + ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
452 + "package 0x%02X\n", bus->chip_id, bus->chip_rev,
453 + bus->chip_package);
454 if (!bus->nr_devices)
455 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
456 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
457 --- a/drivers/ssb/sdio.c
458 +++ b/drivers/ssb/sdio.c
459 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
460 case SSB_SDIO_CIS_ANTGAIN:
461 GOTO_ERROR_ON(tuple->size != 2,
462 "antg tpl size");
463 - sprom->antenna_gain.ghz24.a0 = tuple->data[1];
464 - sprom->antenna_gain.ghz24.a1 = tuple->data[1];
465 - sprom->antenna_gain.ghz24.a2 = tuple->data[1];
466 - sprom->antenna_gain.ghz24.a3 = tuple->data[1];
467 - sprom->antenna_gain.ghz5.a0 = tuple->data[1];
468 - sprom->antenna_gain.ghz5.a1 = tuple->data[1];
469 - sprom->antenna_gain.ghz5.a2 = tuple->data[1];
470 - sprom->antenna_gain.ghz5.a3 = tuple->data[1];
471 + sprom->antenna_gain.a0 = tuple->data[1];
472 + sprom->antenna_gain.a1 = tuple->data[1];
473 + sprom->antenna_gain.a2 = tuple->data[1];
474 + sprom->antenna_gain.a3 = tuple->data[1];
475 break;
476 case SSB_SDIO_CIS_BFLAGS:
477 GOTO_ERROR_ON((tuple->size != 3) &&
478 --- a/drivers/ssb/ssb_private.h
479 +++ b/drivers/ssb/ssb_private.h
480 @@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
481 }
482 #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
483
484 +/* driver_chipcommon_pmu.c */
485 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
486 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
487 +
488 #endif /* LINUX_SSB_PRIVATE_H_ */
489 --- a/include/linux/ssb/ssb.h
490 +++ b/include/linux/ssb/ssb.h
491 @@ -16,6 +16,12 @@ struct pcmcia_device;
492 struct ssb_bus;
493 struct ssb_driver;
494
495 +struct ssb_sprom_core_pwr_info {
496 + u8 itssi_2g, itssi_5g;
497 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
498 + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
499 +};
500 +
501 struct ssb_sprom {
502 u8 revision;
503 u8 il0mac[6]; /* MAC address for 802.11b/g */
504 @@ -26,9 +32,12 @@ struct ssb_sprom {
505 u8 et0mdcport; /* MDIO for enet0 */
506 u8 et1mdcport; /* MDIO for enet1 */
507 u16 board_rev; /* Board revision number from SPROM. */
508 + u16 board_num; /* Board number from SPROM. */
509 + u16 board_type; /* Board type from SPROM. */
510 u8 country_code; /* Country Code */
511 - u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
512 - u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
513 + char alpha2[2]; /* Country Code as two chars like EU or US */
514 + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
515 + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
516 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
517 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
518 u16 pa0b0;
519 @@ -47,10 +56,10 @@ struct ssb_sprom {
520 u8 gpio1; /* GPIO pin 1 */
521 u8 gpio2; /* GPIO pin 2 */
522 u8 gpio3; /* GPIO pin 3 */
523 - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
524 - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
525 - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
526 - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
527 + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
528 + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
529 + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
530 + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
531 u8 itssi_a; /* Idle TSSI Target for A-PHY */
532 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
533 u8 tri2g; /* 2.4GHz TX isolation */
534 @@ -61,8 +70,8 @@ struct ssb_sprom {
535 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
536 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
537 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
538 - u8 rxpo2g; /* 2GHz RX power offset */
539 - u8 rxpo5g; /* 5GHz RX power offset */
540 + s8 rxpo2g; /* 2GHz RX power offset */
541 + s8 rxpo5g; /* 5GHz RX power offset */
542 u8 rssisav2g; /* 2GHz RSSI params */
543 u8 rssismc2g;
544 u8 rssismf2g;
545 @@ -82,16 +91,13 @@ struct ssb_sprom {
546 u16 boardflags2_hi; /* Board flags (bits 48-63) */
547 /* TODO store board flags in a single u64 */
548
549 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
550 +
551 /* Antenna gain values for up to 4 antennas
552 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
553 * loss in the connectors is bigger than the gain. */
554 struct {
555 - struct {
556 - s8 a0, a1, a2, a3;
557 - } ghz24; /* 2.4GHz band */
558 - struct {
559 - s8 a0, a1, a2, a3;
560 - } ghz5; /* 5GHz band */
561 + s8 a0, a1, a2, a3;
562 } antenna_gain;
563
564 struct {
565 @@ -103,14 +109,85 @@ struct ssb_sprom {
566 } ghz5;
567 } fem;
568
569 - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
570 + u16 mcs2gpo[8];
571 + u16 mcs5gpo[8];
572 + u16 mcs5glpo[8];
573 + u16 mcs5ghpo[8];
574 + u8 opo;
575 +
576 + u8 rxgainerr2ga[3];
577 + u8 rxgainerr5gla[3];
578 + u8 rxgainerr5gma[3];
579 + u8 rxgainerr5gha[3];
580 + u8 rxgainerr5gua[3];
581 +
582 + u8 noiselvl2ga[3];
583 + u8 noiselvl5gla[3];
584 + u8 noiselvl5gma[3];
585 + u8 noiselvl5gha[3];
586 + u8 noiselvl5gua[3];
587 +
588 + u8 regrev;
589 + u8 txchain;
590 + u8 rxchain;
591 + u8 antswitch;
592 + u16 cddpo;
593 + u16 stbcpo;
594 + u16 bw40po;
595 + u16 bwduppo;
596 +
597 + u8 tempthresh;
598 + u8 tempoffset;
599 + u16 rawtempsense;
600 + u8 measpower;
601 + u8 tempsense_slope;
602 + u8 tempcorrx;
603 + u8 tempsense_option;
604 + u8 freqoffset_corr;
605 + u8 iqcal_swp_dis;
606 + u8 hw_iqcal_en;
607 + u8 elna2g;
608 + u8 elna5g;
609 + u8 phycal_tempdelta;
610 + u8 temps_period;
611 + u8 temps_hysteresis;
612 + u8 measpower1;
613 + u8 measpower2;
614 + u8 pcieingress_war;
615 +
616 + /* power per rate from sromrev 9 */
617 + u16 cckbw202gpo;
618 + u16 cckbw20ul2gpo;
619 + u32 legofdmbw202gpo;
620 + u32 legofdmbw20ul2gpo;
621 + u32 legofdmbw205glpo;
622 + u32 legofdmbw20ul5glpo;
623 + u32 legofdmbw205gmpo;
624 + u32 legofdmbw20ul5gmpo;
625 + u32 legofdmbw205ghpo;
626 + u32 legofdmbw20ul5ghpo;
627 + u32 mcsbw202gpo;
628 + u32 mcsbw20ul2gpo;
629 + u32 mcsbw402gpo;
630 + u32 mcsbw205glpo;
631 + u32 mcsbw20ul5glpo;
632 + u32 mcsbw405glpo;
633 + u32 mcsbw205gmpo;
634 + u32 mcsbw20ul5gmpo;
635 + u32 mcsbw405gmpo;
636 + u32 mcsbw205ghpo;
637 + u32 mcsbw20ul5ghpo;
638 + u32 mcsbw405ghpo;
639 + u16 mcs32po;
640 + u16 legofdm40duppo;
641 + u8 sar2g;
642 + u8 sar5g;
643 };
644
645 /* Information about the PCB the circuitry is soldered on. */
646 struct ssb_boardinfo {
647 u16 vendor;
648 u16 type;
649 - u8 rev;
650 };
651
652
653 --- a/include/linux/ssb/ssb_driver_gige.h
654 +++ b/include/linux/ssb/ssb_driver_gige.h
655 @@ -2,6 +2,7 @@
656 #define LINUX_SSB_DRIVER_GIGE_H_
657
658 #include <linux/ssb/ssb.h>
659 +#include <linux/bug.h>
660 #include <linux/pci.h>
661 #include <linux/spinlock.h>
662
663 --- a/include/linux/ssb/ssb_regs.h
664 +++ b/include/linux/ssb/ssb_regs.h
665 @@ -228,6 +228,7 @@
666 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
667 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
668 #define SSB_SPROM1_AGAIN_A_SHIFT 8
669 +#define SSB_SPROM1_CCODE 0x0076
670
671 /* SPROM Revision 2 (inherits from rev 1) */
672 #define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
673 @@ -267,6 +268,7 @@
674 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
675
676 /* SPROM Revision 4 */
677 +#define SSB_SPROM4_BOARDREV 0x0042 /* Board revision */
678 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
679 #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
680 #define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
681 @@ -389,6 +391,11 @@
682 #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
683 #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
684 #define SSB_SPROM8_GPIOB_P3_SHIFT 8
685 +#define SSB_SPROM8_LEDDC 0x009A
686 +#define SSB_SPROM8_LEDDC_ON 0xFF00 /* oncount */
687 +#define SSB_SPROM8_LEDDC_ON_SHIFT 8
688 +#define SSB_SPROM8_LEDDC_OFF 0x00FF /* offcount */
689 +#define SSB_SPROM8_LEDDC_OFF_SHIFT 0
690 #define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
691 #define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
692 #define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
693 @@ -404,6 +411,13 @@
694 #define SSB_SPROM8_AGAIN2_SHIFT 0
695 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
696 #define SSB_SPROM8_AGAIN3_SHIFT 8
697 +#define SSB_SPROM8_TXRXC 0x00A2
698 +#define SSB_SPROM8_TXRXC_TXCHAIN 0x000f
699 +#define SSB_SPROM8_TXRXC_TXCHAIN_SHIFT 0
700 +#define SSB_SPROM8_TXRXC_RXCHAIN 0x00f0
701 +#define SSB_SPROM8_TXRXC_RXCHAIN_SHIFT 4
702 +#define SSB_SPROM8_TXRXC_SWITCH 0xff00
703 +#define SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
704 #define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
705 #define SSB_SPROM8_RSSISMF2G 0x000F
706 #define SSB_SPROM8_RSSISMC2G 0x00F0
707 @@ -430,6 +444,7 @@
708 #define SSB_SPROM8_TRI5GH_SHIFT 8
709 #define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
710 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
711 +#define SSB_SPROM8_RXPO2G_SHIFT 0
712 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
713 #define SSB_SPROM8_RXPO5G_SHIFT 8
714 #define SSB_SPROM8_FEM2G 0x00AE
715 @@ -445,10 +460,71 @@
716 #define SSB_SROM8_FEM_ANTSWLUT 0xF800
717 #define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
718 #define SSB_SPROM8_THERMAL 0x00B2
719 -#define SSB_SPROM8_MPWR_RAWTS 0x00B4
720 -#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
721 -#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
722 -#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
723 +#define SSB_SPROM8_THERMAL_OFFSET 0x00ff
724 +#define SSB_SPROM8_THERMAL_OFFSET_SHIFT 0
725 +#define SSB_SPROM8_THERMAL_TRESH 0xff00
726 +#define SSB_SPROM8_THERMAL_TRESH_SHIFT 8
727 +/* Temp sense related entries */
728 +#define SSB_SPROM8_RAWTS 0x00B4
729 +#define SSB_SPROM8_RAWTS_RAWTEMP 0x01ff
730 +#define SSB_SPROM8_RAWTS_RAWTEMP_SHIFT 0
731 +#define SSB_SPROM8_RAWTS_MEASPOWER 0xfe00
732 +#define SSB_SPROM8_RAWTS_MEASPOWER_SHIFT 9
733 +#define SSB_SPROM8_OPT_CORRX 0x00B6
734 +#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE 0x00ff
735 +#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
736 +#define SSB_SPROM8_OPT_CORRX_TEMPCORRX 0xfc00
737 +#define SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT 10
738 +#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION 0x0300
739 +#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT 8
740 +/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
741 +#define SSB_SPROM8_HWIQ_IQSWP 0x00B8
742 +#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR 0x000f
743 +#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
744 +#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP 0x0010
745 +#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
746 +#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
747 +#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
748 +#define SSB_SPROM8_TEMPDELTA 0x00BA
749 +#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
750 +#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
751 +#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
752 +#define SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT 8
753 +#define SSB_SPROM8_TEMPDELTA_HYSTERESIS 0xf000
754 +#define SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
755 +
756 +/* There are 4 blocks with power info sharing the same layout */
757 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
758 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
759 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
760 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
761 +
762 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
763 +#define SSB_SPROM8_2G_MAXP 0x00FF
764 +#define SSB_SPROM8_2G_ITSSI 0xFF00
765 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
766 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
767 +#define SSB_SROM8_2G_PA_1 0x04
768 +#define SSB_SROM8_2G_PA_2 0x06
769 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
770 +#define SSB_SPROM8_5G_MAXP 0x00FF
771 +#define SSB_SPROM8_5G_ITSSI 0xFF00
772 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
773 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
774 +#define SSB_SPROM8_5GH_MAXP 0x00FF
775 +#define SSB_SPROM8_5GL_MAXP 0xFF00
776 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
777 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
778 +#define SSB_SROM8_5G_PA_1 0x0E
779 +#define SSB_SROM8_5G_PA_2 0x10
780 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
781 +#define SSB_SROM8_5GL_PA_1 0x14
782 +#define SSB_SROM8_5GL_PA_2 0x16
783 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
784 +#define SSB_SROM8_5GH_PA_1 0x1A
785 +#define SSB_SROM8_5GH_PA_2 0x1C
786 +
787 +/* TODO: Make it deprecated */
788 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
789 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
790 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
791 @@ -473,12 +549,23 @@
792 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
793 #define SSB_SPROM8_PA1HIB1 0x00DA
794 #define SSB_SPROM8_PA1HIB2 0x00DC
795 +
796 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
797 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
798 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
799 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
800 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
801
802 +#define SSB_SPROM8_2G_MCSPO 0x0152
803 +#define SSB_SPROM8_5G_MCSPO 0x0162
804 +#define SSB_SPROM8_5GL_MCSPO 0x0172
805 +#define SSB_SPROM8_5GH_MCSPO 0x0182
806 +
807 +#define SSB_SPROM8_CDDPO 0x0192
808 +#define SSB_SPROM8_STBCPO 0x0194
809 +#define SSB_SPROM8_BW40PO 0x0196
810 +#define SSB_SPROM8_BWDUPPO 0x0198
811 +
812 /* Values for boardflags_lo read from SPROM */
813 #define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
814 #define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
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