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[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.3 / 025-bcma_backport.patch
1 --- a/arch/mips/bcm47xx/serial.c
2 +++ b/arch/mips/bcm47xx/serial.c
3 @@ -62,7 +62,7 @@ static int __init uart8250_init_bcma(voi
4
5 p->mapbase = (unsigned int) bcma_port->regs;
6 p->membase = (void *) bcma_port->regs;
7 - p->irq = bcma_port->irq + 2;
8 + p->irq = bcma_port->irq;
9 p->uartclk = bcma_port->baud_base;
10 p->regshift = bcma_port->reg_shift;
11 p->iotype = UPIO_MEM;
12 --- a/drivers/bcma/Kconfig
13 +++ b/drivers/bcma/Kconfig
14 @@ -26,16 +26,23 @@ config BCMA_HOST_PCI_POSSIBLE
15 config BCMA_HOST_PCI
16 bool "Support for BCMA on PCI-host bus"
17 depends on BCMA_HOST_PCI_POSSIBLE
18 + default y
19
20 config BCMA_DRIVER_PCI_HOSTMODE
21 bool "Driver for PCI core working in hostmode"
22 - depends on BCMA && MIPS
23 + depends on BCMA && MIPS && BCMA_HOST_PCI
24 help
25 PCI core hostmode operation (external PCI bus).
26
27 config BCMA_HOST_SOC
28 - bool
29 - depends on BCMA_DRIVER_MIPS
30 + bool "Support for BCMA in a SoC"
31 + depends on BCMA
32 + help
33 + Host interface for a Broadcom AIX bus directly mapped into
34 + the memory. This only works with the Broadcom SoCs from the
35 + BCM47XX line.
36 +
37 + If unsure, say N
38
39 config BCMA_DRIVER_MIPS
40 bool "BCMA Broadcom MIPS core driver"
41 @@ -46,6 +53,33 @@ config BCMA_DRIVER_MIPS
42
43 If unsure, say N
44
45 +config BCMA_SFLASH
46 + bool
47 + depends on BCMA_DRIVER_MIPS
48 + default y
49 +
50 +config BCMA_NFLASH
51 + bool
52 + depends on BCMA_DRIVER_MIPS
53 + default y
54 +
55 +config BCMA_DRIVER_GMAC_CMN
56 + bool "BCMA Broadcom GBIT MAC COMMON core driver"
57 + depends on BCMA
58 + help
59 + Driver for the Broadcom GBIT MAC COMMON core attached to Broadcom
60 + specific Advanced Microcontroller Bus.
61 +
62 + If unsure, say N
63 +
64 +config BCMA_DRIVER_GPIO
65 + bool "BCMA GPIO driver"
66 + depends on BCMA && GPIOLIB
67 + help
68 + Driver to provide access to the GPIO pins of the bcma bus.
69 +
70 + If unsure, say N
71 +
72 config BCMA_DEBUG
73 bool "BCMA debugging"
74 depends on BCMA
75 --- a/drivers/bcma/Makefile
76 +++ b/drivers/bcma/Makefile
77 @@ -1,8 +1,12 @@
78 bcma-y += main.o scan.o core.o sprom.o
79 bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
80 +bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
81 +bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
82 bcma-y += driver_pci.o
83 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
84 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
85 +bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
86 +bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o
87 bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
88 bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
89 obj-$(CONFIG_BCMA) += bcma.o
90 --- a/drivers/bcma/bcma_private.h
91 +++ b/drivers/bcma/bcma_private.h
92 @@ -10,10 +10,21 @@
93
94 #define BCMA_CORE_SIZE 0x1000
95
96 +#define bcma_err(bus, fmt, ...) \
97 + pr_err("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
98 +#define bcma_warn(bus, fmt, ...) \
99 + pr_warn("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
100 +#define bcma_info(bus, fmt, ...) \
101 + pr_info("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
102 +#define bcma_debug(bus, fmt, ...) \
103 + pr_debug("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
104 +
105 struct bcma_bus;
106
107 /* main.c */
108 -int bcma_bus_register(struct bcma_bus *bus);
109 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
110 + int timeout);
111 +int __devinit bcma_bus_register(struct bcma_bus *bus);
112 void bcma_bus_unregister(struct bcma_bus *bus);
113 int __init bcma_bus_early_register(struct bcma_bus *bus,
114 struct bcma_device *core_cc,
115 @@ -22,6 +33,8 @@ int __init bcma_bus_early_register(struc
116 int bcma_bus_suspend(struct bcma_bus *bus);
117 int bcma_bus_resume(struct bcma_bus *bus);
118 #endif
119 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
120 + u8 unit);
121
122 /* scan.c */
123 int bcma_bus_scan(struct bcma_bus *bus);
124 @@ -36,11 +49,36 @@ int bcma_sprom_get(struct bcma_bus *bus)
125 /* driver_chipcommon.c */
126 #ifdef CONFIG_BCMA_DRIVER_MIPS
127 void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
128 +extern struct platform_device bcma_pflash_dev;
129 #endif /* CONFIG_BCMA_DRIVER_MIPS */
130
131 /* driver_chipcommon_pmu.c */
132 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
133 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
134 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
135 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
136 +
137 +#ifdef CONFIG_BCMA_SFLASH
138 +/* driver_chipcommon_sflash.c */
139 +int bcma_sflash_init(struct bcma_drv_cc *cc);
140 +extern struct platform_device bcma_sflash_dev;
141 +#else
142 +static inline int bcma_sflash_init(struct bcma_drv_cc *cc)
143 +{
144 + bcma_err(cc->core->bus, "Serial flash not supported\n");
145 + return 0;
146 +}
147 +#endif /* CONFIG_BCMA_SFLASH */
148 +
149 +#ifdef CONFIG_BCMA_NFLASH
150 +/* driver_chipcommon_nflash.c */
151 +int bcma_nflash_init(struct bcma_drv_cc *cc);
152 +extern struct platform_device bcma_nflash_dev;
153 +#else
154 +static inline int bcma_nflash_init(struct bcma_drv_cc *cc)
155 +{
156 + bcma_err(cc->core->bus, "NAND flash not supported\n");
157 + return 0;
158 +}
159 +#endif /* CONFIG_BCMA_NFLASH */
160
161 #ifdef CONFIG_BCMA_HOST_PCI
162 /* host_pci.c */
163 @@ -48,8 +86,29 @@ extern int __init bcma_host_pci_init(voi
164 extern void __exit bcma_host_pci_exit(void);
165 #endif /* CONFIG_BCMA_HOST_PCI */
166
167 +/* driver_pci.c */
168 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
169 +
170 +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
171 +
172 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
173 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
174 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
175 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
176 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
177
178 +#ifdef CONFIG_BCMA_DRIVER_GPIO
179 +/* driver_gpio.c */
180 +int bcma_gpio_init(struct bcma_drv_cc *cc);
181 +int bcma_gpio_unregister(struct bcma_drv_cc *cc);
182 +#else
183 +static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
184 +{
185 + return -ENOTSUPP;
186 +}
187 +static inline int bcma_gpio_unregister(struct bcma_drv_cc *cc)
188 +{
189 + return 0;
190 +}
191 +#endif /* CONFIG_BCMA_DRIVER_GPIO */
192 +
193 #endif
194 --- a/drivers/bcma/core.c
195 +++ b/drivers/bcma/core.c
196 @@ -9,6 +9,25 @@
197 #include <linux/export.h>
198 #include <linux/bcma/bcma.h>
199
200 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
201 + u32 value, int timeout)
202 +{
203 + unsigned long deadline = jiffies + timeout;
204 + u32 val;
205 +
206 + do {
207 + val = bcma_aread32(core, reg);
208 + if ((val & mask) == value)
209 + return true;
210 + cpu_relax();
211 + udelay(10);
212 + } while (!time_after_eq(jiffies, deadline));
213 +
214 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
215 +
216 + return false;
217 +}
218 +
219 bool bcma_core_is_enabled(struct bcma_device *core)
220 {
221 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
222 @@ -25,12 +44,15 @@ void bcma_core_disable(struct bcma_devic
223 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
224 return;
225
226 - bcma_awrite32(core, BCMA_IOCTL, flags);
227 - bcma_aread32(core, BCMA_IOCTL);
228 - udelay(10);
229 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
230
231 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
232 + bcma_aread32(core, BCMA_RESET_CTL);
233 udelay(1);
234 +
235 + bcma_awrite32(core, BCMA_IOCTL, flags);
236 + bcma_aread32(core, BCMA_IOCTL);
237 + udelay(10);
238 }
239 EXPORT_SYMBOL_GPL(bcma_core_disable);
240
241 @@ -42,6 +64,7 @@ int bcma_core_enable(struct bcma_device
242 bcma_aread32(core, BCMA_IOCTL);
243
244 bcma_awrite32(core, BCMA_RESET_CTL, 0);
245 + bcma_aread32(core, BCMA_RESET_CTL);
246 udelay(1);
247
248 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
249 @@ -64,7 +87,7 @@ void bcma_core_set_clockmode(struct bcma
250 switch (clkmode) {
251 case BCMA_CLKMODE_FAST:
252 bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
253 - udelay(64);
254 + usleep_range(64, 300);
255 for (i = 0; i < 1500; i++) {
256 if (bcma_read32(core, BCMA_CLKCTLST) &
257 BCMA_CLKCTLST_HAVEHT) {
258 @@ -74,10 +97,10 @@ void bcma_core_set_clockmode(struct bcma
259 udelay(10);
260 }
261 if (i)
262 - pr_err("HT force timeout\n");
263 + bcma_err(core->bus, "HT force timeout\n");
264 break;
265 case BCMA_CLKMODE_DYNAMIC:
266 - pr_warn("Dynamic clockmode not supported yet!\n");
267 + bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT);
268 break;
269 }
270 }
271 @@ -101,9 +124,15 @@ void bcma_core_pll_ctl(struct bcma_devic
272 udelay(10);
273 }
274 if (i)
275 - pr_err("PLL enable timeout\n");
276 + bcma_err(core->bus, "PLL enable timeout\n");
277 } else {
278 - pr_warn("Disabling PLL not supported yet!\n");
279 + /*
280 + * Mask the PLL but don't wait for it to be disabled. PLL may be
281 + * shared between cores and will be still up if there is another
282 + * core using it.
283 + */
284 + bcma_mask32(core, BCMA_CLKCTLST, ~req);
285 + bcma_read32(core, BCMA_CLKCTLST);
286 }
287 }
288 EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
289 @@ -119,8 +148,8 @@ u32 bcma_core_dma_translation(struct bcm
290 else
291 return BCMA_DMA_TRANSLATION_DMA32_CMT;
292 default:
293 - pr_err("DMA translation unknown for host %d\n",
294 - core->bus->hosttype);
295 + bcma_err(core->bus, "DMA translation unknown for host %d\n",
296 + core->bus->hosttype);
297 }
298 return BCMA_DMA_TRANSLATION_NONE;
299 }
300 --- a/drivers/bcma/driver_chipcommon.c
301 +++ b/drivers/bcma/driver_chipcommon.c
302 @@ -4,12 +4,15 @@
303 *
304 * Copyright 2005, Broadcom Corporation
305 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
306 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
307 *
308 * Licensed under the GNU/GPL. See COPYING for details.
309 */
310
311 #include "bcma_private.h"
312 +#include <linux/bcm47xx_wdt.h>
313 #include <linux/export.h>
314 +#include <linux/platform_device.h>
315 #include <linux/bcma/bcma.h>
316
317 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
318 @@ -22,29 +25,136 @@ static inline u32 bcma_cc_write32_masked
319 return value;
320 }
321
322 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
323 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
324 {
325 - u32 leddc_on = 10;
326 - u32 leddc_off = 90;
327 + if (cc->capabilities & BCMA_CC_CAP_PMU)
328 + return bcma_pmu_get_alp_clock(cc);
329
330 - if (cc->setup_done)
331 + return 20000000;
332 +}
333 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
334 +
335 +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
336 +{
337 + struct bcma_bus *bus = cc->core->bus;
338 + u32 nb;
339 +
340 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
341 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
342 + nb = 32;
343 + else if (cc->core->id.rev < 26)
344 + nb = 16;
345 + else
346 + nb = (cc->core->id.rev >= 37) ? 32 : 24;
347 + } else {
348 + nb = 28;
349 + }
350 + if (nb == 32)
351 + return 0xffffffff;
352 + else
353 + return (1 << nb) - 1;
354 +}
355 +
356 +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
357 + u32 ticks)
358 +{
359 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
360 +
361 + return bcma_chipco_watchdog_timer_set(cc, ticks);
362 +}
363 +
364 +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
365 + u32 ms)
366 +{
367 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
368 + u32 ticks;
369 +
370 + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
371 + return ticks / cc->ticks_per_ms;
372 +}
373 +
374 +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
375 +{
376 + struct bcma_bus *bus = cc->core->bus;
377 +
378 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
379 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
380 + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
381 + return bcma_chipco_get_alp_clock(cc) / 4000;
382 + else
383 + /* based on 32KHz ILP clock */
384 + return 32;
385 + } else {
386 + return bcma_chipco_get_alp_clock(cc) / 1000;
387 + }
388 +}
389 +
390 +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
391 +{
392 + struct bcm47xx_wdt wdt = {};
393 + struct platform_device *pdev;
394 +
395 + wdt.driver_data = cc;
396 + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
397 + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
398 + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
399 +
400 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
401 + cc->core->bus->num, &wdt,
402 + sizeof(wdt));
403 + if (IS_ERR(pdev))
404 + return PTR_ERR(pdev);
405 +
406 + cc->watchdog = pdev;
407 +
408 + return 0;
409 +}
410 +
411 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
412 +{
413 + if (cc->early_setup_done)
414 return;
415
416 + spin_lock_init(&cc->gpio_lock);
417 +
418 if (cc->core->id.rev >= 11)
419 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
420 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
421 if (cc->core->id.rev >= 35)
422 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
423
424 + if (cc->capabilities & BCMA_CC_CAP_PMU)
425 + bcma_pmu_early_init(cc);
426 +
427 + cc->early_setup_done = true;
428 +}
429 +
430 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
431 +{
432 + u32 leddc_on = 10;
433 + u32 leddc_off = 90;
434 +
435 + if (cc->setup_done)
436 + return;
437 +
438 + bcma_core_chipcommon_early_init(cc);
439 +
440 if (cc->core->id.rev >= 20) {
441 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
442 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
443 + u32 pullup = 0, pulldown = 0;
444 +
445 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
446 + pullup = 0x402e0;
447 + pulldown = 0x20500;
448 + }
449 +
450 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
451 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
452 }
453
454 if (cc->capabilities & BCMA_CC_CAP_PMU)
455 bcma_pmu_init(cc);
456 if (cc->capabilities & BCMA_CC_CAP_PCTL)
457 - pr_err("Power control not implemented!\n");
458 + bcma_err(cc->core->bus, "Power control not implemented!\n");
459
460 if (cc->core->id.rev >= 16) {
461 if (cc->core->bus->sprom.leddc_on_time &&
462 @@ -56,15 +166,33 @@ void bcma_core_chipcommon_init(struct bc
463 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
464 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
465 }
466 + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
467
468 cc->setup_done = true;
469 }
470
471 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
472 -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
473 +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
474 {
475 - /* instant NMI */
476 - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
477 + u32 maxt;
478 + enum bcma_clkmode clkmode;
479 +
480 + maxt = bcma_chipco_watchdog_get_max_timer(cc);
481 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
482 + if (ticks == 1)
483 + ticks = 2;
484 + else if (ticks > maxt)
485 + ticks = maxt;
486 + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
487 + } else {
488 + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
489 + bcma_core_set_clockmode(cc->core, clkmode);
490 + if (ticks > maxt)
491 + ticks = maxt;
492 + /* instant NMI */
493 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
494 + }
495 + return ticks;
496 }
497
498 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
499 @@ -84,28 +212,99 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
500
501 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
502 {
503 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
504 + unsigned long flags;
505 + u32 res;
506 +
507 + spin_lock_irqsave(&cc->gpio_lock, flags);
508 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
509 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
510 +
511 + return res;
512 }
513 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
514
515 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
516 {
517 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
518 + unsigned long flags;
519 + u32 res;
520 +
521 + spin_lock_irqsave(&cc->gpio_lock, flags);
522 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
523 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
524 +
525 + return res;
526 }
527 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
528
529 +/*
530 + * If the bit is set to 0, chipcommon controlls this GPIO,
531 + * if the bit is set to 1, it is used by some part of the chip and not our code.
532 + */
533 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
534 {
535 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
536 + unsigned long flags;
537 + u32 res;
538 +
539 + spin_lock_irqsave(&cc->gpio_lock, flags);
540 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
541 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
542 +
543 + return res;
544 }
545 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
546
547 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
548 {
549 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
550 + unsigned long flags;
551 + u32 res;
552 +
553 + spin_lock_irqsave(&cc->gpio_lock, flags);
554 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
555 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
556 +
557 + return res;
558 }
559
560 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
561 {
562 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
563 + unsigned long flags;
564 + u32 res;
565 +
566 + spin_lock_irqsave(&cc->gpio_lock, flags);
567 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
568 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
569 +
570 + return res;
571 +}
572 +
573 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
574 +{
575 + unsigned long flags;
576 + u32 res;
577 +
578 + if (cc->core->id.rev < 20)
579 + return 0;
580 +
581 + spin_lock_irqsave(&cc->gpio_lock, flags);
582 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
583 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
584 +
585 + return res;
586 +}
587 +
588 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
589 +{
590 + unsigned long flags;
591 + u32 res;
592 +
593 + if (cc->core->id.rev < 20)
594 + return 0;
595 +
596 + spin_lock_irqsave(&cc->gpio_lock, flags);
597 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
598 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
599 +
600 + return res;
601 }
602
603 #ifdef CONFIG_BCMA_DRIVER_MIPS
604 @@ -118,8 +317,7 @@ void bcma_chipco_serial_init(struct bcma
605 struct bcma_serial_port *ports = cc->serial_ports;
606
607 if (ccrev >= 11 && ccrev != 15) {
608 - /* Fixed ALP clock */
609 - baud_base = bcma_pmu_alp_clock(cc);
610 + baud_base = bcma_chipco_get_alp_clock(cc);
611 if (ccrev >= 21) {
612 /* Turn off UART clock before switching clocksource. */
613 bcma_cc_write32(cc, BCMA_CC_CORECTL,
614 @@ -137,12 +335,11 @@ void bcma_chipco_serial_init(struct bcma
615 | BCMA_CC_CORECTL_UARTCLKEN);
616 }
617 } else {
618 - pr_err("serial not supported on this device ccrev: 0x%x\n",
619 - ccrev);
620 + bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
621 return;
622 }
623
624 - irq = bcma_core_mips_irq(cc->core);
625 + irq = bcma_core_irq(cc->core);
626
627 /* Determine the registers of the UARTs */
628 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
629 --- /dev/null
630 +++ b/drivers/bcma/driver_chipcommon_nflash.c
631 @@ -0,0 +1,44 @@
632 +/*
633 + * Broadcom specific AMBA
634 + * ChipCommon NAND flash interface
635 + *
636 + * Licensed under the GNU/GPL. See COPYING for details.
637 + */
638 +
639 +#include "bcma_private.h"
640 +
641 +#include <linux/platform_device.h>
642 +#include <linux/bcma/bcma.h>
643 +
644 +struct platform_device bcma_nflash_dev = {
645 + .name = "bcma_nflash",
646 + .num_resources = 0,
647 +};
648 +
649 +/* Initialize NAND flash access */
650 +int bcma_nflash_init(struct bcma_drv_cc *cc)
651 +{
652 + struct bcma_bus *bus = cc->core->bus;
653 +
654 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
655 + cc->core->id.rev != 38) {
656 + bcma_err(bus, "NAND flash on unsupported board!\n");
657 + return -ENOTSUPP;
658 + }
659 +
660 + if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) {
661 + bcma_err(bus, "NAND flash not present according to ChipCommon\n");
662 + return -ENODEV;
663 + }
664 +
665 + cc->nflash.present = true;
666 + if (cc->core->id.rev == 38 &&
667 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
668 + cc->nflash.boot = true;
669 +
670 + /* Prepare platform device, but don't register it yet. It's too early,
671 + * malloc (required by device_private_init) is not available yet. */
672 + bcma_nflash_dev.dev.platform_data = &cc->nflash;
673 +
674 + return 0;
675 +}
676 --- a/drivers/bcma/driver_chipcommon_pmu.c
677 +++ b/drivers/bcma/driver_chipcommon_pmu.c
678 @@ -3,7 +3,8 @@
679 * ChipCommon Power Management Unit driver
680 *
681 * Copyright 2009, Michael Buesch <m@bues.ch>
682 - * Copyright 2007, Broadcom Corporation
683 + * Copyright 2007, 2011, Broadcom Corporation
684 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
685 *
686 * Licensed under the GNU/GPL. See COPYING for details.
687 */
688 @@ -12,12 +13,13 @@
689 #include <linux/export.h>
690 #include <linux/bcma/bcma.h>
691
692 -static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
693 +u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
694 {
695 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
696 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
697 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
698 }
699 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
700
701 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
702 {
703 @@ -54,19 +56,106 @@ void bcma_chipco_regctl_maskset(struct b
704 }
705 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
706
707 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
708 +{
709 + u32 ilp_ctl, alp_hz;
710 +
711 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
712 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
713 + return 0;
714 +
715 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
716 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
717 + usleep_range(1000, 2000);
718 +
719 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
720 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
721 +
722 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
723 +
724 + alp_hz = ilp_ctl * 32768 / 4;
725 + return (alp_hz + 50000) / 100000 * 100;
726 +}
727 +
728 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
729 +{
730 + struct bcma_bus *bus = cc->core->bus;
731 + u32 freq_tgt_target = 0, freq_tgt_current;
732 + u32 pll0, mask;
733 +
734 + switch (bus->chipinfo.id) {
735 + case BCMA_CHIP_ID_BCM43142:
736 + /* pmu2_xtaltab0_adfll_485 */
737 + switch (xtalfreq) {
738 + case 12000:
739 + freq_tgt_target = 0x50D52;
740 + break;
741 + case 20000:
742 + freq_tgt_target = 0x307FE;
743 + break;
744 + case 26000:
745 + freq_tgt_target = 0x254EA;
746 + break;
747 + case 37400:
748 + freq_tgt_target = 0x19EF8;
749 + break;
750 + case 52000:
751 + freq_tgt_target = 0x12A75;
752 + break;
753 + }
754 + break;
755 + }
756 +
757 + if (!freq_tgt_target) {
758 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
759 + xtalfreq);
760 + return;
761 + }
762 +
763 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
764 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
765 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
766 +
767 + if (freq_tgt_current == freq_tgt_target) {
768 + bcma_debug(bus, "Target TGT frequency already set\n");
769 + return;
770 + }
771 +
772 + /* Turn off PLL */
773 + switch (bus->chipinfo.id) {
774 + case BCMA_CHIP_ID_BCM43142:
775 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
776 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
777 +
778 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
779 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
780 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
781 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
782 + break;
783 + }
784 +
785 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
786 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
787 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
788 +
789 + /* Flush */
790 + if (cc->pmu.rev >= 2)
791 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
792 +
793 + /* TODO: Do we need to update OTP? */
794 +}
795 +
796 static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
797 {
798 struct bcma_bus *bus = cc->core->bus;
799 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
800
801 switch (bus->chipinfo.id) {
802 - case 0x4313:
803 - case 0x4331:
804 - case 43224:
805 - case 43225:
806 + case BCMA_CHIP_ID_BCM43142:
807 + if (xtalfreq == 0)
808 + xtalfreq = 20000;
809 + bcma_pmu2_pll_init0(cc, xtalfreq);
810 break;
811 - default:
812 - pr_err("PLL init unknown for device 0x%04X\n",
813 - bus->chipinfo.id);
814 }
815 }
816
817 @@ -76,16 +165,32 @@ static void bcma_pmu_resources_init(stru
818 u32 min_msk = 0, max_msk = 0;
819
820 switch (bus->chipinfo.id) {
821 - case 0x4313:
822 + case BCMA_CHIP_ID_BCM4313:
823 min_msk = 0x200D;
824 max_msk = 0xFFFF;
825 break;
826 - case 43224:
827 - case 43225:
828 + case BCMA_CHIP_ID_BCM43142:
829 + min_msk = BCMA_RES_4314_LPLDO_PU |
830 + BCMA_RES_4314_PMU_SLEEP_DIS |
831 + BCMA_RES_4314_PMU_BG_PU |
832 + BCMA_RES_4314_CBUCK_LPOM_PU |
833 + BCMA_RES_4314_CBUCK_PFM_PU |
834 + BCMA_RES_4314_CLDO_PU |
835 + BCMA_RES_4314_LPLDO2_LVM |
836 + BCMA_RES_4314_WL_PMU_PU |
837 + BCMA_RES_4314_LDO3P3_PU |
838 + BCMA_RES_4314_OTP_PU |
839 + BCMA_RES_4314_WL_PWRSW_PU |
840 + BCMA_RES_4314_LQ_AVAIL |
841 + BCMA_RES_4314_LOGIC_RET |
842 + BCMA_RES_4314_MEM_SLEEP |
843 + BCMA_RES_4314_MACPHY_RET |
844 + BCMA_RES_4314_WL_CORE_READY;
845 + max_msk = 0x3FFFFFFF;
846 break;
847 default:
848 - pr_err("PMU resource config unknown for device 0x%04X\n",
849 - bus->chipinfo.id);
850 + bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
851 + bus->chipinfo.id);
852 }
853
854 /* Set the resource masks. */
855 @@ -93,22 +198,12 @@ static void bcma_pmu_resources_init(stru
856 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
857 if (max_msk)
858 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
859 -}
860
861 -void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
862 -{
863 - struct bcma_bus *bus = cc->core->bus;
864 -
865 - switch (bus->chipinfo.id) {
866 - case 0x4313:
867 - case 0x4331:
868 - case 43224:
869 - case 43225:
870 - break;
871 - default:
872 - pr_err("PMU switch/regulators init unknown for device "
873 - "0x%04X\n", bus->chipinfo.id);
874 - }
875 + /*
876 + * Add some delay; allow resources to come up and settle.
877 + * Delay is required for SoC (early init).
878 + */
879 + mdelay(2);
880 }
881
882 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
883 @@ -122,51 +217,69 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
884 val |= BCMA_CHIPCTL_4331_EXTPA_EN;
885 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
886 val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
887 + else if (bus->chipinfo.rev > 0)
888 + val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
889 } else {
890 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
891 + val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
892 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
893 }
894 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
895 }
896
897 -void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
898 +static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
899 {
900 struct bcma_bus *bus = cc->core->bus;
901
902 switch (bus->chipinfo.id) {
903 - case 0x4313:
904 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
905 + case BCMA_CHIP_ID_BCM4313:
906 + /* enable 12 mA drive strenth for 4313 and set chipControl
907 + register bit 1 */
908 + bcma_chipco_chipctl_maskset(cc, 0,
909 + ~BCMA_CCTRL_4313_12MA_LED_DRIVE,
910 + BCMA_CCTRL_4313_12MA_LED_DRIVE);
911 break;
912 - case 0x4331:
913 - /* BCM4331 workaround is SPROM-related, we put it in sprom.c */
914 + case BCMA_CHIP_ID_BCM4331:
915 + case BCMA_CHIP_ID_BCM43431:
916 + /* Ext PA lines must be enabled for tx on BCM4331 */
917 + bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
918 break;
919 - case 43224:
920 + case BCMA_CHIP_ID_BCM43224:
921 + case BCMA_CHIP_ID_BCM43421:
922 + /* enable 12 mA drive strenth for 43224 and set chipControl
923 + register bit 15 */
924 if (bus->chipinfo.rev == 0) {
925 - pr_err("Workarounds for 43224 rev 0 not fully "
926 - "implemented\n");
927 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
928 + bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
929 + ~BCMA_CCTRL_43224_GPIO_TOGGLE,
930 + BCMA_CCTRL_43224_GPIO_TOGGLE);
931 + bcma_chipco_chipctl_maskset(cc, 0,
932 + ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
933 + BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
934 } else {
935 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
936 + bcma_chipco_chipctl_maskset(cc, 0,
937 + ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
938 + BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
939 }
940 break;
941 - case 43225:
942 - break;
943 default:
944 - pr_err("Workarounds unknown for device 0x%04X\n",
945 - bus->chipinfo.id);
946 + bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
947 + bus->chipinfo.id);
948 }
949 }
950
951 -void bcma_pmu_init(struct bcma_drv_cc *cc)
952 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
953 {
954 u32 pmucap;
955
956 pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
957 cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
958
959 - pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
960 - pmucap);
961 + bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
962 + cc->pmu.rev, pmucap);
963 +}
964
965 +void bcma_pmu_init(struct bcma_drv_cc *cc)
966 +{
967 if (cc->pmu.rev == 1)
968 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
969 ~BCMA_CC_PMU_CTL_NOILPONW);
970 @@ -174,37 +287,48 @@ void bcma_pmu_init(struct bcma_drv_cc *c
971 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
972 BCMA_CC_PMU_CTL_NOILPONW);
973
974 - if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
975 - pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
976 -
977 bcma_pmu_pll_init(cc);
978 bcma_pmu_resources_init(cc);
979 - bcma_pmu_swreg_init(cc);
980 bcma_pmu_workarounds(cc);
981 }
982
983 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
984 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
985 {
986 struct bcma_bus *bus = cc->core->bus;
987
988 switch (bus->chipinfo.id) {
989 - case 0x4716:
990 - case 0x4748:
991 - case 47162:
992 - case 0x4313:
993 - case 0x5357:
994 - case 0x4749:
995 - case 53572:
996 + case BCMA_CHIP_ID_BCM4313:
997 + case BCMA_CHIP_ID_BCM43224:
998 + case BCMA_CHIP_ID_BCM43225:
999 + case BCMA_CHIP_ID_BCM43227:
1000 + case BCMA_CHIP_ID_BCM43228:
1001 + case BCMA_CHIP_ID_BCM4331:
1002 + case BCMA_CHIP_ID_BCM43421:
1003 + case BCMA_CHIP_ID_BCM43428:
1004 + case BCMA_CHIP_ID_BCM43431:
1005 + case BCMA_CHIP_ID_BCM4716:
1006 + case BCMA_CHIP_ID_BCM47162:
1007 + case BCMA_CHIP_ID_BCM4748:
1008 + case BCMA_CHIP_ID_BCM4749:
1009 + case BCMA_CHIP_ID_BCM5357:
1010 + case BCMA_CHIP_ID_BCM53572:
1011 + case BCMA_CHIP_ID_BCM6362:
1012 /* always 20Mhz */
1013 return 20000 * 1000;
1014 - case 0x5356:
1015 - case 0x5300:
1016 + case BCMA_CHIP_ID_BCM4706:
1017 + case BCMA_CHIP_ID_BCM5356:
1018 /* always 25Mhz */
1019 return 25000 * 1000;
1020 + case BCMA_CHIP_ID_BCM43460:
1021 + case BCMA_CHIP_ID_BCM4352:
1022 + case BCMA_CHIP_ID_BCM4360:
1023 + if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
1024 + return 40000 * 1000;
1025 + else
1026 + return 20000 * 1000;
1027 default:
1028 - pr_warn("No ALP clock specified for %04X device, "
1029 - "pmu rev. %d, using default %d Hz\n",
1030 - bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
1031 + bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
1032 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
1033 }
1034 return BCMA_CC_PMU_ALP_CLOCK;
1035 }
1036 @@ -212,7 +336,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
1037 /* Find the output of the "m" pll divider given pll controls that start with
1038 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
1039 */
1040 -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
1041 +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
1042 {
1043 u32 tmp, div, ndiv, p1, p2, fc;
1044 struct bcma_bus *bus = cc->core->bus;
1045 @@ -221,7 +345,8 @@ static u32 bcma_pmu_clock(struct bcma_dr
1046
1047 BUG_ON(!m || m > 4);
1048
1049 - if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
1050 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
1051 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
1052 /* Detect failure in clock setting */
1053 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
1054 if (tmp & 0x40000)
1055 @@ -240,60 +365,96 @@ static u32 bcma_pmu_clock(struct bcma_dr
1056 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
1057
1058 /* Do calculation in Mhz */
1059 - fc = bcma_pmu_alp_clock(cc) / 1000000;
1060 + fc = bcma_pmu_get_alp_clock(cc) / 1000000;
1061 fc = (p1 * ndiv * fc) / p2;
1062
1063 /* Return clock in Hertz */
1064 return (fc / div) * 1000000;
1065 }
1066
1067 +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
1068 +{
1069 + u32 tmp, ndiv, p1div, p2div;
1070 + u32 clock;
1071 +
1072 + BUG_ON(!m || m > 4);
1073 +
1074 + /* Get N, P1 and P2 dividers to determine CPU clock */
1075 + tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
1076 + ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
1077 + >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
1078 + p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
1079 + >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
1080 + p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
1081 + >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
1082 +
1083 + tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
1084 + if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
1085 + /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
1086 + clock = (25000000 / 4) * ndiv * p2div / p1div;
1087 + else
1088 + /* Fixed reference clock 25MHz and m = 2 */
1089 + clock = (25000000 / 2) * ndiv * p2div / p1div;
1090 +
1091 + if (m == BCMA_CC_PMU5_MAINPLL_SSB)
1092 + clock = clock / 4;
1093 +
1094 + return clock;
1095 +}
1096 +
1097 /* query bus clock frequency for PMU-enabled chipcommon */
1098 -u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
1099 +u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
1100 {
1101 struct bcma_bus *bus = cc->core->bus;
1102
1103 switch (bus->chipinfo.id) {
1104 - case 0x4716:
1105 - case 0x4748:
1106 - case 47162:
1107 - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
1108 - BCMA_CC_PMU5_MAINPLL_SSB);
1109 - case 0x5356:
1110 - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
1111 - BCMA_CC_PMU5_MAINPLL_SSB);
1112 - case 0x5357:
1113 - case 0x4749:
1114 - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
1115 - BCMA_CC_PMU5_MAINPLL_SSB);
1116 - case 0x5300:
1117 - return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
1118 - BCMA_CC_PMU5_MAINPLL_SSB);
1119 - case 53572:
1120 + case BCMA_CHIP_ID_BCM4716:
1121 + case BCMA_CHIP_ID_BCM4748:
1122 + case BCMA_CHIP_ID_BCM47162:
1123 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
1124 + BCMA_CC_PMU5_MAINPLL_SSB);
1125 + case BCMA_CHIP_ID_BCM5356:
1126 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
1127 + BCMA_CC_PMU5_MAINPLL_SSB);
1128 + case BCMA_CHIP_ID_BCM5357:
1129 + case BCMA_CHIP_ID_BCM4749:
1130 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
1131 + BCMA_CC_PMU5_MAINPLL_SSB);
1132 + case BCMA_CHIP_ID_BCM4706:
1133 + return bcma_pmu_pll_clock_bcm4706(cc,
1134 + BCMA_CC_PMU4706_MAINPLL_PLL0,
1135 + BCMA_CC_PMU5_MAINPLL_SSB);
1136 + case BCMA_CHIP_ID_BCM53572:
1137 return 75000000;
1138 default:
1139 - pr_warn("No backplane clock specified for %04X device, "
1140 - "pmu rev. %d, using default %d Hz\n",
1141 - bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
1142 + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
1143 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
1144 }
1145 return BCMA_CC_PMU_HT_CLOCK;
1146 }
1147 +EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);
1148
1149 /* query cpu clock frequency for PMU-enabled chipcommon */
1150 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
1151 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
1152 {
1153 struct bcma_bus *bus = cc->core->bus;
1154
1155 - if (bus->chipinfo.id == 53572)
1156 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
1157 return 300000000;
1158
1159 + /* New PMUs can have different clock for bus and CPU */
1160 if (cc->pmu.rev >= 5) {
1161 u32 pll;
1162 switch (bus->chipinfo.id) {
1163 - case 0x5356:
1164 + case BCMA_CHIP_ID_BCM4706:
1165 + return bcma_pmu_pll_clock_bcm4706(cc,
1166 + BCMA_CC_PMU4706_MAINPLL_PLL0,
1167 + BCMA_CC_PMU5_MAINPLL_CPU);
1168 + case BCMA_CHIP_ID_BCM5356:
1169 pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
1170 break;
1171 - case 0x5357:
1172 - case 0x4749:
1173 + case BCMA_CHIP_ID_BCM5357:
1174 + case BCMA_CHIP_ID_BCM4749:
1175 pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
1176 break;
1177 default:
1178 @@ -301,10 +462,189 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
1179 break;
1180 }
1181
1182 - /* TODO: if (bus->chipinfo.id == 0x5300)
1183 - return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
1184 - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
1185 + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
1186 + }
1187 +
1188 + /* On old PMUs CPU has the same clock as the bus */
1189 + return bcma_pmu_get_bus_clock(cc);
1190 +}
1191 +
1192 +static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
1193 + u32 value)
1194 +{
1195 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
1196 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
1197 +}
1198 +
1199 +void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
1200 +{
1201 + u32 tmp = 0;
1202 + u8 phypll_offset = 0;
1203 + u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
1204 + u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
1205 + struct bcma_bus *bus = cc->core->bus;
1206 +
1207 + switch (bus->chipinfo.id) {
1208 + case BCMA_CHIP_ID_BCM5357:
1209 + case BCMA_CHIP_ID_BCM4749:
1210 + case BCMA_CHIP_ID_BCM53572:
1211 + /* 5357[ab]0, 43236[ab]0, and 6362b0 */
1212 +
1213 + /* BCM5357 needs to touch PLL1_PLLCTL[02],
1214 + so offset PLL0_PLLCTL[02] by 6 */
1215 + phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
1216 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
1217 + bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
1218 +
1219 + /* RMW only the P1 divider */
1220 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
1221 + BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
1222 + tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
1223 + tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
1224 + tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
1225 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
1226 +
1227 + /* RMW only the int feedback divider */
1228 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
1229 + BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
1230 + tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
1231 + tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
1232 + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
1233 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
1234 +
1235 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
1236 + break;
1237 +
1238 + case BCMA_CHIP_ID_BCM4331:
1239 + case BCMA_CHIP_ID_BCM43431:
1240 + if (spuravoid == 2) {
1241 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1242 + 0x11500014);
1243 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1244 + 0x0FC00a08);
1245 + } else if (spuravoid == 1) {
1246 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1247 + 0x11500014);
1248 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1249 + 0x0F600a08);
1250 + } else {
1251 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1252 + 0x11100014);
1253 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1254 + 0x03000a08);
1255 + }
1256 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
1257 + break;
1258 +
1259 + case BCMA_CHIP_ID_BCM43224:
1260 + case BCMA_CHIP_ID_BCM43225:
1261 + case BCMA_CHIP_ID_BCM43421:
1262 + if (spuravoid == 1) {
1263 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1264 + 0x11500010);
1265 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1266 + 0x000C0C06);
1267 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1268 + 0x0F600a08);
1269 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1270 + 0x00000000);
1271 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1272 + 0x2001E920);
1273 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1274 + 0x88888815);
1275 + } else {
1276 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1277 + 0x11100010);
1278 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1279 + 0x000c0c06);
1280 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1281 + 0x03000a08);
1282 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1283 + 0x00000000);
1284 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1285 + 0x200005c0);
1286 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1287 + 0x88888815);
1288 + }
1289 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
1290 + break;
1291 +
1292 + case BCMA_CHIP_ID_BCM4716:
1293 + case BCMA_CHIP_ID_BCM4748:
1294 + case BCMA_CHIP_ID_BCM47162:
1295 + if (spuravoid == 1) {
1296 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1297 + 0x11500060);
1298 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1299 + 0x080C0C06);
1300 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1301 + 0x0F600000);
1302 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1303 + 0x00000000);
1304 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1305 + 0x2001E924);
1306 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1307 + 0x88888815);
1308 + } else {
1309 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1310 + 0x11100060);
1311 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1312 + 0x080c0c06);
1313 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1314 + 0x03000000);
1315 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1316 + 0x00000000);
1317 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1318 + 0x200005c0);
1319 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1320 + 0x88888815);
1321 + }
1322 +
1323 + tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
1324 + break;
1325 +
1326 + case BCMA_CHIP_ID_BCM43227:
1327 + case BCMA_CHIP_ID_BCM43228:
1328 + case BCMA_CHIP_ID_BCM43428:
1329 + /* LCNXN */
1330 + /* PLL Settings for spur avoidance on/off mode,
1331 + no on2 support for 43228A0 */
1332 + if (spuravoid == 1) {
1333 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1334 + 0x01100014);
1335 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1336 + 0x040C0C06);
1337 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1338 + 0x03140A08);
1339 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1340 + 0x00333333);
1341 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1342 + 0x202C2820);
1343 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1344 + 0x88888815);
1345 + } else {
1346 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1347 + 0x11100014);
1348 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1349 + 0x040c0c06);
1350 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1351 + 0x03000a08);
1352 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1353 + 0x00000000);
1354 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1355 + 0x200005c0);
1356 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1357 + 0x88888815);
1358 + }
1359 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
1360 + break;
1361 + default:
1362 + bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
1363 + bus->chipinfo.id);
1364 + break;
1365 }
1366
1367 - return bcma_pmu_get_clockcontrol(cc);
1368 + tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
1369 + bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
1370 }
1371 +EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
1372 --- /dev/null
1373 +++ b/drivers/bcma/driver_chipcommon_sflash.c
1374 @@ -0,0 +1,165 @@
1375 +/*
1376 + * Broadcom specific AMBA
1377 + * ChipCommon serial flash interface
1378 + *
1379 + * Licensed under the GNU/GPL. See COPYING for details.
1380 + */
1381 +
1382 +#include "bcma_private.h"
1383 +
1384 +#include <linux/platform_device.h>
1385 +#include <linux/bcma/bcma.h>
1386 +
1387 +static struct resource bcma_sflash_resource = {
1388 + .name = "bcma_sflash",
1389 + .start = BCMA_SOC_FLASH2,
1390 + .end = 0,
1391 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
1392 +};
1393 +
1394 +struct platform_device bcma_sflash_dev = {
1395 + .name = "bcma_sflash",
1396 + .resource = &bcma_sflash_resource,
1397 + .num_resources = 1,
1398 +};
1399 +
1400 +struct bcma_sflash_tbl_e {
1401 + char *name;
1402 + u32 id;
1403 + u32 blocksize;
1404 + u16 numblocks;
1405 +};
1406 +
1407 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
1408 + { "M25P20", 0x11, 0x10000, 4, },
1409 + { "M25P40", 0x12, 0x10000, 8, },
1410 +
1411 + { "M25P16", 0x14, 0x10000, 32, },
1412 + { "M25P32", 0x15, 0x10000, 64, },
1413 + { "M25P64", 0x16, 0x10000, 128, },
1414 + { "M25FL128", 0x17, 0x10000, 256, },
1415 + { 0 },
1416 +};
1417 +
1418 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
1419 + { "SST25WF512", 1, 0x1000, 16, },
1420 + { "SST25VF512", 0x48, 0x1000, 16, },
1421 + { "SST25WF010", 2, 0x1000, 32, },
1422 + { "SST25VF010", 0x49, 0x1000, 32, },
1423 + { "SST25WF020", 3, 0x1000, 64, },
1424 + { "SST25VF020", 0x43, 0x1000, 64, },
1425 + { "SST25WF040", 4, 0x1000, 128, },
1426 + { "SST25VF040", 0x44, 0x1000, 128, },
1427 + { "SST25VF040B", 0x8d, 0x1000, 128, },
1428 + { "SST25WF080", 5, 0x1000, 256, },
1429 + { "SST25VF080B", 0x8e, 0x1000, 256, },
1430 + { "SST25VF016", 0x41, 0x1000, 512, },
1431 + { "SST25VF032", 0x4a, 0x1000, 1024, },
1432 + { "SST25VF064", 0x4b, 0x1000, 2048, },
1433 + { 0 },
1434 +};
1435 +
1436 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
1437 + { "AT45DB011", 0xc, 256, 512, },
1438 + { "AT45DB021", 0x14, 256, 1024, },
1439 + { "AT45DB041", 0x1c, 256, 2048, },
1440 + { "AT45DB081", 0x24, 256, 4096, },
1441 + { "AT45DB161", 0x2c, 512, 4096, },
1442 + { "AT45DB321", 0x34, 512, 8192, },
1443 + { "AT45DB642", 0x3c, 1024, 8192, },
1444 + { 0 },
1445 +};
1446 +
1447 +static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
1448 +{
1449 + int i;
1450 + bcma_cc_write32(cc, BCMA_CC_FLASHCTL,
1451 + BCMA_CC_FLASHCTL_START | opcode);
1452 + for (i = 0; i < 1000; i++) {
1453 + if (!(bcma_cc_read32(cc, BCMA_CC_FLASHCTL) &
1454 + BCMA_CC_FLASHCTL_BUSY))
1455 + return;
1456 + cpu_relax();
1457 + }
1458 + bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
1459 +}
1460 +
1461 +/* Initialize serial flash access */
1462 +int bcma_sflash_init(struct bcma_drv_cc *cc)
1463 +{
1464 + struct bcma_bus *bus = cc->core->bus;
1465 + struct bcma_sflash *sflash = &cc->sflash;
1466 + const struct bcma_sflash_tbl_e *e;
1467 + u32 id, id2;
1468 +
1469 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1470 + case BCMA_CC_FLASHT_STSER:
1471 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP);
1472 +
1473 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0);
1474 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
1475 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
1476 +
1477 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1);
1478 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
1479 + id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
1480 +
1481 + switch (id) {
1482 + case 0xbf:
1483 + for (e = bcma_sflash_sst_tbl; e->name; e++) {
1484 + if (e->id == id2)
1485 + break;
1486 + }
1487 + break;
1488 + case 0x13:
1489 + return -ENOTSUPP;
1490 + default:
1491 + for (e = bcma_sflash_st_tbl; e->name; e++) {
1492 + if (e->id == id)
1493 + break;
1494 + }
1495 + break;
1496 + }
1497 + if (!e->name) {
1498 + bcma_err(bus, "Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2);
1499 + return -ENOTSUPP;
1500 + }
1501 +
1502 + break;
1503 + case BCMA_CC_FLASHT_ATSER:
1504 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
1505 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c;
1506 +
1507 + for (e = bcma_sflash_at_tbl; e->name; e++) {
1508 + if (e->id == id)
1509 + break;
1510 + }
1511 + if (!e->name) {
1512 + bcma_err(bus, "Unsupported Atmel serial flash (id: 0x%X)\n", id);
1513 + return -ENOTSUPP;
1514 + }
1515 +
1516 + break;
1517 + default:
1518 + bcma_err(bus, "Unsupported flash type\n");
1519 + return -ENOTSUPP;
1520 + }
1521 +
1522 + sflash->window = BCMA_SOC_FLASH2;
1523 + sflash->blocksize = e->blocksize;
1524 + sflash->numblocks = e->numblocks;
1525 + sflash->size = sflash->blocksize * sflash->numblocks;
1526 + sflash->present = true;
1527 +
1528 + bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
1529 + e->name, sflash->size / 1024, sflash->blocksize,
1530 + sflash->numblocks);
1531 +
1532 + /* Prepare platform device, but don't register it yet. It's too early,
1533 + * malloc (required by device_private_init) is not available yet. */
1534 + bcma_sflash_dev.resource[0].end = bcma_sflash_dev.resource[0].start +
1535 + sflash->size;
1536 + bcma_sflash_dev.dev.platform_data = sflash;
1537 +
1538 + return 0;
1539 +}
1540 --- /dev/null
1541 +++ b/drivers/bcma/driver_gmac_cmn.c
1542 @@ -0,0 +1,14 @@
1543 +/*
1544 + * Broadcom specific AMBA
1545 + * GBIT MAC COMMON Core
1546 + *
1547 + * Licensed under the GNU/GPL. See COPYING for details.
1548 + */
1549 +
1550 +#include "bcma_private.h"
1551 +#include <linux/bcma/bcma.h>
1552 +
1553 +void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc)
1554 +{
1555 + mutex_init(&gc->phy_mutex);
1556 +}
1557 --- /dev/null
1558 +++ b/drivers/bcma/driver_gpio.c
1559 @@ -0,0 +1,114 @@
1560 +/*
1561 + * Broadcom specific AMBA
1562 + * GPIO driver
1563 + *
1564 + * Copyright 2011, Broadcom Corporation
1565 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
1566 + *
1567 + * Licensed under the GNU/GPL. See COPYING for details.
1568 + */
1569 +
1570 +#include <linux/gpio.h>
1571 +#include <linux/export.h>
1572 +#include <linux/bcma/bcma.h>
1573 +
1574 +#include "bcma_private.h"
1575 +
1576 +static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
1577 +{
1578 + return container_of(chip, struct bcma_drv_cc, gpio);
1579 +}
1580 +
1581 +static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1582 +{
1583 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1584 +
1585 + return !!bcma_chipco_gpio_in(cc, 1 << gpio);
1586 +}
1587 +
1588 +static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
1589 + int value)
1590 +{
1591 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1592 +
1593 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
1594 +}
1595 +
1596 +static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1597 +{
1598 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1599 +
1600 + bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
1601 + return 0;
1602 +}
1603 +
1604 +static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
1605 + int value)
1606 +{
1607 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1608 +
1609 + bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
1610 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
1611 + return 0;
1612 +}
1613 +
1614 +static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
1615 +{
1616 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1617 +
1618 + bcma_chipco_gpio_control(cc, 1 << gpio, 0);
1619 + /* clear pulldown */
1620 + bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
1621 + /* Set pullup */
1622 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
1623 +
1624 + return 0;
1625 +}
1626 +
1627 +static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
1628 +{
1629 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1630 +
1631 + /* clear pullup */
1632 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
1633 +}
1634 +
1635 +static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
1636 +{
1637 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1638 +
1639 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
1640 + return bcma_core_irq(cc->core);
1641 + else
1642 + return -EINVAL;
1643 +}
1644 +
1645 +int bcma_gpio_init(struct bcma_drv_cc *cc)
1646 +{
1647 + struct gpio_chip *chip = &cc->gpio;
1648 +
1649 + chip->label = "bcma_gpio";
1650 + chip->owner = THIS_MODULE;
1651 + chip->request = bcma_gpio_request;
1652 + chip->free = bcma_gpio_free;
1653 + chip->get = bcma_gpio_get_value;
1654 + chip->set = bcma_gpio_set_value;
1655 + chip->direction_input = bcma_gpio_direction_input;
1656 + chip->direction_output = bcma_gpio_direction_output;
1657 + chip->to_irq = bcma_gpio_to_irq;
1658 + chip->ngpio = 16;
1659 + /* There is just one SoC in one device and its GPIO addresses should be
1660 + * deterministic to address them more easily. The other buses could get
1661 + * a random base number. */
1662 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
1663 + chip->base = 0;
1664 + else
1665 + chip->base = -1;
1666 +
1667 + return gpiochip_add(chip);
1668 +}
1669 +
1670 +int bcma_gpio_unregister(struct bcma_drv_cc *cc)
1671 +{
1672 + return gpiochip_remove(&cc->gpio);
1673 +}
1674 --- a/drivers/bcma/driver_mips.c
1675 +++ b/drivers/bcma/driver_mips.c
1676 @@ -14,23 +14,45 @@
1677
1678 #include <linux/bcma/bcma.h>
1679
1680 +#include <linux/mtd/physmap.h>
1681 +#include <linux/platform_device.h>
1682 #include <linux/serial.h>
1683 #include <linux/serial_core.h>
1684 #include <linux/serial_reg.h>
1685 #include <linux/time.h>
1686
1687 +static const char * const part_probes[] = { "bcm47xxpart", NULL };
1688 +
1689 +static struct physmap_flash_data bcma_pflash_data = {
1690 + .part_probe_types = part_probes,
1691 +};
1692 +
1693 +static struct resource bcma_pflash_resource = {
1694 + .name = "bcma_pflash",
1695 + .flags = IORESOURCE_MEM,
1696 +};
1697 +
1698 +struct platform_device bcma_pflash_dev = {
1699 + .name = "physmap-flash",
1700 + .dev = {
1701 + .platform_data = &bcma_pflash_data,
1702 + },
1703 + .resource = &bcma_pflash_resource,
1704 + .num_resources = 1,
1705 +};
1706 +
1707 /* The 47162a0 hangs when reading MIPS DMP registers registers */
1708 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
1709 {
1710 - return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
1711 - dev->id.id == BCMA_CORE_MIPS_74K;
1712 + return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
1713 + dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
1714 }
1715
1716 /* The 5357b0 hangs when reading USB20H DMP registers */
1717 static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
1718 {
1719 - return (dev->bus->chipinfo.id == 0x5357 ||
1720 - dev->bus->chipinfo.id == 0x4749) &&
1721 + return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
1722 + dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
1723 dev->bus->chipinfo.pkg == 11 &&
1724 dev->id.id == BCMA_CORE_USB20_HOST;
1725 }
1726 @@ -74,28 +96,41 @@ static u32 bcma_core_mips_irqflag(struct
1727 return dev->core_index;
1728 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
1729
1730 - return flag & 0x1F;
1731 + if (flag)
1732 + return flag & 0x1F;
1733 + else
1734 + return 0x3f;
1735 }
1736
1737 /* Get the MIPS IRQ assignment for a specified device.
1738 * If unassigned, 0 is returned.
1739 + * If disabled, 5 is returned.
1740 + * If not supported, 6 is returned.
1741 */
1742 -unsigned int bcma_core_mips_irq(struct bcma_device *dev)
1743 +static unsigned int bcma_core_mips_irq(struct bcma_device *dev)
1744 {
1745 struct bcma_device *mdev = dev->bus->drv_mips.core;
1746 u32 irqflag;
1747 unsigned int irq;
1748
1749 irqflag = bcma_core_mips_irqflag(dev);
1750 + if (irqflag == 0x3f)
1751 + return 6;
1752
1753 - for (irq = 1; irq <= 4; irq++)
1754 + for (irq = 0; irq <= 4; irq++)
1755 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
1756 (1 << irqflag))
1757 return irq;
1758
1759 - return 0;
1760 + return 5;
1761 +}
1762 +
1763 +unsigned int bcma_core_irq(struct bcma_device *dev)
1764 +{
1765 + unsigned int mips_irq = bcma_core_mips_irq(dev);
1766 + return mips_irq <= 4 ? mips_irq + 2 : 0;
1767 }
1768 -EXPORT_SYMBOL(bcma_core_mips_irq);
1769 +EXPORT_SYMBOL(bcma_core_irq);
1770
1771 static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
1772 {
1773 @@ -114,8 +149,8 @@ static void bcma_core_mips_set_irq(struc
1774 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
1775 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
1776 ~(1 << irqflag));
1777 - else
1778 - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
1779 + else if (oldirq != 5)
1780 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
1781
1782 /* assign the new one */
1783 if (irq == 0) {
1784 @@ -123,17 +158,17 @@ static void bcma_core_mips_set_irq(struc
1785 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
1786 (1 << irqflag));
1787 } else {
1788 - u32 oldirqflag = bcma_read32(mdev,
1789 - BCMA_MIPS_MIPS74K_INTMASK(irq));
1790 - if (oldirqflag) {
1791 + u32 irqinitmask = bcma_read32(mdev,
1792 + BCMA_MIPS_MIPS74K_INTMASK(irq));
1793 + if (irqinitmask) {
1794 struct bcma_device *core;
1795
1796 /* backplane irq line is in use, find out who uses
1797 * it and set user to irq 0
1798 */
1799 - list_for_each_entry_reverse(core, &bus->cores, list) {
1800 + list_for_each_entry(core, &bus->cores, list) {
1801 if ((1 << bcma_core_mips_irqflag(core)) ==
1802 - oldirqflag) {
1803 + irqinitmask) {
1804 bcma_core_mips_set_irq(core, 0);
1805 break;
1806 }
1807 @@ -143,15 +178,31 @@ static void bcma_core_mips_set_irq(struc
1808 1 << irqflag);
1809 }
1810
1811 - pr_info("set_irq: core 0x%04x, irq %d => %d\n",
1812 - dev->id.id, oldirq + 2, irq + 2);
1813 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
1814 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
1815 +}
1816 +
1817 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
1818 + u16 coreid, u8 unit)
1819 +{
1820 + struct bcma_device *core;
1821 +
1822 + core = bcma_find_core_unit(bus, coreid, unit);
1823 + if (!core) {
1824 + bcma_warn(bus,
1825 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
1826 + coreid, unit);
1827 + return;
1828 + }
1829 +
1830 + bcma_core_mips_set_irq(core, irq);
1831 }
1832
1833 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
1834 {
1835 int i;
1836 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1837 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1838 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1839 for (i = 0; i <= 6; i++)
1840 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
1841 printk("\n");
1842 @@ -161,7 +212,7 @@ static void bcma_core_mips_dump_irq(stru
1843 {
1844 struct bcma_device *core;
1845
1846 - list_for_each_entry_reverse(core, &bus->cores, list) {
1847 + list_for_each_entry(core, &bus->cores, list) {
1848 bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
1849 }
1850 }
1851 @@ -171,9 +222,9 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
1852 struct bcma_bus *bus = mcore->core->bus;
1853
1854 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
1855 - return bcma_pmu_get_clockcpu(&bus->drv_cc);
1856 + return bcma_pmu_get_cpu_clock(&bus->drv_cc);
1857
1858 - pr_err("No PMU available, need this to get the cpu clock\n");
1859 + bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
1860 return 0;
1861 }
1862 EXPORT_SYMBOL(bcma_cpu_clock);
1863 @@ -181,25 +232,81 @@ EXPORT_SYMBOL(bcma_cpu_clock);
1864 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
1865 {
1866 struct bcma_bus *bus = mcore->core->bus;
1867 + struct bcma_drv_cc *cc = &bus->drv_cc;
1868 + struct bcma_pflash *pflash = &cc->pflash;
1869
1870 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
1871 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1872 case BCMA_CC_FLASHT_STSER:
1873 case BCMA_CC_FLASHT_ATSER:
1874 - pr_err("Serial flash not supported.\n");
1875 + bcma_debug(bus, "Found serial flash\n");
1876 + bcma_sflash_init(cc);
1877 break;
1878 case BCMA_CC_FLASHT_PARA:
1879 - pr_info("found parallel flash.\n");
1880 - bus->drv_cc.pflash.window = 0x1c000000;
1881 - bus->drv_cc.pflash.window_size = 0x02000000;
1882 + bcma_debug(bus, "Found parallel flash\n");
1883 + pflash->present = true;
1884 + pflash->window = BCMA_SOC_FLASH2;
1885 + pflash->window_size = BCMA_SOC_FLASH2_SZ;
1886
1887 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
1888 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
1889 BCMA_CC_FLASH_CFG_DS) == 0)
1890 - bus->drv_cc.pflash.buswidth = 1;
1891 + pflash->buswidth = 1;
1892 else
1893 - bus->drv_cc.pflash.buswidth = 2;
1894 + pflash->buswidth = 2;
1895 +
1896 + bcma_pflash_data.width = pflash->buswidth;
1897 + bcma_pflash_resource.start = pflash->window;
1898 + bcma_pflash_resource.end = pflash->window + pflash->window_size;
1899 +
1900 break;
1901 default:
1902 - pr_err("flash not supported.\n");
1903 + bcma_err(bus, "Flash type not supported\n");
1904 + }
1905 +
1906 + if (cc->core->id.rev == 38 ||
1907 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
1908 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
1909 + bcma_debug(bus, "Found NAND flash\n");
1910 + bcma_nflash_init(cc);
1911 + }
1912 + }
1913 +}
1914 +
1915 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
1916 +{
1917 + struct bcma_bus *bus = mcore->core->bus;
1918 +
1919 + if (mcore->early_setup_done)
1920 + return;
1921 +
1922 + bcma_chipco_serial_init(&bus->drv_cc);
1923 + bcma_core_mips_flash_detect(mcore);
1924 +
1925 + mcore->early_setup_done = true;
1926 +}
1927 +
1928 +static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
1929 +{
1930 + struct bcma_device *cpu, *pcie, *i2s;
1931 +
1932 + /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
1933 + * (IRQ flags > 7 are ignored when setting the interrupt masks)
1934 + */
1935 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
1936 + bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
1937 + return;
1938 +
1939 + cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1940 + pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
1941 + i2s = bcma_find_core(bus, BCMA_CORE_I2S);
1942 + if (cpu && pcie && i2s &&
1943 + bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
1944 + bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
1945 + bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
1946 + bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
1947 + bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
1948 + bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
1949 + bcma_debug(bus,
1950 + "Moved i2s interrupt to oob line 7 instead of 8\n");
1951 }
1952 }
1953
1954 @@ -209,48 +316,59 @@ void bcma_core_mips_init(struct bcma_drv
1955 struct bcma_device *core;
1956 bus = mcore->core->bus;
1957
1958 - pr_info("Initializing MIPS core...\n");
1959 + if (mcore->setup_done)
1960 + return;
1961
1962 - if (!mcore->setup_done)
1963 - mcore->assigned_irqs = 1;
1964 + bcma_debug(bus, "Initializing MIPS core...\n");
1965
1966 - /* Assign IRQs to all cores on the bus */
1967 - list_for_each_entry_reverse(core, &bus->cores, list) {
1968 - int mips_irq;
1969 - if (core->irq)
1970 - continue;
1971 -
1972 - mips_irq = bcma_core_mips_irq(core);
1973 - if (mips_irq > 4)
1974 - core->irq = 0;
1975 - else
1976 - core->irq = mips_irq + 2;
1977 - if (core->irq > 5)
1978 - continue;
1979 - switch (core->id.id) {
1980 - case BCMA_CORE_PCI:
1981 - case BCMA_CORE_PCIE:
1982 - case BCMA_CORE_ETHERNET:
1983 - case BCMA_CORE_ETHERNET_GBIT:
1984 - case BCMA_CORE_MAC_GBIT:
1985 - case BCMA_CORE_80211:
1986 - case BCMA_CORE_USB20_HOST:
1987 - /* These devices get their own IRQ line if available,
1988 - * the rest goes on IRQ0
1989 - */
1990 - if (mcore->assigned_irqs <= 4)
1991 - bcma_core_mips_set_irq(core,
1992 - mcore->assigned_irqs++);
1993 - break;
1994 + bcma_core_mips_early_init(mcore);
1995 +
1996 + bcma_fix_i2s_irqflag(bus);
1997 +
1998 + switch (bus->chipinfo.id) {
1999 + case BCMA_CHIP_ID_BCM4716:
2000 + case BCMA_CHIP_ID_BCM4748:
2001 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
2002 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
2003 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
2004 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
2005 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
2006 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
2007 + break;
2008 + case BCMA_CHIP_ID_BCM5356:
2009 + case BCMA_CHIP_ID_BCM47162:
2010 + case BCMA_CHIP_ID_BCM53572:
2011 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
2012 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
2013 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
2014 + break;
2015 + case BCMA_CHIP_ID_BCM5357:
2016 + case BCMA_CHIP_ID_BCM4749:
2017 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
2018 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
2019 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
2020 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
2021 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
2022 + break;
2023 + case BCMA_CHIP_ID_BCM4706:
2024 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
2025 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
2026 + 0);
2027 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
2028 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
2029 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
2030 + 0);
2031 + break;
2032 + default:
2033 + list_for_each_entry(core, &bus->cores, list) {
2034 + core->irq = bcma_core_irq(core);
2035 }
2036 + bcma_err(bus,
2037 + "Unknown device (0x%x) found, can not configure IRQs\n",
2038 + bus->chipinfo.id);
2039 }
2040 - pr_info("IRQ reconfiguration done\n");
2041 + bcma_debug(bus, "IRQ reconfiguration done\n");
2042 bcma_core_mips_dump_irq(bus);
2043
2044 - if (mcore->setup_done)
2045 - return;
2046 -
2047 - bcma_chipco_serial_init(&bus->drv_cc);
2048 - bcma_core_mips_flash_detect(mcore);
2049 mcore->setup_done = true;
2050 }
2051 --- a/drivers/bcma/driver_pci.c
2052 +++ b/drivers/bcma/driver_pci.c
2053 @@ -2,8 +2,9 @@
2054 * Broadcom specific AMBA
2055 * PCI Core
2056 *
2057 - * Copyright 2005, Broadcom Corporation
2058 + * Copyright 2005, 2011, Broadcom Corporation
2059 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
2060 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
2061 *
2062 * Licensed under the GNU/GPL. See COPYING for details.
2063 */
2064 @@ -16,120 +17,131 @@
2065 * R/W ops.
2066 **************************************************/
2067
2068 -static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
2069 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
2070 {
2071 - pcicore_write32(pc, 0x130, address);
2072 - pcicore_read32(pc, 0x130);
2073 - return pcicore_read32(pc, 0x134);
2074 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
2075 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
2076 + return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
2077 }
2078
2079 -#if 0
2080 static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
2081 {
2082 - pcicore_write32(pc, 0x130, address);
2083 - pcicore_read32(pc, 0x130);
2084 - pcicore_write32(pc, 0x134, data);
2085 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
2086 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
2087 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
2088 }
2089 -#endif
2090
2091 -static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
2092 +static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
2093 {
2094 - const u16 mdio_control = 0x128;
2095 - const u16 mdio_data = 0x12C;
2096 u32 v;
2097 int i;
2098
2099 - v = (1 << 30); /* Start of Transaction */
2100 - v |= (1 << 28); /* Write Transaction */
2101 - v |= (1 << 17); /* Turnaround */
2102 - v |= (0x1F << 18);
2103 + v = BCMA_CORE_PCI_MDIODATA_START;
2104 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
2105 + v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
2106 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
2107 + v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
2108 + BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
2109 + v |= BCMA_CORE_PCI_MDIODATA_TA;
2110 v |= (phy << 4);
2111 - pcicore_write32(pc, mdio_data, v);
2112 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
2113
2114 udelay(10);
2115 for (i = 0; i < 200; i++) {
2116 - v = pcicore_read32(pc, mdio_control);
2117 - if (v & 0x100 /* Trans complete */)
2118 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
2119 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
2120 break;
2121 - msleep(1);
2122 + usleep_range(1000, 2000);
2123 }
2124 }
2125
2126 -static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
2127 +static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
2128 {
2129 - const u16 mdio_control = 0x128;
2130 - const u16 mdio_data = 0x12C;
2131 int max_retries = 10;
2132 u16 ret = 0;
2133 u32 v;
2134 int i;
2135
2136 - v = 0x80; /* Enable Preamble Sequence */
2137 - v |= 0x2; /* MDIO Clock Divisor */
2138 - pcicore_write32(pc, mdio_control, v);
2139 + /* enable mdio access to SERDES */
2140 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
2141 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
2142 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
2143
2144 if (pc->core->id.rev >= 10) {
2145 max_retries = 200;
2146 bcma_pcie_mdio_set_phy(pc, device);
2147 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
2148 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
2149 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
2150 + } else {
2151 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
2152 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
2153 }
2154
2155 - v = (1 << 30); /* Start of Transaction */
2156 - v |= (1 << 29); /* Read Transaction */
2157 - v |= (1 << 17); /* Turnaround */
2158 - if (pc->core->id.rev < 10)
2159 - v |= (u32)device << 22;
2160 - v |= (u32)address << 18;
2161 - pcicore_write32(pc, mdio_data, v);
2162 + v = BCMA_CORE_PCI_MDIODATA_START;
2163 + v |= BCMA_CORE_PCI_MDIODATA_READ;
2164 + v |= BCMA_CORE_PCI_MDIODATA_TA;
2165 +
2166 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
2167 /* Wait for the device to complete the transaction */
2168 udelay(10);
2169 for (i = 0; i < max_retries; i++) {
2170 - v = pcicore_read32(pc, mdio_control);
2171 - if (v & 0x100 /* Trans complete */) {
2172 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
2173 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
2174 udelay(10);
2175 - ret = pcicore_read32(pc, mdio_data);
2176 + ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
2177 break;
2178 }
2179 - msleep(1);
2180 + usleep_range(1000, 2000);
2181 }
2182 - pcicore_write32(pc, mdio_control, 0);
2183 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
2184 return ret;
2185 }
2186
2187 -static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
2188 +static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
2189 u8 address, u16 data)
2190 {
2191 - const u16 mdio_control = 0x128;
2192 - const u16 mdio_data = 0x12C;
2193 int max_retries = 10;
2194 u32 v;
2195 int i;
2196
2197 - v = 0x80; /* Enable Preamble Sequence */
2198 - v |= 0x2; /* MDIO Clock Divisor */
2199 - pcicore_write32(pc, mdio_control, v);
2200 + /* enable mdio access to SERDES */
2201 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
2202 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
2203 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
2204
2205 if (pc->core->id.rev >= 10) {
2206 max_retries = 200;
2207 bcma_pcie_mdio_set_phy(pc, device);
2208 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
2209 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
2210 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
2211 + } else {
2212 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
2213 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
2214 }
2215
2216 - v = (1 << 30); /* Start of Transaction */
2217 - v |= (1 << 28); /* Write Transaction */
2218 - v |= (1 << 17); /* Turnaround */
2219 - if (pc->core->id.rev < 10)
2220 - v |= (u32)device << 22;
2221 - v |= (u32)address << 18;
2222 + v = BCMA_CORE_PCI_MDIODATA_START;
2223 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
2224 + v |= BCMA_CORE_PCI_MDIODATA_TA;
2225 v |= data;
2226 - pcicore_write32(pc, mdio_data, v);
2227 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
2228 /* Wait for the device to complete the transaction */
2229 udelay(10);
2230 for (i = 0; i < max_retries; i++) {
2231 - v = pcicore_read32(pc, mdio_control);
2232 - if (v & 0x100 /* Trans complete */)
2233 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
2234 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
2235 break;
2236 - msleep(1);
2237 + usleep_range(1000, 2000);
2238 }
2239 - pcicore_write32(pc, mdio_control, 0);
2240 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
2241 +}
2242 +
2243 +static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
2244 + u8 address, u16 data)
2245 +{
2246 + bcma_pcie_mdio_write(pc, device, address, data);
2247 + return bcma_pcie_mdio_read(pc, device, address);
2248 }
2249
2250 /**************************************************
2251 @@ -138,88 +150,127 @@ static void bcma_pcie_mdio_write(struct
2252
2253 static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
2254 {
2255 - return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
2256 + u32 tmp;
2257 +
2258 + tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
2259 + if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
2260 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
2261 + BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
2262 + else
2263 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
2264 }
2265
2266 static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
2267 {
2268 - const u8 serdes_pll_device = 0x1D;
2269 - const u8 serdes_rx_device = 0x1F;
2270 u16 tmp;
2271
2272 - bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
2273 - bcma_pcicore_polarity_workaround(pc));
2274 - tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
2275 - if (tmp & 0x4000)
2276 - bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
2277 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
2278 + BCMA_CORE_PCI_SERDES_RX_CTRL,
2279 + bcma_pcicore_polarity_workaround(pc));
2280 + tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
2281 + BCMA_CORE_PCI_SERDES_PLL_CTRL);
2282 + if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
2283 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
2284 + BCMA_CORE_PCI_SERDES_PLL_CTRL,
2285 + tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
2286 +}
2287 +
2288 +static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
2289 +{
2290 + struct bcma_device *core = pc->core;
2291 + u16 val16, core_index;
2292 + uint regoff;
2293 +
2294 + regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
2295 + core_index = (u16)core->core_index;
2296 +
2297 + val16 = pcicore_read16(pc, regoff);
2298 + if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
2299 + != core_index) {
2300 + val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) |
2301 + (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
2302 + pcicore_write16(pc, regoff, val16);
2303 + }
2304 }
2305
2306 -/**************************************************
2307 - * Init.
2308 - **************************************************/
2309 -
2310 -static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
2311 +/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
2312 +/* Needs to happen when coming out of 'standby'/'hibernate' */
2313 +static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
2314 {
2315 - bcma_pcicore_serdes_workaround(pc);
2316 + u16 val16;
2317 + uint regoff;
2318 +
2319 + regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);
2320 +
2321 + val16 = pcicore_read16(pc, regoff);
2322 +
2323 + if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
2324 + val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
2325 + pcicore_write16(pc, regoff, val16);
2326 + }
2327 }
2328
2329 -static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
2330 +static void bcma_core_pci_power_save(struct bcma_drv_pci *pc, bool up)
2331 {
2332 - struct bcma_bus *bus = pc->core->bus;
2333 - u16 chipid_top;
2334 + u16 data;
2335
2336 - chipid_top = (bus->chipinfo.id & 0xFF00);
2337 - if (chipid_top != 0x4700 &&
2338 - chipid_top != 0x5300)
2339 - return false;
2340 -
2341 -#ifdef CONFIG_SSB_DRIVER_PCICORE
2342 - if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
2343 - return false;
2344 -#endif /* CONFIG_SSB_DRIVER_PCICORE */
2345 + if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
2346 + data = up ? 0x74 : 0x7C;
2347 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
2348 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
2349 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
2350 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
2351 + } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
2352 + data = up ? 0x75 : 0x7D;
2353 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
2354 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
2355 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
2356 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
2357 + }
2358 +}
2359
2360 -#if 0
2361 - /* TODO: on BCMA we use address from EROM instead of magic formula */
2362 - u32 tmp;
2363 - return !mips_busprobe32(tmp, (bus->mmio +
2364 - (pc->core->core_index * BCMA_CORE_SIZE)));
2365 -#endif
2366 +/**************************************************
2367 + * Init.
2368 + **************************************************/
2369
2370 - return true;
2371 +static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
2372 +{
2373 + bcma_core_pci_fixcfg(pc);
2374 + bcma_pcicore_serdes_workaround(pc);
2375 + bcma_core_pci_config_fixup(pc);
2376 }
2377
2378 -void bcma_core_pci_init(struct bcma_drv_pci *pc)
2379 +void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
2380 {
2381 if (pc->setup_done)
2382 return;
2383
2384 - if (bcma_core_pci_is_in_hostmode(pc)) {
2385 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
2386 + pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
2387 + if (pc->hostmode)
2388 bcma_core_pci_hostmode_init(pc);
2389 -#else
2390 - pr_err("Driver compiled without support for hostmode PCI\n");
2391 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
2392 - } else {
2393 - bcma_core_pci_clientmode_init(pc);
2394 - }
2395
2396 - pc->setup_done = true;
2397 + if (!pc->hostmode)
2398 + bcma_core_pci_clientmode_init(pc);
2399 }
2400
2401 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
2402 bool enable)
2403 {
2404 - struct pci_dev *pdev = pc->core->bus->host_pci;
2405 + struct pci_dev *pdev;
2406 u32 coremask, tmp;
2407 int err = 0;
2408
2409 - if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
2410 + if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
2411 /* This bcma device is not on a PCI host-bus. So the IRQs are
2412 * not routed through the PCI core.
2413 * So we must not enable routing through the PCI core. */
2414 goto out;
2415 }
2416
2417 + pdev = pc->core->bus->host_pci;
2418 +
2419 err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
2420 if (err)
2421 goto out;
2422 @@ -236,3 +287,46 @@ out:
2423 return err;
2424 }
2425 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
2426 +
2427 +static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
2428 +{
2429 + u32 w;
2430 +
2431 + w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
2432 + if (extend)
2433 + w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
2434 + else
2435 + w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
2436 + bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
2437 + bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
2438 +}
2439 +
2440 +void bcma_core_pci_up(struct bcma_bus *bus)
2441 +{
2442 + struct bcma_drv_pci *pc;
2443 +
2444 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
2445 + return;
2446 +
2447 + pc = &bus->drv_pci[0];
2448 +
2449 + bcma_core_pci_power_save(pc, true);
2450 +
2451 + bcma_core_pci_extend_L1timer(pc, true);
2452 +}
2453 +EXPORT_SYMBOL_GPL(bcma_core_pci_up);
2454 +
2455 +void bcma_core_pci_down(struct bcma_bus *bus)
2456 +{
2457 + struct bcma_drv_pci *pc;
2458 +
2459 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
2460 + return;
2461 +
2462 + pc = &bus->drv_pci[0];
2463 +
2464 + bcma_core_pci_extend_L1timer(pc, false);
2465 +
2466 + bcma_core_pci_power_save(pc, false);
2467 +}
2468 +EXPORT_SYMBOL_GPL(bcma_core_pci_down);
2469 --- a/drivers/bcma/driver_pci_host.c
2470 +++ b/drivers/bcma/driver_pci_host.c
2471 @@ -2,13 +2,622 @@
2472 * Broadcom specific AMBA
2473 * PCI Core in hostmode
2474 *
2475 + * Copyright 2005 - 2011, Broadcom Corporation
2476 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
2477 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
2478 + *
2479 * Licensed under the GNU/GPL. See COPYING for details.
2480 */
2481
2482 #include "bcma_private.h"
2483 +#include <linux/pci.h>
2484 +#include <linux/export.h>
2485 #include <linux/bcma/bcma.h>
2486 +#include <asm/paccess.h>
2487 +
2488 +/* Probe a 32bit value on the bus and catch bus exceptions.
2489 + * Returns nonzero on a bus exception.
2490 + * This is MIPS specific */
2491 +#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
2492 +
2493 +/* Assume one-hot slot wiring */
2494 +#define BCMA_PCI_SLOT_MAX 16
2495 +#define PCI_CONFIG_SPACE_SIZE 256
2496 +
2497 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
2498 +{
2499 + struct bcma_bus *bus = pc->core->bus;
2500 + u16 chipid_top;
2501 + u32 tmp;
2502 +
2503 + chipid_top = (bus->chipinfo.id & 0xFF00);
2504 + if (chipid_top != 0x4700 &&
2505 + chipid_top != 0x5300)
2506 + return false;
2507 +
2508 + bcma_core_enable(pc->core, 0);
2509 +
2510 + return !mips_busprobe32(tmp, pc->core->io_addr);
2511 +}
2512 +
2513 +static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
2514 +{
2515 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
2516 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
2517 + return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
2518 +}
2519 +
2520 +static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
2521 + u32 data)
2522 +{
2523 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
2524 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
2525 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
2526 +}
2527 +
2528 +static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
2529 + unsigned int func, unsigned int off)
2530 +{
2531 + u32 addr = 0;
2532 +
2533 + /* Issue config commands only when the data link is up (atleast
2534 + * one external pcie device is present).
2535 + */
2536 + if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
2537 + & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
2538 + goto out;
2539 +
2540 + /* Type 0 transaction */
2541 + /* Slide the PCI window to the appropriate slot */
2542 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
2543 + /* Calculate the address */
2544 + addr = pc->host_controller->host_cfg_addr;
2545 + addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
2546 + addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
2547 + addr |= (off & ~3);
2548 +
2549 +out:
2550 + return addr;
2551 +}
2552 +
2553 +static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
2554 + unsigned int func, unsigned int off,
2555 + void *buf, int len)
2556 +{
2557 + int err = -EINVAL;
2558 + u32 addr, val;
2559 + void __iomem *mmio = 0;
2560 +
2561 + WARN_ON(!pc->hostmode);
2562 + if (unlikely(len != 1 && len != 2 && len != 4))
2563 + goto out;
2564 + if (dev == 0) {
2565 + /* we support only two functions on device 0 */
2566 + if (func > 1)
2567 + goto out;
2568 +
2569 + /* accesses to config registers with offsets >= 256
2570 + * requires indirect access.
2571 + */
2572 + if (off >= PCI_CONFIG_SPACE_SIZE) {
2573 + addr = (func << 12);
2574 + addr |= (off & 0x0FFC);
2575 + val = bcma_pcie_read_config(pc, addr);
2576 + } else {
2577 + addr = BCMA_CORE_PCI_PCICFG0;
2578 + addr |= (func << 8);
2579 + addr |= (off & 0xFC);
2580 + val = pcicore_read32(pc, addr);
2581 + }
2582 + } else {
2583 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
2584 + if (unlikely(!addr))
2585 + goto out;
2586 + err = -ENOMEM;
2587 + mmio = ioremap_nocache(addr, sizeof(val));
2588 + if (!mmio)
2589 + goto out;
2590 +
2591 + if (mips_busprobe32(val, mmio)) {
2592 + val = 0xFFFFFFFF;
2593 + goto unmap;
2594 + }
2595 + }
2596 + val >>= (8 * (off & 3));
2597 +
2598 + switch (len) {
2599 + case 1:
2600 + *((u8 *)buf) = (u8)val;
2601 + break;
2602 + case 2:
2603 + *((u16 *)buf) = (u16)val;
2604 + break;
2605 + case 4:
2606 + *((u32 *)buf) = (u32)val;
2607 + break;
2608 + }
2609 + err = 0;
2610 +unmap:
2611 + if (mmio)
2612 + iounmap(mmio);
2613 +out:
2614 + return err;
2615 +}
2616
2617 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
2618 +static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
2619 + unsigned int func, unsigned int off,
2620 + const void *buf, int len)
2621 {
2622 - pr_err("No support for PCI core in hostmode yet\n");
2623 + int err = -EINVAL;
2624 + u32 addr, val;
2625 + void __iomem *mmio = 0;
2626 + u16 chipid = pc->core->bus->chipinfo.id;
2627 +
2628 + WARN_ON(!pc->hostmode);
2629 + if (unlikely(len != 1 && len != 2 && len != 4))
2630 + goto out;
2631 + if (dev == 0) {
2632 + /* we support only two functions on device 0 */
2633 + if (func > 1)
2634 + goto out;
2635 +
2636 + /* accesses to config registers with offsets >= 256
2637 + * requires indirect access.
2638 + */
2639 + if (off >= PCI_CONFIG_SPACE_SIZE) {
2640 + addr = (func << 12);
2641 + addr |= (off & 0x0FFC);
2642 + val = bcma_pcie_read_config(pc, addr);
2643 + } else {
2644 + addr = BCMA_CORE_PCI_PCICFG0;
2645 + addr |= (func << 8);
2646 + addr |= (off & 0xFC);
2647 + val = pcicore_read32(pc, addr);
2648 + }
2649 + } else {
2650 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
2651 + if (unlikely(!addr))
2652 + goto out;
2653 + err = -ENOMEM;
2654 + mmio = ioremap_nocache(addr, sizeof(val));
2655 + if (!mmio)
2656 + goto out;
2657 +
2658 + if (mips_busprobe32(val, mmio)) {
2659 + val = 0xFFFFFFFF;
2660 + goto unmap;
2661 + }
2662 + }
2663 +
2664 + switch (len) {
2665 + case 1:
2666 + val &= ~(0xFF << (8 * (off & 3)));
2667 + val |= *((const u8 *)buf) << (8 * (off & 3));
2668 + break;
2669 + case 2:
2670 + val &= ~(0xFFFF << (8 * (off & 3)));
2671 + val |= *((const u16 *)buf) << (8 * (off & 3));
2672 + break;
2673 + case 4:
2674 + val = *((const u32 *)buf);
2675 + break;
2676 + }
2677 + if (dev == 0) {
2678 + /* accesses to config registers with offsets >= 256
2679 + * requires indirect access.
2680 + */
2681 + if (off >= PCI_CONFIG_SPACE_SIZE)
2682 + bcma_pcie_write_config(pc, addr, val);
2683 + else
2684 + pcicore_write32(pc, addr, val);
2685 + } else {
2686 + writel(val, mmio);
2687 +
2688 + if (chipid == BCMA_CHIP_ID_BCM4716 ||
2689 + chipid == BCMA_CHIP_ID_BCM4748)
2690 + readl(mmio);
2691 + }
2692 +
2693 + err = 0;
2694 +unmap:
2695 + if (mmio)
2696 + iounmap(mmio);
2697 +out:
2698 + return err;
2699 +}
2700 +
2701 +static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
2702 + unsigned int devfn,
2703 + int reg, int size, u32 *val)
2704 +{
2705 + unsigned long flags;
2706 + int err;
2707 + struct bcma_drv_pci *pc;
2708 + struct bcma_drv_pci_host *pc_host;
2709 +
2710 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
2711 + pc = pc_host->pdev;
2712 +
2713 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
2714 + err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
2715 + PCI_FUNC(devfn), reg, val, size);
2716 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
2717 +
2718 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
2719 +}
2720 +
2721 +static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
2722 + unsigned int devfn,
2723 + int reg, int size, u32 val)
2724 +{
2725 + unsigned long flags;
2726 + int err;
2727 + struct bcma_drv_pci *pc;
2728 + struct bcma_drv_pci_host *pc_host;
2729 +
2730 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
2731 + pc = pc_host->pdev;
2732 +
2733 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
2734 + err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
2735 + PCI_FUNC(devfn), reg, &val, size);
2736 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
2737 +
2738 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
2739 +}
2740 +
2741 +/* return cap_offset if requested capability exists in the PCI config space */
2742 +static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc,
2743 + unsigned int dev,
2744 + unsigned int func, u8 req_cap_id,
2745 + unsigned char *buf, u32 *buflen)
2746 +{
2747 + u8 cap_id;
2748 + u8 cap_ptr = 0;
2749 + u32 bufsize;
2750 + u8 byte_val;
2751 +
2752 + /* check for Header type 0 */
2753 + bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
2754 + sizeof(u8));
2755 + if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL)
2756 + return cap_ptr;
2757 +
2758 + /* check if the capability pointer field exists */
2759 + bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
2760 + sizeof(u8));
2761 + if (!(byte_val & PCI_STATUS_CAP_LIST))
2762 + return cap_ptr;
2763 +
2764 + /* check if the capability pointer is 0x00 */
2765 + bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
2766 + sizeof(u8));
2767 + if (cap_ptr == 0x00)
2768 + return cap_ptr;
2769 +
2770 + /* loop thr'u the capability list and see if the requested capabilty
2771 + * exists */
2772 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
2773 + while (cap_id != req_cap_id) {
2774 + bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
2775 + sizeof(u8));
2776 + if (cap_ptr == 0x00)
2777 + return cap_ptr;
2778 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
2779 + sizeof(u8));
2780 + }
2781 +
2782 + /* found the caller requested capability */
2783 + if ((buf != NULL) && (buflen != NULL)) {
2784 + u8 cap_data;
2785 +
2786 + bufsize = *buflen;
2787 + if (!bufsize)
2788 + return cap_ptr;
2789 +
2790 + *buflen = 0;
2791 +
2792 + /* copy the cpability data excluding cap ID and next ptr */
2793 + cap_data = cap_ptr + 2;
2794 + if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE)
2795 + bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
2796 + *buflen = bufsize;
2797 + while (bufsize--) {
2798 + bcma_extpci_read_config(pc, dev, func, cap_data, buf,
2799 + sizeof(u8));
2800 + cap_data++;
2801 + buf++;
2802 + }
2803 + }
2804 +
2805 + return cap_ptr;
2806 +}
2807 +
2808 +/* If the root port is capable of returning Config Request
2809 + * Retry Status (CRS) Completion Status to software then
2810 + * enable the feature.
2811 + */
2812 +static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
2813 +{
2814 + struct bcma_bus *bus = pc->core->bus;
2815 + u8 cap_ptr, root_ctrl, root_cap, dev;
2816 + u16 val16;
2817 + int i;
2818 +
2819 + cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
2820 + NULL);
2821 + root_cap = cap_ptr + PCI_EXP_RTCAP;
2822 + bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
2823 + if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
2824 + /* Enable CRS software visibility */
2825 + root_ctrl = cap_ptr + PCI_EXP_RTCTL;
2826 + val16 = PCI_EXP_RTCTL_CRSSVE;
2827 + bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
2828 + sizeof(u16));
2829 +
2830 + /* Initiate a configuration request to read the vendor id
2831 + * field of the device function's config space header after
2832 + * 100 ms wait time from the end of Reset. If the device is
2833 + * not done with its internal initialization, it must at
2834 + * least return a completion TLP, with a completion status
2835 + * of "Configuration Request Retry Status (CRS)". The root
2836 + * complex must complete the request to the host by returning
2837 + * a read-data value of 0001h for the Vendor ID field and
2838 + * all 1s for any additional bytes included in the request.
2839 + * Poll using the config reads for max wait time of 1 sec or
2840 + * until we receive the successful completion status. Repeat
2841 + * the procedure for all the devices.
2842 + */
2843 + for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
2844 + for (i = 0; i < 100000; i++) {
2845 + bcma_extpci_read_config(pc, dev, 0,
2846 + PCI_VENDOR_ID, &val16,
2847 + sizeof(val16));
2848 + if (val16 != 0x1)
2849 + break;
2850 + udelay(10);
2851 + }
2852 + if (val16 == 0x1)
2853 + bcma_err(bus, "PCI: Broken device in slot %d\n",
2854 + dev);
2855 + }
2856 + }
2857 +}
2858 +
2859 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
2860 +{
2861 + struct bcma_bus *bus = pc->core->bus;
2862 + struct bcma_drv_pci_host *pc_host;
2863 + u32 tmp;
2864 + u32 pci_membase_1G;
2865 + unsigned long io_map_base;
2866 +
2867 + bcma_info(bus, "PCIEcore in host mode found\n");
2868 +
2869 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
2870 + bcma_info(bus, "This PCIE core is disabled and not working\n");
2871 + return;
2872 + }
2873 +
2874 + pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
2875 + if (!pc_host) {
2876 + bcma_err(bus, "can not allocate memory");
2877 + return;
2878 + }
2879 +
2880 + spin_lock_init(&pc_host->cfgspace_lock);
2881 +
2882 + pc->host_controller = pc_host;
2883 + pc_host->pci_controller.io_resource = &pc_host->io_resource;
2884 + pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
2885 + pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
2886 + pc_host->pdev = pc;
2887 +
2888 + pci_membase_1G = BCMA_SOC_PCI_DMA;
2889 + pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
2890 +
2891 + pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
2892 + pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
2893 +
2894 + pc_host->mem_resource.name = "BCMA PCIcore external memory",
2895 + pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
2896 + pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
2897 + pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
2898 +
2899 + pc_host->io_resource.name = "BCMA PCIcore external I/O",
2900 + pc_host->io_resource.start = 0x100;
2901 + pc_host->io_resource.end = 0x7FF;
2902 + pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
2903 +
2904 + /* Reset RC */
2905 + usleep_range(3000, 5000);
2906 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
2907 + msleep(50);
2908 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
2909 + BCMA_CORE_PCI_CTL_RST_OE);
2910 +
2911 + /* 64 MB I/O access window. On 4716, use
2912 + * sbtopcie0 to access the device registers. We
2913 + * can't use address match 2 (1 GB window) region
2914 + * as mips can't generate 64-bit address on the
2915 + * backplane.
2916 + */
2917 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 ||
2918 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
2919 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
2920 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
2921 + BCMA_SOC_PCI_MEM_SZ - 1;
2922 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2923 + BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
2924 + } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
2925 + tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
2926 + tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
2927 + tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
2928 + if (pc->core->core_unit == 0) {
2929 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
2930 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
2931 + BCMA_SOC_PCI_MEM_SZ - 1;
2932 + pc_host->io_resource.start = 0x100;
2933 + pc_host->io_resource.end = 0x47F;
2934 + pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
2935 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2936 + tmp | BCMA_SOC_PCI_MEM);
2937 + } else if (pc->core->core_unit == 1) {
2938 + pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
2939 + pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
2940 + BCMA_SOC_PCI_MEM_SZ - 1;
2941 + pc_host->io_resource.start = 0x480;
2942 + pc_host->io_resource.end = 0x7FF;
2943 + pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
2944 + pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
2945 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2946 + tmp | BCMA_SOC_PCI1_MEM);
2947 + }
2948 + } else
2949 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2950 + BCMA_CORE_PCI_SBTOPCI_IO);
2951 +
2952 + /* 64 MB configuration access window */
2953 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
2954 +
2955 + /* 1 GB memory access window */
2956 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
2957 + BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
2958 +
2959 +
2960 + /* As per PCI Express Base Spec 1.1 we need to wait for
2961 + * at least 100 ms from the end of a reset (cold/warm/hot)
2962 + * before issuing configuration requests to PCI Express
2963 + * devices.
2964 + */
2965 + msleep(100);
2966 +
2967 + bcma_core_pci_enable_crs(pc);
2968 +
2969 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
2970 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
2971 + u16 val16;
2972 + bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
2973 + &val16, sizeof(val16));
2974 + val16 |= (2 << 5); /* Max payload size of 512 */
2975 + val16 |= (2 << 12); /* MRRS 512 */
2976 + bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
2977 + &val16, sizeof(val16));
2978 + }
2979 +
2980 + /* Enable PCI bridge BAR0 memory & master access */
2981 + tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
2982 + bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
2983 +
2984 + /* Enable PCI interrupts */
2985 + pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
2986 +
2987 + /* Ok, ready to run, register it to the system.
2988 + * The following needs change, if we want to port hostmode
2989 + * to non-MIPS platform. */
2990 + io_map_base = (unsigned long)ioremap_nocache(pc_host->mem_resource.start,
2991 + resource_size(&pc_host->mem_resource));
2992 + pc_host->pci_controller.io_map_base = io_map_base;
2993 + set_io_port_base(pc_host->pci_controller.io_map_base);
2994 + /* Give some time to the PCI controller to configure itself with the new
2995 + * values. Not waiting at this point causes crashes of the machine. */
2996 + usleep_range(10000, 15000);
2997 + register_pci_controller(&pc_host->pci_controller);
2998 + return;
2999 +}
3000 +
3001 +/* Early PCI fixup for a device on the PCI-core bridge. */
3002 +static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
3003 +{
3004 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
3005 + /* This is not a device on the PCI-core bridge. */
3006 + return;
3007 + }
3008 + if (PCI_SLOT(dev->devfn) != 0)
3009 + return;
3010 +
3011 + pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
3012 +
3013 + /* Enable PCI bridge bus mastering and memory space */
3014 + pci_set_master(dev);
3015 + if (pcibios_enable_device(dev, ~0) < 0) {
3016 + pr_err("PCI: BCMA bridge enable failed\n");
3017 + return;
3018 + }
3019 +
3020 + /* Enable PCI bridge BAR1 prefetch and burst */
3021 + pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
3022 +}
3023 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
3024 +
3025 +/* Early PCI fixup for all PCI-cores to set the correct memory address. */
3026 +static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
3027 +{
3028 + struct resource *res;
3029 + int pos, err;
3030 +
3031 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
3032 + /* This is not a device on the PCI-core bridge. */
3033 + return;
3034 + }
3035 + if (PCI_SLOT(dev->devfn) == 0)
3036 + return;
3037 +
3038 + pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
3039 +
3040 + for (pos = 0; pos < 6; pos++) {
3041 + res = &dev->resource[pos];
3042 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
3043 + err = pci_assign_resource(dev, pos);
3044 + if (err)
3045 + pr_err("PCI: Problem fixing up the addresses on %s\n",
3046 + pci_name(dev));
3047 + }
3048 + }
3049 +}
3050 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
3051 +
3052 +/* This function is called when doing a pci_enable_device().
3053 + * We must first check if the device is a device on the PCI-core bridge. */
3054 +int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
3055 +{
3056 + struct bcma_drv_pci_host *pc_host;
3057 + int readrq;
3058 +
3059 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
3060 + /* This is not a device on the PCI-core bridge. */
3061 + return -ENODEV;
3062 + }
3063 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
3064 + pci_ops);
3065 +
3066 + pr_info("PCI: Fixing up device %s\n", pci_name(dev));
3067 +
3068 + /* Fix up interrupt lines */
3069 + dev->irq = bcma_core_irq(pc_host->pdev->core);
3070 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
3071 +
3072 + readrq = pcie_get_readrq(dev);
3073 + if (readrq > 128) {
3074 + pr_info("change PCIe max read request size from %i to 128\n", readrq);
3075 + pcie_set_readrq(dev, 128);
3076 + }
3077 + return 0;
3078 +}
3079 +EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
3080 +
3081 +/* PCI device IRQ mapping. */
3082 +int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
3083 +{
3084 + struct bcma_drv_pci_host *pc_host;
3085 +
3086 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
3087 + /* This is not a device on the PCI-core bridge. */
3088 + return -ENODEV;
3089 + }
3090 +
3091 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
3092 + pci_ops);
3093 + return bcma_core_irq(pc_host->pdev->core);
3094 }
3095 +EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
3096 --- a/drivers/bcma/host_pci.c
3097 +++ b/drivers/bcma/host_pci.c
3098 @@ -18,7 +18,7 @@ static void bcma_host_pci_switch_core(st
3099 pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
3100 core->wrap);
3101 core->bus->mapped_core = core;
3102 - pr_debug("Switched to core: 0x%X\n", core->id.id);
3103 + bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id);
3104 }
3105
3106 /* Provides access to the requested core. Returns base offset that has to be
3107 @@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct
3108 }
3109
3110 #ifdef CONFIG_BCMA_BLOCKIO
3111 -void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
3112 - size_t count, u16 offset, u8 reg_width)
3113 +static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
3114 + size_t count, u16 offset, u8 reg_width)
3115 {
3116 void __iomem *addr = core->bus->mmio + offset;
3117 if (core->bus->mapped_core != core)
3118 @@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm
3119 }
3120 }
3121
3122 -void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
3123 - size_t count, u16 offset, u8 reg_width)
3124 +static void bcma_host_pci_block_write(struct bcma_device *core,
3125 + const void *buffer, size_t count,
3126 + u16 offset, u8 reg_width)
3127 {
3128 void __iomem *addr = core->bus->mmio + offset;
3129 if (core->bus->mapped_core != core)
3130 @@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc
3131 iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
3132 }
3133
3134 -const struct bcma_host_ops bcma_host_pci_ops = {
3135 +static const struct bcma_host_ops bcma_host_pci_ops = {
3136 .read8 = bcma_host_pci_read8,
3137 .read16 = bcma_host_pci_read16,
3138 .read32 = bcma_host_pci_read32,
3139 @@ -154,8 +155,8 @@ const struct bcma_host_ops bcma_host_pci
3140 .awrite32 = bcma_host_pci_awrite32,
3141 };
3142
3143 -static int bcma_host_pci_probe(struct pci_dev *dev,
3144 - const struct pci_device_id *id)
3145 +static int __devinit bcma_host_pci_probe(struct pci_dev *dev,
3146 + const struct pci_device_id *id)
3147 {
3148 struct bcma_bus *bus;
3149 int err = -ENOMEM;
3150 @@ -188,7 +189,7 @@ static int bcma_host_pci_probe(struct pc
3151
3152 /* SSB needed additional powering up, do we have any AMBA PCI cards? */
3153 if (!pci_is_pcie(dev))
3154 - pr_err("PCI card detected, report problems.\n");
3155 + bcma_err(bus, "PCI card detected, report problems.\n");
3156
3157 /* Map MMIO */
3158 err = -ENOMEM;
3159 @@ -201,6 +202,9 @@ static int bcma_host_pci_probe(struct pc
3160 bus->hosttype = BCMA_HOSTTYPE_PCI;
3161 bus->ops = &bcma_host_pci_ops;
3162
3163 + bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
3164 + bus->boardinfo.type = bus->host_pci->subsystem_device;
3165 +
3166 /* Register */
3167 err = bcma_bus_register(bus);
3168 if (err)
3169 @@ -222,7 +226,7 @@ err_kfree_bus:
3170 return err;
3171 }
3172
3173 -static void bcma_host_pci_remove(struct pci_dev *dev)
3174 +static void __devexit bcma_host_pci_remove(struct pci_dev *dev)
3175 {
3176 struct bcma_bus *bus = pci_get_drvdata(dev);
3177
3178 @@ -234,7 +238,7 @@ static void bcma_host_pci_remove(struct
3179 pci_set_drvdata(dev, NULL);
3180 }
3181
3182 -#ifdef CONFIG_PM
3183 +#ifdef CONFIG_PM_SLEEP
3184 static int bcma_host_pci_suspend(struct device *dev)
3185 {
3186 struct pci_dev *pdev = to_pci_dev(dev);
3187 @@ -257,17 +261,21 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
3188 bcma_host_pci_resume);
3189 #define BCMA_PM_OPS (&bcma_pm_ops)
3190
3191 -#else /* CONFIG_PM */
3192 +#else /* CONFIG_PM_SLEEP */
3193
3194 #define BCMA_PM_OPS NULL
3195
3196 -#endif /* CONFIG_PM */
3197 +#endif /* CONFIG_PM_SLEEP */
3198
3199 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
3200 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
3201 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
3202 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
3203 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
3204 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
3205 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
3206 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
3207 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
3208 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
3209 { 0, },
3210 };
3211 @@ -277,7 +285,7 @@ static struct pci_driver bcma_pci_bridge
3212 .name = "bcma-pci-bridge",
3213 .id_table = bcma_pci_bridge_tbl,
3214 .probe = bcma_host_pci_probe,
3215 - .remove = bcma_host_pci_remove,
3216 + .remove = __devexit_p(bcma_host_pci_remove),
3217 .driver.pm = BCMA_PM_OPS,
3218 };
3219
3220 --- a/drivers/bcma/host_soc.c
3221 +++ b/drivers/bcma/host_soc.c
3222 @@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc
3223 writel(value, core->io_wrap + offset);
3224 }
3225
3226 -const struct bcma_host_ops bcma_host_soc_ops = {
3227 +static const struct bcma_host_ops bcma_host_soc_ops = {
3228 .read8 = bcma_host_soc_read8,
3229 .read16 = bcma_host_soc_read16,
3230 .read32 = bcma_host_soc_read32,
3231 --- a/drivers/bcma/main.c
3232 +++ b/drivers/bcma/main.c
3233 @@ -7,12 +7,19 @@
3234
3235 #include "bcma_private.h"
3236 #include <linux/module.h>
3237 +#include <linux/platform_device.h>
3238 #include <linux/bcma/bcma.h>
3239 #include <linux/slab.h>
3240
3241 MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
3242 MODULE_LICENSE("GPL");
3243
3244 +/* contains the number the next bus should get. */
3245 +static unsigned int bcma_bus_next_num = 0;
3246 +
3247 +/* bcma_buses_mutex locks the bcma_bus_next_num */
3248 +static DEFINE_MUTEX(bcma_buses_mutex);
3249 +
3250 static int bcma_bus_match(struct device *dev, struct device_driver *drv);
3251 static int bcma_device_probe(struct device *dev);
3252 static int bcma_device_remove(struct device *dev);
3253 @@ -55,7 +62,14 @@ static struct bus_type bcma_bus_type = {
3254 .dev_attrs = bcma_device_attrs,
3255 };
3256
3257 -static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
3258 +static u16 bcma_cc_core_id(struct bcma_bus *bus)
3259 +{
3260 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
3261 + return BCMA_CORE_4706_CHIPCOMMON;
3262 + return BCMA_CORE_CHIPCOMMON;
3263 +}
3264 +
3265 +struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
3266 {
3267 struct bcma_device *core;
3268
3269 @@ -65,6 +79,38 @@ static struct bcma_device *bcma_find_cor
3270 }
3271 return NULL;
3272 }
3273 +EXPORT_SYMBOL_GPL(bcma_find_core);
3274 +
3275 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
3276 + u8 unit)
3277 +{
3278 + struct bcma_device *core;
3279 +
3280 + list_for_each_entry(core, &bus->cores, list) {
3281 + if (core->id.id == coreid && core->core_unit == unit)
3282 + return core;
3283 + }
3284 + return NULL;
3285 +}
3286 +
3287 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
3288 + int timeout)
3289 +{
3290 + unsigned long deadline = jiffies + timeout;
3291 + u32 val;
3292 +
3293 + do {
3294 + val = bcma_read32(core, reg);
3295 + if ((val & mask) == value)
3296 + return true;
3297 + cpu_relax();
3298 + udelay(10);
3299 + } while (!time_after_eq(jiffies, deadline));
3300 +
3301 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
3302 +
3303 + return false;
3304 +}
3305
3306 static void bcma_release_core_dev(struct device *dev)
3307 {
3308 @@ -84,16 +130,23 @@ static int bcma_register_cores(struct bc
3309 list_for_each_entry(core, &bus->cores, list) {
3310 /* We support that cores ourself */
3311 switch (core->id.id) {
3312 + case BCMA_CORE_4706_CHIPCOMMON:
3313 case BCMA_CORE_CHIPCOMMON:
3314 case BCMA_CORE_PCI:
3315 case BCMA_CORE_PCIE:
3316 case BCMA_CORE_MIPS_74K:
3317 + case BCMA_CORE_4706_MAC_GBIT_COMMON:
3318 continue;
3319 }
3320
3321 + /* Only first GMAC core on BCM4706 is connected and working */
3322 + if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
3323 + core->core_unit > 0)
3324 + continue;
3325 +
3326 core->dev.release = bcma_release_core_dev;
3327 core->dev.bus = &bcma_bus_type;
3328 - dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id);
3329 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
3330
3331 switch (bus->hosttype) {
3332 case BCMA_HOSTTYPE_PCI:
3333 @@ -111,41 +164,98 @@ static int bcma_register_cores(struct bc
3334
3335 err = device_register(&core->dev);
3336 if (err) {
3337 - pr_err("Could not register dev for core 0x%03X\n",
3338 - core->id.id);
3339 + bcma_err(bus,
3340 + "Could not register dev for core 0x%03X\n",
3341 + core->id.id);
3342 continue;
3343 }
3344 core->dev_registered = true;
3345 dev_id++;
3346 }
3347
3348 +#ifdef CONFIG_BCMA_DRIVER_MIPS
3349 + if (bus->drv_cc.pflash.present) {
3350 + err = platform_device_register(&bcma_pflash_dev);
3351 + if (err)
3352 + bcma_err(bus, "Error registering parallel flash\n");
3353 + }
3354 +#endif
3355 +
3356 +#ifdef CONFIG_BCMA_SFLASH
3357 + if (bus->drv_cc.sflash.present) {
3358 + err = platform_device_register(&bcma_sflash_dev);
3359 + if (err)
3360 + bcma_err(bus, "Error registering serial flash\n");
3361 + }
3362 +#endif
3363 +
3364 +#ifdef CONFIG_BCMA_NFLASH
3365 + if (bus->drv_cc.nflash.present) {
3366 + err = platform_device_register(&bcma_nflash_dev);
3367 + if (err)
3368 + bcma_err(bus, "Error registering NAND flash\n");
3369 + }
3370 +#endif
3371 + err = bcma_gpio_init(&bus->drv_cc);
3372 + if (err == -ENOTSUPP)
3373 + bcma_debug(bus, "GPIO driver not activated\n");
3374 + else if (err)
3375 + bcma_err(bus, "Error registering GPIO driver: %i\n", err);
3376 +
3377 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
3378 + err = bcma_chipco_watchdog_register(&bus->drv_cc);
3379 + if (err)
3380 + bcma_err(bus, "Error registering watchdog driver\n");
3381 + }
3382 +
3383 return 0;
3384 }
3385
3386 static void bcma_unregister_cores(struct bcma_bus *bus)
3387 {
3388 - struct bcma_device *core;
3389 + struct bcma_device *core, *tmp;
3390
3391 - list_for_each_entry(core, &bus->cores, list) {
3392 + list_for_each_entry_safe(core, tmp, &bus->cores, list) {
3393 + list_del(&core->list);
3394 if (core->dev_registered)
3395 device_unregister(&core->dev);
3396 }
3397 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
3398 + platform_device_unregister(bus->drv_cc.watchdog);
3399 }
3400
3401 -int bcma_bus_register(struct bcma_bus *bus)
3402 +int __devinit bcma_bus_register(struct bcma_bus *bus)
3403 {
3404 int err;
3405 struct bcma_device *core;
3406
3407 + mutex_lock(&bcma_buses_mutex);
3408 + bus->num = bcma_bus_next_num++;
3409 + mutex_unlock(&bcma_buses_mutex);
3410 +
3411 /* Scan for devices (cores) */
3412 err = bcma_bus_scan(bus);
3413 if (err) {
3414 - pr_err("Failed to scan: %d\n", err);
3415 - return -1;
3416 + bcma_err(bus, "Failed to scan: %d\n", err);
3417 + return err;
3418 }
3419
3420 + /* Early init CC core */
3421 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
3422 + if (core) {
3423 + bus->drv_cc.core = core;
3424 + bcma_core_chipcommon_early_init(&bus->drv_cc);
3425 + }
3426 +
3427 + /* Try to get SPROM */
3428 + err = bcma_sprom_get(bus);
3429 + if (err == -ENOENT) {
3430 + bcma_err(bus, "No SPROM available\n");
3431 + } else if (err)
3432 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
3433 +
3434 /* Init CC core */
3435 - core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
3436 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
3437 if (core) {
3438 bus->drv_cc.core = core;
3439 bcma_core_chipcommon_init(&bus->drv_cc);
3440 @@ -159,30 +269,54 @@ int bcma_bus_register(struct bcma_bus *b
3441 }
3442
3443 /* Init PCIE core */
3444 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
3445 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
3446 if (core) {
3447 - bus->drv_pci.core = core;
3448 - bcma_core_pci_init(&bus->drv_pci);
3449 + bus->drv_pci[0].core = core;
3450 + bcma_core_pci_init(&bus->drv_pci[0]);
3451 }
3452
3453 - /* Try to get SPROM */
3454 - err = bcma_sprom_get(bus);
3455 - if (err == -ENOENT) {
3456 - pr_err("No SPROM available\n");
3457 - } else if (err)
3458 - pr_err("Failed to get SPROM: %d\n", err);
3459 + /* Init PCIE core */
3460 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
3461 + if (core) {
3462 + bus->drv_pci[1].core = core;
3463 + bcma_core_pci_init(&bus->drv_pci[1]);
3464 + }
3465 +
3466 + /* Init GBIT MAC COMMON core */
3467 + core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
3468 + if (core) {
3469 + bus->drv_gmac_cmn.core = core;
3470 + bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
3471 + }
3472
3473 /* Register found cores */
3474 bcma_register_cores(bus);
3475
3476 - pr_info("Bus registered\n");
3477 + bcma_info(bus, "Bus registered\n");
3478
3479 return 0;
3480 }
3481
3482 void bcma_bus_unregister(struct bcma_bus *bus)
3483 {
3484 + struct bcma_device *cores[3];
3485 + int err;
3486 +
3487 + err = bcma_gpio_unregister(&bus->drv_cc);
3488 + if (err == -EBUSY)
3489 + bcma_err(bus, "Some GPIOs are still in use.\n");
3490 + else if (err)
3491 + bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
3492 +
3493 + cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
3494 + cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
3495 + cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
3496 +
3497 bcma_unregister_cores(bus);
3498 +
3499 + kfree(cores[2]);
3500 + kfree(cores[1]);
3501 + kfree(cores[0]);
3502 }
3503
3504 int __init bcma_bus_early_register(struct bcma_bus *bus,
3505 @@ -196,14 +330,14 @@ int __init bcma_bus_early_register(struc
3506 bcma_init_bus(bus);
3507
3508 match.manuf = BCMA_MANUF_BCM;
3509 - match.id = BCMA_CORE_CHIPCOMMON;
3510 + match.id = bcma_cc_core_id(bus);
3511 match.class = BCMA_CL_SIM;
3512 match.rev = BCMA_ANY_REV;
3513
3514 /* Scan for chip common core */
3515 err = bcma_bus_scan_early(bus, &match, core_cc);
3516 if (err) {
3517 - pr_err("Failed to scan for common core: %d\n", err);
3518 + bcma_err(bus, "Failed to scan for common core: %d\n", err);
3519 return -1;
3520 }
3521
3522 @@ -215,25 +349,25 @@ int __init bcma_bus_early_register(struc
3523 /* Scan for mips core */
3524 err = bcma_bus_scan_early(bus, &match, core_mips);
3525 if (err) {
3526 - pr_err("Failed to scan for mips core: %d\n", err);
3527 + bcma_err(bus, "Failed to scan for mips core: %d\n", err);
3528 return -1;
3529 }
3530
3531 - /* Init CC core */
3532 - core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
3533 + /* Early init CC core */
3534 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
3535 if (core) {
3536 bus->drv_cc.core = core;
3537 - bcma_core_chipcommon_init(&bus->drv_cc);
3538 + bcma_core_chipcommon_early_init(&bus->drv_cc);
3539 }
3540
3541 - /* Init MIPS core */
3542 + /* Early init MIPS core */
3543 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
3544 if (core) {
3545 bus->drv_mips.core = core;
3546 - bcma_core_mips_init(&bus->drv_mips);
3547 + bcma_core_mips_early_init(&bus->drv_mips);
3548 }
3549
3550 - pr_info("Early bus registered\n");
3551 + bcma_info(bus, "Early bus registered\n");
3552
3553 return 0;
3554 }
3555 @@ -259,8 +393,7 @@ int bcma_bus_resume(struct bcma_bus *bus
3556 struct bcma_device *core;
3557
3558 /* Init CC core */
3559 - core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
3560 - if (core) {
3561 + if (bus->drv_cc.core) {
3562 bus->drv_cc.setup_done = false;
3563 bcma_core_chipcommon_init(&bus->drv_cc);
3564 }
3565 --- a/drivers/bcma/scan.c
3566 +++ b/drivers/bcma/scan.c
3567 @@ -19,15 +19,39 @@ struct bcma_device_id_name {
3568 u16 id;
3569 const char *name;
3570 };
3571 -struct bcma_device_id_name bcma_device_names[] = {
3572 +
3573 +static const struct bcma_device_id_name bcma_arm_device_names[] = {
3574 + { BCMA_CORE_4706_MAC_GBIT_COMMON, "BCM4706 GBit MAC Common" },
3575 + { BCMA_CORE_ARM_1176, "ARM 1176" },
3576 + { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
3577 + { BCMA_CORE_ARM_CM3, "ARM CM3" },
3578 +};
3579 +
3580 +static const struct bcma_device_id_name bcma_bcm_device_names[] = {
3581 { BCMA_CORE_OOB_ROUTER, "OOB Router" },
3582 + { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
3583 + { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
3584 + { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
3585 + { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
3586 + { BCMA_CORE_DMA, "DMA" },
3587 + { BCMA_CORE_SDIO3, "SDIO3" },
3588 + { BCMA_CORE_USB20, "USB 2.0" },
3589 + { BCMA_CORE_USB30, "USB 3.0" },
3590 + { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
3591 + { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
3592 + { BCMA_CORE_ROM, "ROM" },
3593 + { BCMA_CORE_NAND, "NAND flash controller" },
3594 + { BCMA_CORE_QSPI, "SPI flash controller" },
3595 + { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
3596 + { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
3597 + { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
3598 + { BCMA_CORE_ALTA, "ALTA (I2S)" },
3599 { BCMA_CORE_INVALID, "Invalid" },
3600 { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
3601 { BCMA_CORE_ILINE20, "ILine 20" },
3602 { BCMA_CORE_SRAM, "SRAM" },
3603 { BCMA_CORE_SDRAM, "SDRAM" },
3604 { BCMA_CORE_PCI, "PCI" },
3605 - { BCMA_CORE_MIPS, "MIPS" },
3606 { BCMA_CORE_ETHERNET, "Fast Ethernet" },
3607 { BCMA_CORE_V90, "V90" },
3608 { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
3609 @@ -44,7 +68,6 @@ struct bcma_device_id_name bcma_device_n
3610 { BCMA_CORE_PHY_A, "PHY A" },
3611 { BCMA_CORE_PHY_B, "PHY B" },
3612 { BCMA_CORE_PHY_G, "PHY G" },
3613 - { BCMA_CORE_MIPS_3302, "MIPS 3302" },
3614 { BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
3615 { BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
3616 { BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
3617 @@ -58,15 +81,11 @@ struct bcma_device_id_name bcma_device_n
3618 { BCMA_CORE_PHY_N, "PHY N" },
3619 { BCMA_CORE_SRAM_CTL, "SRAM Controller" },
3620 { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
3621 - { BCMA_CORE_ARM_1176, "ARM 1176" },
3622 - { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
3623 { BCMA_CORE_PHY_LP, "PHY LP" },
3624 { BCMA_CORE_PMU, "PMU" },
3625 { BCMA_CORE_PHY_SSN, "PHY SSN" },
3626 { BCMA_CORE_SDIO_DEV, "SDIO Device" },
3627 - { BCMA_CORE_ARM_CM3, "ARM CM3" },
3628 { BCMA_CORE_PHY_HT, "PHY HT" },
3629 - { BCMA_CORE_MIPS_74K, "MIPS 74K" },
3630 { BCMA_CORE_MAC_GBIT, "GBit MAC" },
3631 { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
3632 { BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
3633 @@ -77,18 +96,45 @@ struct bcma_device_id_name bcma_device_n
3634 { BCMA_CORE_I2S, "I2S" },
3635 { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
3636 { BCMA_CORE_SHIM, "SHIM" },
3637 + { BCMA_CORE_PCIE2, "PCIe Gen2" },
3638 + { BCMA_CORE_ARM_CR4, "ARM CR4" },
3639 { BCMA_CORE_DEFAULT, "Default" },
3640 };
3641 -const char *bcma_device_name(struct bcma_device_id *id)
3642 +
3643 +static const struct bcma_device_id_name bcma_mips_device_names[] = {
3644 + { BCMA_CORE_MIPS, "MIPS" },
3645 + { BCMA_CORE_MIPS_3302, "MIPS 3302" },
3646 + { BCMA_CORE_MIPS_74K, "MIPS 74K" },
3647 +};
3648 +
3649 +static const char *bcma_device_name(const struct bcma_device_id *id)
3650 {
3651 - int i;
3652 + const struct bcma_device_id_name *names;
3653 + int size, i;
3654
3655 - if (id->manuf == BCMA_MANUF_BCM) {
3656 - for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
3657 - if (bcma_device_names[i].id == id->id)
3658 - return bcma_device_names[i].name;
3659 - }
3660 + /* search manufacturer specific names */
3661 + switch (id->manuf) {
3662 + case BCMA_MANUF_ARM:
3663 + names = bcma_arm_device_names;
3664 + size = ARRAY_SIZE(bcma_arm_device_names);
3665 + break;
3666 + case BCMA_MANUF_BCM:
3667 + names = bcma_bcm_device_names;
3668 + size = ARRAY_SIZE(bcma_bcm_device_names);
3669 + break;
3670 + case BCMA_MANUF_MIPS:
3671 + names = bcma_mips_device_names;
3672 + size = ARRAY_SIZE(bcma_mips_device_names);
3673 + break;
3674 + default:
3675 + return "UNKNOWN";
3676 + }
3677 +
3678 + for (i = 0; i < size; i++) {
3679 + if (names[i].id == id->id)
3680 + return names[i].name;
3681 }
3682 +
3683 return "UNKNOWN";
3684 }
3685
3686 @@ -105,19 +151,19 @@ static void bcma_scan_switch_core(struct
3687 addr);
3688 }
3689
3690 -static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
3691 +static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr)
3692 {
3693 u32 ent = readl(*eromptr);
3694 (*eromptr)++;
3695 return ent;
3696 }
3697
3698 -static void bcma_erom_push_ent(u32 **eromptr)
3699 +static void bcma_erom_push_ent(u32 __iomem **eromptr)
3700 {
3701 (*eromptr)--;
3702 }
3703
3704 -static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
3705 +static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr)
3706 {
3707 u32 ent = bcma_erom_get_ent(bus, eromptr);
3708 if (!(ent & SCAN_ER_VALID))
3709 @@ -127,14 +173,14 @@ static s32 bcma_erom_get_ci(struct bcma_
3710 return ent;
3711 }
3712
3713 -static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
3714 +static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr)
3715 {
3716 u32 ent = bcma_erom_get_ent(bus, eromptr);
3717 bcma_erom_push_ent(eromptr);
3718 return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
3719 }
3720
3721 -static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
3722 +static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr)
3723 {
3724 u32 ent = bcma_erom_get_ent(bus, eromptr);
3725 bcma_erom_push_ent(eromptr);
3726 @@ -143,7 +189,7 @@ static bool bcma_erom_is_bridge(struct b
3727 ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
3728 }
3729
3730 -static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
3731 +static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr)
3732 {
3733 u32 ent;
3734 while (1) {
3735 @@ -157,7 +203,7 @@ static void bcma_erom_skip_component(str
3736 bcma_erom_push_ent(eromptr);
3737 }
3738
3739 -static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
3740 +static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr)
3741 {
3742 u32 ent = bcma_erom_get_ent(bus, eromptr);
3743 if (!(ent & SCAN_ER_VALID))
3744 @@ -167,7 +213,7 @@ static s32 bcma_erom_get_mst_port(struct
3745 return ent;
3746 }
3747
3748 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
3749 +static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
3750 u32 type, u8 port)
3751 {
3752 u32 addrl, addrh, sizel, sizeh = 0;
3753 @@ -179,7 +225,7 @@ static s32 bcma_erom_get_addr_desc(struc
3754 ((ent & SCAN_ADDR_TYPE) != type) ||
3755 (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
3756 bcma_erom_push_ent(eromptr);
3757 - return -EINVAL;
3758 + return (u32)-EINVAL;
3759 }
3760
3761 addrl = ent & SCAN_ADDR_ADDR;
3762 @@ -212,11 +258,24 @@ static struct bcma_device *bcma_find_cor
3763 return NULL;
3764 }
3765
3766 +static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid)
3767 +{
3768 + struct bcma_device *core;
3769 +
3770 + list_for_each_entry_reverse(core, &bus->cores, list) {
3771 + if (core->id.id == coreid)
3772 + return core;
3773 + }
3774 + return NULL;
3775 +}
3776 +
3777 +#define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO)
3778 +
3779 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
3780 struct bcma_device_id *match, int core_num,
3781 struct bcma_device *core)
3782 {
3783 - s32 tmp;
3784 + u32 tmp;
3785 u8 i, j;
3786 s32 cia, cib;
3787 u8 ports[2], wrappers[2];
3788 @@ -252,11 +311,15 @@ static int bcma_get_next_core(struct bcm
3789
3790 /* check if component is a core at all */
3791 if (wrappers[0] + wrappers[1] == 0) {
3792 - /* we could save addrl of the router
3793 - if (cid == BCMA_CORE_OOB_ROUTER)
3794 - */
3795 - bcma_erom_skip_component(bus, eromptr);
3796 - return -ENXIO;
3797 + /* Some specific cores don't need wrappers */
3798 + switch (core->id.id) {
3799 + case BCMA_CORE_4706_MAC_GBIT_COMMON:
3800 + /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
3801 + break;
3802 + default:
3803 + bcma_erom_skip_component(bus, eromptr);
3804 + return -ENXIO;
3805 + }
3806 }
3807
3808 if (bcma_erom_is_bridge(bus, eromptr)) {
3809 @@ -286,19 +349,36 @@ static int bcma_get_next_core(struct bcm
3810 return -EILSEQ;
3811 }
3812
3813 + /* First Slave Address Descriptor should be port 0:
3814 + * the main register space for the core
3815 + */
3816 + tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
3817 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
3818 + /* Try again to see if it is a bridge */
3819 + tmp = bcma_erom_get_addr_desc(bus, eromptr,
3820 + SCAN_ADDR_TYPE_BRIDGE, 0);
3821 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
3822 + return -EILSEQ;
3823 + } else {
3824 + bcma_info(bus, "Bridge found\n");
3825 + return -ENXIO;
3826 + }
3827 + }
3828 + core->addr = tmp;
3829 +
3830 /* get & parse slave ports */
3831 for (i = 0; i < ports[1]; i++) {
3832 for (j = 0; ; j++) {
3833 tmp = bcma_erom_get_addr_desc(bus, eromptr,
3834 SCAN_ADDR_TYPE_SLAVE, i);
3835 - if (tmp < 0) {
3836 + if (IS_ERR_VALUE_U32(tmp)) {
3837 /* no more entries for port _i_ */
3838 /* pr_debug("erom: slave port %d "
3839 * "has %d descriptors\n", i, j); */
3840 break;
3841 } else {
3842 if (i == 0 && j == 0)
3843 - core->addr = tmp;
3844 + core->addr1 = tmp;
3845 }
3846 }
3847 }
3848 @@ -308,7 +388,7 @@ static int bcma_get_next_core(struct bcm
3849 for (j = 0; ; j++) {
3850 tmp = bcma_erom_get_addr_desc(bus, eromptr,
3851 SCAN_ADDR_TYPE_MWRAP, i);
3852 - if (tmp < 0) {
3853 + if (IS_ERR_VALUE_U32(tmp)) {
3854 /* no more entries for port _i_ */
3855 /* pr_debug("erom: master wrapper %d "
3856 * "has %d descriptors\n", i, j); */
3857 @@ -326,7 +406,7 @@ static int bcma_get_next_core(struct bcm
3858 for (j = 0; ; j++) {
3859 tmp = bcma_erom_get_addr_desc(bus, eromptr,
3860 SCAN_ADDR_TYPE_SWRAP, i + hack);
3861 - if (tmp < 0) {
3862 + if (IS_ERR_VALUE_U32(tmp)) {
3863 /* no more entries for port _i_ */
3864 /* pr_debug("erom: master wrapper %d "
3865 * has %d descriptors\n", i, j); */
3866 @@ -353,6 +433,7 @@ static int bcma_get_next_core(struct bcm
3867 void bcma_init_bus(struct bcma_bus *bus)
3868 {
3869 s32 tmp;
3870 + struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
3871
3872 if (bus->init_done)
3873 return;
3874 @@ -363,9 +444,12 @@ void bcma_init_bus(struct bcma_bus *bus)
3875 bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
3876
3877 tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
3878 - bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
3879 - bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
3880 - bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
3881 + chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
3882 + chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
3883 + chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
3884 + bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
3885 + chipinfo->id, chipinfo->rev, chipinfo->pkg);
3886 +
3887 bus->init_done = true;
3888 }
3889
3890 @@ -392,9 +476,12 @@ int bcma_bus_scan(struct bcma_bus *bus)
3891 bcma_scan_switch_core(bus, erombase);
3892
3893 while (eromptr < eromend) {
3894 + struct bcma_device *other_core;
3895 struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
3896 - if (!core)
3897 - return -ENOMEM;
3898 + if (!core) {
3899 + err = -ENOMEM;
3900 + goto out;
3901 + }
3902 INIT_LIST_HEAD(&core->list);
3903 core->bus = bus;
3904
3905 @@ -409,25 +496,28 @@ int bcma_bus_scan(struct bcma_bus *bus)
3906 } else if (err == -ESPIPE) {
3907 break;
3908 }
3909 - return err;
3910 + goto out;
3911 }
3912
3913 core->core_index = core_num++;
3914 bus->nr_cores++;
3915 + other_core = bcma_find_core_reverse(bus, core->id.id);
3916 + core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
3917
3918 - pr_info("Core %d found: %s "
3919 - "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3920 - core->core_index, bcma_device_name(&core->id),
3921 - core->id.manuf, core->id.id, core->id.rev,
3922 - core->id.class);
3923 + bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3924 + core->core_index, bcma_device_name(&core->id),
3925 + core->id.manuf, core->id.id, core->id.rev,
3926 + core->id.class);
3927
3928 - list_add(&core->list, &bus->cores);
3929 + list_add_tail(&core->list, &bus->cores);
3930 }
3931
3932 + err = 0;
3933 +out:
3934 if (bus->hosttype == BCMA_HOSTTYPE_SOC)
3935 iounmap(eromptr);
3936
3937 - return 0;
3938 + return err;
3939 }
3940
3941 int __init bcma_bus_scan_early(struct bcma_bus *bus,
3942 @@ -467,21 +557,21 @@ int __init bcma_bus_scan_early(struct bc
3943 else if (err == -ESPIPE)
3944 break;
3945 else if (err < 0)
3946 - return err;
3947 + goto out;
3948
3949 core->core_index = core_num++;
3950 bus->nr_cores++;
3951 - pr_info("Core %d found: %s "
3952 - "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3953 - core->core_index, bcma_device_name(&core->id),
3954 - core->id.manuf, core->id.id, core->id.rev,
3955 - core->id.class);
3956 + bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3957 + core->core_index, bcma_device_name(&core->id),
3958 + core->id.manuf, core->id.id, core->id.rev,
3959 + core->id.class);
3960
3961 - list_add(&core->list, &bus->cores);
3962 + list_add_tail(&core->list, &bus->cores);
3963 err = 0;
3964 break;
3965 }
3966
3967 +out:
3968 if (bus->hosttype == BCMA_HOSTTYPE_SOC)
3969 iounmap(eromptr);
3970
3971 --- a/drivers/bcma/scan.h
3972 +++ b/drivers/bcma/scan.h
3973 @@ -27,7 +27,7 @@
3974 #define SCAN_CIB_NMW 0x0007C000
3975 #define SCAN_CIB_NMW_SHIFT 14
3976 #define SCAN_CIB_NSW 0x00F80000
3977 -#define SCAN_CIB_NSW_SHIFT 17
3978 +#define SCAN_CIB_NSW_SHIFT 19
3979 #define SCAN_CIB_REV 0xFF000000
3980 #define SCAN_CIB_REV_SHIFT 24
3981
3982 --- a/drivers/bcma/sprom.c
3983 +++ b/drivers/bcma/sprom.c
3984 @@ -2,6 +2,8 @@
3985 * Broadcom specific AMBA
3986 * SPROM reading
3987 *
3988 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
3989 + *
3990 * Licensed under the GNU/GPL. See COPYING for details.
3991 */
3992
3993 @@ -14,18 +16,68 @@
3994 #include <linux/dma-mapping.h>
3995 #include <linux/slab.h>
3996
3997 -#define SPOFF(offset) ((offset) / sizeof(u16))
3998 +static int(*get_fallback_sprom)(struct bcma_bus *dev, struct ssb_sprom *out);
3999 +
4000 +/**
4001 + * bcma_arch_register_fallback_sprom - Registers a method providing a
4002 + * fallback SPROM if no SPROM is found.
4003 + *
4004 + * @sprom_callback: The callback function.
4005 + *
4006 + * With this function the architecture implementation may register a
4007 + * callback handler which fills the SPROM data structure. The fallback is
4008 + * used for PCI based BCMA devices, where no valid SPROM can be found
4009 + * in the shadow registers and to provide the SPROM for SoCs where BCMA is
4010 + * to controll the system bus.
4011 + *
4012 + * This function is useful for weird architectures that have a half-assed
4013 + * BCMA device hardwired to their PCI bus.
4014 + *
4015 + * This function is available for architecture code, only. So it is not
4016 + * exported.
4017 + */
4018 +int bcma_arch_register_fallback_sprom(int (*sprom_callback)(struct bcma_bus *bus,
4019 + struct ssb_sprom *out))
4020 +{
4021 + if (get_fallback_sprom)
4022 + return -EEXIST;
4023 + get_fallback_sprom = sprom_callback;
4024 +
4025 + return 0;
4026 +}
4027 +
4028 +static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus,
4029 + struct ssb_sprom *out)
4030 +{
4031 + int err;
4032 +
4033 + if (!get_fallback_sprom) {
4034 + err = -ENOENT;
4035 + goto fail;
4036 + }
4037 +
4038 + err = get_fallback_sprom(bus, out);
4039 + if (err)
4040 + goto fail;
4041 +
4042 + bcma_debug(bus, "Using SPROM revision %d provided by platform.\n",
4043 + bus->sprom.revision);
4044 + return 0;
4045 +fail:
4046 + bcma_warn(bus, "Using fallback SPROM failed (err %d)\n", err);
4047 + return err;
4048 +}
4049
4050 /**************************************************
4051 * R/W ops.
4052 **************************************************/
4053
4054 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
4055 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
4056 + size_t words)
4057 {
4058 int i;
4059 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
4060 - sprom[i] = bcma_read16(bus->drv_cc.core,
4061 - offset + (i * 2));
4062 + for (i = 0; i < words; i++)
4063 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
4064 }
4065
4066 /**************************************************
4067 @@ -72,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
4068 return t[crc ^ data];
4069 }
4070
4071 -static u8 bcma_sprom_crc(const u16 *sprom)
4072 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
4073 {
4074 int word;
4075 u8 crc = 0xFF;
4076
4077 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
4078 + for (word = 0; word < words - 1; word++) {
4079 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
4080 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
4081 }
4082 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
4083 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
4084 crc ^= 0xFF;
4085
4086 return crc;
4087 }
4088
4089 -static int bcma_sprom_check_crc(const u16 *sprom)
4090 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
4091 {
4092 u8 crc;
4093 u8 expected_crc;
4094 u16 tmp;
4095
4096 - crc = bcma_sprom_crc(sprom);
4097 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
4098 + crc = bcma_sprom_crc(sprom, words);
4099 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
4100 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
4101 if (crc != expected_crc)
4102 return -EPROTO;
4103 @@ -102,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
4104 return 0;
4105 }
4106
4107 -static int bcma_sprom_valid(const u16 *sprom)
4108 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
4109 + size_t words)
4110 {
4111 u16 revision;
4112 int err;
4113
4114 - err = bcma_sprom_check_crc(sprom);
4115 + err = bcma_sprom_check_crc(sprom, words);
4116 if (err)
4117 return err;
4118
4119 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
4120 - if (revision != 8 && revision != 9) {
4121 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
4122 + if (revision != 8 && revision != 9 && revision != 10) {
4123 pr_err("Unsupported SPROM revision: %d\n", revision);
4124 return -ENOENT;
4125 }
4126
4127 + bus->sprom.revision = revision;
4128 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
4129 +
4130 return 0;
4131 }
4132
4133 @@ -124,124 +180,439 @@ static int bcma_sprom_valid(const u16 *s
4134 * SPROM extraction.
4135 **************************************************/
4136
4137 +#define SPOFF(offset) ((offset) / sizeof(u16))
4138 +
4139 +#define SPEX(_field, _offset, _mask, _shift) \
4140 + bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
4141 +
4142 +#define SPEX32(_field, _offset, _mask, _shift) \
4143 + bus->sprom._field = ((((u32)sprom[SPOFF((_offset)+2)] << 16 | \
4144 + sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))
4145 +
4146 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
4147 + do { \
4148 + SPEX(_field[0], _offset + 0, _mask, _shift); \
4149 + SPEX(_field[1], _offset + 2, _mask, _shift); \
4150 + SPEX(_field[2], _offset + 4, _mask, _shift); \
4151 + SPEX(_field[3], _offset + 6, _mask, _shift); \
4152 + SPEX(_field[4], _offset + 8, _mask, _shift); \
4153 + SPEX(_field[5], _offset + 10, _mask, _shift); \
4154 + SPEX(_field[6], _offset + 12, _mask, _shift); \
4155 + SPEX(_field[7], _offset + 14, _mask, _shift); \
4156 + } while (0)
4157 +
4158 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
4159 {
4160 - u16 v;
4161 + u16 v, o;
4162 int i;
4163 -
4164 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
4165 - SSB_SPROM_REVISION_REV;
4166 + u16 pwr_info_offset[] = {
4167 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
4168 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
4169 + };
4170 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
4171 + ARRAY_SIZE(bus->sprom.core_pwr_info));
4172
4173 for (i = 0; i < 3; i++) {
4174 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
4175 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
4176 }
4177
4178 - bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)];
4179 + SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
4180 + SPEX(board_type, SSB_SPROM1_SPID, ~0, 0);
4181 +
4182 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
4183 + SSB_SPROM4_TXPID2G0_SHIFT);
4184 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G1,
4185 + SSB_SPROM4_TXPID2G1_SHIFT);
4186 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G2,
4187 + SSB_SPROM4_TXPID2G2_SHIFT);
4188 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G3,
4189 + SSB_SPROM4_TXPID2G3_SHIFT);
4190 +
4191 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL0,
4192 + SSB_SPROM4_TXPID5GL0_SHIFT);
4193 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL1,
4194 + SSB_SPROM4_TXPID5GL1_SHIFT);
4195 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL2,
4196 + SSB_SPROM4_TXPID5GL2_SHIFT);
4197 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL3,
4198 + SSB_SPROM4_TXPID5GL3_SHIFT);
4199 +
4200 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G0,
4201 + SSB_SPROM4_TXPID5G0_SHIFT);
4202 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G1,
4203 + SSB_SPROM4_TXPID5G1_SHIFT);
4204 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G2,
4205 + SSB_SPROM4_TXPID5G2_SHIFT);
4206 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G3,
4207 + SSB_SPROM4_TXPID5G3_SHIFT);
4208 +
4209 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH0,
4210 + SSB_SPROM4_TXPID5GH0_SHIFT);
4211 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH1,
4212 + SSB_SPROM4_TXPID5GH1_SHIFT);
4213 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH2,
4214 + SSB_SPROM4_TXPID5GH2_SHIFT);
4215 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH3,
4216 + SSB_SPROM4_TXPID5GH3_SHIFT);
4217 +
4218 + SPEX(boardflags_lo, SSB_SPROM8_BFLLO, ~0, 0);
4219 + SPEX(boardflags_hi, SSB_SPROM8_BFLHI, ~0, 0);
4220 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, ~0, 0);
4221 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, ~0, 0);
4222 +
4223 + SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
4224 + SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
4225 +
4226 + /* Extract cores power info info */
4227 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
4228 + o = pwr_info_offset[i];
4229 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
4230 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
4231 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
4232 + SSB_SPROM8_2G_MAXP, 0);
4233 +
4234 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
4235 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
4236 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
4237 +
4238 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
4239 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
4240 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
4241 + SSB_SPROM8_5G_MAXP, 0);
4242 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
4243 + SSB_SPROM8_5GH_MAXP, 0);
4244 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
4245 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
4246 +
4247 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
4248 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
4249 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
4250 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
4251 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
4252 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
4253 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
4254 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
4255 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
4256 + }
4257 +
4258 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TSSIPOS,
4259 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
4260 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_EXTPA_GAIN,
4261 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
4262 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_PDET_RANGE,
4263 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
4264 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TR_ISO,
4265 + SSB_SROM8_FEM_TR_ISO_SHIFT);
4266 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_ANTSWLUT,
4267 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
4268 +
4269 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TSSIPOS,
4270 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
4271 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_EXTPA_GAIN,
4272 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
4273 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_PDET_RANGE,
4274 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
4275 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TR_ISO,
4276 + SSB_SROM8_FEM_TR_ISO_SHIFT);
4277 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_ANTSWLUT,
4278 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
4279 +
4280 + SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
4281 + SSB_SPROM8_ANTAVAIL_A_SHIFT);
4282 + SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
4283 + SSB_SPROM8_ANTAVAIL_BG_SHIFT);
4284 + SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
4285 + SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
4286 + SSB_SPROM8_ITSSI_BG_SHIFT);
4287 + SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
4288 + SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
4289 + SSB_SPROM8_ITSSI_A_SHIFT);
4290 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
4291 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
4292 + SSB_SPROM8_MAXP_AL_SHIFT);
4293 + SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
4294 + SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
4295 + SSB_SPROM8_GPIOA_P1_SHIFT);
4296 + SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
4297 + SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
4298 + SSB_SPROM8_GPIOB_P3_SHIFT);
4299 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
4300 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
4301 + SSB_SPROM8_TRI5G_SHIFT);
4302 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
4303 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
4304 + SSB_SPROM8_TRI5GH_SHIFT);
4305 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G,
4306 + SSB_SPROM8_RXPO2G_SHIFT);
4307 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
4308 + SSB_SPROM8_RXPO5G_SHIFT);
4309 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
4310 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
4311 + SSB_SPROM8_RSSISMC2G_SHIFT);
4312 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
4313 + SSB_SPROM8_RSSISAV2G_SHIFT);
4314 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
4315 + SSB_SPROM8_BXA2G_SHIFT);
4316 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
4317 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
4318 + SSB_SPROM8_RSSISMC5G_SHIFT);
4319 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
4320 + SSB_SPROM8_RSSISAV5G_SHIFT);
4321 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
4322 + SSB_SPROM8_BXA5G_SHIFT);
4323 +
4324 + SPEX(pa0b0, SSB_SPROM8_PA0B0, ~0, 0);
4325 + SPEX(pa0b1, SSB_SPROM8_PA0B1, ~0, 0);
4326 + SPEX(pa0b2, SSB_SPROM8_PA0B2, ~0, 0);
4327 + SPEX(pa1b0, SSB_SPROM8_PA1B0, ~0, 0);
4328 + SPEX(pa1b1, SSB_SPROM8_PA1B1, ~0, 0);
4329 + SPEX(pa1b2, SSB_SPROM8_PA1B2, ~0, 0);
4330 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, ~0, 0);
4331 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, ~0, 0);
4332 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, ~0, 0);
4333 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, ~0, 0);
4334 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, ~0, 0);
4335 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, ~0, 0);
4336 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, ~0, 0);
4337 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, ~0, 0);
4338 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, ~0, 0);
4339 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, ~0, 0);
4340 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
4341 +
4342 + /* Extract the antenna gain values. */
4343 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
4344 + SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
4345 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
4346 + SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
4347 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
4348 + SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
4349 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
4350 + SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
4351 +
4352 + SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
4353 + SSB_SPROM8_LEDDC_ON_SHIFT);
4354 + SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
4355 + SSB_SPROM8_LEDDC_OFF_SHIFT);
4356 +
4357 + SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
4358 + SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
4359 + SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
4360 + SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
4361 + SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
4362 + SSB_SPROM8_TXRXC_SWITCH_SHIFT);
4363 +
4364 + SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
4365 +
4366 + SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
4367 + SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
4368 + SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
4369 + SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
4370 +
4371 + SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
4372 + SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
4373 + SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
4374 + SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
4375 + SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
4376 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
4377 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
4378 + SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
4379 + SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
4380 + SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
4381 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
4382 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
4383 + SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
4384 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
4385 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
4386 + SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
4387 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
4388 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
4389 + SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
4390 + SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
4391 +
4392 + SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
4393 + SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
4394 + SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
4395 + SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
4396 +
4397 + SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
4398 + SSB_SPROM8_THERMAL_TRESH_SHIFT);
4399 + SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
4400 + SSB_SPROM8_THERMAL_OFFSET_SHIFT);
4401 + SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
4402 + SSB_SPROM8_TEMPDELTA_PHYCAL,
4403 + SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
4404 + SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
4405 + SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
4406 + SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
4407 + SSB_SPROM8_TEMPDELTA_HYSTERESIS,
4408 + SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
4409 +}
4410 +
4411 +/*
4412 + * Indicates the presence of external SPROM.
4413 + */
4414 +static bool bcma_sprom_ext_available(struct bcma_bus *bus)
4415 +{
4416 + u32 chip_status;
4417 + u32 srom_control;
4418 + u32 present_mask;
4419 +
4420 + if (bus->drv_cc.core->id.rev >= 31) {
4421 + if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
4422 + return false;
4423 +
4424 + srom_control = bcma_read32(bus->drv_cc.core,
4425 + BCMA_CC_SROM_CONTROL);
4426 + return srom_control & BCMA_CC_SROM_CONTROL_PRESENT;
4427 + }
4428 +
4429 + /* older chipcommon revisions use chip status register */
4430 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
4431 + switch (bus->chipinfo.id) {
4432 + case BCMA_CHIP_ID_BCM4313:
4433 + present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT;
4434 + break;
4435 +
4436 + case BCMA_CHIP_ID_BCM4331:
4437 + present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT;
4438 + break;
4439
4440 - bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
4441 - SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT;
4442 - bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
4443 - SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT;
4444 - bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
4445 - SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT;
4446 - bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
4447 - SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT;
4448 -
4449 - bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
4450 - SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT;
4451 - bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
4452 - SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT;
4453 - bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
4454 - SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT;
4455 - bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
4456 - SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT;
4457 -
4458 - bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
4459 - SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT;
4460 - bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
4461 - SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT;
4462 - bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
4463 - SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT;
4464 - bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
4465 - SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT;
4466 -
4467 - bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
4468 - SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT;
4469 - bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
4470 - SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT;
4471 - bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
4472 - SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT;
4473 - bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
4474 - SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT;
4475 -
4476 - bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
4477 - bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
4478 - bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
4479 - bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
4480 -
4481 - bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
4482 -
4483 - bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
4484 - SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
4485 - bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
4486 - SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
4487 - bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
4488 - SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
4489 - bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
4490 - SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
4491 - bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
4492 - SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
4493 -
4494 - bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
4495 - SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
4496 - bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
4497 - SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
4498 - bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
4499 - SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
4500 - bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
4501 - SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
4502 - bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
4503 - SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
4504 + default:
4505 + return true;
4506 + }
4507 +
4508 + return chip_status & present_mask;
4509 +}
4510 +
4511 +/*
4512 + * Indicates that on-chip OTP memory is present and enabled.
4513 + */
4514 +static bool bcma_sprom_onchip_available(struct bcma_bus *bus)
4515 +{
4516 + u32 chip_status;
4517 + u32 otpsize = 0;
4518 + bool present;
4519 +
4520 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
4521 + switch (bus->chipinfo.id) {
4522 + case BCMA_CHIP_ID_BCM4313:
4523 + present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT;
4524 + break;
4525 +
4526 + case BCMA_CHIP_ID_BCM4331:
4527 + present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
4528 + break;
4529 + case BCMA_CHIP_ID_BCM43142:
4530 + case BCMA_CHIP_ID_BCM43224:
4531 + case BCMA_CHIP_ID_BCM43225:
4532 + /* for these chips OTP is always available */
4533 + present = true;
4534 + break;
4535 + case BCMA_CHIP_ID_BCM43227:
4536 + case BCMA_CHIP_ID_BCM43228:
4537 + case BCMA_CHIP_ID_BCM43428:
4538 + present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT;
4539 + break;
4540 + default:
4541 + present = false;
4542 + break;
4543 + }
4544 +
4545 + if (present) {
4546 + otpsize = bus->drv_cc.capabilities & BCMA_CC_CAP_OTPS;
4547 + otpsize >>= BCMA_CC_CAP_OTPS_SHIFT;
4548 + }
4549 +
4550 + return otpsize != 0;
4551 +}
4552 +
4553 +/*
4554 + * Verify OTP is filled and determine the byte
4555 + * offset where SPROM data is located.
4556 + *
4557 + * On error, returns 0; byte offset otherwise.
4558 + */
4559 +static int bcma_sprom_onchip_offset(struct bcma_bus *bus)
4560 +{
4561 + struct bcma_device *cc = bus->drv_cc.core;
4562 + u32 offset;
4563 +
4564 + /* verify OTP status */
4565 + if ((bcma_read32(cc, BCMA_CC_OTPS) & BCMA_CC_OTPS_GU_PROG_HW) == 0)
4566 + return 0;
4567 +
4568 + /* obtain bit offset from otplayout register */
4569 + offset = (bcma_read32(cc, BCMA_CC_OTPL) & BCMA_CC_OTPL_GURGN_OFFSET);
4570 + return BCMA_CC_SPROM + (offset >> 3);
4571 }
4572
4573 int bcma_sprom_get(struct bcma_bus *bus)
4574 {
4575 - u16 offset;
4576 + u16 offset = BCMA_CC_SPROM;
4577 u16 *sprom;
4578 - int err = 0;
4579 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
4580 + SSB_SPROMSIZE_WORDS_R10, };
4581 + int i, err = 0;
4582
4583 if (!bus->drv_cc.core)
4584 return -EOPNOTSUPP;
4585
4586 - if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
4587 - return -ENOENT;
4588 + if (!bcma_sprom_ext_available(bus)) {
4589 + bool sprom_onchip;
4590
4591 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
4592 - GFP_KERNEL);
4593 - if (!sprom)
4594 - return -ENOMEM;
4595 + /*
4596 + * External SPROM takes precedence so check
4597 + * on-chip OTP only when no external SPROM
4598 + * is present.
4599 + */
4600 + sprom_onchip = bcma_sprom_onchip_available(bus);
4601 + if (sprom_onchip) {
4602 + /* determine offset */
4603 + offset = bcma_sprom_onchip_offset(bus);
4604 + }
4605 + if (!offset || !sprom_onchip) {
4606 + /*
4607 + * Maybe there is no SPROM on the device?
4608 + * Now we ask the arch code if there is some sprom
4609 + * available for this device in some other storage.
4610 + */
4611 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
4612 + return err;
4613 + }
4614 + }
4615
4616 - if (bus->chipinfo.id == 0x4331)
4617 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
4618 + bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
4619 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
4620
4621 - /* Most cards have SPROM moved by additional offset 0x30 (48 dwords).
4622 - * According to brcm80211 this applies to cards with PCIe rev >= 6
4623 - * TODO: understand this condition and use it */
4624 - offset = (bus->chipinfo.id == 0x4331) ? BCMA_CC_SPROM :
4625 - BCMA_CC_SPROM_PCIE6;
4626 - bcma_sprom_read(bus, offset, sprom);
4627 + bcma_debug(bus, "SPROM offset 0x%x\n", offset);
4628 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
4629 + size_t words = sprom_sizes[i];
4630 +
4631 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
4632 + if (!sprom)
4633 + return -ENOMEM;
4634 +
4635 + bcma_sprom_read(bus, offset, sprom, words);
4636 + err = bcma_sprom_valid(bus, sprom, words);
4637 + if (!err)
4638 + break;
4639
4640 - if (bus->chipinfo.id == 0x4331)
4641 - bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
4642 + kfree(sprom);
4643 + }
4644
4645 - err = bcma_sprom_valid(sprom);
4646 - if (err)
4647 - goto out;
4648 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
4649 + bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
4650 + bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
4651
4652 - bcma_sprom_extract_r8(bus, sprom);
4653 + if (err) {
4654 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
4655 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
4656 + } else {
4657 + bcma_sprom_extract_r8(bus, sprom);
4658 + kfree(sprom);
4659 + }
4660
4661 -out:
4662 - kfree(sprom);
4663 return err;
4664 }
4665 --- a/include/linux/bcma/bcma.h
4666 +++ b/include/linux/bcma/bcma.h
4667 @@ -7,9 +7,10 @@
4668 #include <linux/bcma/bcma_driver_chipcommon.h>
4669 #include <linux/bcma/bcma_driver_pci.h>
4670 #include <linux/bcma/bcma_driver_mips.h>
4671 +#include <linux/bcma/bcma_driver_gmac_cmn.h>
4672 #include <linux/ssb/ssb.h> /* SPROM sharing */
4673
4674 -#include "bcma_regs.h"
4675 +#include <linux/bcma/bcma_regs.h>
4676
4677 struct bcma_device;
4678 struct bcma_bus;
4679 @@ -26,6 +27,11 @@ struct bcma_chipinfo {
4680 u8 pkg;
4681 };
4682
4683 +struct bcma_boardinfo {
4684 + u16 vendor;
4685 + u16 type;
4686 +};
4687 +
4688 enum bcma_clkmode {
4689 BCMA_CLKMODE_FAST,
4690 BCMA_CLKMODE_DYNAMIC,
4691 @@ -65,6 +71,25 @@ struct bcma_host_ops {
4692
4693 /* Core-ID values. */
4694 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
4695 +#define BCMA_CORE_4706_CHIPCOMMON 0x500
4696 +#define BCMA_CORE_PCIEG2 0x501
4697 +#define BCMA_CORE_DMA 0x502
4698 +#define BCMA_CORE_SDIO3 0x503
4699 +#define BCMA_CORE_USB20 0x504
4700 +#define BCMA_CORE_USB30 0x505
4701 +#define BCMA_CORE_A9JTAG 0x506
4702 +#define BCMA_CORE_DDR23 0x507
4703 +#define BCMA_CORE_ROM 0x508
4704 +#define BCMA_CORE_NAND 0x509
4705 +#define BCMA_CORE_QSPI 0x50A
4706 +#define BCMA_CORE_CHIPCOMMON_B 0x50B
4707 +#define BCMA_CORE_4706_SOC_RAM 0x50E
4708 +#define BCMA_CORE_ARMCA9 0x510
4709 +#define BCMA_CORE_4706_MAC_GBIT 0x52D
4710 +#define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
4711 +#define BCMA_CORE_ALTA 0x534 /* I2S core */
4712 +#define BCMA_CORE_4706_MAC_GBIT_COMMON 0x5DC
4713 +#define BCMA_CORE_DDR23_PHY 0x5DD
4714 #define BCMA_CORE_INVALID 0x700
4715 #define BCMA_CORE_CHIPCOMMON 0x800
4716 #define BCMA_CORE_ILINE20 0x801
4717 @@ -121,10 +146,109 @@ struct bcma_host_ops {
4718 #define BCMA_CORE_I2S 0x834
4719 #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
4720 #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
4721 +#define BCMA_CORE_PHY_AC 0x83B
4722 +#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
4723 +#define BCMA_CORE_USB30_DEV 0x83D
4724 +#define BCMA_CORE_ARM_CR4 0x83E
4725 #define BCMA_CORE_DEFAULT 0xFFF
4726
4727 #define BCMA_MAX_NR_CORES 16
4728
4729 +/* Chip IDs of PCIe devices */
4730 +#define BCMA_CHIP_ID_BCM4313 0x4313
4731 +#define BCMA_CHIP_ID_BCM43142 43142
4732 +#define BCMA_CHIP_ID_BCM43224 43224
4733 +#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
4734 +#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
4735 +#define BCMA_CHIP_ID_BCM43225 43225
4736 +#define BCMA_CHIP_ID_BCM43227 43227
4737 +#define BCMA_CHIP_ID_BCM43228 43228
4738 +#define BCMA_CHIP_ID_BCM43421 43421
4739 +#define BCMA_CHIP_ID_BCM43428 43428
4740 +#define BCMA_CHIP_ID_BCM43431 43431
4741 +#define BCMA_CHIP_ID_BCM43460 43460
4742 +#define BCMA_CHIP_ID_BCM4331 0x4331
4743 +#define BCMA_CHIP_ID_BCM6362 0x6362
4744 +#define BCMA_CHIP_ID_BCM4360 0x4360
4745 +#define BCMA_CHIP_ID_BCM4352 0x4352
4746 +
4747 +/* Chip IDs of SoCs */
4748 +#define BCMA_CHIP_ID_BCM4706 0x5300
4749 +#define BCMA_PKG_ID_BCM4706L 1
4750 +#define BCMA_CHIP_ID_BCM4716 0x4716
4751 +#define BCMA_PKG_ID_BCM4716 8
4752 +#define BCMA_PKG_ID_BCM4717 9
4753 +#define BCMA_PKG_ID_BCM4718 10
4754 +#define BCMA_CHIP_ID_BCM47162 47162
4755 +#define BCMA_CHIP_ID_BCM4748 0x4748
4756 +#define BCMA_CHIP_ID_BCM4749 0x4749
4757 +#define BCMA_CHIP_ID_BCM5356 0x5356
4758 +#define BCMA_CHIP_ID_BCM5357 0x5357
4759 +#define BCMA_PKG_ID_BCM5358 9
4760 +#define BCMA_PKG_ID_BCM47186 10
4761 +#define BCMA_PKG_ID_BCM5357 11
4762 +#define BCMA_CHIP_ID_BCM53572 53572
4763 +#define BCMA_PKG_ID_BCM47188 9
4764 +#define BCMA_CHIP_ID_BCM4707 53010
4765 +#define BCMA_PKG_ID_BCM4707 1
4766 +#define BCMA_PKG_ID_BCM4708 2
4767 +#define BCMA_PKG_ID_BCM4709 0
4768 +#define BCMA_CHIP_ID_BCM53018 53018
4769 +
4770 +/* Board types (on PCI usually equals to the subsystem dev id) */
4771 +/* BCM4313 */
4772 +#define BCMA_BOARD_TYPE_BCM94313BU 0X050F
4773 +#define BCMA_BOARD_TYPE_BCM94313HM 0X0510
4774 +#define BCMA_BOARD_TYPE_BCM94313EPA 0X0511
4775 +#define BCMA_BOARD_TYPE_BCM94313HMG 0X051C
4776 +/* BCM4716 */
4777 +#define BCMA_BOARD_TYPE_BCM94716NR2 0X04CD
4778 +/* BCM43224 */
4779 +#define BCMA_BOARD_TYPE_BCM943224X21 0X056E
4780 +#define BCMA_BOARD_TYPE_BCM943224X21_FCC 0X00D1
4781 +#define BCMA_BOARD_TYPE_BCM943224X21B 0X00E9
4782 +#define BCMA_BOARD_TYPE_BCM943224M93 0X008B
4783 +#define BCMA_BOARD_TYPE_BCM943224M93A 0X0090
4784 +#define BCMA_BOARD_TYPE_BCM943224X16 0X0093
4785 +#define BCMA_BOARD_TYPE_BCM94322X9 0X008D
4786 +#define BCMA_BOARD_TYPE_BCM94322M35E 0X008E
4787 +/* BCM43228 */
4788 +#define BCMA_BOARD_TYPE_BCM943228BU8 0X0540
4789 +#define BCMA_BOARD_TYPE_BCM943228BU9 0X0541
4790 +#define BCMA_BOARD_TYPE_BCM943228BU 0X0542
4791 +#define BCMA_BOARD_TYPE_BCM943227HM4L 0X0543
4792 +#define BCMA_BOARD_TYPE_BCM943227HMB 0X0544
4793 +#define BCMA_BOARD_TYPE_BCM943228HM4L 0X0545
4794 +#define BCMA_BOARD_TYPE_BCM943228SD 0X0573
4795 +/* BCM4331 */
4796 +#define BCMA_BOARD_TYPE_BCM94331X19 0X00D6
4797 +#define BCMA_BOARD_TYPE_BCM94331X28 0X00E4
4798 +#define BCMA_BOARD_TYPE_BCM94331X28B 0X010E
4799 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX 0X00E4
4800 +#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC
4801 +#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED
4802 +#define BCMA_BOARD_TYPE_BCM94331X29B 0X00EF
4803 +#define BCMA_BOARD_TYPE_BCM94331CSAX 0X00EF
4804 +#define BCMA_BOARD_TYPE_BCM94331X19C 0X00F5
4805 +#define BCMA_BOARD_TYPE_BCM94331X33 0X00F4
4806 +#define BCMA_BOARD_TYPE_BCM94331BU 0X0523
4807 +#define BCMA_BOARD_TYPE_BCM94331S9BU 0X0524
4808 +#define BCMA_BOARD_TYPE_BCM94331MC 0X0525
4809 +#define BCMA_BOARD_TYPE_BCM94331MCI 0X0526
4810 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT4 0X0527
4811 +#define BCMA_BOARD_TYPE_BCM94331HM 0X0574
4812 +#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL 0X059B
4813 +#define BCMA_BOARD_TYPE_BCM94331MCH5 0X05A9
4814 +#define BCMA_BOARD_TYPE_BCM94331CS 0X05C6
4815 +#define BCMA_BOARD_TYPE_BCM94331CD 0X05DA
4816 +/* BCM53572 */
4817 +#define BCMA_BOARD_TYPE_BCM953572BU 0X058D
4818 +#define BCMA_BOARD_TYPE_BCM953572NR2 0X058E
4819 +#define BCMA_BOARD_TYPE_BCM947188NR2 0X058F
4820 +#define BCMA_BOARD_TYPE_BCM953572SDRNR2 0X0590
4821 +/* BCM43142 */
4822 +#define BCMA_BOARD_TYPE_BCM943142HM 0X05E0
4823 +
4824 struct bcma_device {
4825 struct bcma_bus *bus;
4826 struct bcma_device_id id;
4827 @@ -136,8 +260,10 @@ struct bcma_device {
4828 bool dev_registered;
4829
4830 u8 core_index;
4831 + u8 core_unit;
4832
4833 u32 addr;
4834 + u32 addr1;
4835 u32 wrap;
4836
4837 void __iomem *io_addr;
4838 @@ -175,6 +301,12 @@ int __bcma_driver_register(struct bcma_d
4839
4840 extern void bcma_driver_unregister(struct bcma_driver *drv);
4841
4842 +/* Set a fallback SPROM.
4843 + * See kdoc at the function definition for complete documentation. */
4844 +extern int bcma_arch_register_fallback_sprom(
4845 + int (*sprom_callback)(struct bcma_bus *bus,
4846 + struct ssb_sprom *out));
4847 +
4848 struct bcma_bus {
4849 /* The MMIO area. */
4850 void __iomem *mmio;
4851 @@ -191,14 +323,18 @@ struct bcma_bus {
4852
4853 struct bcma_chipinfo chipinfo;
4854
4855 + struct bcma_boardinfo boardinfo;
4856 +
4857 struct bcma_device *mapped_core;
4858 struct list_head cores;
4859 u8 nr_cores;
4860 u8 init_done:1;
4861 + u8 num;
4862
4863 struct bcma_drv_cc drv_cc;
4864 - struct bcma_drv_pci drv_pci;
4865 + struct bcma_drv_pci drv_pci[2];
4866 struct bcma_drv_mips drv_mips;
4867 + struct bcma_drv_gmac_cmn drv_gmac_cmn;
4868
4869 /* We decided to share SPROM struct with SSB as long as we do not need
4870 * any hacks for BCMA. This simplifies drivers code. */
4871 @@ -282,6 +418,7 @@ static inline void bcma_maskset16(struct
4872 bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
4873 }
4874
4875 +extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
4876 extern bool bcma_core_is_enabled(struct bcma_device *core);
4877 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
4878 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
4879 @@ -289,6 +426,7 @@ extern void bcma_core_set_clockmode(stru
4880 enum bcma_clkmode clkmode);
4881 extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
4882 bool on);
4883 +extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
4884 #define BCMA_DMA_TRANSLATION_MASK 0xC0000000
4885 #define BCMA_DMA_TRANSLATION_NONE 0x00000000
4886 #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
4887 --- a/include/linux/bcma/bcma_driver_chipcommon.h
4888 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
4889 @@ -1,6 +1,9 @@
4890 #ifndef LINUX_BCMA_DRIVER_CC_H_
4891 #define LINUX_BCMA_DRIVER_CC_H_
4892
4893 +#include <linux/platform_device.h>
4894 +#include <linux/gpio.h>
4895 +
4896 /** ChipCommon core registers. **/
4897 #define BCMA_CC_ID 0x0000
4898 #define BCMA_CC_ID_ID 0x0000FFFF
4899 @@ -24,7 +27,7 @@
4900 #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
4901 #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
4902 #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
4903 -#define BCMA_CC_FLASHT_NFLASH 0x00000200
4904 +#define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */
4905 #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
4906 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
4907 #define BCMA_PLLTYPE_NONE 0x00000000
4908 @@ -45,6 +48,7 @@
4909 #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
4910 #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
4911 #define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
4912 +#define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */
4913 #define BCMA_CC_CORECTL 0x0008
4914 #define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
4915 #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
4916 @@ -56,6 +60,9 @@
4917 #define BCMA_CC_OTPS_HW_PROTECT 0x00000001
4918 #define BCMA_CC_OTPS_SW_PROTECT 0x00000002
4919 #define BCMA_CC_OTPS_CID_PROTECT 0x00000004
4920 +#define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */
4921 +#define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8
4922 +#define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */
4923 #define BCMA_CC_OTPC 0x0014 /* OTP control */
4924 #define BCMA_CC_OTPC_RECWAIT 0xFF000000
4925 #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
4926 @@ -72,6 +79,8 @@
4927 #define BCMA_CC_OTPP_READ 0x40000000
4928 #define BCMA_CC_OTPP_START 0x80000000
4929 #define BCMA_CC_OTPP_BUSY 0x80000000
4930 +#define BCMA_CC_OTPL 0x001C /* OTP layout */
4931 +#define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
4932 #define BCMA_CC_IRQSTAT 0x0020
4933 #define BCMA_CC_IRQMASK 0x0024
4934 #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
4935 @@ -79,6 +88,23 @@
4936 #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
4937 #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
4938 #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
4939 +#define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
4940 +#define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
4941 +#define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
4942 +#define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
4943 +#define BCMA_CC_CHIPST_43228_ILP_DIV_EN 0x00000001
4944 +#define BCMA_CC_CHIPST_43228_OTP_PRESENT 0x00000002
4945 +#define BCMA_CC_CHIPST_43228_SERDES_REFCLK_PADSEL 0x00000004
4946 +#define BCMA_CC_CHIPST_43228_SDIO_MODE 0x00000008
4947 +#define BCMA_CC_CHIPST_43228_SDIO_OTP_PRESENT 0x00000010
4948 +#define BCMA_CC_CHIPST_43228_SDIO_RESET 0x00000020
4949 +#define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
4950 +#define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
4951 +#define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
4952 +#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
4953 +#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
4954 +#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
4955 +#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
4956 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
4957 #define BCMA_CC_JCMD_START 0x80000000
4958 #define BCMA_CC_JCMD_BUSY 0x80000000
4959 @@ -108,10 +134,58 @@
4960 #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
4961 #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
4962 #define BCMA_CC_FLASHCTL 0x0040
4963 +/* Start/busy bit in flashcontrol */
4964 +#define BCMA_CC_FLASHCTL_OPCODE 0x000000ff
4965 +#define BCMA_CC_FLASHCTL_ACTION 0x00000700
4966 +#define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
4967 #define BCMA_CC_FLASHCTL_START 0x80000000
4968 #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
4969 +/* Flashcontrol action + opcodes for ST flashes */
4970 +#define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
4971 +#define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
4972 +#define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
4973 +#define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
4974 +#define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
4975 +#define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */
4976 +#define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */
4977 +#define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */
4978 +#define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
4979 +#define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */
4980 +#define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
4981 +#define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
4982 +/* Flashcontrol action + opcodes for Atmel flashes */
4983 +#define BCMA_CC_FLASHCTL_AT_READ 0x07e8
4984 +#define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2
4985 +#define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7
4986 +#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384
4987 +#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387
4988 +#define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283
4989 +#define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286
4990 +#define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288
4991 +#define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289
4992 +#define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281
4993 +#define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250
4994 +#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
4995 +#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
4996 +#define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253
4997 +#define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255
4998 +#define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260
4999 +#define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261
5000 +#define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
5001 +#define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
5002 #define BCMA_CC_FLASHADDR 0x0044
5003 #define BCMA_CC_FLASHDATA 0x0048
5004 +/* Status register bits for ST flashes */
5005 +#define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */
5006 +#define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */
5007 +#define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */
5008 +#define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2
5009 +#define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */
5010 +/* Status register bits for Atmel flashes */
5011 +#define BCMA_CC_FLASHDATA_AT_READY 0x80
5012 +#define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40
5013 +#define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38
5014 +#define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3
5015 #define BCMA_CC_BCAST_ADDR 0x0050
5016 #define BCMA_CC_BCAST_DATA 0x0054
5017 #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
5018 @@ -181,6 +255,45 @@
5019 #define BCMA_CC_FLASH_CFG 0x0128
5020 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
5021 #define BCMA_CC_FLASH_WAITCNT 0x012C
5022 +#define BCMA_CC_SROM_CONTROL 0x0190
5023 +#define BCMA_CC_SROM_CONTROL_START 0x80000000
5024 +#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
5025 +#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
5026 +#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
5027 +#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
5028 +#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
5029 +#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
5030 +#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
5031 +#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
5032 +#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
5033 +#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
5034 +#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
5035 +#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
5036 +#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
5037 +#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
5038 +/* Block 0x140 - 0x190 registers are chipset specific */
5039 +#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
5040 +#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
5041 +#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
5042 +#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
5043 +#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
5044 +#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
5045 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
5046 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
5047 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
5048 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
5049 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
5050 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
5051 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
5052 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
5053 +/* NAND flash registers for BCM4706 (corerev = 31) */
5054 +#define BCMA_CC_NFLASH_CTL 0x01A0
5055 +#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
5056 +#define BCMA_CC_NFLASH_CONF 0x01A4
5057 +#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
5058 +#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
5059 +#define BCMA_CC_NFLASH_DATA 0x01B0
5060 +#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
5061 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
5062 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
5063 #define BCMA_CC_UART0_DATA 0x0300
5064 @@ -203,6 +316,9 @@
5065 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
5066 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
5067 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
5068 +#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
5069 +#define BCMA_CC_PMU_CTL_RES_SHIFT 13
5070 +#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
5071 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
5072 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
5073 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
5074 @@ -214,6 +330,8 @@
5075 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
5076 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
5077 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
5078 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
5079 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
5080 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
5081 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
5082 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
5083 @@ -239,8 +357,66 @@
5084 #define BCMA_CC_REGCTL_DATA 0x065C
5085 #define BCMA_CC_PLLCTL_ADDR 0x0660
5086 #define BCMA_CC_PLLCTL_DATA 0x0664
5087 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
5088 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
5089 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
5090 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
5091 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
5092 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
5093 -#define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */
5094 +/* NAND flash MLC controller registers (corerev >= 38) */
5095 +#define BCMA_CC_NAND_REVISION 0x0C00
5096 +#define BCMA_CC_NAND_CMD_START 0x0C04
5097 +#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
5098 +#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
5099 +#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
5100 +#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
5101 +#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
5102 +#define BCMA_CC_NAND_SPARE_RD0 0x0C20
5103 +#define BCMA_CC_NAND_SPARE_RD4 0x0C24
5104 +#define BCMA_CC_NAND_SPARE_RD8 0x0C28
5105 +#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
5106 +#define BCMA_CC_NAND_SPARE_WR0 0x0C30
5107 +#define BCMA_CC_NAND_SPARE_WR4 0x0C34
5108 +#define BCMA_CC_NAND_SPARE_WR8 0x0C38
5109 +#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
5110 +#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
5111 +#define BCMA_CC_NAND_CONFIG 0x0C48
5112 +#define BCMA_CC_NAND_TIMING_1 0x0C50
5113 +#define BCMA_CC_NAND_TIMING_2 0x0C54
5114 +#define BCMA_CC_NAND_SEMAPHORE 0x0C58
5115 +#define BCMA_CC_NAND_DEVID 0x0C60
5116 +#define BCMA_CC_NAND_DEVID_X 0x0C64
5117 +#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
5118 +#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
5119 +#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
5120 +#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
5121 +#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
5122 +#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
5123 +#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
5124 +#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
5125 +#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
5126 +#define BCMA_CC_NAND_READ_ADDR 0x0C94
5127 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
5128 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
5129 +#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
5130 +#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
5131 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
5132 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
5133 +#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
5134 +#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
5135 +#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
5136 +#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
5137 +#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
5138 +#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
5139 +#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
5140 +#define BCMA_CC_NAND_SPARE_RD16 0x0D30
5141 +#define BCMA_CC_NAND_SPARE_RD20 0x0D34
5142 +#define BCMA_CC_NAND_SPARE_RD24 0x0D38
5143 +#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
5144 +#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
5145 +#define BCMA_CC_NAND_CACHE_DATA 0x0D44
5146 +#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
5147 +#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
5148
5149 /* Divider allocation in 4716/47162/5356 */
5150 #define BCMA_CC_PMU5_MAINPLL_CPU 1
5151 @@ -256,6 +432,32 @@
5152
5153 /* 4706 PMU */
5154 #define BCMA_CC_PMU4706_MAINPLL_PLL0 0
5155 +#define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */
5156 +#define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000
5157 +#define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16
5158 +#define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000
5159 +#define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12
5160 +#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8
5161 +#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3
5162 +#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
5163 +#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
5164 +
5165 +/* PMU rev 15 */
5166 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
5167 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
5168 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
5169 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
5170 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
5171 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
5172 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
5173 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
5174 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
5175 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
5176 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
5177 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
5178 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
5179 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
5180 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
5181
5182 /* ALP clock on pre-PMU chips */
5183 #define BCMA_CC_PMU_ALP_CLOCK 20000000
5184 @@ -284,6 +486,19 @@
5185 #define BCMA_CC_PPL_PCHI_OFF 5
5186 #define BCMA_CC_PPL_PCHI_MASK 0x0000003f
5187
5188 +#define BCMA_CC_PMU_PLL_CTL0 0
5189 +#define BCMA_CC_PMU_PLL_CTL1 1
5190 +#define BCMA_CC_PMU_PLL_CTL2 2
5191 +#define BCMA_CC_PMU_PLL_CTL3 3
5192 +#define BCMA_CC_PMU_PLL_CTL4 4
5193 +#define BCMA_CC_PMU_PLL_CTL5 5
5194 +
5195 +#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
5196 +#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20
5197 +
5198 +#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
5199 +#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
5200 +
5201 /* BCM4331 ChipControl numbers. */
5202 #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
5203 #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
5204 @@ -297,9 +512,56 @@
5205 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
5206 #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
5207 #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
5208 +#define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */
5209 #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
5210 #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
5211
5212 +/* 43224 chip-specific ChipControl register bits */
5213 +#define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
5214 +#define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
5215 +#define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
5216 +
5217 +/* 4313 Chip specific ChipControl register bits */
5218 +#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
5219 +
5220 +/* BCM5357 ChipControl register bits */
5221 +#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
5222 +#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
5223 +#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
5224 +#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
5225 +#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
5226 +
5227 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
5228 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
5229 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
5230 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
5231 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
5232 +#define BCMA_RES_4314_CLDO_PU BIT(5)
5233 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
5234 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
5235 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
5236 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
5237 +#define BCMA_RES_4314_OTP_PU BIT(10)
5238 +#define BCMA_RES_4314_XTAL_PU BIT(11)
5239 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
5240 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
5241 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
5242 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
5243 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
5244 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
5245 +#define BCMA_RES_4314_ILP_REQ BIT(18)
5246 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
5247 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
5248 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
5249 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
5250 +#define BCMA_RES_4314_RADIO_PU BIT(23)
5251 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
5252 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
5253 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
5254 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
5255 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
5256 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
5257 +
5258 /* Data for the PMU, if available.
5259 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
5260 */
5261 @@ -310,11 +572,36 @@ struct bcma_chipcommon_pmu {
5262
5263 #ifdef CONFIG_BCMA_DRIVER_MIPS
5264 struct bcma_pflash {
5265 + bool present;
5266 u8 buswidth;
5267 u32 window;
5268 u32 window_size;
5269 };
5270
5271 +#ifdef CONFIG_BCMA_SFLASH
5272 +struct bcma_sflash {
5273 + bool present;
5274 + u32 window;
5275 + u32 blocksize;
5276 + u16 numblocks;
5277 + u32 size;
5278 +
5279 + struct mtd_info *mtd;
5280 + void *priv;
5281 +};
5282 +#endif
5283 +
5284 +#ifdef CONFIG_BCMA_NFLASH
5285 +struct mtd_info;
5286 +
5287 +struct bcma_nflash {
5288 + bool present;
5289 + bool boot; /* This is the flash the SoC boots from */
5290 +
5291 + struct mtd_info *mtd;
5292 +};
5293 +#endif
5294 +
5295 struct bcma_serial_port {
5296 void *regs;
5297 unsigned long clockspeed;
5298 @@ -330,15 +617,30 @@ struct bcma_drv_cc {
5299 u32 capabilities;
5300 u32 capabilities_ext;
5301 u8 setup_done:1;
5302 + u8 early_setup_done:1;
5303 /* Fast Powerup Delay constant */
5304 u16 fast_pwrup_delay;
5305 struct bcma_chipcommon_pmu pmu;
5306 #ifdef CONFIG_BCMA_DRIVER_MIPS
5307 struct bcma_pflash pflash;
5308 +#ifdef CONFIG_BCMA_SFLASH
5309 + struct bcma_sflash sflash;
5310 +#endif
5311 +#ifdef CONFIG_BCMA_NFLASH
5312 + struct bcma_nflash nflash;
5313 +#endif
5314
5315 int nr_serial_ports;
5316 struct bcma_serial_port serial_ports[4];
5317 #endif /* CONFIG_BCMA_DRIVER_MIPS */
5318 + u32 ticks_per_ms;
5319 + struct platform_device *watchdog;
5320 +
5321 + /* Lock for GPIO register access. */
5322 + spinlock_t gpio_lock;
5323 +#ifdef CONFIG_BCMA_DRIVER_GPIO
5324 + struct gpio_chip gpio;
5325 +#endif
5326 };
5327
5328 /* Register access */
5329 @@ -355,14 +657,16 @@ struct bcma_drv_cc {
5330 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
5331
5332 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
5333 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
5334
5335 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
5336 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
5337
5338 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
5339
5340 -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
5341 - u32 ticks);
5342 +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
5343 +
5344 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
5345
5346 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
5347
5348 @@ -375,9 +679,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
5349 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
5350 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
5351 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
5352 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
5353 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
5354
5355 /* PMU support */
5356 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
5357 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
5358
5359 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
5360 u32 value);
5361 @@ -387,5 +694,8 @@ extern void bcma_chipco_chipctl_maskset(
5362 u32 offset, u32 mask, u32 set);
5363 extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
5364 u32 offset, u32 mask, u32 set);
5365 +extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
5366 +
5367 +extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
5368
5369 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
5370 --- /dev/null
5371 +++ b/include/linux/bcma/bcma_driver_gmac_cmn.h
5372 @@ -0,0 +1,100 @@
5373 +#ifndef LINUX_BCMA_DRIVER_GMAC_CMN_H_
5374 +#define LINUX_BCMA_DRIVER_GMAC_CMN_H_
5375 +
5376 +#include <linux/types.h>
5377 +
5378 +#define BCMA_GMAC_CMN_STAG0 0x000
5379 +#define BCMA_GMAC_CMN_STAG1 0x004
5380 +#define BCMA_GMAC_CMN_STAG2 0x008
5381 +#define BCMA_GMAC_CMN_STAG3 0x00C
5382 +#define BCMA_GMAC_CMN_PARSER_CTL 0x020
5383 +#define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
5384 +#define BCMA_GMAC_CMN_PHY_ACCESS 0x100
5385 +#define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
5386 +#define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
5387 +#define BCMA_GMAC_CMN_PA_ADDR_SHIFT 16
5388 +#define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
5389 +#define BCMA_GMAC_CMN_PA_REG_SHIFT 24
5390 +#define BCMA_GMAC_CMN_PA_WRITE 0x20000000
5391 +#define BCMA_GMAC_CMN_PA_START 0x40000000
5392 +#define BCMA_GMAC_CMN_PHY_CTL 0x104
5393 +#define BCMA_GMAC_CMN_PC_EPA_MASK 0x0000001f
5394 +#define BCMA_GMAC_CMN_PC_MCT_MASK 0x007f0000
5395 +#define BCMA_GMAC_CMN_PC_MCT_SHIFT 16
5396 +#define BCMA_GMAC_CMN_PC_MTE 0x00800000
5397 +#define BCMA_GMAC_CMN_GMAC0_RGMII_CTL 0x110
5398 +#define BCMA_GMAC_CMN_CFP_ACCESS 0x200
5399 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA0 0x210
5400 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA1 0x214
5401 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA2 0x218
5402 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA3 0x21C
5403 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA4 0x220
5404 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA5 0x224
5405 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA6 0x228
5406 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA7 0x22C
5407 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK0 0x230
5408 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK1 0x234
5409 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK2 0x238
5410 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK3 0x23C
5411 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK4 0x240
5412 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK5 0x244
5413 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK6 0x248
5414 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK7 0x24C
5415 +#define BCMA_GMAC_CMN_CFP_ACTION_DATA 0x250
5416 +#define BCMA_GMAC_CMN_TCAM_BIST_CTL 0x2A0
5417 +#define BCMA_GMAC_CMN_TCAM_BIST_STATUS 0x2A4
5418 +#define BCMA_GMAC_CMN_TCAM_CMP_STATUS 0x2A8
5419 +#define BCMA_GMAC_CMN_TCAM_DISABLE 0x2AC
5420 +#define BCMA_GMAC_CMN_TCAM_TEST_CTL 0x2F0
5421 +#define BCMA_GMAC_CMN_UDF_0_A3_A0 0x300
5422 +#define BCMA_GMAC_CMN_UDF_0_A7_A4 0x304
5423 +#define BCMA_GMAC_CMN_UDF_0_A8 0x308
5424 +#define BCMA_GMAC_CMN_UDF_1_A3_A0 0x310
5425 +#define BCMA_GMAC_CMN_UDF_1_A7_A4 0x314
5426 +#define BCMA_GMAC_CMN_UDF_1_A8 0x318
5427 +#define BCMA_GMAC_CMN_UDF_2_A3_A0 0x320
5428 +#define BCMA_GMAC_CMN_UDF_2_A7_A4 0x324
5429 +#define BCMA_GMAC_CMN_UDF_2_A8 0x328
5430 +#define BCMA_GMAC_CMN_UDF_0_B3_B0 0x330
5431 +#define BCMA_GMAC_CMN_UDF_0_B7_B4 0x334
5432 +#define BCMA_GMAC_CMN_UDF_0_B8 0x338
5433 +#define BCMA_GMAC_CMN_UDF_1_B3_B0 0x340
5434 +#define BCMA_GMAC_CMN_UDF_1_B7_B4 0x344
5435 +#define BCMA_GMAC_CMN_UDF_1_B8 0x348
5436 +#define BCMA_GMAC_CMN_UDF_2_B3_B0 0x350
5437 +#define BCMA_GMAC_CMN_UDF_2_B7_B4 0x354
5438 +#define BCMA_GMAC_CMN_UDF_2_B8 0x358
5439 +#define BCMA_GMAC_CMN_UDF_0_C3_C0 0x360
5440 +#define BCMA_GMAC_CMN_UDF_0_C7_C4 0x364
5441 +#define BCMA_GMAC_CMN_UDF_0_C8 0x368
5442 +#define BCMA_GMAC_CMN_UDF_1_C3_C0 0x370
5443 +#define BCMA_GMAC_CMN_UDF_1_C7_C4 0x374
5444 +#define BCMA_GMAC_CMN_UDF_1_C8 0x378
5445 +#define BCMA_GMAC_CMN_UDF_2_C3_C0 0x380
5446 +#define BCMA_GMAC_CMN_UDF_2_C7_C4 0x384
5447 +#define BCMA_GMAC_CMN_UDF_2_C8 0x388
5448 +#define BCMA_GMAC_CMN_UDF_0_D3_D0 0x390
5449 +#define BCMA_GMAC_CMN_UDF_0_D7_D4 0x394
5450 +#define BCMA_GMAC_CMN_UDF_0_D11_D8 0x394
5451 +
5452 +struct bcma_drv_gmac_cmn {
5453 + struct bcma_device *core;
5454 +
5455 + /* Drivers accessing BCMA_GMAC_CMN_PHY_ACCESS and
5456 + * BCMA_GMAC_CMN_PHY_CTL need to take that mutex first. */
5457 + struct mutex phy_mutex;
5458 +};
5459 +
5460 +/* Register access */
5461 +#define gmac_cmn_read16(gc, offset) bcma_read16((gc)->core, offset)
5462 +#define gmac_cmn_read32(gc, offset) bcma_read32((gc)->core, offset)
5463 +#define gmac_cmn_write16(gc, offset, val) bcma_write16((gc)->core, offset, val)
5464 +#define gmac_cmn_write32(gc, offset, val) bcma_write32((gc)->core, offset, val)
5465 +
5466 +#ifdef CONFIG_BCMA_DRIVER_GMAC_CMN
5467 +extern void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc);
5468 +#else
5469 +static inline void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) { }
5470 +#endif
5471 +
5472 +#endif /* LINUX_BCMA_DRIVER_GMAC_CMN_H_ */
5473 --- a/include/linux/bcma/bcma_driver_mips.h
5474 +++ b/include/linux/bcma/bcma_driver_mips.h
5475 @@ -28,6 +28,7 @@
5476 #define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
5477 #define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
5478
5479 +#define BCMA_MIPS_OOBSELINA74 0x004
5480 #define BCMA_MIPS_OOBSELOUTA30 0x100
5481
5482 struct bcma_device;
5483 @@ -35,17 +36,24 @@ struct bcma_device;
5484 struct bcma_drv_mips {
5485 struct bcma_device *core;
5486 u8 setup_done:1;
5487 - unsigned int assigned_irqs;
5488 + u8 early_setup_done:1;
5489 };
5490
5491 #ifdef CONFIG_BCMA_DRIVER_MIPS
5492 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
5493 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
5494 +
5495 +extern unsigned int bcma_core_irq(struct bcma_device *core);
5496 #else
5497 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
5498 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
5499 +
5500 +static inline unsigned int bcma_core_irq(struct bcma_device *core)
5501 +{
5502 + return 0;
5503 +}
5504 #endif
5505
5506 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
5507
5508 -extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
5509 -
5510 #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
5511 --- a/include/linux/bcma/bcma_driver_pci.h
5512 +++ b/include/linux/bcma/bcma_driver_pci.h
5513 @@ -53,11 +53,47 @@ struct pci_dev;
5514 #define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
5515 #define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
5516 #define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
5517 +#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
5518 +#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
5519 +#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */
5520 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
5521 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2
5522 +#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
5523 +#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
5524 +#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */
5525 +#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */
5526 +#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */
5527 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
5528 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
5529 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
5530 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
5531 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
5532 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
5533 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
5534 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
5535 +#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */
5536 +#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */
5537 +#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */
5538 +#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
5539 +#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
5540 +#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
5541 +#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
5542 +#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
5543 +#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */
5544 +#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */
5545 +#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */
5546 #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
5547 #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
5548 #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
5549 #define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
5550 #define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
5551 +#define BCMA_CORE_PCI_SPROM_PI_OFFSET 0 /* first word */
5552 +#define BCMA_CORE_PCI_SPROM_PI_MASK 0xf000 /* bit 15:12 */
5553 +#define BCMA_CORE_PCI_SPROM_PI_SHIFT 12 /* bit 15:12 */
5554 +#define BCMA_CORE_PCI_SPROM_MISC_CONFIG 5 /* word 5 */
5555 +#define BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
5556 +#define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
5557 +#define BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800 /* bit 11 */
5558
5559 /* SBtoPCIx */
5560 #define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
5561 @@ -72,20 +108,142 @@ struct pci_dev;
5562 #define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
5563 #define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
5564
5565 +/* PCIE protocol PHY diagnostic registers */
5566 +#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */
5567 +#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */
5568 +#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */
5569 +#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
5570 +#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
5571 +#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
5572 +#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
5573 +#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */
5574 +#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */
5575 +#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */
5576 +#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
5577 +#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
5578 +#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */
5579 +#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
5580 +#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
5581 +#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
5582 +#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
5583 +
5584 +/* PCIE protocol DLLP diagnostic registers */
5585 +#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */
5586 +#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */
5587 +#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */
5588 +#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)
5589 +#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
5590 +#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
5591 +#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
5592 +#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
5593 +#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
5594 +#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */
5595 +#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
5596 +#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
5597 +#define BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */
5598 +#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
5599 +#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
5600 +#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
5601 +#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
5602 +#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
5603 +#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
5604 +#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */
5605 +#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
5606 +#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */
5607 +#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */
5608 +#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
5609 +
5610 +/* SERDES RX registers */
5611 +#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */
5612 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
5613 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
5614 +#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */
5615 +#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */
5616 +#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */
5617 +
5618 +/* SERDES PLL registers */
5619 +#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */
5620 +#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
5621 +
5622 /* PCIcore specific boardflags */
5623 #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
5624
5625 +/* PCIE Config space accessing MACROS */
5626 +#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */
5627 +#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */
5628 +#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */
5629 +#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */
5630 +
5631 +#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */
5632 +#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */
5633 +#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
5634 +#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
5635 +
5636 +#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
5637 +
5638 +#define BCMA_CORE_PCI_
5639 +
5640 +/* MDIO devices (SERDES modules) */
5641 +#define BCMA_CORE_PCI_MDIO_IEEE0 0x000
5642 +#define BCMA_CORE_PCI_MDIO_IEEE1 0x001
5643 +#define BCMA_CORE_PCI_MDIO_BLK0 0x800
5644 +#define BCMA_CORE_PCI_MDIO_BLK1 0x801
5645 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16
5646 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17
5647 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18
5648 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19
5649 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A
5650 +#define BCMA_CORE_PCI_MDIO_BLK2 0x802
5651 +#define BCMA_CORE_PCI_MDIO_BLK3 0x803
5652 +#define BCMA_CORE_PCI_MDIO_BLK4 0x804
5653 +#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */
5654 +#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820
5655 +#define BCMA_CORE_PCI_MDIO_SERDESID 0x831
5656 +#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840
5657 +
5658 +/* PCIE Root Capability Register bits (Host mode only) */
5659 +#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
5660 +
5661 +struct bcma_drv_pci;
5662 +struct bcma_bus;
5663 +
5664 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
5665 +struct bcma_drv_pci_host {
5666 + struct bcma_drv_pci *pdev;
5667 +
5668 + u32 host_cfg_addr;
5669 + spinlock_t cfgspace_lock;
5670 +
5671 + struct pci_controller pci_controller;
5672 + struct pci_ops pci_ops;
5673 + struct resource mem_resource;
5674 + struct resource io_resource;
5675 +};
5676 +#endif
5677 +
5678 struct bcma_drv_pci {
5679 struct bcma_device *core;
5680 u8 setup_done:1;
5681 + u8 hostmode:1;
5682 +
5683 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
5684 + struct bcma_drv_pci_host *host_controller;
5685 +#endif
5686 };
5687
5688 /* Register access */
5689 +#define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)
5690 #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
5691 +#define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)
5692 #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
5693
5694 -extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
5695 +extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc);
5696 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
5697 struct bcma_device *core, bool enable);
5698 +extern void bcma_core_pci_up(struct bcma_bus *bus);
5699 +extern void bcma_core_pci_down(struct bcma_bus *bus);
5700 +
5701 +extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
5702 +extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
5703
5704 #endif /* LINUX_BCMA_DRIVER_PCI_H_ */
5705 --- a/include/linux/bcma/bcma_regs.h
5706 +++ b/include/linux/bcma/bcma_regs.h
5707 @@ -11,11 +11,13 @@
5708 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
5709 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
5710 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
5711 +#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8
5712 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
5713 #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
5714 #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
5715 #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
5716 #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
5717 +#define BCMA_CLKCTLST_EXTRESST_SHIFT 24
5718 /* Is there any BCM4328 on BCMA bus? */
5719 #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
5720 #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
5721 @@ -35,6 +37,7 @@
5722 #define BCMA_IOST_BIST_DONE 0x8000
5723 #define BCMA_RESET_CTL 0x0800
5724 #define BCMA_RESET_CTL_RESET 0x0001
5725 +#define BCMA_RESET_ST 0x0804
5726
5727 /* BCMA PCI config space registers. */
5728 #define BCMA_PCI_PMCSR 0x44
5729 @@ -56,4 +59,36 @@
5730 #define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
5731 #define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
5732
5733 +/* SiliconBackplane Address Map.
5734 + * All regions may not exist on all chips.
5735 + */
5736 +#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */
5737 +#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
5738 +#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024)
5739 +#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
5740 +#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
5741 +#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */
5742 +
5743 +
5744 +#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
5745 +#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */
5746 +#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
5747 +#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2
5748 + * (2 ZettaBytes), low 32 bits
5749 + */
5750 +#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2
5751 + * (2 ZettaBytes), high 32 bits
5752 + */
5753 +
5754 +#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
5755 +#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
5756 +#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2
5757 + * (2 ZettaBytes), high 32 bits
5758 + */
5759 +
5760 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
5761 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
5762 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
5763 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
5764 +
5765 #endif /* LINUX_BCMA_REGS_H_ */
5766 --- a/drivers/net/wireless/b43/main.c
5767 +++ b/drivers/net/wireless/b43/main.c
5768 @@ -4618,7 +4618,7 @@ static int b43_wireless_core_init(struct
5769 switch (dev->dev->bus_type) {
5770 #ifdef CONFIG_B43_BCMA
5771 case B43_BUS_BCMA:
5772 - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
5773 + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
5774 dev->dev->bdev, true);
5775 break;
5776 #endif
5777 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
5778 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
5779 @@ -533,7 +533,7 @@ ai_buscore_setup(struct si_info *sii, st
5780
5781 /* fixup necessary chip/core configurations */
5782 if (!sii->pch) {
5783 - sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci.core);
5784 + sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci[0].core);
5785 if (sii->pch == NULL)
5786 return false;
5787 }
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