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kernel/generic: add a few missing kernel config symbols
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.3 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -29,7 +29,7 @@ config BCMA_HOST_PCI
4
5 config BCMA_DRIVER_PCI_HOSTMODE
6 bool "Driver for PCI core working in hostmode"
7 - depends on BCMA && MIPS
8 + depends on BCMA && MIPS && BCMA_HOST_PCI
9 help
10 PCI core hostmode operation (external PCI bus).
11
12 @@ -46,6 +46,33 @@ config BCMA_DRIVER_MIPS
13
14 If unsure, say N
15
16 +config BCMA_SFLASH
17 + bool
18 + depends on BCMA_DRIVER_MIPS
19 + default y
20 +
21 +config BCMA_NFLASH
22 + bool
23 + depends on BCMA_DRIVER_MIPS
24 + default y
25 +
26 +config BCMA_DRIVER_GMAC_CMN
27 + bool "BCMA Broadcom GBIT MAC COMMON core driver"
28 + depends on BCMA
29 + help
30 + Driver for the Broadcom GBIT MAC COMMON core attached to Broadcom
31 + specific Advanced Microcontroller Bus.
32 +
33 + If unsure, say N
34 +
35 +config BCMA_DRIVER_GPIO
36 + bool "BCMA GPIO driver"
37 + depends on BCMA && GPIOLIB
38 + help
39 + Driver to provide access to the GPIO pins of the bcma bus.
40 +
41 + If unsure, say N
42 +
43 config BCMA_DEBUG
44 bool "BCMA debugging"
45 depends on BCMA
46 --- a/drivers/bcma/Makefile
47 +++ b/drivers/bcma/Makefile
48 @@ -1,8 +1,12 @@
49 bcma-y += main.o scan.o core.o sprom.o
50 bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
51 +bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
52 +bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
53 bcma-y += driver_pci.o
54 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
55 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
56 +bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
57 +bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o
58 bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
59 bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
60 obj-$(CONFIG_BCMA) += bcma.o
61 --- a/drivers/bcma/bcma_private.h
62 +++ b/drivers/bcma/bcma_private.h
63 @@ -10,10 +10,19 @@
64
65 #define BCMA_CORE_SIZE 0x1000
66
67 +#define bcma_err(bus, fmt, ...) \
68 + pr_err("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
69 +#define bcma_warn(bus, fmt, ...) \
70 + pr_warn("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
71 +#define bcma_info(bus, fmt, ...) \
72 + pr_info("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
73 +#define bcma_debug(bus, fmt, ...) \
74 + pr_debug("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
75 +
76 struct bcma_bus;
77
78 /* main.c */
79 -int bcma_bus_register(struct bcma_bus *bus);
80 +int __devinit bcma_bus_register(struct bcma_bus *bus);
81 void bcma_bus_unregister(struct bcma_bus *bus);
82 int __init bcma_bus_early_register(struct bcma_bus *bus,
83 struct bcma_device *core_cc,
84 @@ -22,6 +31,8 @@ int __init bcma_bus_early_register(struc
85 int bcma_bus_suspend(struct bcma_bus *bus);
86 int bcma_bus_resume(struct bcma_bus *bus);
87 #endif
88 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
89 + u8 unit);
90
91 /* scan.c */
92 int bcma_bus_scan(struct bcma_bus *bus);
93 @@ -39,8 +50,32 @@ void bcma_chipco_serial_init(struct bcma
94 #endif /* CONFIG_BCMA_DRIVER_MIPS */
95
96 /* driver_chipcommon_pmu.c */
97 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
98 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
99 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
100 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
101 +
102 +#ifdef CONFIG_BCMA_SFLASH
103 +/* driver_chipcommon_sflash.c */
104 +int bcma_sflash_init(struct bcma_drv_cc *cc);
105 +extern struct platform_device bcma_sflash_dev;
106 +#else
107 +static inline int bcma_sflash_init(struct bcma_drv_cc *cc)
108 +{
109 + bcma_err(cc->core->bus, "Serial flash not supported\n");
110 + return 0;
111 +}
112 +#endif /* CONFIG_BCMA_SFLASH */
113 +
114 +#ifdef CONFIG_BCMA_NFLASH
115 +/* driver_chipcommon_nflash.c */
116 +int bcma_nflash_init(struct bcma_drv_cc *cc);
117 +extern struct platform_device bcma_nflash_dev;
118 +#else
119 +static inline int bcma_nflash_init(struct bcma_drv_cc *cc)
120 +{
121 + bcma_err(cc->core->bus, "NAND flash not supported\n");
122 + return 0;
123 +}
124 +#endif /* CONFIG_BCMA_NFLASH */
125
126 #ifdef CONFIG_BCMA_HOST_PCI
127 /* host_pci.c */
128 @@ -48,8 +83,24 @@ extern int __init bcma_host_pci_init(voi
129 extern void __exit bcma_host_pci_exit(void);
130 #endif /* CONFIG_BCMA_HOST_PCI */
131
132 +/* driver_pci.c */
133 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
134 +
135 +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
136 +
137 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
138 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
139 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
140 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
141 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
142
143 +#ifdef CONFIG_BCMA_DRIVER_GPIO
144 +/* driver_gpio.c */
145 +int bcma_gpio_init(struct bcma_drv_cc *cc);
146 +#else
147 +static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
148 +{
149 + return -ENOTSUPP;
150 +}
151 +#endif /* CONFIG_BCMA_DRIVER_GPIO */
152 +
153 #endif
154 --- a/drivers/bcma/core.c
155 +++ b/drivers/bcma/core.c
156 @@ -30,6 +30,7 @@ void bcma_core_disable(struct bcma_devic
157 udelay(10);
158
159 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
160 + bcma_aread32(core, BCMA_RESET_CTL);
161 udelay(1);
162 }
163 EXPORT_SYMBOL_GPL(bcma_core_disable);
164 @@ -64,7 +65,7 @@ void bcma_core_set_clockmode(struct bcma
165 switch (clkmode) {
166 case BCMA_CLKMODE_FAST:
167 bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
168 - udelay(64);
169 + usleep_range(64, 300);
170 for (i = 0; i < 1500; i++) {
171 if (bcma_read32(core, BCMA_CLKCTLST) &
172 BCMA_CLKCTLST_HAVEHT) {
173 @@ -74,10 +75,10 @@ void bcma_core_set_clockmode(struct bcma
174 udelay(10);
175 }
176 if (i)
177 - pr_err("HT force timeout\n");
178 + bcma_err(core->bus, "HT force timeout\n");
179 break;
180 case BCMA_CLKMODE_DYNAMIC:
181 - pr_warn("Dynamic clockmode not supported yet!\n");
182 + bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT);
183 break;
184 }
185 }
186 @@ -101,9 +102,9 @@ void bcma_core_pll_ctl(struct bcma_devic
187 udelay(10);
188 }
189 if (i)
190 - pr_err("PLL enable timeout\n");
191 + bcma_err(core->bus, "PLL enable timeout\n");
192 } else {
193 - pr_warn("Disabling PLL not supported yet!\n");
194 + bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
195 }
196 }
197 EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
198 @@ -119,8 +120,8 @@ u32 bcma_core_dma_translation(struct bcm
199 else
200 return BCMA_DMA_TRANSLATION_DMA32_CMT;
201 default:
202 - pr_err("DMA translation unknown for host %d\n",
203 - core->bus->hosttype);
204 + bcma_err(core->bus, "DMA translation unknown for host %d\n",
205 + core->bus->hosttype);
206 }
207 return BCMA_DMA_TRANSLATION_NONE;
208 }
209 --- a/drivers/bcma/driver_chipcommon.c
210 +++ b/drivers/bcma/driver_chipcommon.c
211 @@ -4,12 +4,15 @@
212 *
213 * Copyright 2005, Broadcom Corporation
214 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
215 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
216 *
217 * Licensed under the GNU/GPL. See COPYING for details.
218 */
219
220 #include "bcma_private.h"
221 +#include <linux/bcm47xx_wdt.h>
222 #include <linux/export.h>
223 +#include <linux/platform_device.h>
224 #include <linux/bcma/bcma.h>
225
226 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
227 @@ -22,20 +25,120 @@ static inline u32 bcma_cc_write32_masked
228 return value;
229 }
230
231 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
232 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
233 {
234 - u32 leddc_on = 10;
235 - u32 leddc_off = 90;
236 + if (cc->capabilities & BCMA_CC_CAP_PMU)
237 + return bcma_pmu_get_alp_clock(cc);
238
239 - if (cc->setup_done)
240 + return 20000000;
241 +}
242 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
243 +
244 +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
245 +{
246 + struct bcma_bus *bus = cc->core->bus;
247 + u32 nb;
248 +
249 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
250 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
251 + nb = 32;
252 + else if (cc->core->id.rev < 26)
253 + nb = 16;
254 + else
255 + nb = (cc->core->id.rev >= 37) ? 32 : 24;
256 + } else {
257 + nb = 28;
258 + }
259 + if (nb == 32)
260 + return 0xffffffff;
261 + else
262 + return (1 << nb) - 1;
263 +}
264 +
265 +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
266 + u32 ticks)
267 +{
268 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
269 +
270 + return bcma_chipco_watchdog_timer_set(cc, ticks);
271 +}
272 +
273 +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
274 + u32 ms)
275 +{
276 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
277 + u32 ticks;
278 +
279 + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
280 + return ticks / cc->ticks_per_ms;
281 +}
282 +
283 +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
284 +{
285 + struct bcma_bus *bus = cc->core->bus;
286 +
287 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
288 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
289 + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
290 + return bcma_chipco_get_alp_clock(cc) / 4000;
291 + else
292 + /* based on 32KHz ILP clock */
293 + return 32;
294 + } else {
295 + return bcma_chipco_get_alp_clock(cc) / 1000;
296 + }
297 +}
298 +
299 +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
300 +{
301 + struct bcm47xx_wdt wdt = {};
302 + struct platform_device *pdev;
303 +
304 + wdt.driver_data = cc;
305 + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
306 + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
307 + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
308 +
309 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
310 + cc->core->bus->num, &wdt,
311 + sizeof(wdt));
312 + if (IS_ERR(pdev))
313 + return PTR_ERR(pdev);
314 +
315 + cc->watchdog = pdev;
316 +
317 + return 0;
318 +}
319 +
320 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
321 +{
322 + if (cc->early_setup_done)
323 return;
324
325 + spin_lock_init(&cc->gpio_lock);
326 +
327 if (cc->core->id.rev >= 11)
328 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
329 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
330 if (cc->core->id.rev >= 35)
331 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
332
333 + if (cc->capabilities & BCMA_CC_CAP_PMU)
334 + bcma_pmu_early_init(cc);
335 +
336 + cc->early_setup_done = true;
337 +}
338 +
339 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
340 +{
341 + u32 leddc_on = 10;
342 + u32 leddc_off = 90;
343 +
344 + if (cc->setup_done)
345 + return;
346 +
347 + bcma_core_chipcommon_early_init(cc);
348 +
349 if (cc->core->id.rev >= 20) {
350 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
351 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
352 @@ -44,7 +147,7 @@ void bcma_core_chipcommon_init(struct bc
353 if (cc->capabilities & BCMA_CC_CAP_PMU)
354 bcma_pmu_init(cc);
355 if (cc->capabilities & BCMA_CC_CAP_PCTL)
356 - pr_err("Power control not implemented!\n");
357 + bcma_err(cc->core->bus, "Power control not implemented!\n");
358
359 if (cc->core->id.rev >= 16) {
360 if (cc->core->bus->sprom.leddc_on_time &&
361 @@ -56,15 +159,33 @@ void bcma_core_chipcommon_init(struct bc
362 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
363 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
364 }
365 + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
366
367 cc->setup_done = true;
368 }
369
370 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
371 -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
372 +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
373 {
374 - /* instant NMI */
375 - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
376 + u32 maxt;
377 + enum bcma_clkmode clkmode;
378 +
379 + maxt = bcma_chipco_watchdog_get_max_timer(cc);
380 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
381 + if (ticks == 1)
382 + ticks = 2;
383 + else if (ticks > maxt)
384 + ticks = maxt;
385 + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
386 + } else {
387 + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
388 + bcma_core_set_clockmode(cc->core, clkmode);
389 + if (ticks > maxt)
390 + ticks = maxt;
391 + /* instant NMI */
392 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
393 + }
394 + return ticks;
395 }
396
397 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
398 @@ -84,28 +205,99 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
399
400 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
401 {
402 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
403 + unsigned long flags;
404 + u32 res;
405 +
406 + spin_lock_irqsave(&cc->gpio_lock, flags);
407 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
408 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
409 +
410 + return res;
411 }
412 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
413
414 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
415 {
416 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
417 + unsigned long flags;
418 + u32 res;
419 +
420 + spin_lock_irqsave(&cc->gpio_lock, flags);
421 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
422 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
423 +
424 + return res;
425 }
426 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
427
428 +/*
429 + * If the bit is set to 0, chipcommon controlls this GPIO,
430 + * if the bit is set to 1, it is used by some part of the chip and not our code.
431 + */
432 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
433 {
434 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
435 + unsigned long flags;
436 + u32 res;
437 +
438 + spin_lock_irqsave(&cc->gpio_lock, flags);
439 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
440 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
441 +
442 + return res;
443 }
444 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
445
446 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
447 {
448 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
449 + unsigned long flags;
450 + u32 res;
451 +
452 + spin_lock_irqsave(&cc->gpio_lock, flags);
453 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
454 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
455 +
456 + return res;
457 }
458
459 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
460 {
461 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
462 + unsigned long flags;
463 + u32 res;
464 +
465 + spin_lock_irqsave(&cc->gpio_lock, flags);
466 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
467 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
468 +
469 + return res;
470 +}
471 +
472 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
473 +{
474 + unsigned long flags;
475 + u32 res;
476 +
477 + if (cc->core->id.rev < 20)
478 + return 0;
479 +
480 + spin_lock_irqsave(&cc->gpio_lock, flags);
481 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
482 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
483 +
484 + return res;
485 +}
486 +
487 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
488 +{
489 + unsigned long flags;
490 + u32 res;
491 +
492 + if (cc->core->id.rev < 20)
493 + return 0;
494 +
495 + spin_lock_irqsave(&cc->gpio_lock, flags);
496 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
497 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
498 +
499 + return res;
500 }
501
502 #ifdef CONFIG_BCMA_DRIVER_MIPS
503 @@ -118,8 +310,7 @@ void bcma_chipco_serial_init(struct bcma
504 struct bcma_serial_port *ports = cc->serial_ports;
505
506 if (ccrev >= 11 && ccrev != 15) {
507 - /* Fixed ALP clock */
508 - baud_base = bcma_pmu_alp_clock(cc);
509 + baud_base = bcma_chipco_get_alp_clock(cc);
510 if (ccrev >= 21) {
511 /* Turn off UART clock before switching clocksource. */
512 bcma_cc_write32(cc, BCMA_CC_CORECTL,
513 @@ -137,8 +328,7 @@ void bcma_chipco_serial_init(struct bcma
514 | BCMA_CC_CORECTL_UARTCLKEN);
515 }
516 } else {
517 - pr_err("serial not supported on this device ccrev: 0x%x\n",
518 - ccrev);
519 + bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
520 return;
521 }
522
523 --- /dev/null
524 +++ b/drivers/bcma/driver_chipcommon_nflash.c
525 @@ -0,0 +1,44 @@
526 +/*
527 + * Broadcom specific AMBA
528 + * ChipCommon NAND flash interface
529 + *
530 + * Licensed under the GNU/GPL. See COPYING for details.
531 + */
532 +
533 +#include <linux/platform_device.h>
534 +#include <linux/bcma/bcma.h>
535 +
536 +#include "bcma_private.h"
537 +
538 +struct platform_device bcma_nflash_dev = {
539 + .name = "bcma_nflash",
540 + .num_resources = 0,
541 +};
542 +
543 +/* Initialize NAND flash access */
544 +int bcma_nflash_init(struct bcma_drv_cc *cc)
545 +{
546 + struct bcma_bus *bus = cc->core->bus;
547 +
548 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
549 + cc->core->id.rev != 0x38) {
550 + bcma_err(bus, "NAND flash on unsupported board!\n");
551 + return -ENOTSUPP;
552 + }
553 +
554 + if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) {
555 + bcma_err(bus, "NAND flash not present according to ChipCommon\n");
556 + return -ENODEV;
557 + }
558 +
559 + cc->nflash.present = true;
560 + if (cc->core->id.rev == 38 &&
561 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
562 + cc->nflash.boot = true;
563 +
564 + /* Prepare platform device, but don't register it yet. It's too early,
565 + * malloc (required by device_private_init) is not available yet. */
566 + bcma_nflash_dev.dev.platform_data = &cc->nflash;
567 +
568 + return 0;
569 +}
570 --- a/drivers/bcma/driver_chipcommon_pmu.c
571 +++ b/drivers/bcma/driver_chipcommon_pmu.c
572 @@ -3,7 +3,8 @@
573 * ChipCommon Power Management Unit driver
574 *
575 * Copyright 2009, Michael Buesch <m@bues.ch>
576 - * Copyright 2007, Broadcom Corporation
577 + * Copyright 2007, 2011, Broadcom Corporation
578 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
579 *
580 * Licensed under the GNU/GPL. See COPYING for details.
581 */
582 @@ -12,12 +13,13 @@
583 #include <linux/export.h>
584 #include <linux/bcma/bcma.h>
585
586 -static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
587 +u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
588 {
589 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
590 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
591 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
592 }
593 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
594
595 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
596 {
597 @@ -54,38 +56,19 @@ void bcma_chipco_regctl_maskset(struct b
598 }
599 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
600
601 -static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
602 -{
603 - struct bcma_bus *bus = cc->core->bus;
604 -
605 - switch (bus->chipinfo.id) {
606 - case 0x4313:
607 - case 0x4331:
608 - case 43224:
609 - case 43225:
610 - break;
611 - default:
612 - pr_err("PLL init unknown for device 0x%04X\n",
613 - bus->chipinfo.id);
614 - }
615 -}
616 -
617 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
618 {
619 struct bcma_bus *bus = cc->core->bus;
620 u32 min_msk = 0, max_msk = 0;
621
622 switch (bus->chipinfo.id) {
623 - case 0x4313:
624 + case BCMA_CHIP_ID_BCM4313:
625 min_msk = 0x200D;
626 max_msk = 0xFFFF;
627 break;
628 - case 43224:
629 - case 43225:
630 - break;
631 default:
632 - pr_err("PMU resource config unknown for device 0x%04X\n",
633 - bus->chipinfo.id);
634 + bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
635 + bus->chipinfo.id);
636 }
637
638 /* Set the resource masks. */
639 @@ -93,22 +76,12 @@ static void bcma_pmu_resources_init(stru
640 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
641 if (max_msk)
642 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
643 -}
644 -
645 -void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
646 -{
647 - struct bcma_bus *bus = cc->core->bus;
648
649 - switch (bus->chipinfo.id) {
650 - case 0x4313:
651 - case 0x4331:
652 - case 43224:
653 - case 43225:
654 - break;
655 - default:
656 - pr_err("PMU switch/regulators init unknown for device "
657 - "0x%04X\n", bus->chipinfo.id);
658 - }
659 + /*
660 + * Add some delay; allow resources to come up and settle.
661 + * Delay is required for SoC (early init).
662 + */
663 + mdelay(2);
664 }
665
666 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
667 @@ -122,51 +95,69 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
668 val |= BCMA_CHIPCTL_4331_EXTPA_EN;
669 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
670 val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
671 + else if (bus->chipinfo.rev > 0)
672 + val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
673 } else {
674 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
675 + val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
676 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
677 }
678 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
679 }
680
681 -void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
682 +static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
683 {
684 struct bcma_bus *bus = cc->core->bus;
685
686 switch (bus->chipinfo.id) {
687 - case 0x4313:
688 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
689 + case BCMA_CHIP_ID_BCM4313:
690 + /* enable 12 mA drive strenth for 4313 and set chipControl
691 + register bit 1 */
692 + bcma_chipco_chipctl_maskset(cc, 0,
693 + ~BCMA_CCTRL_4313_12MA_LED_DRIVE,
694 + BCMA_CCTRL_4313_12MA_LED_DRIVE);
695 break;
696 - case 0x4331:
697 - /* BCM4331 workaround is SPROM-related, we put it in sprom.c */
698 + case BCMA_CHIP_ID_BCM4331:
699 + case BCMA_CHIP_ID_BCM43431:
700 + /* Ext PA lines must be enabled for tx on BCM4331 */
701 + bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
702 break;
703 - case 43224:
704 + case BCMA_CHIP_ID_BCM43224:
705 + case BCMA_CHIP_ID_BCM43421:
706 + /* enable 12 mA drive strenth for 43224 and set chipControl
707 + register bit 15 */
708 if (bus->chipinfo.rev == 0) {
709 - pr_err("Workarounds for 43224 rev 0 not fully "
710 - "implemented\n");
711 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
712 + bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
713 + ~BCMA_CCTRL_43224_GPIO_TOGGLE,
714 + BCMA_CCTRL_43224_GPIO_TOGGLE);
715 + bcma_chipco_chipctl_maskset(cc, 0,
716 + ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
717 + BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
718 } else {
719 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
720 + bcma_chipco_chipctl_maskset(cc, 0,
721 + ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
722 + BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
723 }
724 break;
725 - case 43225:
726 - break;
727 default:
728 - pr_err("Workarounds unknown for device 0x%04X\n",
729 - bus->chipinfo.id);
730 + bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
731 + bus->chipinfo.id);
732 }
733 }
734
735 -void bcma_pmu_init(struct bcma_drv_cc *cc)
736 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
737 {
738 u32 pmucap;
739
740 pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
741 cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
742
743 - pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
744 - pmucap);
745 + bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
746 + cc->pmu.rev, pmucap);
747 +}
748
749 +void bcma_pmu_init(struct bcma_drv_cc *cc)
750 +{
751 if (cc->pmu.rev == 1)
752 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
753 ~BCMA_CC_PMU_CTL_NOILPONW);
754 @@ -174,37 +165,47 @@ void bcma_pmu_init(struct bcma_drv_cc *c
755 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
756 BCMA_CC_PMU_CTL_NOILPONW);
757
758 - if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
759 - pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
760 -
761 - bcma_pmu_pll_init(cc);
762 bcma_pmu_resources_init(cc);
763 - bcma_pmu_swreg_init(cc);
764 bcma_pmu_workarounds(cc);
765 }
766
767 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
768 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
769 {
770 struct bcma_bus *bus = cc->core->bus;
771
772 switch (bus->chipinfo.id) {
773 - case 0x4716:
774 - case 0x4748:
775 - case 47162:
776 - case 0x4313:
777 - case 0x5357:
778 - case 0x4749:
779 - case 53572:
780 + case BCMA_CHIP_ID_BCM4313:
781 + case BCMA_CHIP_ID_BCM43224:
782 + case BCMA_CHIP_ID_BCM43225:
783 + case BCMA_CHIP_ID_BCM43227:
784 + case BCMA_CHIP_ID_BCM43228:
785 + case BCMA_CHIP_ID_BCM4331:
786 + case BCMA_CHIP_ID_BCM43421:
787 + case BCMA_CHIP_ID_BCM43428:
788 + case BCMA_CHIP_ID_BCM43431:
789 + case BCMA_CHIP_ID_BCM4716:
790 + case BCMA_CHIP_ID_BCM47162:
791 + case BCMA_CHIP_ID_BCM4748:
792 + case BCMA_CHIP_ID_BCM4749:
793 + case BCMA_CHIP_ID_BCM5357:
794 + case BCMA_CHIP_ID_BCM53572:
795 + case BCMA_CHIP_ID_BCM6362:
796 /* always 20Mhz */
797 return 20000 * 1000;
798 - case 0x5356:
799 - case 0x5300:
800 + case BCMA_CHIP_ID_BCM4706:
801 + case BCMA_CHIP_ID_BCM5356:
802 /* always 25Mhz */
803 return 25000 * 1000;
804 + case BCMA_CHIP_ID_BCM43460:
805 + case BCMA_CHIP_ID_BCM4352:
806 + case BCMA_CHIP_ID_BCM4360:
807 + if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
808 + return 40000 * 1000;
809 + else
810 + return 20000 * 1000;
811 default:
812 - pr_warn("No ALP clock specified for %04X device, "
813 - "pmu rev. %d, using default %d Hz\n",
814 - bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
815 + bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
816 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
817 }
818 return BCMA_CC_PMU_ALP_CLOCK;
819 }
820 @@ -212,7 +213,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
821 /* Find the output of the "m" pll divider given pll controls that start with
822 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
823 */
824 -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
825 +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
826 {
827 u32 tmp, div, ndiv, p1, p2, fc;
828 struct bcma_bus *bus = cc->core->bus;
829 @@ -221,7 +222,8 @@ static u32 bcma_pmu_clock(struct bcma_dr
830
831 BUG_ON(!m || m > 4);
832
833 - if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
834 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
835 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
836 /* Detect failure in clock setting */
837 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
838 if (tmp & 0x40000)
839 @@ -240,60 +242,95 @@ static u32 bcma_pmu_clock(struct bcma_dr
840 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
841
842 /* Do calculation in Mhz */
843 - fc = bcma_pmu_alp_clock(cc) / 1000000;
844 + fc = bcma_pmu_get_alp_clock(cc) / 1000000;
845 fc = (p1 * ndiv * fc) / p2;
846
847 /* Return clock in Hertz */
848 return (fc / div) * 1000000;
849 }
850
851 +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
852 +{
853 + u32 tmp, ndiv, p1div, p2div;
854 + u32 clock;
855 +
856 + BUG_ON(!m || m > 4);
857 +
858 + /* Get N, P1 and P2 dividers to determine CPU clock */
859 + tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
860 + ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
861 + >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
862 + p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
863 + >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
864 + p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
865 + >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
866 +
867 + tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
868 + if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
869 + /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
870 + clock = (25000000 / 4) * ndiv * p2div / p1div;
871 + else
872 + /* Fixed reference clock 25MHz and m = 2 */
873 + clock = (25000000 / 2) * ndiv * p2div / p1div;
874 +
875 + if (m == BCMA_CC_PMU5_MAINPLL_SSB)
876 + clock = clock / 4;
877 +
878 + return clock;
879 +}
880 +
881 /* query bus clock frequency for PMU-enabled chipcommon */
882 -u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
883 +static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
884 {
885 struct bcma_bus *bus = cc->core->bus;
886
887 switch (bus->chipinfo.id) {
888 - case 0x4716:
889 - case 0x4748:
890 - case 47162:
891 - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
892 - BCMA_CC_PMU5_MAINPLL_SSB);
893 - case 0x5356:
894 - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
895 - BCMA_CC_PMU5_MAINPLL_SSB);
896 - case 0x5357:
897 - case 0x4749:
898 - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
899 - BCMA_CC_PMU5_MAINPLL_SSB);
900 - case 0x5300:
901 - return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
902 - BCMA_CC_PMU5_MAINPLL_SSB);
903 - case 53572:
904 + case BCMA_CHIP_ID_BCM4716:
905 + case BCMA_CHIP_ID_BCM4748:
906 + case BCMA_CHIP_ID_BCM47162:
907 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
908 + BCMA_CC_PMU5_MAINPLL_SSB);
909 + case BCMA_CHIP_ID_BCM5356:
910 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
911 + BCMA_CC_PMU5_MAINPLL_SSB);
912 + case BCMA_CHIP_ID_BCM5357:
913 + case BCMA_CHIP_ID_BCM4749:
914 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
915 + BCMA_CC_PMU5_MAINPLL_SSB);
916 + case BCMA_CHIP_ID_BCM4706:
917 + return bcma_pmu_pll_clock_bcm4706(cc,
918 + BCMA_CC_PMU4706_MAINPLL_PLL0,
919 + BCMA_CC_PMU5_MAINPLL_SSB);
920 + case BCMA_CHIP_ID_BCM53572:
921 return 75000000;
922 default:
923 - pr_warn("No backplane clock specified for %04X device, "
924 - "pmu rev. %d, using default %d Hz\n",
925 - bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
926 + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
927 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
928 }
929 return BCMA_CC_PMU_HT_CLOCK;
930 }
931
932 /* query cpu clock frequency for PMU-enabled chipcommon */
933 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
934 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
935 {
936 struct bcma_bus *bus = cc->core->bus;
937
938 - if (bus->chipinfo.id == 53572)
939 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
940 return 300000000;
941
942 + /* New PMUs can have different clock for bus and CPU */
943 if (cc->pmu.rev >= 5) {
944 u32 pll;
945 switch (bus->chipinfo.id) {
946 - case 0x5356:
947 + case BCMA_CHIP_ID_BCM4706:
948 + return bcma_pmu_pll_clock_bcm4706(cc,
949 + BCMA_CC_PMU4706_MAINPLL_PLL0,
950 + BCMA_CC_PMU5_MAINPLL_CPU);
951 + case BCMA_CHIP_ID_BCM5356:
952 pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
953 break;
954 - case 0x5357:
955 - case 0x4749:
956 + case BCMA_CHIP_ID_BCM5357:
957 + case BCMA_CHIP_ID_BCM4749:
958 pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
959 break;
960 default:
961 @@ -301,10 +338,189 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
962 break;
963 }
964
965 - /* TODO: if (bus->chipinfo.id == 0x5300)
966 - return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
967 - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
968 + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
969 + }
970 +
971 + /* On old PMUs CPU has the same clock as the bus */
972 + return bcma_pmu_get_bus_clock(cc);
973 +}
974 +
975 +static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
976 + u32 value)
977 +{
978 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
979 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
980 +}
981 +
982 +void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
983 +{
984 + u32 tmp = 0;
985 + u8 phypll_offset = 0;
986 + u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
987 + u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
988 + struct bcma_bus *bus = cc->core->bus;
989 +
990 + switch (bus->chipinfo.id) {
991 + case BCMA_CHIP_ID_BCM5357:
992 + case BCMA_CHIP_ID_BCM4749:
993 + case BCMA_CHIP_ID_BCM53572:
994 + /* 5357[ab]0, 43236[ab]0, and 6362b0 */
995 +
996 + /* BCM5357 needs to touch PLL1_PLLCTL[02],
997 + so offset PLL0_PLLCTL[02] by 6 */
998 + phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
999 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
1000 + bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
1001 +
1002 + /* RMW only the P1 divider */
1003 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
1004 + BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
1005 + tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
1006 + tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
1007 + tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
1008 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
1009 +
1010 + /* RMW only the int feedback divider */
1011 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
1012 + BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
1013 + tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
1014 + tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
1015 + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
1016 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
1017 +
1018 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
1019 + break;
1020 +
1021 + case BCMA_CHIP_ID_BCM4331:
1022 + case BCMA_CHIP_ID_BCM43431:
1023 + if (spuravoid == 2) {
1024 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1025 + 0x11500014);
1026 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1027 + 0x0FC00a08);
1028 + } else if (spuravoid == 1) {
1029 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1030 + 0x11500014);
1031 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1032 + 0x0F600a08);
1033 + } else {
1034 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1035 + 0x11100014);
1036 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1037 + 0x03000a08);
1038 + }
1039 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
1040 + break;
1041 +
1042 + case BCMA_CHIP_ID_BCM43224:
1043 + case BCMA_CHIP_ID_BCM43225:
1044 + case BCMA_CHIP_ID_BCM43421:
1045 + if (spuravoid == 1) {
1046 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1047 + 0x11500010);
1048 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1049 + 0x000C0C06);
1050 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1051 + 0x0F600a08);
1052 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1053 + 0x00000000);
1054 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1055 + 0x2001E920);
1056 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1057 + 0x88888815);
1058 + } else {
1059 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1060 + 0x11100010);
1061 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1062 + 0x000c0c06);
1063 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1064 + 0x03000a08);
1065 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1066 + 0x00000000);
1067 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1068 + 0x200005c0);
1069 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1070 + 0x88888815);
1071 + }
1072 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
1073 + break;
1074 +
1075 + case BCMA_CHIP_ID_BCM4716:
1076 + case BCMA_CHIP_ID_BCM4748:
1077 + case BCMA_CHIP_ID_BCM47162:
1078 + if (spuravoid == 1) {
1079 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1080 + 0x11500060);
1081 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1082 + 0x080C0C06);
1083 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1084 + 0x0F600000);
1085 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1086 + 0x00000000);
1087 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1088 + 0x2001E924);
1089 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1090 + 0x88888815);
1091 + } else {
1092 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1093 + 0x11100060);
1094 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1095 + 0x080c0c06);
1096 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1097 + 0x03000000);
1098 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1099 + 0x00000000);
1100 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1101 + 0x200005c0);
1102 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1103 + 0x88888815);
1104 + }
1105 +
1106 + tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
1107 + break;
1108 +
1109 + case BCMA_CHIP_ID_BCM43227:
1110 + case BCMA_CHIP_ID_BCM43228:
1111 + case BCMA_CHIP_ID_BCM43428:
1112 + /* LCNXN */
1113 + /* PLL Settings for spur avoidance on/off mode,
1114 + no on2 support for 43228A0 */
1115 + if (spuravoid == 1) {
1116 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1117 + 0x01100014);
1118 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1119 + 0x040C0C06);
1120 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1121 + 0x03140A08);
1122 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1123 + 0x00333333);
1124 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1125 + 0x202C2820);
1126 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1127 + 0x88888815);
1128 + } else {
1129 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1130 + 0x11100014);
1131 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1132 + 0x040c0c06);
1133 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1134 + 0x03000a08);
1135 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1136 + 0x00000000);
1137 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1138 + 0x200005c0);
1139 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1140 + 0x88888815);
1141 + }
1142 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
1143 + break;
1144 + default:
1145 + bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
1146 + bus->chipinfo.id);
1147 + break;
1148 }
1149
1150 - return bcma_pmu_get_clockcontrol(cc);
1151 + tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
1152 + bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
1153 }
1154 +EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
1155 --- /dev/null
1156 +++ b/drivers/bcma/driver_chipcommon_sflash.c
1157 @@ -0,0 +1,165 @@
1158 +/*
1159 + * Broadcom specific AMBA
1160 + * ChipCommon serial flash interface
1161 + *
1162 + * Licensed under the GNU/GPL. See COPYING for details.
1163 + */
1164 +
1165 +#include <linux/platform_device.h>
1166 +#include <linux/bcma/bcma.h>
1167 +
1168 +#include "bcma_private.h"
1169 +
1170 +static struct resource bcma_sflash_resource = {
1171 + .name = "bcma_sflash",
1172 + .start = BCMA_SOC_FLASH2,
1173 + .end = 0,
1174 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
1175 +};
1176 +
1177 +struct platform_device bcma_sflash_dev = {
1178 + .name = "bcma_sflash",
1179 + .resource = &bcma_sflash_resource,
1180 + .num_resources = 1,
1181 +};
1182 +
1183 +struct bcma_sflash_tbl_e {
1184 + char *name;
1185 + u32 id;
1186 + u32 blocksize;
1187 + u16 numblocks;
1188 +};
1189 +
1190 +static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
1191 + { "M25P20", 0x11, 0x10000, 4, },
1192 + { "M25P40", 0x12, 0x10000, 8, },
1193 +
1194 + { "M25P16", 0x14, 0x10000, 32, },
1195 + { "M25P32", 0x15, 0x10000, 64, },
1196 + { "M25P64", 0x16, 0x10000, 128, },
1197 + { "M25FL128", 0x17, 0x10000, 256, },
1198 + { 0 },
1199 +};
1200 +
1201 +static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
1202 + { "SST25WF512", 1, 0x1000, 16, },
1203 + { "SST25VF512", 0x48, 0x1000, 16, },
1204 + { "SST25WF010", 2, 0x1000, 32, },
1205 + { "SST25VF010", 0x49, 0x1000, 32, },
1206 + { "SST25WF020", 3, 0x1000, 64, },
1207 + { "SST25VF020", 0x43, 0x1000, 64, },
1208 + { "SST25WF040", 4, 0x1000, 128, },
1209 + { "SST25VF040", 0x44, 0x1000, 128, },
1210 + { "SST25VF040B", 0x8d, 0x1000, 128, },
1211 + { "SST25WF080", 5, 0x1000, 256, },
1212 + { "SST25VF080B", 0x8e, 0x1000, 256, },
1213 + { "SST25VF016", 0x41, 0x1000, 512, },
1214 + { "SST25VF032", 0x4a, 0x1000, 1024, },
1215 + { "SST25VF064", 0x4b, 0x1000, 2048, },
1216 + { 0 },
1217 +};
1218 +
1219 +static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
1220 + { "AT45DB011", 0xc, 256, 512, },
1221 + { "AT45DB021", 0x14, 256, 1024, },
1222 + { "AT45DB041", 0x1c, 256, 2048, },
1223 + { "AT45DB081", 0x24, 256, 4096, },
1224 + { "AT45DB161", 0x2c, 512, 4096, },
1225 + { "AT45DB321", 0x34, 512, 8192, },
1226 + { "AT45DB642", 0x3c, 1024, 8192, },
1227 + { 0 },
1228 +};
1229 +
1230 +static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
1231 +{
1232 + int i;
1233 + bcma_cc_write32(cc, BCMA_CC_FLASHCTL,
1234 + BCMA_CC_FLASHCTL_START | opcode);
1235 + for (i = 0; i < 1000; i++) {
1236 + if (!(bcma_cc_read32(cc, BCMA_CC_FLASHCTL) &
1237 + BCMA_CC_FLASHCTL_BUSY))
1238 + return;
1239 + cpu_relax();
1240 + }
1241 + bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
1242 +}
1243 +
1244 +/* Initialize serial flash access */
1245 +int bcma_sflash_init(struct bcma_drv_cc *cc)
1246 +{
1247 + struct bcma_bus *bus = cc->core->bus;
1248 + struct bcma_sflash *sflash = &cc->sflash;
1249 + struct bcma_sflash_tbl_e *e;
1250 + u32 id, id2;
1251 +
1252 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1253 + case BCMA_CC_FLASHT_STSER:
1254 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP);
1255 +
1256 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0);
1257 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
1258 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
1259 +
1260 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1);
1261 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
1262 + id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
1263 +
1264 + switch (id) {
1265 + case 0xbf:
1266 + for (e = bcma_sflash_sst_tbl; e->name; e++) {
1267 + if (e->id == id2)
1268 + break;
1269 + }
1270 + break;
1271 + case 0x13:
1272 + return -ENOTSUPP;
1273 + default:
1274 + for (e = bcma_sflash_st_tbl; e->name; e++) {
1275 + if (e->id == id)
1276 + break;
1277 + }
1278 + break;
1279 + }
1280 + if (!e->name) {
1281 + bcma_err(bus, "Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2);
1282 + return -ENOTSUPP;
1283 + }
1284 +
1285 + break;
1286 + case BCMA_CC_FLASHT_ATSER:
1287 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
1288 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c;
1289 +
1290 + for (e = bcma_sflash_at_tbl; e->name; e++) {
1291 + if (e->id == id)
1292 + break;
1293 + }
1294 + if (!e->name) {
1295 + bcma_err(bus, "Unsupported Atmel serial flash (id: 0x%X)\n", id);
1296 + return -ENOTSUPP;
1297 + }
1298 +
1299 + break;
1300 + default:
1301 + bcma_err(bus, "Unsupported flash type\n");
1302 + return -ENOTSUPP;
1303 + }
1304 +
1305 + sflash->window = BCMA_SOC_FLASH2;
1306 + sflash->blocksize = e->blocksize;
1307 + sflash->numblocks = e->numblocks;
1308 + sflash->size = sflash->blocksize * sflash->numblocks;
1309 + sflash->present = true;
1310 +
1311 + bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
1312 + e->name, sflash->size / 1024, sflash->blocksize,
1313 + sflash->numblocks);
1314 +
1315 + /* Prepare platform device, but don't register it yet. It's too early,
1316 + * malloc (required by device_private_init) is not available yet. */
1317 + bcma_sflash_dev.resource[0].end = bcma_sflash_dev.resource[0].start +
1318 + sflash->size;
1319 + bcma_sflash_dev.dev.platform_data = sflash;
1320 +
1321 + return 0;
1322 +}
1323 --- /dev/null
1324 +++ b/drivers/bcma/driver_gmac_cmn.c
1325 @@ -0,0 +1,14 @@
1326 +/*
1327 + * Broadcom specific AMBA
1328 + * GBIT MAC COMMON Core
1329 + *
1330 + * Licensed under the GNU/GPL. See COPYING for details.
1331 + */
1332 +
1333 +#include "bcma_private.h"
1334 +#include <linux/bcma/bcma.h>
1335 +
1336 +void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc)
1337 +{
1338 + mutex_init(&gc->phy_mutex);
1339 +}
1340 --- /dev/null
1341 +++ b/drivers/bcma/driver_gpio.c
1342 @@ -0,0 +1,98 @@
1343 +/*
1344 + * Broadcom specific AMBA
1345 + * GPIO driver
1346 + *
1347 + * Copyright 2011, Broadcom Corporation
1348 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
1349 + *
1350 + * Licensed under the GNU/GPL. See COPYING for details.
1351 + */
1352 +
1353 +#include <linux/gpio.h>
1354 +#include <linux/export.h>
1355 +#include <linux/bcma/bcma.h>
1356 +
1357 +#include "bcma_private.h"
1358 +
1359 +static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
1360 +{
1361 + return container_of(chip, struct bcma_drv_cc, gpio);
1362 +}
1363 +
1364 +static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1365 +{
1366 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1367 +
1368 + return !!bcma_chipco_gpio_in(cc, 1 << gpio);
1369 +}
1370 +
1371 +static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
1372 + int value)
1373 +{
1374 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1375 +
1376 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
1377 +}
1378 +
1379 +static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1380 +{
1381 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1382 +
1383 + bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
1384 + return 0;
1385 +}
1386 +
1387 +static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
1388 + int value)
1389 +{
1390 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1391 +
1392 + bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
1393 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
1394 + return 0;
1395 +}
1396 +
1397 +static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
1398 +{
1399 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1400 +
1401 + bcma_chipco_gpio_control(cc, 1 << gpio, 0);
1402 + /* clear pulldown */
1403 + bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
1404 + /* Set pullup */
1405 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
1406 +
1407 + return 0;
1408 +}
1409 +
1410 +static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
1411 +{
1412 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1413 +
1414 + /* clear pullup */
1415 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
1416 +}
1417 +
1418 +int bcma_gpio_init(struct bcma_drv_cc *cc)
1419 +{
1420 + struct gpio_chip *chip = &cc->gpio;
1421 +
1422 + chip->label = "bcma_gpio";
1423 + chip->owner = THIS_MODULE;
1424 + chip->request = bcma_gpio_request;
1425 + chip->free = bcma_gpio_free;
1426 + chip->get = bcma_gpio_get_value;
1427 + chip->set = bcma_gpio_set_value;
1428 + chip->direction_input = bcma_gpio_direction_input;
1429 + chip->direction_output = bcma_gpio_direction_output;
1430 + chip->ngpio = 16;
1431 + /* There is just one SoC in one device and its GPIO addresses should be
1432 + * deterministic to address them more easily. The other buses could get
1433 + * a random base number. */
1434 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
1435 + chip->base = 0;
1436 + else
1437 + chip->base = -1;
1438 +
1439 + return gpiochip_add(chip);
1440 +}
1441 --- a/drivers/bcma/driver_mips.c
1442 +++ b/drivers/bcma/driver_mips.c
1443 @@ -22,15 +22,15 @@
1444 /* The 47162a0 hangs when reading MIPS DMP registers registers */
1445 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
1446 {
1447 - return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
1448 - dev->id.id == BCMA_CORE_MIPS_74K;
1449 + return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
1450 + dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
1451 }
1452
1453 /* The 5357b0 hangs when reading USB20H DMP registers */
1454 static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
1455 {
1456 - return (dev->bus->chipinfo.id == 0x5357 ||
1457 - dev->bus->chipinfo.id == 0x4749) &&
1458 + return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
1459 + dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
1460 dev->bus->chipinfo.pkg == 11 &&
1461 dev->id.id == BCMA_CORE_USB20_HOST;
1462 }
1463 @@ -74,11 +74,16 @@ static u32 bcma_core_mips_irqflag(struct
1464 return dev->core_index;
1465 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
1466
1467 - return flag & 0x1F;
1468 + if (flag)
1469 + return flag & 0x1F;
1470 + else
1471 + return 0x3f;
1472 }
1473
1474 /* Get the MIPS IRQ assignment for a specified device.
1475 * If unassigned, 0 is returned.
1476 + * If disabled, 5 is returned.
1477 + * If not supported, 6 is returned.
1478 */
1479 unsigned int bcma_core_mips_irq(struct bcma_device *dev)
1480 {
1481 @@ -87,13 +92,15 @@ unsigned int bcma_core_mips_irq(struct b
1482 unsigned int irq;
1483
1484 irqflag = bcma_core_mips_irqflag(dev);
1485 + if (irqflag == 0x3f)
1486 + return 6;
1487
1488 - for (irq = 1; irq <= 4; irq++)
1489 + for (irq = 0; irq <= 4; irq++)
1490 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
1491 (1 << irqflag))
1492 return irq;
1493
1494 - return 0;
1495 + return 5;
1496 }
1497 EXPORT_SYMBOL(bcma_core_mips_irq);
1498
1499 @@ -114,8 +121,8 @@ static void bcma_core_mips_set_irq(struc
1500 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
1501 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
1502 ~(1 << irqflag));
1503 - else
1504 - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
1505 + else if (oldirq != 5)
1506 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
1507
1508 /* assign the new one */
1509 if (irq == 0) {
1510 @@ -123,17 +130,17 @@ static void bcma_core_mips_set_irq(struc
1511 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
1512 (1 << irqflag));
1513 } else {
1514 - u32 oldirqflag = bcma_read32(mdev,
1515 - BCMA_MIPS_MIPS74K_INTMASK(irq));
1516 - if (oldirqflag) {
1517 + u32 irqinitmask = bcma_read32(mdev,
1518 + BCMA_MIPS_MIPS74K_INTMASK(irq));
1519 + if (irqinitmask) {
1520 struct bcma_device *core;
1521
1522 /* backplane irq line is in use, find out who uses
1523 * it and set user to irq 0
1524 */
1525 - list_for_each_entry_reverse(core, &bus->cores, list) {
1526 + list_for_each_entry(core, &bus->cores, list) {
1527 if ((1 << bcma_core_mips_irqflag(core)) ==
1528 - oldirqflag) {
1529 + irqinitmask) {
1530 bcma_core_mips_set_irq(core, 0);
1531 break;
1532 }
1533 @@ -143,15 +150,31 @@ static void bcma_core_mips_set_irq(struc
1534 1 << irqflag);
1535 }
1536
1537 - pr_info("set_irq: core 0x%04x, irq %d => %d\n",
1538 - dev->id.id, oldirq + 2, irq + 2);
1539 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
1540 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
1541 +}
1542 +
1543 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
1544 + u16 coreid, u8 unit)
1545 +{
1546 + struct bcma_device *core;
1547 +
1548 + core = bcma_find_core_unit(bus, coreid, unit);
1549 + if (!core) {
1550 + bcma_warn(bus,
1551 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
1552 + coreid, unit);
1553 + return;
1554 + }
1555 +
1556 + bcma_core_mips_set_irq(core, irq);
1557 }
1558
1559 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
1560 {
1561 int i;
1562 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1563 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1564 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1565 for (i = 0; i <= 6; i++)
1566 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
1567 printk("\n");
1568 @@ -161,7 +184,7 @@ static void bcma_core_mips_dump_irq(stru
1569 {
1570 struct bcma_device *core;
1571
1572 - list_for_each_entry_reverse(core, &bus->cores, list) {
1573 + list_for_each_entry(core, &bus->cores, list) {
1574 bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
1575 }
1576 }
1577 @@ -171,9 +194,9 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
1578 struct bcma_bus *bus = mcore->core->bus;
1579
1580 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
1581 - return bcma_pmu_get_clockcpu(&bus->drv_cc);
1582 + return bcma_pmu_get_cpu_clock(&bus->drv_cc);
1583
1584 - pr_err("No PMU available, need this to get the cpu clock\n");
1585 + bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
1586 return 0;
1587 }
1588 EXPORT_SYMBOL(bcma_cpu_clock);
1589 @@ -181,76 +204,109 @@ EXPORT_SYMBOL(bcma_cpu_clock);
1590 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
1591 {
1592 struct bcma_bus *bus = mcore->core->bus;
1593 + struct bcma_drv_cc *cc = &bus->drv_cc;
1594
1595 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
1596 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1597 case BCMA_CC_FLASHT_STSER:
1598 case BCMA_CC_FLASHT_ATSER:
1599 - pr_err("Serial flash not supported.\n");
1600 + bcma_debug(bus, "Found serial flash\n");
1601 + bcma_sflash_init(cc);
1602 break;
1603 case BCMA_CC_FLASHT_PARA:
1604 - pr_info("found parallel flash.\n");
1605 - bus->drv_cc.pflash.window = 0x1c000000;
1606 - bus->drv_cc.pflash.window_size = 0x02000000;
1607 + bcma_debug(bus, "Found parallel flash\n");
1608 + cc->pflash.present = true;
1609 + cc->pflash.window = BCMA_SOC_FLASH2;
1610 + cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
1611
1612 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
1613 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
1614 BCMA_CC_FLASH_CFG_DS) == 0)
1615 - bus->drv_cc.pflash.buswidth = 1;
1616 + cc->pflash.buswidth = 1;
1617 else
1618 - bus->drv_cc.pflash.buswidth = 2;
1619 + cc->pflash.buswidth = 2;
1620 break;
1621 default:
1622 - pr_err("flash not supported.\n");
1623 + bcma_err(bus, "Flash type not supported\n");
1624 + }
1625 +
1626 + if (cc->core->id.rev == 38 ||
1627 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
1628 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
1629 + bcma_debug(bus, "Found NAND flash\n");
1630 + bcma_nflash_init(cc);
1631 + }
1632 }
1633 }
1634
1635 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
1636 +{
1637 + struct bcma_bus *bus = mcore->core->bus;
1638 +
1639 + if (mcore->early_setup_done)
1640 + return;
1641 +
1642 + bcma_chipco_serial_init(&bus->drv_cc);
1643 + bcma_core_mips_flash_detect(mcore);
1644 +
1645 + mcore->early_setup_done = true;
1646 +}
1647 +
1648 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
1649 {
1650 struct bcma_bus *bus;
1651 struct bcma_device *core;
1652 bus = mcore->core->bus;
1653
1654 - pr_info("Initializing MIPS core...\n");
1655 + if (mcore->setup_done)
1656 + return;
1657 +
1658 + bcma_debug(bus, "Initializing MIPS core...\n");
1659
1660 - if (!mcore->setup_done)
1661 - mcore->assigned_irqs = 1;
1662 + bcma_core_mips_early_init(mcore);
1663
1664 - /* Assign IRQs to all cores on the bus */
1665 - list_for_each_entry_reverse(core, &bus->cores, list) {
1666 - int mips_irq;
1667 - if (core->irq)
1668 - continue;
1669 -
1670 - mips_irq = bcma_core_mips_irq(core);
1671 - if (mips_irq > 4)
1672 - core->irq = 0;
1673 - else
1674 - core->irq = mips_irq + 2;
1675 - if (core->irq > 5)
1676 - continue;
1677 - switch (core->id.id) {
1678 - case BCMA_CORE_PCI:
1679 - case BCMA_CORE_PCIE:
1680 - case BCMA_CORE_ETHERNET:
1681 - case BCMA_CORE_ETHERNET_GBIT:
1682 - case BCMA_CORE_MAC_GBIT:
1683 - case BCMA_CORE_80211:
1684 - case BCMA_CORE_USB20_HOST:
1685 - /* These devices get their own IRQ line if available,
1686 - * the rest goes on IRQ0
1687 - */
1688 - if (mcore->assigned_irqs <= 4)
1689 - bcma_core_mips_set_irq(core,
1690 - mcore->assigned_irqs++);
1691 - break;
1692 + switch (bus->chipinfo.id) {
1693 + case BCMA_CHIP_ID_BCM4716:
1694 + case BCMA_CHIP_ID_BCM4748:
1695 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1696 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1697 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1698 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
1699 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1700 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1701 + break;
1702 + case BCMA_CHIP_ID_BCM5356:
1703 + case BCMA_CHIP_ID_BCM47162:
1704 + case BCMA_CHIP_ID_BCM53572:
1705 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1706 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1707 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1708 + break;
1709 + case BCMA_CHIP_ID_BCM5357:
1710 + case BCMA_CHIP_ID_BCM4749:
1711 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1712 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1713 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1714 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1715 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1716 + break;
1717 + case BCMA_CHIP_ID_BCM4706:
1718 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
1719 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
1720 + 0);
1721 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
1722 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
1723 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
1724 + 0);
1725 + break;
1726 + default:
1727 + list_for_each_entry(core, &bus->cores, list) {
1728 + core->irq = bcma_core_mips_irq(core) + 2;
1729 }
1730 + bcma_err(bus,
1731 + "Unknown device (0x%x) found, can not configure IRQs\n",
1732 + bus->chipinfo.id);
1733 }
1734 - pr_info("IRQ reconfiguration done\n");
1735 + bcma_debug(bus, "IRQ reconfiguration done\n");
1736 bcma_core_mips_dump_irq(bus);
1737
1738 - if (mcore->setup_done)
1739 - return;
1740 -
1741 - bcma_chipco_serial_init(&bus->drv_cc);
1742 - bcma_core_mips_flash_detect(mcore);
1743 mcore->setup_done = true;
1744 }
1745 --- a/drivers/bcma/driver_pci.c
1746 +++ b/drivers/bcma/driver_pci.c
1747 @@ -2,8 +2,9 @@
1748 * Broadcom specific AMBA
1749 * PCI Core
1750 *
1751 - * Copyright 2005, Broadcom Corporation
1752 + * Copyright 2005, 2011, Broadcom Corporation
1753 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1754 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
1755 *
1756 * Licensed under the GNU/GPL. See COPYING for details.
1757 */
1758 @@ -16,120 +17,124 @@
1759 * R/W ops.
1760 **************************************************/
1761
1762 -static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
1763 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
1764 {
1765 - pcicore_write32(pc, 0x130, address);
1766 - pcicore_read32(pc, 0x130);
1767 - return pcicore_read32(pc, 0x134);
1768 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
1769 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
1770 + return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
1771 }
1772
1773 -#if 0
1774 static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
1775 {
1776 - pcicore_write32(pc, 0x130, address);
1777 - pcicore_read32(pc, 0x130);
1778 - pcicore_write32(pc, 0x134, data);
1779 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
1780 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
1781 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
1782 }
1783 -#endif
1784
1785 static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
1786 {
1787 - const u16 mdio_control = 0x128;
1788 - const u16 mdio_data = 0x12C;
1789 u32 v;
1790 int i;
1791
1792 - v = (1 << 30); /* Start of Transaction */
1793 - v |= (1 << 28); /* Write Transaction */
1794 - v |= (1 << 17); /* Turnaround */
1795 - v |= (0x1F << 18);
1796 + v = BCMA_CORE_PCI_MDIODATA_START;
1797 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
1798 + v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
1799 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
1800 + v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
1801 + BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
1802 + v |= BCMA_CORE_PCI_MDIODATA_TA;
1803 v |= (phy << 4);
1804 - pcicore_write32(pc, mdio_data, v);
1805 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
1806
1807 udelay(10);
1808 for (i = 0; i < 200; i++) {
1809 - v = pcicore_read32(pc, mdio_control);
1810 - if (v & 0x100 /* Trans complete */)
1811 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1812 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1813 break;
1814 - msleep(1);
1815 + usleep_range(1000, 2000);
1816 }
1817 }
1818
1819 static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
1820 {
1821 - const u16 mdio_control = 0x128;
1822 - const u16 mdio_data = 0x12C;
1823 int max_retries = 10;
1824 u16 ret = 0;
1825 u32 v;
1826 int i;
1827
1828 - v = 0x80; /* Enable Preamble Sequence */
1829 - v |= 0x2; /* MDIO Clock Divisor */
1830 - pcicore_write32(pc, mdio_control, v);
1831 + /* enable mdio access to SERDES */
1832 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
1833 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
1834 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
1835
1836 if (pc->core->id.rev >= 10) {
1837 max_retries = 200;
1838 bcma_pcie_mdio_set_phy(pc, device);
1839 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
1840 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
1841 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
1842 + } else {
1843 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
1844 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
1845 }
1846
1847 - v = (1 << 30); /* Start of Transaction */
1848 - v |= (1 << 29); /* Read Transaction */
1849 - v |= (1 << 17); /* Turnaround */
1850 - if (pc->core->id.rev < 10)
1851 - v |= (u32)device << 22;
1852 - v |= (u32)address << 18;
1853 - pcicore_write32(pc, mdio_data, v);
1854 + v = BCMA_CORE_PCI_MDIODATA_START;
1855 + v |= BCMA_CORE_PCI_MDIODATA_READ;
1856 + v |= BCMA_CORE_PCI_MDIODATA_TA;
1857 +
1858 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
1859 /* Wait for the device to complete the transaction */
1860 udelay(10);
1861 for (i = 0; i < max_retries; i++) {
1862 - v = pcicore_read32(pc, mdio_control);
1863 - if (v & 0x100 /* Trans complete */) {
1864 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1865 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
1866 udelay(10);
1867 - ret = pcicore_read32(pc, mdio_data);
1868 + ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
1869 break;
1870 }
1871 - msleep(1);
1872 + usleep_range(1000, 2000);
1873 }
1874 - pcicore_write32(pc, mdio_control, 0);
1875 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1876 return ret;
1877 }
1878
1879 static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
1880 u8 address, u16 data)
1881 {
1882 - const u16 mdio_control = 0x128;
1883 - const u16 mdio_data = 0x12C;
1884 int max_retries = 10;
1885 u32 v;
1886 int i;
1887
1888 - v = 0x80; /* Enable Preamble Sequence */
1889 - v |= 0x2; /* MDIO Clock Divisor */
1890 - pcicore_write32(pc, mdio_control, v);
1891 + /* enable mdio access to SERDES */
1892 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
1893 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
1894 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
1895
1896 if (pc->core->id.rev >= 10) {
1897 max_retries = 200;
1898 bcma_pcie_mdio_set_phy(pc, device);
1899 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
1900 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
1901 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
1902 + } else {
1903 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
1904 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
1905 }
1906
1907 - v = (1 << 30); /* Start of Transaction */
1908 - v |= (1 << 28); /* Write Transaction */
1909 - v |= (1 << 17); /* Turnaround */
1910 - if (pc->core->id.rev < 10)
1911 - v |= (u32)device << 22;
1912 - v |= (u32)address << 18;
1913 + v = BCMA_CORE_PCI_MDIODATA_START;
1914 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
1915 + v |= BCMA_CORE_PCI_MDIODATA_TA;
1916 v |= data;
1917 - pcicore_write32(pc, mdio_data, v);
1918 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
1919 /* Wait for the device to complete the transaction */
1920 udelay(10);
1921 for (i = 0; i < max_retries; i++) {
1922 - v = pcicore_read32(pc, mdio_control);
1923 - if (v & 0x100 /* Trans complete */)
1924 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1925 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1926 break;
1927 - msleep(1);
1928 + usleep_range(1000, 2000);
1929 }
1930 - pcicore_write32(pc, mdio_control, 0);
1931 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1932 }
1933
1934 /**************************************************
1935 @@ -138,88 +143,108 @@ static void bcma_pcie_mdio_write(struct
1936
1937 static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
1938 {
1939 - return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
1940 + u32 tmp;
1941 +
1942 + tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
1943 + if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
1944 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
1945 + BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
1946 + else
1947 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
1948 }
1949
1950 static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
1951 {
1952 - const u8 serdes_pll_device = 0x1D;
1953 - const u8 serdes_rx_device = 0x1F;
1954 u16 tmp;
1955
1956 - bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
1957 - bcma_pcicore_polarity_workaround(pc));
1958 - tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
1959 - if (tmp & 0x4000)
1960 - bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
1961 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
1962 + BCMA_CORE_PCI_SERDES_RX_CTRL,
1963 + bcma_pcicore_polarity_workaround(pc));
1964 + tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
1965 + BCMA_CORE_PCI_SERDES_PLL_CTRL);
1966 + if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
1967 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
1968 + BCMA_CORE_PCI_SERDES_PLL_CTRL,
1969 + tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
1970 +}
1971 +
1972 +static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
1973 +{
1974 + struct bcma_device *core = pc->core;
1975 + u16 val16, core_index;
1976 + uint regoff;
1977 +
1978 + regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
1979 + core_index = (u16)core->core_index;
1980 +
1981 + val16 = pcicore_read16(pc, regoff);
1982 + if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
1983 + != core_index) {
1984 + val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) |
1985 + (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
1986 + pcicore_write16(pc, regoff, val16);
1987 + }
1988 +}
1989 +
1990 +/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
1991 +/* Needs to happen when coming out of 'standby'/'hibernate' */
1992 +static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
1993 +{
1994 + u16 val16;
1995 + uint regoff;
1996 +
1997 + regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);
1998 +
1999 + val16 = pcicore_read16(pc, regoff);
2000 +
2001 + if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
2002 + val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
2003 + pcicore_write16(pc, regoff, val16);
2004 + }
2005 }
2006
2007 /**************************************************
2008 * Init.
2009 **************************************************/
2010
2011 -static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
2012 +static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
2013 {
2014 + bcma_core_pci_fixcfg(pc);
2015 bcma_pcicore_serdes_workaround(pc);
2016 + bcma_core_pci_config_fixup(pc);
2017 }
2018
2019 -static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
2020 -{
2021 - struct bcma_bus *bus = pc->core->bus;
2022 - u16 chipid_top;
2023 -
2024 - chipid_top = (bus->chipinfo.id & 0xFF00);
2025 - if (chipid_top != 0x4700 &&
2026 - chipid_top != 0x5300)
2027 - return false;
2028 -
2029 -#ifdef CONFIG_SSB_DRIVER_PCICORE
2030 - if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
2031 - return false;
2032 -#endif /* CONFIG_SSB_DRIVER_PCICORE */
2033 -
2034 -#if 0
2035 - /* TODO: on BCMA we use address from EROM instead of magic formula */
2036 - u32 tmp;
2037 - return !mips_busprobe32(tmp, (bus->mmio +
2038 - (pc->core->core_index * BCMA_CORE_SIZE)));
2039 -#endif
2040 -
2041 - return true;
2042 -}
2043 -
2044 -void bcma_core_pci_init(struct bcma_drv_pci *pc)
2045 +void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
2046 {
2047 if (pc->setup_done)
2048 return;
2049
2050 - if (bcma_core_pci_is_in_hostmode(pc)) {
2051 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
2052 + pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
2053 + if (pc->hostmode)
2054 bcma_core_pci_hostmode_init(pc);
2055 -#else
2056 - pr_err("Driver compiled without support for hostmode PCI\n");
2057 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
2058 - } else {
2059 - bcma_core_pci_clientmode_init(pc);
2060 - }
2061
2062 - pc->setup_done = true;
2063 + if (!pc->hostmode)
2064 + bcma_core_pci_clientmode_init(pc);
2065 }
2066
2067 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
2068 bool enable)
2069 {
2070 - struct pci_dev *pdev = pc->core->bus->host_pci;
2071 + struct pci_dev *pdev;
2072 u32 coremask, tmp;
2073 int err = 0;
2074
2075 - if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
2076 + if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
2077 /* This bcma device is not on a PCI host-bus. So the IRQs are
2078 * not routed through the PCI core.
2079 * So we must not enable routing through the PCI core. */
2080 goto out;
2081 }
2082
2083 + pdev = pc->core->bus->host_pci;
2084 +
2085 err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
2086 if (err)
2087 goto out;
2088 @@ -236,3 +261,17 @@ out:
2089 return err;
2090 }
2091 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
2092 +
2093 +void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
2094 +{
2095 + u32 w;
2096 +
2097 + w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
2098 + if (extend)
2099 + w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
2100 + else
2101 + w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
2102 + bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
2103 + bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
2104 +}
2105 +EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
2106 --- a/drivers/bcma/driver_pci_host.c
2107 +++ b/drivers/bcma/driver_pci_host.c
2108 @@ -2,13 +2,600 @@
2109 * Broadcom specific AMBA
2110 * PCI Core in hostmode
2111 *
2112 + * Copyright 2005 - 2011, Broadcom Corporation
2113 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
2114 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
2115 + *
2116 * Licensed under the GNU/GPL. See COPYING for details.
2117 */
2118
2119 #include "bcma_private.h"
2120 +#include <linux/pci.h>
2121 +#include <linux/export.h>
2122 #include <linux/bcma/bcma.h>
2123 +#include <asm/paccess.h>
2124 +
2125 +/* Probe a 32bit value on the bus and catch bus exceptions.
2126 + * Returns nonzero on a bus exception.
2127 + * This is MIPS specific */
2128 +#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
2129 +
2130 +/* Assume one-hot slot wiring */
2131 +#define BCMA_PCI_SLOT_MAX 16
2132 +#define PCI_CONFIG_SPACE_SIZE 256
2133 +
2134 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
2135 +{
2136 + struct bcma_bus *bus = pc->core->bus;
2137 + u16 chipid_top;
2138 + u32 tmp;
2139 +
2140 + chipid_top = (bus->chipinfo.id & 0xFF00);
2141 + if (chipid_top != 0x4700 &&
2142 + chipid_top != 0x5300)
2143 + return false;
2144 +
2145 + bcma_core_enable(pc->core, 0);
2146 +
2147 + return !mips_busprobe32(tmp, pc->core->io_addr);
2148 +}
2149 +
2150 +static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
2151 +{
2152 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
2153 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
2154 + return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
2155 +}
2156 +
2157 +static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
2158 + u32 data)
2159 +{
2160 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
2161 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
2162 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
2163 +}
2164 +
2165 +static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
2166 + unsigned int func, unsigned int off)
2167 +{
2168 + u32 addr = 0;
2169 +
2170 + /* Issue config commands only when the data link is up (atleast
2171 + * one external pcie device is present).
2172 + */
2173 + if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
2174 + & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
2175 + goto out;
2176 +
2177 + /* Type 0 transaction */
2178 + /* Slide the PCI window to the appropriate slot */
2179 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
2180 + /* Calculate the address */
2181 + addr = pc->host_controller->host_cfg_addr;
2182 + addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
2183 + addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
2184 + addr |= (off & ~3);
2185 +
2186 +out:
2187 + return addr;
2188 +}
2189
2190 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
2191 +static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
2192 + unsigned int func, unsigned int off,
2193 + void *buf, int len)
2194 {
2195 - pr_err("No support for PCI core in hostmode yet\n");
2196 + int err = -EINVAL;
2197 + u32 addr, val;
2198 + void __iomem *mmio = 0;
2199 +
2200 + WARN_ON(!pc->hostmode);
2201 + if (unlikely(len != 1 && len != 2 && len != 4))
2202 + goto out;
2203 + if (dev == 0) {
2204 + /* we support only two functions on device 0 */
2205 + if (func > 1)
2206 + return -EINVAL;
2207 +
2208 + /* accesses to config registers with offsets >= 256
2209 + * requires indirect access.
2210 + */
2211 + if (off >= PCI_CONFIG_SPACE_SIZE) {
2212 + addr = (func << 12);
2213 + addr |= (off & 0x0FFF);
2214 + val = bcma_pcie_read_config(pc, addr);
2215 + } else {
2216 + addr = BCMA_CORE_PCI_PCICFG0;
2217 + addr |= (func << 8);
2218 + addr |= (off & 0xfc);
2219 + val = pcicore_read32(pc, addr);
2220 + }
2221 + } else {
2222 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
2223 + if (unlikely(!addr))
2224 + goto out;
2225 + err = -ENOMEM;
2226 + mmio = ioremap_nocache(addr, sizeof(val));
2227 + if (!mmio)
2228 + goto out;
2229 +
2230 + if (mips_busprobe32(val, mmio)) {
2231 + val = 0xffffffff;
2232 + goto unmap;
2233 + }
2234 +
2235 + val = readl(mmio);
2236 + }
2237 + val >>= (8 * (off & 3));
2238 +
2239 + switch (len) {
2240 + case 1:
2241 + *((u8 *)buf) = (u8)val;
2242 + break;
2243 + case 2:
2244 + *((u16 *)buf) = (u16)val;
2245 + break;
2246 + case 4:
2247 + *((u32 *)buf) = (u32)val;
2248 + break;
2249 + }
2250 + err = 0;
2251 +unmap:
2252 + if (mmio)
2253 + iounmap(mmio);
2254 +out:
2255 + return err;
2256 +}
2257 +
2258 +static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
2259 + unsigned int func, unsigned int off,
2260 + const void *buf, int len)
2261 +{
2262 + int err = -EINVAL;
2263 + u32 addr = 0, val = 0;
2264 + void __iomem *mmio = 0;
2265 + u16 chipid = pc->core->bus->chipinfo.id;
2266 +
2267 + WARN_ON(!pc->hostmode);
2268 + if (unlikely(len != 1 && len != 2 && len != 4))
2269 + goto out;
2270 + if (dev == 0) {
2271 + /* accesses to config registers with offsets >= 256
2272 + * requires indirect access.
2273 + */
2274 + if (off < PCI_CONFIG_SPACE_SIZE) {
2275 + addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
2276 + addr |= (func << 8);
2277 + addr |= (off & 0xfc);
2278 + mmio = ioremap_nocache(addr, sizeof(val));
2279 + if (!mmio)
2280 + goto out;
2281 + }
2282 + } else {
2283 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
2284 + if (unlikely(!addr))
2285 + goto out;
2286 + err = -ENOMEM;
2287 + mmio = ioremap_nocache(addr, sizeof(val));
2288 + if (!mmio)
2289 + goto out;
2290 +
2291 + if (mips_busprobe32(val, mmio)) {
2292 + val = 0xffffffff;
2293 + goto unmap;
2294 + }
2295 + }
2296 +
2297 + switch (len) {
2298 + case 1:
2299 + val = readl(mmio);
2300 + val &= ~(0xFF << (8 * (off & 3)));
2301 + val |= *((const u8 *)buf) << (8 * (off & 3));
2302 + break;
2303 + case 2:
2304 + val = readl(mmio);
2305 + val &= ~(0xFFFF << (8 * (off & 3)));
2306 + val |= *((const u16 *)buf) << (8 * (off & 3));
2307 + break;
2308 + case 4:
2309 + val = *((const u32 *)buf);
2310 + break;
2311 + }
2312 + if (dev == 0 && !addr) {
2313 + /* accesses to config registers with offsets >= 256
2314 + * requires indirect access.
2315 + */
2316 + addr = (func << 12);
2317 + addr |= (off & 0x0FFF);
2318 + bcma_pcie_write_config(pc, addr, val);
2319 + } else {
2320 + writel(val, mmio);
2321 +
2322 + if (chipid == BCMA_CHIP_ID_BCM4716 ||
2323 + chipid == BCMA_CHIP_ID_BCM4748)
2324 + readl(mmio);
2325 + }
2326 +
2327 + err = 0;
2328 +unmap:
2329 + if (mmio)
2330 + iounmap(mmio);
2331 +out:
2332 + return err;
2333 +}
2334 +
2335 +static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
2336 + unsigned int devfn,
2337 + int reg, int size, u32 *val)
2338 +{
2339 + unsigned long flags;
2340 + int err;
2341 + struct bcma_drv_pci *pc;
2342 + struct bcma_drv_pci_host *pc_host;
2343 +
2344 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
2345 + pc = pc_host->pdev;
2346 +
2347 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
2348 + err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
2349 + PCI_FUNC(devfn), reg, val, size);
2350 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
2351 +
2352 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
2353 +}
2354 +
2355 +static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
2356 + unsigned int devfn,
2357 + int reg, int size, u32 val)
2358 +{
2359 + unsigned long flags;
2360 + int err;
2361 + struct bcma_drv_pci *pc;
2362 + struct bcma_drv_pci_host *pc_host;
2363 +
2364 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
2365 + pc = pc_host->pdev;
2366 +
2367 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
2368 + err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
2369 + PCI_FUNC(devfn), reg, &val, size);
2370 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
2371 +
2372 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
2373 +}
2374 +
2375 +/* return cap_offset if requested capability exists in the PCI config space */
2376 +static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc,
2377 + unsigned int dev,
2378 + unsigned int func, u8 req_cap_id,
2379 + unsigned char *buf, u32 *buflen)
2380 +{
2381 + u8 cap_id;
2382 + u8 cap_ptr = 0;
2383 + u32 bufsize;
2384 + u8 byte_val;
2385 +
2386 + /* check for Header type 0 */
2387 + bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
2388 + sizeof(u8));
2389 + if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
2390 + return cap_ptr;
2391 +
2392 + /* check if the capability pointer field exists */
2393 + bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
2394 + sizeof(u8));
2395 + if (!(byte_val & PCI_STATUS_CAP_LIST))
2396 + return cap_ptr;
2397 +
2398 + /* check if the capability pointer is 0x00 */
2399 + bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
2400 + sizeof(u8));
2401 + if (cap_ptr == 0x00)
2402 + return cap_ptr;
2403 +
2404 + /* loop thr'u the capability list and see if the requested capabilty
2405 + * exists */
2406 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
2407 + while (cap_id != req_cap_id) {
2408 + bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
2409 + sizeof(u8));
2410 + if (cap_ptr == 0x00)
2411 + return cap_ptr;
2412 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
2413 + sizeof(u8));
2414 + }
2415 +
2416 + /* found the caller requested capability */
2417 + if ((buf != NULL) && (buflen != NULL)) {
2418 + u8 cap_data;
2419 +
2420 + bufsize = *buflen;
2421 + if (!bufsize)
2422 + return cap_ptr;
2423 +
2424 + *buflen = 0;
2425 +
2426 + /* copy the cpability data excluding cap ID and next ptr */
2427 + cap_data = cap_ptr + 2;
2428 + if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE)
2429 + bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
2430 + *buflen = bufsize;
2431 + while (bufsize--) {
2432 + bcma_extpci_read_config(pc, dev, func, cap_data, buf,
2433 + sizeof(u8));
2434 + cap_data++;
2435 + buf++;
2436 + }
2437 + }
2438 +
2439 + return cap_ptr;
2440 +}
2441 +
2442 +/* If the root port is capable of returning Config Request
2443 + * Retry Status (CRS) Completion Status to software then
2444 + * enable the feature.
2445 + */
2446 +static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
2447 +{
2448 + struct bcma_bus *bus = pc->core->bus;
2449 + u8 cap_ptr, root_ctrl, root_cap, dev;
2450 + u16 val16;
2451 + int i;
2452 +
2453 + cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
2454 + NULL);
2455 + root_cap = cap_ptr + PCI_EXP_RTCAP;
2456 + bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
2457 + if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
2458 + /* Enable CRS software visibility */
2459 + root_ctrl = cap_ptr + PCI_EXP_RTCTL;
2460 + val16 = PCI_EXP_RTCTL_CRSSVE;
2461 + bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
2462 + sizeof(u16));
2463 +
2464 + /* Initiate a configuration request to read the vendor id
2465 + * field of the device function's config space header after
2466 + * 100 ms wait time from the end of Reset. If the device is
2467 + * not done with its internal initialization, it must at
2468 + * least return a completion TLP, with a completion status
2469 + * of "Configuration Request Retry Status (CRS)". The root
2470 + * complex must complete the request to the host by returning
2471 + * a read-data value of 0001h for the Vendor ID field and
2472 + * all 1s for any additional bytes included in the request.
2473 + * Poll using the config reads for max wait time of 1 sec or
2474 + * until we receive the successful completion status. Repeat
2475 + * the procedure for all the devices.
2476 + */
2477 + for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
2478 + for (i = 0; i < 100000; i++) {
2479 + bcma_extpci_read_config(pc, dev, 0,
2480 + PCI_VENDOR_ID, &val16,
2481 + sizeof(val16));
2482 + if (val16 != 0x1)
2483 + break;
2484 + udelay(10);
2485 + }
2486 + if (val16 == 0x1)
2487 + bcma_err(bus, "PCI: Broken device in slot %d\n",
2488 + dev);
2489 + }
2490 + }
2491 +}
2492 +
2493 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
2494 +{
2495 + struct bcma_bus *bus = pc->core->bus;
2496 + struct bcma_drv_pci_host *pc_host;
2497 + u32 tmp;
2498 + u32 pci_membase_1G;
2499 + unsigned long io_map_base;
2500 +
2501 + bcma_info(bus, "PCIEcore in host mode found\n");
2502 +
2503 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
2504 + bcma_info(bus, "This PCIE core is disabled and not working\n");
2505 + return;
2506 + }
2507 +
2508 + pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
2509 + if (!pc_host) {
2510 + bcma_err(bus, "can not allocate memory");
2511 + return;
2512 + }
2513 +
2514 + pc->host_controller = pc_host;
2515 + pc_host->pci_controller.io_resource = &pc_host->io_resource;
2516 + pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
2517 + pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
2518 + pc_host->pdev = pc;
2519 +
2520 + pci_membase_1G = BCMA_SOC_PCI_DMA;
2521 + pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
2522 +
2523 + pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
2524 + pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
2525 +
2526 + pc_host->mem_resource.name = "BCMA PCIcore external memory",
2527 + pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
2528 + pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
2529 + pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
2530 +
2531 + pc_host->io_resource.name = "BCMA PCIcore external I/O",
2532 + pc_host->io_resource.start = 0x100;
2533 + pc_host->io_resource.end = 0x7FF;
2534 + pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
2535 +
2536 + /* Reset RC */
2537 + usleep_range(3000, 5000);
2538 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
2539 + usleep_range(1000, 2000);
2540 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
2541 + BCMA_CORE_PCI_CTL_RST_OE);
2542 +
2543 + /* 64 MB I/O access window. On 4716, use
2544 + * sbtopcie0 to access the device registers. We
2545 + * can't use address match 2 (1 GB window) region
2546 + * as mips can't generate 64-bit address on the
2547 + * backplane.
2548 + */
2549 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 ||
2550 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
2551 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
2552 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
2553 + BCMA_SOC_PCI_MEM_SZ - 1;
2554 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2555 + BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
2556 + } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
2557 + tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
2558 + tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
2559 + tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
2560 + if (pc->core->core_unit == 0) {
2561 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
2562 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
2563 + BCMA_SOC_PCI_MEM_SZ - 1;
2564 + pc_host->io_resource.start = 0x100;
2565 + pc_host->io_resource.end = 0x47F;
2566 + pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
2567 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2568 + tmp | BCMA_SOC_PCI_MEM);
2569 + } else if (pc->core->core_unit == 1) {
2570 + pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
2571 + pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
2572 + BCMA_SOC_PCI_MEM_SZ - 1;
2573 + pc_host->io_resource.start = 0x480;
2574 + pc_host->io_resource.end = 0x7FF;
2575 + pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
2576 + pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
2577 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2578 + tmp | BCMA_SOC_PCI1_MEM);
2579 + }
2580 + } else
2581 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2582 + BCMA_CORE_PCI_SBTOPCI_IO);
2583 +
2584 + /* 64 MB configuration access window */
2585 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
2586 +
2587 + /* 1 GB memory access window */
2588 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
2589 + BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
2590 +
2591 +
2592 + /* As per PCI Express Base Spec 1.1 we need to wait for
2593 + * at least 100 ms from the end of a reset (cold/warm/hot)
2594 + * before issuing configuration requests to PCI Express
2595 + * devices.
2596 + */
2597 + msleep(100);
2598 +
2599 + bcma_core_pci_enable_crs(pc);
2600 +
2601 + /* Enable PCI bridge BAR0 memory & master access */
2602 + tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
2603 + bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
2604 +
2605 + /* Enable PCI interrupts */
2606 + pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
2607 +
2608 + /* Ok, ready to run, register it to the system.
2609 + * The following needs change, if we want to port hostmode
2610 + * to non-MIPS platform. */
2611 + io_map_base = (unsigned long)ioremap_nocache(pc_host->mem_resource.start,
2612 + resource_size(&pc_host->mem_resource));
2613 + pc_host->pci_controller.io_map_base = io_map_base;
2614 + set_io_port_base(pc_host->pci_controller.io_map_base);
2615 + /* Give some time to the PCI controller to configure itself with the new
2616 + * values. Not waiting at this point causes crashes of the machine. */
2617 + usleep_range(10000, 15000);
2618 + register_pci_controller(&pc_host->pci_controller);
2619 + return;
2620 +}
2621 +
2622 +/* Early PCI fixup for a device on the PCI-core bridge. */
2623 +static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
2624 +{
2625 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2626 + /* This is not a device on the PCI-core bridge. */
2627 + return;
2628 + }
2629 + if (PCI_SLOT(dev->devfn) != 0)
2630 + return;
2631 +
2632 + pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
2633 +
2634 + /* Enable PCI bridge bus mastering and memory space */
2635 + pci_set_master(dev);
2636 + if (pcibios_enable_device(dev, ~0) < 0) {
2637 + pr_err("PCI: BCMA bridge enable failed\n");
2638 + return;
2639 + }
2640 +
2641 + /* Enable PCI bridge BAR1 prefetch and burst */
2642 + pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
2643 +}
2644 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
2645 +
2646 +/* Early PCI fixup for all PCI-cores to set the correct memory address. */
2647 +static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
2648 +{
2649 + struct resource *res;
2650 + int pos, err;
2651 +
2652 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2653 + /* This is not a device on the PCI-core bridge. */
2654 + return;
2655 + }
2656 + if (PCI_SLOT(dev->devfn) == 0)
2657 + return;
2658 +
2659 + pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
2660 +
2661 + for (pos = 0; pos < 6; pos++) {
2662 + res = &dev->resource[pos];
2663 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
2664 + err = pci_assign_resource(dev, pos);
2665 + if (err)
2666 + pr_err("PCI: Problem fixing up the addresses on %s\n",
2667 + pci_name(dev));
2668 + }
2669 + }
2670 +}
2671 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
2672 +
2673 +/* This function is called when doing a pci_enable_device().
2674 + * We must first check if the device is a device on the PCI-core bridge. */
2675 +int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
2676 +{
2677 + struct bcma_drv_pci_host *pc_host;
2678 +
2679 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2680 + /* This is not a device on the PCI-core bridge. */
2681 + return -ENODEV;
2682 + }
2683 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
2684 + pci_ops);
2685 +
2686 + pr_info("PCI: Fixing up device %s\n", pci_name(dev));
2687 +
2688 + /* Fix up interrupt lines */
2689 + dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
2690 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
2691 +
2692 + return 0;
2693 +}
2694 +EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
2695 +
2696 +/* PCI device IRQ mapping. */
2697 +int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
2698 +{
2699 + struct bcma_drv_pci_host *pc_host;
2700 +
2701 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2702 + /* This is not a device on the PCI-core bridge. */
2703 + return -ENODEV;
2704 + }
2705 +
2706 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
2707 + pci_ops);
2708 + return bcma_core_mips_irq(pc_host->pdev->core) + 2;
2709 }
2710 +EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
2711 --- a/drivers/bcma/host_pci.c
2712 +++ b/drivers/bcma/host_pci.c
2713 @@ -18,7 +18,7 @@ static void bcma_host_pci_switch_core(st
2714 pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
2715 core->wrap);
2716 core->bus->mapped_core = core;
2717 - pr_debug("Switched to core: 0x%X\n", core->id.id);
2718 + bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id);
2719 }
2720
2721 /* Provides access to the requested core. Returns base offset that has to be
2722 @@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct
2723 }
2724
2725 #ifdef CONFIG_BCMA_BLOCKIO
2726 -void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
2727 - size_t count, u16 offset, u8 reg_width)
2728 +static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
2729 + size_t count, u16 offset, u8 reg_width)
2730 {
2731 void __iomem *addr = core->bus->mmio + offset;
2732 if (core->bus->mapped_core != core)
2733 @@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm
2734 }
2735 }
2736
2737 -void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
2738 - size_t count, u16 offset, u8 reg_width)
2739 +static void bcma_host_pci_block_write(struct bcma_device *core,
2740 + const void *buffer, size_t count,
2741 + u16 offset, u8 reg_width)
2742 {
2743 void __iomem *addr = core->bus->mmio + offset;
2744 if (core->bus->mapped_core != core)
2745 @@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc
2746 iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
2747 }
2748
2749 -const struct bcma_host_ops bcma_host_pci_ops = {
2750 +static const struct bcma_host_ops bcma_host_pci_ops = {
2751 .read8 = bcma_host_pci_read8,
2752 .read16 = bcma_host_pci_read16,
2753 .read32 = bcma_host_pci_read32,
2754 @@ -154,8 +155,8 @@ const struct bcma_host_ops bcma_host_pci
2755 .awrite32 = bcma_host_pci_awrite32,
2756 };
2757
2758 -static int bcma_host_pci_probe(struct pci_dev *dev,
2759 - const struct pci_device_id *id)
2760 +static int __devinit bcma_host_pci_probe(struct pci_dev *dev,
2761 + const struct pci_device_id *id)
2762 {
2763 struct bcma_bus *bus;
2764 int err = -ENOMEM;
2765 @@ -188,7 +189,7 @@ static int bcma_host_pci_probe(struct pc
2766
2767 /* SSB needed additional powering up, do we have any AMBA PCI cards? */
2768 if (!pci_is_pcie(dev))
2769 - pr_err("PCI card detected, report problems.\n");
2770 + bcma_err(bus, "PCI card detected, report problems.\n");
2771
2772 /* Map MMIO */
2773 err = -ENOMEM;
2774 @@ -201,6 +202,9 @@ static int bcma_host_pci_probe(struct pc
2775 bus->hosttype = BCMA_HOSTTYPE_PCI;
2776 bus->ops = &bcma_host_pci_ops;
2777
2778 + bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
2779 + bus->boardinfo.type = bus->host_pci->subsystem_device;
2780 +
2781 /* Register */
2782 err = bcma_bus_register(bus);
2783 if (err)
2784 @@ -222,7 +226,7 @@ err_kfree_bus:
2785 return err;
2786 }
2787
2788 -static void bcma_host_pci_remove(struct pci_dev *dev)
2789 +static void __devexit bcma_host_pci_remove(struct pci_dev *dev)
2790 {
2791 struct bcma_bus *bus = pci_get_drvdata(dev);
2792
2793 @@ -234,7 +238,7 @@ static void bcma_host_pci_remove(struct
2794 pci_set_drvdata(dev, NULL);
2795 }
2796
2797 -#ifdef CONFIG_PM
2798 +#ifdef CONFIG_PM_SLEEP
2799 static int bcma_host_pci_suspend(struct device *dev)
2800 {
2801 struct pci_dev *pdev = to_pci_dev(dev);
2802 @@ -257,17 +261,20 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
2803 bcma_host_pci_resume);
2804 #define BCMA_PM_OPS (&bcma_pm_ops)
2805
2806 -#else /* CONFIG_PM */
2807 +#else /* CONFIG_PM_SLEEP */
2808
2809 #define BCMA_PM_OPS NULL
2810
2811 -#endif /* CONFIG_PM */
2812 +#endif /* CONFIG_PM_SLEEP */
2813
2814 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
2815 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
2816 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
2817 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
2818 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
2819 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
2820 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
2821 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
2822 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
2823 { 0, },
2824 };
2825 @@ -277,7 +284,7 @@ static struct pci_driver bcma_pci_bridge
2826 .name = "bcma-pci-bridge",
2827 .id_table = bcma_pci_bridge_tbl,
2828 .probe = bcma_host_pci_probe,
2829 - .remove = bcma_host_pci_remove,
2830 + .remove = __devexit_p(bcma_host_pci_remove),
2831 .driver.pm = BCMA_PM_OPS,
2832 };
2833
2834 --- a/drivers/bcma/host_soc.c
2835 +++ b/drivers/bcma/host_soc.c
2836 @@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc
2837 writel(value, core->io_wrap + offset);
2838 }
2839
2840 -const struct bcma_host_ops bcma_host_soc_ops = {
2841 +static const struct bcma_host_ops bcma_host_soc_ops = {
2842 .read8 = bcma_host_soc_read8,
2843 .read16 = bcma_host_soc_read16,
2844 .read32 = bcma_host_soc_read32,
2845 --- a/drivers/bcma/main.c
2846 +++ b/drivers/bcma/main.c
2847 @@ -7,12 +7,19 @@
2848
2849 #include "bcma_private.h"
2850 #include <linux/module.h>
2851 +#include <linux/platform_device.h>
2852 #include <linux/bcma/bcma.h>
2853 #include <linux/slab.h>
2854
2855 MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
2856 MODULE_LICENSE("GPL");
2857
2858 +/* contains the number the next bus should get. */
2859 +static unsigned int bcma_bus_next_num = 0;
2860 +
2861 +/* bcma_buses_mutex locks the bcma_bus_next_num */
2862 +static DEFINE_MUTEX(bcma_buses_mutex);
2863 +
2864 static int bcma_bus_match(struct device *dev, struct device_driver *drv);
2865 static int bcma_device_probe(struct device *dev);
2866 static int bcma_device_remove(struct device *dev);
2867 @@ -55,7 +62,14 @@ static struct bus_type bcma_bus_type = {
2868 .dev_attrs = bcma_device_attrs,
2869 };
2870
2871 -static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
2872 +static u16 bcma_cc_core_id(struct bcma_bus *bus)
2873 +{
2874 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
2875 + return BCMA_CORE_4706_CHIPCOMMON;
2876 + return BCMA_CORE_CHIPCOMMON;
2877 +}
2878 +
2879 +struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
2880 {
2881 struct bcma_device *core;
2882
2883 @@ -65,6 +79,19 @@ static struct bcma_device *bcma_find_cor
2884 }
2885 return NULL;
2886 }
2887 +EXPORT_SYMBOL_GPL(bcma_find_core);
2888 +
2889 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
2890 + u8 unit)
2891 +{
2892 + struct bcma_device *core;
2893 +
2894 + list_for_each_entry(core, &bus->cores, list) {
2895 + if (core->id.id == coreid && core->core_unit == unit)
2896 + return core;
2897 + }
2898 + return NULL;
2899 +}
2900
2901 static void bcma_release_core_dev(struct device *dev)
2902 {
2903 @@ -84,16 +111,18 @@ static int bcma_register_cores(struct bc
2904 list_for_each_entry(core, &bus->cores, list) {
2905 /* We support that cores ourself */
2906 switch (core->id.id) {
2907 + case BCMA_CORE_4706_CHIPCOMMON:
2908 case BCMA_CORE_CHIPCOMMON:
2909 case BCMA_CORE_PCI:
2910 case BCMA_CORE_PCIE:
2911 case BCMA_CORE_MIPS_74K:
2912 + case BCMA_CORE_4706_MAC_GBIT_COMMON:
2913 continue;
2914 }
2915
2916 core->dev.release = bcma_release_core_dev;
2917 core->dev.bus = &bcma_bus_type;
2918 - dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id);
2919 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
2920
2921 switch (bus->hosttype) {
2922 case BCMA_HOSTTYPE_PCI:
2923 @@ -111,41 +140,90 @@ static int bcma_register_cores(struct bc
2924
2925 err = device_register(&core->dev);
2926 if (err) {
2927 - pr_err("Could not register dev for core 0x%03X\n",
2928 - core->id.id);
2929 + bcma_err(bus,
2930 + "Could not register dev for core 0x%03X\n",
2931 + core->id.id);
2932 continue;
2933 }
2934 core->dev_registered = true;
2935 dev_id++;
2936 }
2937
2938 +#ifdef CONFIG_BCMA_SFLASH
2939 + if (bus->drv_cc.sflash.present) {
2940 + err = platform_device_register(&bcma_sflash_dev);
2941 + if (err)
2942 + bcma_err(bus, "Error registering serial flash\n");
2943 + }
2944 +#endif
2945 +
2946 +#ifdef CONFIG_BCMA_NFLASH
2947 + if (bus->drv_cc.nflash.present) {
2948 + err = platform_device_register(&bcma_nflash_dev);
2949 + if (err)
2950 + bcma_err(bus, "Error registering NAND flash\n");
2951 + }
2952 +#endif
2953 + err = bcma_gpio_init(&bus->drv_cc);
2954 + if (err == -ENOTSUPP)
2955 + bcma_debug(bus, "GPIO driver not activated\n");
2956 + else if (err)
2957 + bcma_err(bus, "Error registering GPIO driver: %i\n", err);
2958 +
2959 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
2960 + err = bcma_chipco_watchdog_register(&bus->drv_cc);
2961 + if (err)
2962 + bcma_err(bus, "Error registering watchdog driver\n");
2963 + }
2964 +
2965 return 0;
2966 }
2967
2968 static void bcma_unregister_cores(struct bcma_bus *bus)
2969 {
2970 - struct bcma_device *core;
2971 + struct bcma_device *core, *tmp;
2972
2973 - list_for_each_entry(core, &bus->cores, list) {
2974 + list_for_each_entry_safe(core, tmp, &bus->cores, list) {
2975 + list_del(&core->list);
2976 if (core->dev_registered)
2977 device_unregister(&core->dev);
2978 }
2979 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
2980 + platform_device_unregister(bus->drv_cc.watchdog);
2981 }
2982
2983 -int bcma_bus_register(struct bcma_bus *bus)
2984 +int __devinit bcma_bus_register(struct bcma_bus *bus)
2985 {
2986 int err;
2987 struct bcma_device *core;
2988
2989 + mutex_lock(&bcma_buses_mutex);
2990 + bus->num = bcma_bus_next_num++;
2991 + mutex_unlock(&bcma_buses_mutex);
2992 +
2993 /* Scan for devices (cores) */
2994 err = bcma_bus_scan(bus);
2995 if (err) {
2996 - pr_err("Failed to scan: %d\n", err);
2997 + bcma_err(bus, "Failed to scan: %d\n", err);
2998 return -1;
2999 }
3000
3001 + /* Early init CC core */
3002 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
3003 + if (core) {
3004 + bus->drv_cc.core = core;
3005 + bcma_core_chipcommon_early_init(&bus->drv_cc);
3006 + }
3007 +
3008 + /* Try to get SPROM */
3009 + err = bcma_sprom_get(bus);
3010 + if (err == -ENOENT) {
3011 + bcma_err(bus, "No SPROM available\n");
3012 + } else if (err)
3013 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
3014 +
3015 /* Init CC core */
3016 - core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
3017 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
3018 if (core) {
3019 bus->drv_cc.core = core;
3020 bcma_core_chipcommon_init(&bus->drv_cc);
3021 @@ -159,30 +237,47 @@ int bcma_bus_register(struct bcma_bus *b
3022 }
3023
3024 /* Init PCIE core */
3025 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
3026 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
3027 if (core) {
3028 - bus->drv_pci.core = core;
3029 - bcma_core_pci_init(&bus->drv_pci);
3030 + bus->drv_pci[0].core = core;
3031 + bcma_core_pci_init(&bus->drv_pci[0]);
3032 }
3033
3034 - /* Try to get SPROM */
3035 - err = bcma_sprom_get(bus);
3036 - if (err == -ENOENT) {
3037 - pr_err("No SPROM available\n");
3038 - } else if (err)
3039 - pr_err("Failed to get SPROM: %d\n", err);
3040 + /* Init PCIE core */
3041 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
3042 + if (core) {
3043 + bus->drv_pci[1].core = core;
3044 + bcma_core_pci_init(&bus->drv_pci[1]);
3045 + }
3046 +
3047 + /* Init GBIT MAC COMMON core */
3048 + core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
3049 + if (core) {
3050 + bus->drv_gmac_cmn.core = core;
3051 + bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
3052 + }
3053
3054 /* Register found cores */
3055 bcma_register_cores(bus);
3056
3057 - pr_info("Bus registered\n");
3058 + bcma_info(bus, "Bus registered\n");
3059
3060 return 0;
3061 }
3062
3063 void bcma_bus_unregister(struct bcma_bus *bus)
3064 {
3065 + struct bcma_device *cores[3];
3066 +
3067 + cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
3068 + cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
3069 + cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
3070 +
3071 bcma_unregister_cores(bus);
3072 +
3073 + kfree(cores[2]);
3074 + kfree(cores[1]);
3075 + kfree(cores[0]);
3076 }
3077
3078 int __init bcma_bus_early_register(struct bcma_bus *bus,
3079 @@ -196,14 +291,14 @@ int __init bcma_bus_early_register(struc
3080 bcma_init_bus(bus);
3081
3082 match.manuf = BCMA_MANUF_BCM;
3083 - match.id = BCMA_CORE_CHIPCOMMON;
3084 + match.id = bcma_cc_core_id(bus);
3085 match.class = BCMA_CL_SIM;
3086 match.rev = BCMA_ANY_REV;
3087
3088 /* Scan for chip common core */
3089 err = bcma_bus_scan_early(bus, &match, core_cc);
3090 if (err) {
3091 - pr_err("Failed to scan for common core: %d\n", err);
3092 + bcma_err(bus, "Failed to scan for common core: %d\n", err);
3093 return -1;
3094 }
3095
3096 @@ -215,25 +310,25 @@ int __init bcma_bus_early_register(struc
3097 /* Scan for mips core */
3098 err = bcma_bus_scan_early(bus, &match, core_mips);
3099 if (err) {
3100 - pr_err("Failed to scan for mips core: %d\n", err);
3101 + bcma_err(bus, "Failed to scan for mips core: %d\n", err);
3102 return -1;
3103 }
3104
3105 - /* Init CC core */
3106 - core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
3107 + /* Early init CC core */
3108 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
3109 if (core) {
3110 bus->drv_cc.core = core;
3111 - bcma_core_chipcommon_init(&bus->drv_cc);
3112 + bcma_core_chipcommon_early_init(&bus->drv_cc);
3113 }
3114
3115 - /* Init MIPS core */
3116 + /* Early init MIPS core */
3117 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
3118 if (core) {
3119 bus->drv_mips.core = core;
3120 - bcma_core_mips_init(&bus->drv_mips);
3121 + bcma_core_mips_early_init(&bus->drv_mips);
3122 }
3123
3124 - pr_info("Early bus registered\n");
3125 + bcma_info(bus, "Early bus registered\n");
3126
3127 return 0;
3128 }
3129 @@ -259,8 +354,7 @@ int bcma_bus_resume(struct bcma_bus *bus
3130 struct bcma_device *core;
3131
3132 /* Init CC core */
3133 - core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
3134 - if (core) {
3135 + if (bus->drv_cc.core) {
3136 bus->drv_cc.setup_done = false;
3137 bcma_core_chipcommon_init(&bus->drv_cc);
3138 }
3139 --- a/drivers/bcma/scan.c
3140 +++ b/drivers/bcma/scan.c
3141 @@ -19,15 +19,27 @@ struct bcma_device_id_name {
3142 u16 id;
3143 const char *name;
3144 };
3145 -struct bcma_device_id_name bcma_device_names[] = {
3146 +
3147 +static const struct bcma_device_id_name bcma_arm_device_names[] = {
3148 + { BCMA_CORE_4706_MAC_GBIT_COMMON, "BCM4706 GBit MAC Common" },
3149 + { BCMA_CORE_ARM_1176, "ARM 1176" },
3150 + { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
3151 + { BCMA_CORE_ARM_CM3, "ARM CM3" },
3152 +};
3153 +
3154 +static const struct bcma_device_id_name bcma_bcm_device_names[] = {
3155 { BCMA_CORE_OOB_ROUTER, "OOB Router" },
3156 + { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
3157 + { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
3158 + { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
3159 + { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
3160 + { BCMA_CORE_ALTA, "ALTA (I2S)" },
3161 { BCMA_CORE_INVALID, "Invalid" },
3162 { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
3163 { BCMA_CORE_ILINE20, "ILine 20" },
3164 { BCMA_CORE_SRAM, "SRAM" },
3165 { BCMA_CORE_SDRAM, "SDRAM" },
3166 { BCMA_CORE_PCI, "PCI" },
3167 - { BCMA_CORE_MIPS, "MIPS" },
3168 { BCMA_CORE_ETHERNET, "Fast Ethernet" },
3169 { BCMA_CORE_V90, "V90" },
3170 { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
3171 @@ -44,7 +56,6 @@ struct bcma_device_id_name bcma_device_n
3172 { BCMA_CORE_PHY_A, "PHY A" },
3173 { BCMA_CORE_PHY_B, "PHY B" },
3174 { BCMA_CORE_PHY_G, "PHY G" },
3175 - { BCMA_CORE_MIPS_3302, "MIPS 3302" },
3176 { BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
3177 { BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
3178 { BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
3179 @@ -58,15 +69,11 @@ struct bcma_device_id_name bcma_device_n
3180 { BCMA_CORE_PHY_N, "PHY N" },
3181 { BCMA_CORE_SRAM_CTL, "SRAM Controller" },
3182 { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
3183 - { BCMA_CORE_ARM_1176, "ARM 1176" },
3184 - { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
3185 { BCMA_CORE_PHY_LP, "PHY LP" },
3186 { BCMA_CORE_PMU, "PMU" },
3187 { BCMA_CORE_PHY_SSN, "PHY SSN" },
3188 { BCMA_CORE_SDIO_DEV, "SDIO Device" },
3189 - { BCMA_CORE_ARM_CM3, "ARM CM3" },
3190 { BCMA_CORE_PHY_HT, "PHY HT" },
3191 - { BCMA_CORE_MIPS_74K, "MIPS 74K" },
3192 { BCMA_CORE_MAC_GBIT, "GBit MAC" },
3193 { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
3194 { BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
3195 @@ -79,16 +86,41 @@ struct bcma_device_id_name bcma_device_n
3196 { BCMA_CORE_SHIM, "SHIM" },
3197 { BCMA_CORE_DEFAULT, "Default" },
3198 };
3199 -const char *bcma_device_name(struct bcma_device_id *id)
3200 +
3201 +static const struct bcma_device_id_name bcma_mips_device_names[] = {
3202 + { BCMA_CORE_MIPS, "MIPS" },
3203 + { BCMA_CORE_MIPS_3302, "MIPS 3302" },
3204 + { BCMA_CORE_MIPS_74K, "MIPS 74K" },
3205 +};
3206 +
3207 +static const char *bcma_device_name(const struct bcma_device_id *id)
3208 {
3209 - int i;
3210 + const struct bcma_device_id_name *names;
3211 + int size, i;
3212
3213 - if (id->manuf == BCMA_MANUF_BCM) {
3214 - for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
3215 - if (bcma_device_names[i].id == id->id)
3216 - return bcma_device_names[i].name;
3217 - }
3218 + /* search manufacturer specific names */
3219 + switch (id->manuf) {
3220 + case BCMA_MANUF_ARM:
3221 + names = bcma_arm_device_names;
3222 + size = ARRAY_SIZE(bcma_arm_device_names);
3223 + break;
3224 + case BCMA_MANUF_BCM:
3225 + names = bcma_bcm_device_names;
3226 + size = ARRAY_SIZE(bcma_bcm_device_names);
3227 + break;
3228 + case BCMA_MANUF_MIPS:
3229 + names = bcma_mips_device_names;
3230 + size = ARRAY_SIZE(bcma_mips_device_names);
3231 + break;
3232 + default:
3233 + return "UNKNOWN";
3234 }
3235 +
3236 + for (i = 0; i < size; i++) {
3237 + if (names[i].id == id->id)
3238 + return names[i].name;
3239 + }
3240 +
3241 return "UNKNOWN";
3242 }
3243
3244 @@ -212,6 +244,17 @@ static struct bcma_device *bcma_find_cor
3245 return NULL;
3246 }
3247
3248 +static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid)
3249 +{
3250 + struct bcma_device *core;
3251 +
3252 + list_for_each_entry_reverse(core, &bus->cores, list) {
3253 + if (core->id.id == coreid)
3254 + return core;
3255 + }
3256 + return NULL;
3257 +}
3258 +
3259 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
3260 struct bcma_device_id *match, int core_num,
3261 struct bcma_device *core)
3262 @@ -252,11 +295,15 @@ static int bcma_get_next_core(struct bcm
3263
3264 /* check if component is a core at all */
3265 if (wrappers[0] + wrappers[1] == 0) {
3266 - /* we could save addrl of the router
3267 - if (cid == BCMA_CORE_OOB_ROUTER)
3268 - */
3269 - bcma_erom_skip_component(bus, eromptr);
3270 - return -ENXIO;
3271 + /* Some specific cores don't need wrappers */
3272 + switch (core->id.id) {
3273 + case BCMA_CORE_4706_MAC_GBIT_COMMON:
3274 + /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
3275 + break;
3276 + default:
3277 + bcma_erom_skip_component(bus, eromptr);
3278 + return -ENXIO;
3279 + }
3280 }
3281
3282 if (bcma_erom_is_bridge(bus, eromptr)) {
3283 @@ -286,6 +333,23 @@ static int bcma_get_next_core(struct bcm
3284 return -EILSEQ;
3285 }
3286
3287 + /* First Slave Address Descriptor should be port 0:
3288 + * the main register space for the core
3289 + */
3290 + tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
3291 + if (tmp <= 0) {
3292 + /* Try again to see if it is a bridge */
3293 + tmp = bcma_erom_get_addr_desc(bus, eromptr,
3294 + SCAN_ADDR_TYPE_BRIDGE, 0);
3295 + if (tmp <= 0) {
3296 + return -EILSEQ;
3297 + } else {
3298 + bcma_info(bus, "Bridge found\n");
3299 + return -ENXIO;
3300 + }
3301 + }
3302 + core->addr = tmp;
3303 +
3304 /* get & parse slave ports */
3305 for (i = 0; i < ports[1]; i++) {
3306 for (j = 0; ; j++) {
3307 @@ -298,7 +362,7 @@ static int bcma_get_next_core(struct bcm
3308 break;
3309 } else {
3310 if (i == 0 && j == 0)
3311 - core->addr = tmp;
3312 + core->addr1 = tmp;
3313 }
3314 }
3315 }
3316 @@ -353,6 +417,7 @@ static int bcma_get_next_core(struct bcm
3317 void bcma_init_bus(struct bcma_bus *bus)
3318 {
3319 s32 tmp;
3320 + struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
3321
3322 if (bus->init_done)
3323 return;
3324 @@ -363,9 +428,12 @@ void bcma_init_bus(struct bcma_bus *bus)
3325 bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
3326
3327 tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
3328 - bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
3329 - bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
3330 - bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
3331 + chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
3332 + chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
3333 + chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
3334 + bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
3335 + chipinfo->id, chipinfo->rev, chipinfo->pkg);
3336 +
3337 bus->init_done = true;
3338 }
3339
3340 @@ -392,9 +460,12 @@ int bcma_bus_scan(struct bcma_bus *bus)
3341 bcma_scan_switch_core(bus, erombase);
3342
3343 while (eromptr < eromend) {
3344 + struct bcma_device *other_core;
3345 struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
3346 - if (!core)
3347 - return -ENOMEM;
3348 + if (!core) {
3349 + err = -ENOMEM;
3350 + goto out;
3351 + }
3352 INIT_LIST_HEAD(&core->list);
3353 core->bus = bus;
3354
3355 @@ -409,25 +480,28 @@ int bcma_bus_scan(struct bcma_bus *bus)
3356 } else if (err == -ESPIPE) {
3357 break;
3358 }
3359 - return err;
3360 + goto out;
3361 }
3362
3363 core->core_index = core_num++;
3364 bus->nr_cores++;
3365 + other_core = bcma_find_core_reverse(bus, core->id.id);
3366 + core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
3367
3368 - pr_info("Core %d found: %s "
3369 - "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3370 - core->core_index, bcma_device_name(&core->id),
3371 - core->id.manuf, core->id.id, core->id.rev,
3372 - core->id.class);
3373 + bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3374 + core->core_index, bcma_device_name(&core->id),
3375 + core->id.manuf, core->id.id, core->id.rev,
3376 + core->id.class);
3377
3378 - list_add(&core->list, &bus->cores);
3379 + list_add_tail(&core->list, &bus->cores);
3380 }
3381
3382 + err = 0;
3383 +out:
3384 if (bus->hosttype == BCMA_HOSTTYPE_SOC)
3385 iounmap(eromptr);
3386
3387 - return 0;
3388 + return err;
3389 }
3390
3391 int __init bcma_bus_scan_early(struct bcma_bus *bus,
3392 @@ -467,21 +541,21 @@ int __init bcma_bus_scan_early(struct bc
3393 else if (err == -ESPIPE)
3394 break;
3395 else if (err < 0)
3396 - return err;
3397 + goto out;
3398
3399 core->core_index = core_num++;
3400 bus->nr_cores++;
3401 - pr_info("Core %d found: %s "
3402 - "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3403 - core->core_index, bcma_device_name(&core->id),
3404 - core->id.manuf, core->id.id, core->id.rev,
3405 - core->id.class);
3406 + bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3407 + core->core_index, bcma_device_name(&core->id),
3408 + core->id.manuf, core->id.id, core->id.rev,
3409 + core->id.class);
3410
3411 - list_add(&core->list, &bus->cores);
3412 + list_add_tail(&core->list, &bus->cores);
3413 err = 0;
3414 break;
3415 }
3416
3417 +out:
3418 if (bus->hosttype == BCMA_HOSTTYPE_SOC)
3419 iounmap(eromptr);
3420
3421 --- a/drivers/bcma/scan.h
3422 +++ b/drivers/bcma/scan.h
3423 @@ -27,7 +27,7 @@
3424 #define SCAN_CIB_NMW 0x0007C000
3425 #define SCAN_CIB_NMW_SHIFT 14
3426 #define SCAN_CIB_NSW 0x00F80000
3427 -#define SCAN_CIB_NSW_SHIFT 17
3428 +#define SCAN_CIB_NSW_SHIFT 19
3429 #define SCAN_CIB_REV 0xFF000000
3430 #define SCAN_CIB_REV_SHIFT 24
3431
3432 --- a/drivers/bcma/sprom.c
3433 +++ b/drivers/bcma/sprom.c
3434 @@ -2,6 +2,8 @@
3435 * Broadcom specific AMBA
3436 * SPROM reading
3437 *
3438 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
3439 + *
3440 * Licensed under the GNU/GPL. See COPYING for details.
3441 */
3442
3443 @@ -14,7 +16,57 @@
3444 #include <linux/dma-mapping.h>
3445 #include <linux/slab.h>
3446
3447 -#define SPOFF(offset) ((offset) / sizeof(u16))
3448 +static int(*get_fallback_sprom)(struct bcma_bus *dev, struct ssb_sprom *out);
3449 +
3450 +/**
3451 + * bcma_arch_register_fallback_sprom - Registers a method providing a
3452 + * fallback SPROM if no SPROM is found.
3453 + *
3454 + * @sprom_callback: The callback function.
3455 + *
3456 + * With this function the architecture implementation may register a
3457 + * callback handler which fills the SPROM data structure. The fallback is
3458 + * used for PCI based BCMA devices, where no valid SPROM can be found
3459 + * in the shadow registers and to provide the SPROM for SoCs where BCMA is
3460 + * to controll the system bus.
3461 + *
3462 + * This function is useful for weird architectures that have a half-assed
3463 + * BCMA device hardwired to their PCI bus.
3464 + *
3465 + * This function is available for architecture code, only. So it is not
3466 + * exported.
3467 + */
3468 +int bcma_arch_register_fallback_sprom(int (*sprom_callback)(struct bcma_bus *bus,
3469 + struct ssb_sprom *out))
3470 +{
3471 + if (get_fallback_sprom)
3472 + return -EEXIST;
3473 + get_fallback_sprom = sprom_callback;
3474 +
3475 + return 0;
3476 +}
3477 +
3478 +static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus,
3479 + struct ssb_sprom *out)
3480 +{
3481 + int err;
3482 +
3483 + if (!get_fallback_sprom) {
3484 + err = -ENOENT;
3485 + goto fail;
3486 + }
3487 +
3488 + err = get_fallback_sprom(bus, out);
3489 + if (err)
3490 + goto fail;
3491 +
3492 + bcma_debug(bus, "Using SPROM revision %d provided by platform.\n",
3493 + bus->sprom.revision);
3494 + return 0;
3495 +fail:
3496 + bcma_warn(bus, "Using fallback SPROM failed (err %d)\n", err);
3497 + return err;
3498 +}
3499
3500 /**************************************************
3501 * R/W ops.
3502 @@ -124,10 +176,37 @@ static int bcma_sprom_valid(const u16 *s
3503 * SPROM extraction.
3504 **************************************************/
3505
3506 +#define SPOFF(offset) ((offset) / sizeof(u16))
3507 +
3508 +#define SPEX(_field, _offset, _mask, _shift) \
3509 + bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
3510 +
3511 +#define SPEX32(_field, _offset, _mask, _shift) \
3512 + bus->sprom._field = ((((u32)sprom[SPOFF((_offset)+2)] << 16 | \
3513 + sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))
3514 +
3515 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
3516 + do { \
3517 + SPEX(_field[0], _offset + 0, _mask, _shift); \
3518 + SPEX(_field[1], _offset + 2, _mask, _shift); \
3519 + SPEX(_field[2], _offset + 4, _mask, _shift); \
3520 + SPEX(_field[3], _offset + 6, _mask, _shift); \
3521 + SPEX(_field[4], _offset + 8, _mask, _shift); \
3522 + SPEX(_field[5], _offset + 10, _mask, _shift); \
3523 + SPEX(_field[6], _offset + 12, _mask, _shift); \
3524 + SPEX(_field[7], _offset + 14, _mask, _shift); \
3525 + } while (0)
3526 +
3527 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
3528 {
3529 - u16 v;
3530 + u16 v, o;
3531 int i;
3532 + u16 pwr_info_offset[] = {
3533 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
3534 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
3535 + };
3536 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
3537 + ARRAY_SIZE(bus->sprom.core_pwr_info));
3538
3539 bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
3540 SSB_SPROM_REVISION_REV;
3541 @@ -137,107 +216,390 @@ static void bcma_sprom_extract_r8(struct
3542 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
3543 }
3544
3545 - bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)];
3546 + SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
3547 +
3548 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
3549 + SSB_SPROM4_TXPID2G0_SHIFT);
3550 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G1,
3551 + SSB_SPROM4_TXPID2G1_SHIFT);
3552 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G2,
3553 + SSB_SPROM4_TXPID2G2_SHIFT);
3554 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G3,
3555 + SSB_SPROM4_TXPID2G3_SHIFT);
3556 +
3557 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL0,
3558 + SSB_SPROM4_TXPID5GL0_SHIFT);
3559 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL1,
3560 + SSB_SPROM4_TXPID5GL1_SHIFT);
3561 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL2,
3562 + SSB_SPROM4_TXPID5GL2_SHIFT);
3563 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL3,
3564 + SSB_SPROM4_TXPID5GL3_SHIFT);
3565 +
3566 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G0,
3567 + SSB_SPROM4_TXPID5G0_SHIFT);
3568 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G1,
3569 + SSB_SPROM4_TXPID5G1_SHIFT);
3570 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G2,
3571 + SSB_SPROM4_TXPID5G2_SHIFT);
3572 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G3,
3573 + SSB_SPROM4_TXPID5G3_SHIFT);
3574 +
3575 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH0,
3576 + SSB_SPROM4_TXPID5GH0_SHIFT);
3577 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH1,
3578 + SSB_SPROM4_TXPID5GH1_SHIFT);
3579 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH2,
3580 + SSB_SPROM4_TXPID5GH2_SHIFT);
3581 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH3,
3582 + SSB_SPROM4_TXPID5GH3_SHIFT);
3583 +
3584 + SPEX(boardflags_lo, SSB_SPROM8_BFLLO, ~0, 0);
3585 + SPEX(boardflags_hi, SSB_SPROM8_BFLHI, ~0, 0);
3586 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, ~0, 0);
3587 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, ~0, 0);
3588 +
3589 + SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
3590 + SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
3591 +
3592 + /* Extract cores power info info */
3593 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
3594 + o = pwr_info_offset[i];
3595 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
3596 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
3597 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
3598 + SSB_SPROM8_2G_MAXP, 0);
3599 +
3600 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
3601 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
3602 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
3603 +
3604 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
3605 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
3606 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
3607 + SSB_SPROM8_5G_MAXP, 0);
3608 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
3609 + SSB_SPROM8_5GH_MAXP, 0);
3610 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
3611 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
3612 +
3613 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
3614 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
3615 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
3616 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
3617 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
3618 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
3619 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
3620 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
3621 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
3622 + }
3623
3624 - bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
3625 - SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT;
3626 - bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
3627 - SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT;
3628 - bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
3629 - SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT;
3630 - bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
3631 - SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT;
3632 -
3633 - bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
3634 - SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT;
3635 - bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
3636 - SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT;
3637 - bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
3638 - SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT;
3639 - bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
3640 - SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT;
3641 -
3642 - bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
3643 - SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT;
3644 - bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
3645 - SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT;
3646 - bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
3647 - SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT;
3648 - bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
3649 - SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT;
3650 -
3651 - bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
3652 - SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT;
3653 - bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
3654 - SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT;
3655 - bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
3656 - SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT;
3657 - bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
3658 - SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT;
3659 -
3660 - bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
3661 - bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
3662 - bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
3663 - bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
3664 -
3665 - bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
3666 -
3667 - bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3668 - SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
3669 - bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3670 - SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
3671 - bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3672 - SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
3673 - bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3674 - SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
3675 - bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3676 - SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
3677 -
3678 - bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3679 - SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
3680 - bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3681 - SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
3682 - bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3683 - SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
3684 - bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3685 - SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
3686 - bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3687 - SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
3688 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TSSIPOS,
3689 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
3690 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_EXTPA_GAIN,
3691 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
3692 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_PDET_RANGE,
3693 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
3694 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TR_ISO,
3695 + SSB_SROM8_FEM_TR_ISO_SHIFT);
3696 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_ANTSWLUT,
3697 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
3698 +
3699 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TSSIPOS,
3700 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
3701 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_EXTPA_GAIN,
3702 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
3703 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_PDET_RANGE,
3704 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
3705 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TR_ISO,
3706 + SSB_SROM8_FEM_TR_ISO_SHIFT);
3707 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_ANTSWLUT,
3708 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
3709 +
3710 + SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
3711 + SSB_SPROM8_ANTAVAIL_A_SHIFT);
3712 + SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
3713 + SSB_SPROM8_ANTAVAIL_BG_SHIFT);
3714 + SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
3715 + SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
3716 + SSB_SPROM8_ITSSI_BG_SHIFT);
3717 + SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
3718 + SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
3719 + SSB_SPROM8_ITSSI_A_SHIFT);
3720 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
3721 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
3722 + SSB_SPROM8_MAXP_AL_SHIFT);
3723 + SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
3724 + SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
3725 + SSB_SPROM8_GPIOA_P1_SHIFT);
3726 + SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
3727 + SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
3728 + SSB_SPROM8_GPIOB_P3_SHIFT);
3729 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
3730 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
3731 + SSB_SPROM8_TRI5G_SHIFT);
3732 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
3733 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
3734 + SSB_SPROM8_TRI5GH_SHIFT);
3735 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G,
3736 + SSB_SPROM8_RXPO2G_SHIFT);
3737 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
3738 + SSB_SPROM8_RXPO5G_SHIFT);
3739 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
3740 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
3741 + SSB_SPROM8_RSSISMC2G_SHIFT);
3742 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
3743 + SSB_SPROM8_RSSISAV2G_SHIFT);
3744 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
3745 + SSB_SPROM8_BXA2G_SHIFT);
3746 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
3747 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
3748 + SSB_SPROM8_RSSISMC5G_SHIFT);
3749 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
3750 + SSB_SPROM8_RSSISAV5G_SHIFT);
3751 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
3752 + SSB_SPROM8_BXA5G_SHIFT);
3753 +
3754 + SPEX(pa0b0, SSB_SPROM8_PA0B0, ~0, 0);
3755 + SPEX(pa0b1, SSB_SPROM8_PA0B1, ~0, 0);
3756 + SPEX(pa0b2, SSB_SPROM8_PA0B2, ~0, 0);
3757 + SPEX(pa1b0, SSB_SPROM8_PA1B0, ~0, 0);
3758 + SPEX(pa1b1, SSB_SPROM8_PA1B1, ~0, 0);
3759 + SPEX(pa1b2, SSB_SPROM8_PA1B2, ~0, 0);
3760 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, ~0, 0);
3761 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, ~0, 0);
3762 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, ~0, 0);
3763 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, ~0, 0);
3764 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, ~0, 0);
3765 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, ~0, 0);
3766 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, ~0, 0);
3767 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, ~0, 0);
3768 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, ~0, 0);
3769 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, ~0, 0);
3770 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
3771 +
3772 + /* Extract the antenna gain values. */
3773 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
3774 + SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
3775 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
3776 + SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
3777 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
3778 + SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
3779 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
3780 + SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
3781 +
3782 + SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
3783 + SSB_SPROM8_LEDDC_ON_SHIFT);
3784 + SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
3785 + SSB_SPROM8_LEDDC_OFF_SHIFT);
3786 +
3787 + SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
3788 + SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
3789 + SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
3790 + SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
3791 + SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
3792 + SSB_SPROM8_TXRXC_SWITCH_SHIFT);
3793 +
3794 + SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
3795 +
3796 + SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
3797 + SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
3798 + SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
3799 + SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
3800 +
3801 + SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
3802 + SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
3803 + SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
3804 + SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
3805 + SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
3806 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
3807 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
3808 + SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
3809 + SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
3810 + SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
3811 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
3812 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
3813 + SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
3814 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
3815 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
3816 + SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
3817 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
3818 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
3819 + SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
3820 + SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
3821 +
3822 + SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
3823 + SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
3824 + SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
3825 + SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
3826 +
3827 + SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
3828 + SSB_SPROM8_THERMAL_TRESH_SHIFT);
3829 + SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
3830 + SSB_SPROM8_THERMAL_OFFSET_SHIFT);
3831 + SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
3832 + SSB_SPROM8_TEMPDELTA_PHYCAL,
3833 + SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
3834 + SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
3835 + SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
3836 + SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
3837 + SSB_SPROM8_TEMPDELTA_HYSTERESIS,
3838 + SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
3839 +}
3840 +
3841 +/*
3842 + * Indicates the presence of external SPROM.
3843 + */
3844 +static bool bcma_sprom_ext_available(struct bcma_bus *bus)
3845 +{
3846 + u32 chip_status;
3847 + u32 srom_control;
3848 + u32 present_mask;
3849 +
3850 + if (bus->drv_cc.core->id.rev >= 31) {
3851 + if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
3852 + return false;
3853 +
3854 + srom_control = bcma_read32(bus->drv_cc.core,
3855 + BCMA_CC_SROM_CONTROL);
3856 + return srom_control & BCMA_CC_SROM_CONTROL_PRESENT;
3857 + }
3858 +
3859 + /* older chipcommon revisions use chip status register */
3860 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
3861 + switch (bus->chipinfo.id) {
3862 + case BCMA_CHIP_ID_BCM4313:
3863 + present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT;
3864 + break;
3865 +
3866 + case BCMA_CHIP_ID_BCM4331:
3867 + present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT;
3868 + break;
3869 +
3870 + default:
3871 + return true;
3872 + }
3873 +
3874 + return chip_status & present_mask;
3875 +}
3876 +
3877 +/*
3878 + * Indicates that on-chip OTP memory is present and enabled.
3879 + */
3880 +static bool bcma_sprom_onchip_available(struct bcma_bus *bus)
3881 +{
3882 + u32 chip_status;
3883 + u32 otpsize = 0;
3884 + bool present;
3885 +
3886 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
3887 + switch (bus->chipinfo.id) {
3888 + case BCMA_CHIP_ID_BCM4313:
3889 + present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT;
3890 + break;
3891 +
3892 + case BCMA_CHIP_ID_BCM4331:
3893 + present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
3894 + break;
3895 +
3896 + case BCMA_CHIP_ID_BCM43224:
3897 + case BCMA_CHIP_ID_BCM43225:
3898 + /* for these chips OTP is always available */
3899 + present = true;
3900 + break;
3901 + case BCMA_CHIP_ID_BCM43227:
3902 + case BCMA_CHIP_ID_BCM43228:
3903 + case BCMA_CHIP_ID_BCM43428:
3904 + present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT;
3905 + break;
3906 + default:
3907 + present = false;
3908 + break;
3909 + }
3910 +
3911 + if (present) {
3912 + otpsize = bus->drv_cc.capabilities & BCMA_CC_CAP_OTPS;
3913 + otpsize >>= BCMA_CC_CAP_OTPS_SHIFT;
3914 + }
3915 +
3916 + return otpsize != 0;
3917 +}
3918 +
3919 +/*
3920 + * Verify OTP is filled and determine the byte
3921 + * offset where SPROM data is located.
3922 + *
3923 + * On error, returns 0; byte offset otherwise.
3924 + */
3925 +static int bcma_sprom_onchip_offset(struct bcma_bus *bus)
3926 +{
3927 + struct bcma_device *cc = bus->drv_cc.core;
3928 + u32 offset;
3929 +
3930 + /* verify OTP status */
3931 + if ((bcma_read32(cc, BCMA_CC_OTPS) & BCMA_CC_OTPS_GU_PROG_HW) == 0)
3932 + return 0;
3933 +
3934 + /* obtain bit offset from otplayout register */
3935 + offset = (bcma_read32(cc, BCMA_CC_OTPL) & BCMA_CC_OTPL_GURGN_OFFSET);
3936 + return BCMA_CC_SPROM + (offset >> 3);
3937 }
3938
3939 int bcma_sprom_get(struct bcma_bus *bus)
3940 {
3941 - u16 offset;
3942 + u16 offset = BCMA_CC_SPROM;
3943 u16 *sprom;
3944 int err = 0;
3945
3946 if (!bus->drv_cc.core)
3947 return -EOPNOTSUPP;
3948
3949 - if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
3950 - return -ENOENT;
3951 + if (!bcma_sprom_ext_available(bus)) {
3952 + bool sprom_onchip;
3953 +
3954 + /*
3955 + * External SPROM takes precedence so check
3956 + * on-chip OTP only when no external SPROM
3957 + * is present.
3958 + */
3959 + sprom_onchip = bcma_sprom_onchip_available(bus);
3960 + if (sprom_onchip) {
3961 + /* determine offset */
3962 + offset = bcma_sprom_onchip_offset(bus);
3963 + }
3964 + if (!offset || !sprom_onchip) {
3965 + /*
3966 + * Maybe there is no SPROM on the device?
3967 + * Now we ask the arch code if there is some sprom
3968 + * available for this device in some other storage.
3969 + */
3970 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
3971 + return err;
3972 + }
3973 + }
3974
3975 sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
3976 GFP_KERNEL);
3977 if (!sprom)
3978 return -ENOMEM;
3979
3980 - if (bus->chipinfo.id == 0x4331)
3981 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
3982 + bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
3983 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
3984
3985 - /* Most cards have SPROM moved by additional offset 0x30 (48 dwords).
3986 - * According to brcm80211 this applies to cards with PCIe rev >= 6
3987 - * TODO: understand this condition and use it */
3988 - offset = (bus->chipinfo.id == 0x4331) ? BCMA_CC_SPROM :
3989 - BCMA_CC_SPROM_PCIE6;
3990 + bcma_debug(bus, "SPROM offset 0x%x\n", offset);
3991 bcma_sprom_read(bus, offset, sprom);
3992
3993 - if (bus->chipinfo.id == 0x4331)
3994 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
3995 + bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
3996 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
3997
3998 err = bcma_sprom_valid(sprom);
3999 - if (err)
4000 + if (err) {
4001 + bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
4002 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
4003 goto out;
4004 + }
4005
4006 bcma_sprom_extract_r8(bus, sprom);
4007
4008 --- a/include/linux/bcma/bcma.h
4009 +++ b/include/linux/bcma/bcma.h
4010 @@ -7,9 +7,10 @@
4011 #include <linux/bcma/bcma_driver_chipcommon.h>
4012 #include <linux/bcma/bcma_driver_pci.h>
4013 #include <linux/bcma/bcma_driver_mips.h>
4014 +#include <linux/bcma/bcma_driver_gmac_cmn.h>
4015 #include <linux/ssb/ssb.h> /* SPROM sharing */
4016
4017 -#include "bcma_regs.h"
4018 +#include <linux/bcma/bcma_regs.h>
4019
4020 struct bcma_device;
4021 struct bcma_bus;
4022 @@ -26,6 +27,11 @@ struct bcma_chipinfo {
4023 u8 pkg;
4024 };
4025
4026 +struct bcma_boardinfo {
4027 + u16 vendor;
4028 + u16 type;
4029 +};
4030 +
4031 enum bcma_clkmode {
4032 BCMA_CLKMODE_FAST,
4033 BCMA_CLKMODE_DYNAMIC,
4034 @@ -65,6 +71,13 @@ struct bcma_host_ops {
4035
4036 /* Core-ID values. */
4037 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
4038 +#define BCMA_CORE_4706_CHIPCOMMON 0x500
4039 +#define BCMA_CORE_4706_SOC_RAM 0x50E
4040 +#define BCMA_CORE_4706_MAC_GBIT 0x52D
4041 +#define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
4042 +#define BCMA_CORE_ALTA 0x534 /* I2S core */
4043 +#define BCMA_CORE_4706_MAC_GBIT_COMMON 0x5DC
4044 +#define BCMA_CORE_DDR23_PHY 0x5DD
4045 #define BCMA_CORE_INVALID 0x700
4046 #define BCMA_CORE_CHIPCOMMON 0x800
4047 #define BCMA_CORE_ILINE20 0x801
4048 @@ -121,10 +134,46 @@ struct bcma_host_ops {
4049 #define BCMA_CORE_I2S 0x834
4050 #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
4051 #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
4052 +#define BCMA_CORE_ARM_CR4 0x83e
4053 #define BCMA_CORE_DEFAULT 0xFFF
4054
4055 #define BCMA_MAX_NR_CORES 16
4056
4057 +/* Chip IDs of PCIe devices */
4058 +#define BCMA_CHIP_ID_BCM4313 0x4313
4059 +#define BCMA_CHIP_ID_BCM43224 43224
4060 +#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
4061 +#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
4062 +#define BCMA_CHIP_ID_BCM43225 43225
4063 +#define BCMA_CHIP_ID_BCM43227 43227
4064 +#define BCMA_CHIP_ID_BCM43228 43228
4065 +#define BCMA_CHIP_ID_BCM43421 43421
4066 +#define BCMA_CHIP_ID_BCM43428 43428
4067 +#define BCMA_CHIP_ID_BCM43431 43431
4068 +#define BCMA_CHIP_ID_BCM43460 43460
4069 +#define BCMA_CHIP_ID_BCM4331 0x4331
4070 +#define BCMA_CHIP_ID_BCM6362 0x6362
4071 +#define BCMA_CHIP_ID_BCM4360 0x4360
4072 +#define BCMA_CHIP_ID_BCM4352 0x4352
4073 +
4074 +/* Chip IDs of SoCs */
4075 +#define BCMA_CHIP_ID_BCM4706 0x5300
4076 +#define BCMA_PKG_ID_BCM4706L 1
4077 +#define BCMA_CHIP_ID_BCM4716 0x4716
4078 +#define BCMA_PKG_ID_BCM4716 8
4079 +#define BCMA_PKG_ID_BCM4717 9
4080 +#define BCMA_PKG_ID_BCM4718 10
4081 +#define BCMA_CHIP_ID_BCM47162 47162
4082 +#define BCMA_CHIP_ID_BCM4748 0x4748
4083 +#define BCMA_CHIP_ID_BCM4749 0x4749
4084 +#define BCMA_CHIP_ID_BCM5356 0x5356
4085 +#define BCMA_CHIP_ID_BCM5357 0x5357
4086 +#define BCMA_PKG_ID_BCM5358 9
4087 +#define BCMA_PKG_ID_BCM47186 10
4088 +#define BCMA_PKG_ID_BCM5357 11
4089 +#define BCMA_CHIP_ID_BCM53572 53572
4090 +#define BCMA_PKG_ID_BCM47188 9
4091 +
4092 struct bcma_device {
4093 struct bcma_bus *bus;
4094 struct bcma_device_id id;
4095 @@ -136,8 +185,10 @@ struct bcma_device {
4096 bool dev_registered;
4097
4098 u8 core_index;
4099 + u8 core_unit;
4100
4101 u32 addr;
4102 + u32 addr1;
4103 u32 wrap;
4104
4105 void __iomem *io_addr;
4106 @@ -175,6 +226,12 @@ int __bcma_driver_register(struct bcma_d
4107
4108 extern void bcma_driver_unregister(struct bcma_driver *drv);
4109
4110 +/* Set a fallback SPROM.
4111 + * See kdoc at the function definition for complete documentation. */
4112 +extern int bcma_arch_register_fallback_sprom(
4113 + int (*sprom_callback)(struct bcma_bus *bus,
4114 + struct ssb_sprom *out));
4115 +
4116 struct bcma_bus {
4117 /* The MMIO area. */
4118 void __iomem *mmio;
4119 @@ -191,14 +248,18 @@ struct bcma_bus {
4120
4121 struct bcma_chipinfo chipinfo;
4122
4123 + struct bcma_boardinfo boardinfo;
4124 +
4125 struct bcma_device *mapped_core;
4126 struct list_head cores;
4127 u8 nr_cores;
4128 u8 init_done:1;
4129 + u8 num;
4130
4131 struct bcma_drv_cc drv_cc;
4132 - struct bcma_drv_pci drv_pci;
4133 + struct bcma_drv_pci drv_pci[2];
4134 struct bcma_drv_mips drv_mips;
4135 + struct bcma_drv_gmac_cmn drv_gmac_cmn;
4136
4137 /* We decided to share SPROM struct with SSB as long as we do not need
4138 * any hacks for BCMA. This simplifies drivers code. */
4139 @@ -282,6 +343,7 @@ static inline void bcma_maskset16(struct
4140 bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
4141 }
4142
4143 +extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
4144 extern bool bcma_core_is_enabled(struct bcma_device *core);
4145 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
4146 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
4147 @@ -289,6 +351,7 @@ extern void bcma_core_set_clockmode(stru
4148 enum bcma_clkmode clkmode);
4149 extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
4150 bool on);
4151 +extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
4152 #define BCMA_DMA_TRANSLATION_MASK 0xC0000000
4153 #define BCMA_DMA_TRANSLATION_NONE 0x00000000
4154 #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
4155 --- a/include/linux/bcma/bcma_driver_chipcommon.h
4156 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
4157 @@ -1,6 +1,9 @@
4158 #ifndef LINUX_BCMA_DRIVER_CC_H_
4159 #define LINUX_BCMA_DRIVER_CC_H_
4160
4161 +#include <linux/platform_device.h>
4162 +#include <linux/gpio.h>
4163 +
4164 /** ChipCommon core registers. **/
4165 #define BCMA_CC_ID 0x0000
4166 #define BCMA_CC_ID_ID 0x0000FFFF
4167 @@ -24,7 +27,7 @@
4168 #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
4169 #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
4170 #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
4171 -#define BCMA_CC_FLASHT_NFLASH 0x00000200
4172 +#define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */
4173 #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
4174 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
4175 #define BCMA_PLLTYPE_NONE 0x00000000
4176 @@ -45,6 +48,7 @@
4177 #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
4178 #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
4179 #define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
4180 +#define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */
4181 #define BCMA_CC_CORECTL 0x0008
4182 #define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
4183 #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
4184 @@ -56,6 +60,9 @@
4185 #define BCMA_CC_OTPS_HW_PROTECT 0x00000001
4186 #define BCMA_CC_OTPS_SW_PROTECT 0x00000002
4187 #define BCMA_CC_OTPS_CID_PROTECT 0x00000004
4188 +#define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */
4189 +#define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8
4190 +#define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */
4191 #define BCMA_CC_OTPC 0x0014 /* OTP control */
4192 #define BCMA_CC_OTPC_RECWAIT 0xFF000000
4193 #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
4194 @@ -72,6 +79,8 @@
4195 #define BCMA_CC_OTPP_READ 0x40000000
4196 #define BCMA_CC_OTPP_START 0x80000000
4197 #define BCMA_CC_OTPP_BUSY 0x80000000
4198 +#define BCMA_CC_OTPL 0x001C /* OTP layout */
4199 +#define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
4200 #define BCMA_CC_IRQSTAT 0x0020
4201 #define BCMA_CC_IRQMASK 0x0024
4202 #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
4203 @@ -79,6 +88,23 @@
4204 #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
4205 #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
4206 #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
4207 +#define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
4208 +#define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
4209 +#define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
4210 +#define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
4211 +#define BCMA_CC_CHIPST_43228_ILP_DIV_EN 0x00000001
4212 +#define BCMA_CC_CHIPST_43228_OTP_PRESENT 0x00000002
4213 +#define BCMA_CC_CHIPST_43228_SERDES_REFCLK_PADSEL 0x00000004
4214 +#define BCMA_CC_CHIPST_43228_SDIO_MODE 0x00000008
4215 +#define BCMA_CC_CHIPST_43228_SDIO_OTP_PRESENT 0x00000010
4216 +#define BCMA_CC_CHIPST_43228_SDIO_RESET 0x00000020
4217 +#define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
4218 +#define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
4219 +#define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
4220 +#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
4221 +#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
4222 +#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
4223 +#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
4224 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
4225 #define BCMA_CC_JCMD_START 0x80000000
4226 #define BCMA_CC_JCMD_BUSY 0x80000000
4227 @@ -108,10 +134,58 @@
4228 #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
4229 #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
4230 #define BCMA_CC_FLASHCTL 0x0040
4231 +/* Start/busy bit in flashcontrol */
4232 +#define BCMA_CC_FLASHCTL_OPCODE 0x000000ff
4233 +#define BCMA_CC_FLASHCTL_ACTION 0x00000700
4234 +#define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
4235 #define BCMA_CC_FLASHCTL_START 0x80000000
4236 #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
4237 +/* Flashcontrol action + opcodes for ST flashes */
4238 +#define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
4239 +#define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
4240 +#define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
4241 +#define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
4242 +#define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
4243 +#define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */
4244 +#define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */
4245 +#define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */
4246 +#define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
4247 +#define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */
4248 +#define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
4249 +#define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
4250 +/* Flashcontrol action + opcodes for Atmel flashes */
4251 +#define BCMA_CC_FLASHCTL_AT_READ 0x07e8
4252 +#define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2
4253 +#define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7
4254 +#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384
4255 +#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387
4256 +#define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283
4257 +#define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286
4258 +#define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288
4259 +#define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289
4260 +#define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281
4261 +#define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250
4262 +#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
4263 +#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
4264 +#define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253
4265 +#define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255
4266 +#define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260
4267 +#define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261
4268 +#define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
4269 +#define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
4270 #define BCMA_CC_FLASHADDR 0x0044
4271 #define BCMA_CC_FLASHDATA 0x0048
4272 +/* Status register bits for ST flashes */
4273 +#define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */
4274 +#define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */
4275 +#define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */
4276 +#define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2
4277 +#define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */
4278 +/* Status register bits for Atmel flashes */
4279 +#define BCMA_CC_FLASHDATA_AT_READY 0x80
4280 +#define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40
4281 +#define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38
4282 +#define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3
4283 #define BCMA_CC_BCAST_ADDR 0x0050
4284 #define BCMA_CC_BCAST_DATA 0x0054
4285 #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
4286 @@ -181,6 +255,45 @@
4287 #define BCMA_CC_FLASH_CFG 0x0128
4288 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
4289 #define BCMA_CC_FLASH_WAITCNT 0x012C
4290 +#define BCMA_CC_SROM_CONTROL 0x0190
4291 +#define BCMA_CC_SROM_CONTROL_START 0x80000000
4292 +#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
4293 +#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
4294 +#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
4295 +#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
4296 +#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
4297 +#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
4298 +#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
4299 +#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
4300 +#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
4301 +#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
4302 +#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
4303 +#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
4304 +#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
4305 +#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
4306 +/* Block 0x140 - 0x190 registers are chipset specific */
4307 +#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
4308 +#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
4309 +#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
4310 +#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
4311 +#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
4312 +#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
4313 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
4314 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
4315 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
4316 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
4317 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
4318 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
4319 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
4320 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
4321 +/* NAND flash registers for BCM4706 (corerev = 31) */
4322 +#define BCMA_CC_NFLASH_CTL 0x01A0
4323 +#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
4324 +#define BCMA_CC_NFLASH_CONF 0x01A4
4325 +#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
4326 +#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
4327 +#define BCMA_CC_NFLASH_DATA 0x01B0
4328 +#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
4329 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
4330 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
4331 #define BCMA_CC_UART0_DATA 0x0300
4332 @@ -203,6 +316,9 @@
4333 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
4334 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
4335 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
4336 +#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
4337 +#define BCMA_CC_PMU_CTL_RES_SHIFT 13
4338 +#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
4339 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
4340 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
4341 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
4342 @@ -240,7 +356,60 @@
4343 #define BCMA_CC_PLLCTL_ADDR 0x0660
4344 #define BCMA_CC_PLLCTL_DATA 0x0664
4345 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
4346 -#define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */
4347 +/* NAND flash MLC controller registers (corerev >= 38) */
4348 +#define BCMA_CC_NAND_REVISION 0x0C00
4349 +#define BCMA_CC_NAND_CMD_START 0x0C04
4350 +#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
4351 +#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
4352 +#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
4353 +#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
4354 +#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
4355 +#define BCMA_CC_NAND_SPARE_RD0 0x0C20
4356 +#define BCMA_CC_NAND_SPARE_RD4 0x0C24
4357 +#define BCMA_CC_NAND_SPARE_RD8 0x0C28
4358 +#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
4359 +#define BCMA_CC_NAND_SPARE_WR0 0x0C30
4360 +#define BCMA_CC_NAND_SPARE_WR4 0x0C34
4361 +#define BCMA_CC_NAND_SPARE_WR8 0x0C38
4362 +#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
4363 +#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
4364 +#define BCMA_CC_NAND_CONFIG 0x0C48
4365 +#define BCMA_CC_NAND_TIMING_1 0x0C50
4366 +#define BCMA_CC_NAND_TIMING_2 0x0C54
4367 +#define BCMA_CC_NAND_SEMAPHORE 0x0C58
4368 +#define BCMA_CC_NAND_DEVID 0x0C60
4369 +#define BCMA_CC_NAND_DEVID_X 0x0C64
4370 +#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
4371 +#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
4372 +#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
4373 +#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
4374 +#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
4375 +#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
4376 +#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
4377 +#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
4378 +#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
4379 +#define BCMA_CC_NAND_READ_ADDR 0x0C94
4380 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
4381 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
4382 +#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
4383 +#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
4384 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
4385 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
4386 +#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
4387 +#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
4388 +#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
4389 +#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
4390 +#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
4391 +#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
4392 +#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
4393 +#define BCMA_CC_NAND_SPARE_RD16 0x0D30
4394 +#define BCMA_CC_NAND_SPARE_RD20 0x0D34
4395 +#define BCMA_CC_NAND_SPARE_RD24 0x0D38
4396 +#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
4397 +#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
4398 +#define BCMA_CC_NAND_CACHE_DATA 0x0D44
4399 +#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
4400 +#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
4401
4402 /* Divider allocation in 4716/47162/5356 */
4403 #define BCMA_CC_PMU5_MAINPLL_CPU 1
4404 @@ -256,6 +425,15 @@
4405
4406 /* 4706 PMU */
4407 #define BCMA_CC_PMU4706_MAINPLL_PLL0 0
4408 +#define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */
4409 +#define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000
4410 +#define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16
4411 +#define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000
4412 +#define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12
4413 +#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8
4414 +#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3
4415 +#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
4416 +#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
4417
4418 /* ALP clock on pre-PMU chips */
4419 #define BCMA_CC_PMU_ALP_CLOCK 20000000
4420 @@ -284,6 +462,19 @@
4421 #define BCMA_CC_PPL_PCHI_OFF 5
4422 #define BCMA_CC_PPL_PCHI_MASK 0x0000003f
4423
4424 +#define BCMA_CC_PMU_PLL_CTL0 0
4425 +#define BCMA_CC_PMU_PLL_CTL1 1
4426 +#define BCMA_CC_PMU_PLL_CTL2 2
4427 +#define BCMA_CC_PMU_PLL_CTL3 3
4428 +#define BCMA_CC_PMU_PLL_CTL4 4
4429 +#define BCMA_CC_PMU_PLL_CTL5 5
4430 +
4431 +#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
4432 +#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20
4433 +
4434 +#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
4435 +#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
4436 +
4437 /* BCM4331 ChipControl numbers. */
4438 #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
4439 #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
4440 @@ -297,9 +488,25 @@
4441 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
4442 #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
4443 #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
4444 +#define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */
4445 #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
4446 #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
4447
4448 +/* 43224 chip-specific ChipControl register bits */
4449 +#define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
4450 +#define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
4451 +#define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
4452 +
4453 +/* 4313 Chip specific ChipControl register bits */
4454 +#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
4455 +
4456 +/* BCM5357 ChipControl register bits */
4457 +#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
4458 +#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
4459 +#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
4460 +#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
4461 +#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
4462 +
4463 /* Data for the PMU, if available.
4464 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
4465 */
4466 @@ -310,11 +517,35 @@ struct bcma_chipcommon_pmu {
4467
4468 #ifdef CONFIG_BCMA_DRIVER_MIPS
4469 struct bcma_pflash {
4470 + bool present;
4471 u8 buswidth;
4472 u32 window;
4473 u32 window_size;
4474 };
4475
4476 +#ifdef CONFIG_BCMA_SFLASH
4477 +struct bcma_sflash {
4478 + bool present;
4479 + u32 window;
4480 + u32 blocksize;
4481 + u16 numblocks;
4482 + u32 size;
4483 +
4484 + struct mtd_info *mtd;
4485 +};
4486 +#endif
4487 +
4488 +#ifdef CONFIG_BCMA_NFLASH
4489 +struct mtd_info;
4490 +
4491 +struct bcma_nflash {
4492 + bool present;
4493 + bool boot; /* This is the flash the SoC boots from */
4494 +
4495 + struct mtd_info *mtd;
4496 +};
4497 +#endif
4498 +
4499 struct bcma_serial_port {
4500 void *regs;
4501 unsigned long clockspeed;
4502 @@ -330,15 +561,30 @@ struct bcma_drv_cc {
4503 u32 capabilities;
4504 u32 capabilities_ext;
4505 u8 setup_done:1;
4506 + u8 early_setup_done:1;
4507 /* Fast Powerup Delay constant */
4508 u16 fast_pwrup_delay;
4509 struct bcma_chipcommon_pmu pmu;
4510 #ifdef CONFIG_BCMA_DRIVER_MIPS
4511 struct bcma_pflash pflash;
4512 +#ifdef CONFIG_BCMA_SFLASH
4513 + struct bcma_sflash sflash;
4514 +#endif
4515 +#ifdef CONFIG_BCMA_NFLASH
4516 + struct bcma_nflash nflash;
4517 +#endif
4518
4519 int nr_serial_ports;
4520 struct bcma_serial_port serial_ports[4];
4521 #endif /* CONFIG_BCMA_DRIVER_MIPS */
4522 + u32 ticks_per_ms;
4523 + struct platform_device *watchdog;
4524 +
4525 + /* Lock for GPIO register access. */
4526 + spinlock_t gpio_lock;
4527 +#ifdef CONFIG_BCMA_DRIVER_GPIO
4528 + struct gpio_chip gpio;
4529 +#endif
4530 };
4531
4532 /* Register access */
4533 @@ -355,14 +601,16 @@ struct bcma_drv_cc {
4534 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
4535
4536 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
4537 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
4538
4539 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
4540 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
4541
4542 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
4543
4544 -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
4545 - u32 ticks);
4546 +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
4547 +
4548 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
4549
4550 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
4551
4552 @@ -375,9 +623,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
4553 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
4554 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
4555 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
4556 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
4557 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
4558
4559 /* PMU support */
4560 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
4561 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
4562
4563 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
4564 u32 value);
4565 @@ -387,5 +638,6 @@ extern void bcma_chipco_chipctl_maskset(
4566 u32 offset, u32 mask, u32 set);
4567 extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
4568 u32 offset, u32 mask, u32 set);
4569 +extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
4570
4571 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
4572 --- /dev/null
4573 +++ b/include/linux/bcma/bcma_driver_gmac_cmn.h
4574 @@ -0,0 +1,100 @@
4575 +#ifndef LINUX_BCMA_DRIVER_GMAC_CMN_H_
4576 +#define LINUX_BCMA_DRIVER_GMAC_CMN_H_
4577 +
4578 +#include <linux/types.h>
4579 +
4580 +#define BCMA_GMAC_CMN_STAG0 0x000
4581 +#define BCMA_GMAC_CMN_STAG1 0x004
4582 +#define BCMA_GMAC_CMN_STAG2 0x008
4583 +#define BCMA_GMAC_CMN_STAG3 0x00C
4584 +#define BCMA_GMAC_CMN_PARSER_CTL 0x020
4585 +#define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
4586 +#define BCMA_GMAC_CMN_PHY_ACCESS 0x100
4587 +#define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
4588 +#define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
4589 +#define BCMA_GMAC_CMN_PA_ADDR_SHIFT 16
4590 +#define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
4591 +#define BCMA_GMAC_CMN_PA_REG_SHIFT 24
4592 +#define BCMA_GMAC_CMN_PA_WRITE 0x20000000
4593 +#define BCMA_GMAC_CMN_PA_START 0x40000000
4594 +#define BCMA_GMAC_CMN_PHY_CTL 0x104
4595 +#define BCMA_GMAC_CMN_PC_EPA_MASK 0x0000001f
4596 +#define BCMA_GMAC_CMN_PC_MCT_MASK 0x007f0000
4597 +#define BCMA_GMAC_CMN_PC_MCT_SHIFT 16
4598 +#define BCMA_GMAC_CMN_PC_MTE 0x00800000
4599 +#define BCMA_GMAC_CMN_GMAC0_RGMII_CTL 0x110
4600 +#define BCMA_GMAC_CMN_CFP_ACCESS 0x200
4601 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA0 0x210
4602 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA1 0x214
4603 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA2 0x218
4604 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA3 0x21C
4605 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA4 0x220
4606 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA5 0x224
4607 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA6 0x228
4608 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA7 0x22C
4609 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK0 0x230
4610 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK1 0x234
4611 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK2 0x238
4612 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK3 0x23C
4613 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK4 0x240
4614 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK5 0x244
4615 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK6 0x248
4616 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK7 0x24C
4617 +#define BCMA_GMAC_CMN_CFP_ACTION_DATA 0x250
4618 +#define BCMA_GMAC_CMN_TCAM_BIST_CTL 0x2A0
4619 +#define BCMA_GMAC_CMN_TCAM_BIST_STATUS 0x2A4
4620 +#define BCMA_GMAC_CMN_TCAM_CMP_STATUS 0x2A8
4621 +#define BCMA_GMAC_CMN_TCAM_DISABLE 0x2AC
4622 +#define BCMA_GMAC_CMN_TCAM_TEST_CTL 0x2F0
4623 +#define BCMA_GMAC_CMN_UDF_0_A3_A0 0x300
4624 +#define BCMA_GMAC_CMN_UDF_0_A7_A4 0x304
4625 +#define BCMA_GMAC_CMN_UDF_0_A8 0x308
4626 +#define BCMA_GMAC_CMN_UDF_1_A3_A0 0x310
4627 +#define BCMA_GMAC_CMN_UDF_1_A7_A4 0x314
4628 +#define BCMA_GMAC_CMN_UDF_1_A8 0x318
4629 +#define BCMA_GMAC_CMN_UDF_2_A3_A0 0x320
4630 +#define BCMA_GMAC_CMN_UDF_2_A7_A4 0x324
4631 +#define BCMA_GMAC_CMN_UDF_2_A8 0x328
4632 +#define BCMA_GMAC_CMN_UDF_0_B3_B0 0x330
4633 +#define BCMA_GMAC_CMN_UDF_0_B7_B4 0x334
4634 +#define BCMA_GMAC_CMN_UDF_0_B8 0x338
4635 +#define BCMA_GMAC_CMN_UDF_1_B3_B0 0x340
4636 +#define BCMA_GMAC_CMN_UDF_1_B7_B4 0x344
4637 +#define BCMA_GMAC_CMN_UDF_1_B8 0x348
4638 +#define BCMA_GMAC_CMN_UDF_2_B3_B0 0x350
4639 +#define BCMA_GMAC_CMN_UDF_2_B7_B4 0x354
4640 +#define BCMA_GMAC_CMN_UDF_2_B8 0x358
4641 +#define BCMA_GMAC_CMN_UDF_0_C3_C0 0x360
4642 +#define BCMA_GMAC_CMN_UDF_0_C7_C4 0x364
4643 +#define BCMA_GMAC_CMN_UDF_0_C8 0x368
4644 +#define BCMA_GMAC_CMN_UDF_1_C3_C0 0x370
4645 +#define BCMA_GMAC_CMN_UDF_1_C7_C4 0x374
4646 +#define BCMA_GMAC_CMN_UDF_1_C8 0x378
4647 +#define BCMA_GMAC_CMN_UDF_2_C3_C0 0x380
4648 +#define BCMA_GMAC_CMN_UDF_2_C7_C4 0x384
4649 +#define BCMA_GMAC_CMN_UDF_2_C8 0x388
4650 +#define BCMA_GMAC_CMN_UDF_0_D3_D0 0x390
4651 +#define BCMA_GMAC_CMN_UDF_0_D7_D4 0x394
4652 +#define BCMA_GMAC_CMN_UDF_0_D11_D8 0x394
4653 +
4654 +struct bcma_drv_gmac_cmn {
4655 + struct bcma_device *core;
4656 +
4657 + /* Drivers accessing BCMA_GMAC_CMN_PHY_ACCESS and
4658 + * BCMA_GMAC_CMN_PHY_CTL need to take that mutex first. */
4659 + struct mutex phy_mutex;
4660 +};
4661 +
4662 +/* Register access */
4663 +#define gmac_cmn_read16(gc, offset) bcma_read16((gc)->core, offset)
4664 +#define gmac_cmn_read32(gc, offset) bcma_read32((gc)->core, offset)
4665 +#define gmac_cmn_write16(gc, offset, val) bcma_write16((gc)->core, offset, val)
4666 +#define gmac_cmn_write32(gc, offset, val) bcma_write32((gc)->core, offset, val)
4667 +
4668 +#ifdef CONFIG_BCMA_DRIVER_GMAC_CMN
4669 +extern void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc);
4670 +#else
4671 +static inline void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) { }
4672 +#endif
4673 +
4674 +#endif /* LINUX_BCMA_DRIVER_GMAC_CMN_H_ */
4675 --- a/include/linux/bcma/bcma_driver_mips.h
4676 +++ b/include/linux/bcma/bcma_driver_mips.h
4677 @@ -35,13 +35,15 @@ struct bcma_device;
4678 struct bcma_drv_mips {
4679 struct bcma_device *core;
4680 u8 setup_done:1;
4681 - unsigned int assigned_irqs;
4682 + u8 early_setup_done:1;
4683 };
4684
4685 #ifdef CONFIG_BCMA_DRIVER_MIPS
4686 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
4687 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
4688 #else
4689 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
4690 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
4691 #endif
4692
4693 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
4694 --- a/include/linux/bcma/bcma_driver_pci.h
4695 +++ b/include/linux/bcma/bcma_driver_pci.h
4696 @@ -53,11 +53,47 @@ struct pci_dev;
4697 #define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
4698 #define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
4699 #define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
4700 +#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
4701 +#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
4702 +#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */
4703 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
4704 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2
4705 +#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
4706 +#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
4707 +#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */
4708 +#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */
4709 +#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */
4710 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
4711 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
4712 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
4713 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
4714 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
4715 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
4716 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
4717 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
4718 +#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */
4719 +#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */
4720 +#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */
4721 +#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
4722 +#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
4723 +#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
4724 +#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
4725 +#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
4726 +#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */
4727 +#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */
4728 +#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */
4729 #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
4730 #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
4731 #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
4732 #define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
4733 #define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
4734 +#define BCMA_CORE_PCI_SPROM_PI_OFFSET 0 /* first word */
4735 +#define BCMA_CORE_PCI_SPROM_PI_MASK 0xf000 /* bit 15:12 */
4736 +#define BCMA_CORE_PCI_SPROM_PI_SHIFT 12 /* bit 15:12 */
4737 +#define BCMA_CORE_PCI_SPROM_MISC_CONFIG 5 /* word 5 */
4738 +#define BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
4739 +#define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
4740 +#define BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800 /* bit 11 */
4741
4742 /* SBtoPCIx */
4743 #define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
4744 @@ -72,20 +108,118 @@ struct pci_dev;
4745 #define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
4746 #define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
4747
4748 +/* PCIE protocol PHY diagnostic registers */
4749 +#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */
4750 +#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */
4751 +#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */
4752 +#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
4753 +#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
4754 +#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
4755 +#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
4756 +#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */
4757 +#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */
4758 +#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */
4759 +#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
4760 +#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
4761 +#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */
4762 +#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
4763 +#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
4764 +#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
4765 +#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
4766 +
4767 +/* PCIE protocol DLLP diagnostic registers */
4768 +#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */
4769 +#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */
4770 +#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */
4771 +#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)
4772 +#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
4773 +#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
4774 +#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
4775 +#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
4776 +#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
4777 +#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */
4778 +#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
4779 +#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
4780 +#define BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */
4781 +#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
4782 +#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
4783 +#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
4784 +#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
4785 +#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
4786 +#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
4787 +#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */
4788 +#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
4789 +#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */
4790 +#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */
4791 +#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
4792 +
4793 +/* SERDES RX registers */
4794 +#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */
4795 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
4796 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
4797 +#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */
4798 +#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */
4799 +#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */
4800 +
4801 +/* SERDES PLL registers */
4802 +#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */
4803 +#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
4804 +
4805 /* PCIcore specific boardflags */
4806 #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
4807
4808 +/* PCIE Config space accessing MACROS */
4809 +#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */
4810 +#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */
4811 +#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */
4812 +#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */
4813 +
4814 +#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */
4815 +#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */
4816 +#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
4817 +#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
4818 +
4819 +/* PCIE Root Capability Register bits (Host mode only) */
4820 +#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
4821 +
4822 +struct bcma_drv_pci;
4823 +
4824 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
4825 +struct bcma_drv_pci_host {
4826 + struct bcma_drv_pci *pdev;
4827 +
4828 + u32 host_cfg_addr;
4829 + spinlock_t cfgspace_lock;
4830 +
4831 + struct pci_controller pci_controller;
4832 + struct pci_ops pci_ops;
4833 + struct resource mem_resource;
4834 + struct resource io_resource;
4835 +};
4836 +#endif
4837 +
4838 struct bcma_drv_pci {
4839 struct bcma_device *core;
4840 u8 setup_done:1;
4841 + u8 hostmode:1;
4842 +
4843 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
4844 + struct bcma_drv_pci_host *host_controller;
4845 +#endif
4846 };
4847
4848 /* Register access */
4849 +#define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)
4850 #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
4851 +#define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)
4852 #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
4853
4854 -extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
4855 +extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc);
4856 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
4857 struct bcma_device *core, bool enable);
4858 +extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
4859 +
4860 +extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
4861 +extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
4862
4863 #endif /* LINUX_BCMA_DRIVER_PCI_H_ */
4864 --- a/include/linux/bcma/bcma_regs.h
4865 +++ b/include/linux/bcma/bcma_regs.h
4866 @@ -11,11 +11,13 @@
4867 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
4868 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
4869 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
4870 +#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8
4871 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
4872 #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
4873 #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
4874 #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
4875 #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
4876 +#define BCMA_CLKCTLST_EXTRESST_SHIFT 24
4877 /* Is there any BCM4328 on BCMA bus? */
4878 #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
4879 #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
4880 @@ -35,6 +37,7 @@
4881 #define BCMA_IOST_BIST_DONE 0x8000
4882 #define BCMA_RESET_CTL 0x0800
4883 #define BCMA_RESET_CTL_RESET 0x0001
4884 +#define BCMA_RESET_ST 0x0804
4885
4886 /* BCMA PCI config space registers. */
4887 #define BCMA_PCI_PMCSR 0x44
4888 @@ -56,4 +59,36 @@
4889 #define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
4890 #define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
4891
4892 +/* SiliconBackplane Address Map.
4893 + * All regions may not exist on all chips.
4894 + */
4895 +#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */
4896 +#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
4897 +#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024)
4898 +#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
4899 +#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
4900 +#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */
4901 +
4902 +
4903 +#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
4904 +#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */
4905 +#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
4906 +#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2
4907 + * (2 ZettaBytes), low 32 bits
4908 + */
4909 +#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2
4910 + * (2 ZettaBytes), high 32 bits
4911 + */
4912 +
4913 +#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
4914 +#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
4915 +#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2
4916 + * (2 ZettaBytes), high 32 bits
4917 + */
4918 +
4919 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
4920 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
4921 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
4922 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
4923 +
4924 #endif /* LINUX_BCMA_REGS_H_ */
4925 --- a/drivers/net/wireless/b43/main.c
4926 +++ b/drivers/net/wireless/b43/main.c
4927 @@ -4618,7 +4618,7 @@ static int b43_wireless_core_init(struct
4928 switch (dev->dev->bus_type) {
4929 #ifdef CONFIG_B43_BCMA
4930 case B43_BUS_BCMA:
4931 - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4932 + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
4933 dev->dev->bdev, true);
4934 break;
4935 #endif
4936 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
4937 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
4938 @@ -533,7 +533,7 @@ ai_buscore_setup(struct si_info *sii, st
4939
4940 /* fixup necessary chip/core configurations */
4941 if (!sii->pch) {
4942 - sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci.core);
4943 + sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci[0].core);
4944 if (sii->pch == NULL)
4945 return false;
4946 }
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