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kernel: update bcma and ssb to master-2013-01-09 from wireless-testing
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.3 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -29,7 +29,7 @@ config BCMA_HOST_PCI
4
5 config BCMA_DRIVER_PCI_HOSTMODE
6 bool "Driver for PCI core working in hostmode"
7 - depends on BCMA && MIPS
8 + depends on BCMA && MIPS && BCMA_HOST_PCI
9 help
10 PCI core hostmode operation (external PCI bus).
11
12 @@ -46,6 +46,33 @@ config BCMA_DRIVER_MIPS
13
14 If unsure, say N
15
16 +config BCMA_SFLASH
17 + bool
18 + depends on BCMA_DRIVER_MIPS
19 + default y
20 +
21 +config BCMA_NFLASH
22 + bool
23 + depends on BCMA_DRIVER_MIPS
24 + default y
25 +
26 +config BCMA_DRIVER_GMAC_CMN
27 + bool "BCMA Broadcom GBIT MAC COMMON core driver"
28 + depends on BCMA
29 + help
30 + Driver for the Broadcom GBIT MAC COMMON core attached to Broadcom
31 + specific Advanced Microcontroller Bus.
32 +
33 + If unsure, say N
34 +
35 +config BCMA_DRIVER_GPIO
36 + bool "BCMA GPIO driver"
37 + depends on BCMA && GPIOLIB
38 + help
39 + Driver to provide access to the GPIO pins of the bcma bus.
40 +
41 + If unsure, say N
42 +
43 config BCMA_DEBUG
44 bool "BCMA debugging"
45 depends on BCMA
46 --- a/drivers/bcma/Makefile
47 +++ b/drivers/bcma/Makefile
48 @@ -1,8 +1,12 @@
49 bcma-y += main.o scan.o core.o sprom.o
50 bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
51 +bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
52 +bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
53 bcma-y += driver_pci.o
54 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
55 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
56 +bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
57 +bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o
58 bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
59 bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
60 obj-$(CONFIG_BCMA) += bcma.o
61 --- a/drivers/bcma/bcma_private.h
62 +++ b/drivers/bcma/bcma_private.h
63 @@ -10,10 +10,19 @@
64
65 #define BCMA_CORE_SIZE 0x1000
66
67 +#define bcma_err(bus, fmt, ...) \
68 + pr_err("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
69 +#define bcma_warn(bus, fmt, ...) \
70 + pr_warn("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
71 +#define bcma_info(bus, fmt, ...) \
72 + pr_info("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
73 +#define bcma_debug(bus, fmt, ...) \
74 + pr_debug("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
75 +
76 struct bcma_bus;
77
78 /* main.c */
79 -int bcma_bus_register(struct bcma_bus *bus);
80 +int __devinit bcma_bus_register(struct bcma_bus *bus);
81 void bcma_bus_unregister(struct bcma_bus *bus);
82 int __init bcma_bus_early_register(struct bcma_bus *bus,
83 struct bcma_device *core_cc,
84 @@ -22,6 +31,8 @@ int __init bcma_bus_early_register(struc
85 int bcma_bus_suspend(struct bcma_bus *bus);
86 int bcma_bus_resume(struct bcma_bus *bus);
87 #endif
88 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
89 + u8 unit);
90
91 /* scan.c */
92 int bcma_bus_scan(struct bcma_bus *bus);
93 @@ -39,8 +50,32 @@ void bcma_chipco_serial_init(struct bcma
94 #endif /* CONFIG_BCMA_DRIVER_MIPS */
95
96 /* driver_chipcommon_pmu.c */
97 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
98 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
99 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
100 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
101 +
102 +#ifdef CONFIG_BCMA_SFLASH
103 +/* driver_chipcommon_sflash.c */
104 +int bcma_sflash_init(struct bcma_drv_cc *cc);
105 +extern struct platform_device bcma_sflash_dev;
106 +#else
107 +static inline int bcma_sflash_init(struct bcma_drv_cc *cc)
108 +{
109 + bcma_err(cc->core->bus, "Serial flash not supported\n");
110 + return 0;
111 +}
112 +#endif /* CONFIG_BCMA_SFLASH */
113 +
114 +#ifdef CONFIG_BCMA_NFLASH
115 +/* driver_chipcommon_nflash.c */
116 +int bcma_nflash_init(struct bcma_drv_cc *cc);
117 +extern struct platform_device bcma_nflash_dev;
118 +#else
119 +static inline int bcma_nflash_init(struct bcma_drv_cc *cc)
120 +{
121 + bcma_err(cc->core->bus, "NAND flash not supported\n");
122 + return 0;
123 +}
124 +#endif /* CONFIG_BCMA_NFLASH */
125
126 #ifdef CONFIG_BCMA_HOST_PCI
127 /* host_pci.c */
128 @@ -48,8 +83,24 @@ extern int __init bcma_host_pci_init(voi
129 extern void __exit bcma_host_pci_exit(void);
130 #endif /* CONFIG_BCMA_HOST_PCI */
131
132 +/* driver_pci.c */
133 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
134 +
135 +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
136 +
137 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
138 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
139 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
140 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
141 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
142
143 +#ifdef CONFIG_BCMA_DRIVER_GPIO
144 +/* driver_gpio.c */
145 +int bcma_gpio_init(struct bcma_drv_cc *cc);
146 +#else
147 +static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
148 +{
149 + return -ENOTSUPP;
150 +}
151 +#endif /* CONFIG_BCMA_DRIVER_GPIO */
152 +
153 #endif
154 --- a/drivers/bcma/core.c
155 +++ b/drivers/bcma/core.c
156 @@ -30,6 +30,7 @@ void bcma_core_disable(struct bcma_devic
157 udelay(10);
158
159 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
160 + bcma_aread32(core, BCMA_RESET_CTL);
161 udelay(1);
162 }
163 EXPORT_SYMBOL_GPL(bcma_core_disable);
164 @@ -64,7 +65,7 @@ void bcma_core_set_clockmode(struct bcma
165 switch (clkmode) {
166 case BCMA_CLKMODE_FAST:
167 bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
168 - udelay(64);
169 + usleep_range(64, 300);
170 for (i = 0; i < 1500; i++) {
171 if (bcma_read32(core, BCMA_CLKCTLST) &
172 BCMA_CLKCTLST_HAVEHT) {
173 @@ -74,10 +75,10 @@ void bcma_core_set_clockmode(struct bcma
174 udelay(10);
175 }
176 if (i)
177 - pr_err("HT force timeout\n");
178 + bcma_err(core->bus, "HT force timeout\n");
179 break;
180 case BCMA_CLKMODE_DYNAMIC:
181 - pr_warn("Dynamic clockmode not supported yet!\n");
182 + bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT);
183 break;
184 }
185 }
186 @@ -101,9 +102,9 @@ void bcma_core_pll_ctl(struct bcma_devic
187 udelay(10);
188 }
189 if (i)
190 - pr_err("PLL enable timeout\n");
191 + bcma_err(core->bus, "PLL enable timeout\n");
192 } else {
193 - pr_warn("Disabling PLL not supported yet!\n");
194 + bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
195 }
196 }
197 EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
198 @@ -119,8 +120,8 @@ u32 bcma_core_dma_translation(struct bcm
199 else
200 return BCMA_DMA_TRANSLATION_DMA32_CMT;
201 default:
202 - pr_err("DMA translation unknown for host %d\n",
203 - core->bus->hosttype);
204 + bcma_err(core->bus, "DMA translation unknown for host %d\n",
205 + core->bus->hosttype);
206 }
207 return BCMA_DMA_TRANSLATION_NONE;
208 }
209 --- a/drivers/bcma/driver_chipcommon.c
210 +++ b/drivers/bcma/driver_chipcommon.c
211 @@ -4,12 +4,15 @@
212 *
213 * Copyright 2005, Broadcom Corporation
214 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
215 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
216 *
217 * Licensed under the GNU/GPL. See COPYING for details.
218 */
219
220 #include "bcma_private.h"
221 +#include <linux/bcm47xx_wdt.h>
222 #include <linux/export.h>
223 +#include <linux/platform_device.h>
224 #include <linux/bcma/bcma.h>
225
226 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
227 @@ -22,20 +25,119 @@ static inline u32 bcma_cc_write32_masked
228 return value;
229 }
230
231 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
232 +static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
233 {
234 - u32 leddc_on = 10;
235 - u32 leddc_off = 90;
236 + if (cc->capabilities & BCMA_CC_CAP_PMU)
237 + return bcma_pmu_get_alp_clock(cc);
238
239 - if (cc->setup_done)
240 + return 20000000;
241 +}
242 +
243 +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
244 +{
245 + struct bcma_bus *bus = cc->core->bus;
246 + u32 nb;
247 +
248 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
249 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
250 + nb = 32;
251 + else if (cc->core->id.rev < 26)
252 + nb = 16;
253 + else
254 + nb = (cc->core->id.rev >= 37) ? 32 : 24;
255 + } else {
256 + nb = 28;
257 + }
258 + if (nb == 32)
259 + return 0xffffffff;
260 + else
261 + return (1 << nb) - 1;
262 +}
263 +
264 +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
265 + u32 ticks)
266 +{
267 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
268 +
269 + return bcma_chipco_watchdog_timer_set(cc, ticks);
270 +}
271 +
272 +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
273 + u32 ms)
274 +{
275 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
276 + u32 ticks;
277 +
278 + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
279 + return ticks / cc->ticks_per_ms;
280 +}
281 +
282 +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
283 +{
284 + struct bcma_bus *bus = cc->core->bus;
285 +
286 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
287 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
288 + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
289 + return bcma_chipco_get_alp_clock(cc) / 4000;
290 + else
291 + /* based on 32KHz ILP clock */
292 + return 32;
293 + } else {
294 + return bcma_chipco_get_alp_clock(cc) / 1000;
295 + }
296 +}
297 +
298 +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
299 +{
300 + struct bcm47xx_wdt wdt = {};
301 + struct platform_device *pdev;
302 +
303 + wdt.driver_data = cc;
304 + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
305 + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
306 + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
307 +
308 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
309 + cc->core->bus->num, &wdt,
310 + sizeof(wdt));
311 + if (IS_ERR(pdev))
312 + return PTR_ERR(pdev);
313 +
314 + cc->watchdog = pdev;
315 +
316 + return 0;
317 +}
318 +
319 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
320 +{
321 + if (cc->early_setup_done)
322 return;
323
324 + spin_lock_init(&cc->gpio_lock);
325 +
326 if (cc->core->id.rev >= 11)
327 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
328 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
329 if (cc->core->id.rev >= 35)
330 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
331
332 + if (cc->capabilities & BCMA_CC_CAP_PMU)
333 + bcma_pmu_early_init(cc);
334 +
335 + cc->early_setup_done = true;
336 +}
337 +
338 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
339 +{
340 + u32 leddc_on = 10;
341 + u32 leddc_off = 90;
342 +
343 + if (cc->setup_done)
344 + return;
345 +
346 + bcma_core_chipcommon_early_init(cc);
347 +
348 if (cc->core->id.rev >= 20) {
349 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
350 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
351 @@ -44,7 +146,7 @@ void bcma_core_chipcommon_init(struct bc
352 if (cc->capabilities & BCMA_CC_CAP_PMU)
353 bcma_pmu_init(cc);
354 if (cc->capabilities & BCMA_CC_CAP_PCTL)
355 - pr_err("Power control not implemented!\n");
356 + bcma_err(cc->core->bus, "Power control not implemented!\n");
357
358 if (cc->core->id.rev >= 16) {
359 if (cc->core->bus->sprom.leddc_on_time &&
360 @@ -56,15 +158,33 @@ void bcma_core_chipcommon_init(struct bc
361 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
362 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
363 }
364 + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
365
366 cc->setup_done = true;
367 }
368
369 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
370 -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
371 +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
372 {
373 - /* instant NMI */
374 - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
375 + u32 maxt;
376 + enum bcma_clkmode clkmode;
377 +
378 + maxt = bcma_chipco_watchdog_get_max_timer(cc);
379 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
380 + if (ticks == 1)
381 + ticks = 2;
382 + else if (ticks > maxt)
383 + ticks = maxt;
384 + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
385 + } else {
386 + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
387 + bcma_core_set_clockmode(cc->core, clkmode);
388 + if (ticks > maxt)
389 + ticks = maxt;
390 + /* instant NMI */
391 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
392 + }
393 + return ticks;
394 }
395
396 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
397 @@ -84,28 +204,97 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
398
399 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
400 {
401 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
402 + unsigned long flags;
403 + u32 res;
404 +
405 + spin_lock_irqsave(&cc->gpio_lock, flags);
406 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
407 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
408 +
409 + return res;
410 }
411
412 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
413 {
414 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
415 + unsigned long flags;
416 + u32 res;
417 +
418 + spin_lock_irqsave(&cc->gpio_lock, flags);
419 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
420 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
421 +
422 + return res;
423 }
424
425 +/*
426 + * If the bit is set to 0, chipcommon controlls this GPIO,
427 + * if the bit is set to 1, it is used by some part of the chip and not our code.
428 + */
429 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
430 {
431 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
432 + unsigned long flags;
433 + u32 res;
434 +
435 + spin_lock_irqsave(&cc->gpio_lock, flags);
436 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
437 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
438 +
439 + return res;
440 }
441 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
442
443 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
444 {
445 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
446 + unsigned long flags;
447 + u32 res;
448 +
449 + spin_lock_irqsave(&cc->gpio_lock, flags);
450 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
451 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
452 +
453 + return res;
454 }
455
456 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
457 {
458 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
459 + unsigned long flags;
460 + u32 res;
461 +
462 + spin_lock_irqsave(&cc->gpio_lock, flags);
463 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
464 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
465 +
466 + return res;
467 +}
468 +
469 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
470 +{
471 + unsigned long flags;
472 + u32 res;
473 +
474 + if (cc->core->id.rev < 20)
475 + return 0;
476 +
477 + spin_lock_irqsave(&cc->gpio_lock, flags);
478 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
479 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
480 +
481 + return res;
482 +}
483 +
484 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
485 +{
486 + unsigned long flags;
487 + u32 res;
488 +
489 + if (cc->core->id.rev < 20)
490 + return 0;
491 +
492 + spin_lock_irqsave(&cc->gpio_lock, flags);
493 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
494 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
495 +
496 + return res;
497 }
498
499 #ifdef CONFIG_BCMA_DRIVER_MIPS
500 @@ -118,8 +307,7 @@ void bcma_chipco_serial_init(struct bcma
501 struct bcma_serial_port *ports = cc->serial_ports;
502
503 if (ccrev >= 11 && ccrev != 15) {
504 - /* Fixed ALP clock */
505 - baud_base = bcma_pmu_alp_clock(cc);
506 + baud_base = bcma_chipco_get_alp_clock(cc);
507 if (ccrev >= 21) {
508 /* Turn off UART clock before switching clocksource. */
509 bcma_cc_write32(cc, BCMA_CC_CORECTL,
510 @@ -137,8 +325,7 @@ void bcma_chipco_serial_init(struct bcma
511 | BCMA_CC_CORECTL_UARTCLKEN);
512 }
513 } else {
514 - pr_err("serial not supported on this device ccrev: 0x%x\n",
515 - ccrev);
516 + bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
517 return;
518 }
519
520 --- /dev/null
521 +++ b/drivers/bcma/driver_chipcommon_nflash.c
522 @@ -0,0 +1,44 @@
523 +/*
524 + * Broadcom specific AMBA
525 + * ChipCommon NAND flash interface
526 + *
527 + * Licensed under the GNU/GPL. See COPYING for details.
528 + */
529 +
530 +#include <linux/platform_device.h>
531 +#include <linux/bcma/bcma.h>
532 +
533 +#include "bcma_private.h"
534 +
535 +struct platform_device bcma_nflash_dev = {
536 + .name = "bcma_nflash",
537 + .num_resources = 0,
538 +};
539 +
540 +/* Initialize NAND flash access */
541 +int bcma_nflash_init(struct bcma_drv_cc *cc)
542 +{
543 + struct bcma_bus *bus = cc->core->bus;
544 +
545 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
546 + cc->core->id.rev != 0x38) {
547 + bcma_err(bus, "NAND flash on unsupported board!\n");
548 + return -ENOTSUPP;
549 + }
550 +
551 + if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) {
552 + bcma_err(bus, "NAND flash not present according to ChipCommon\n");
553 + return -ENODEV;
554 + }
555 +
556 + cc->nflash.present = true;
557 + if (cc->core->id.rev == 38 &&
558 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
559 + cc->nflash.boot = true;
560 +
561 + /* Prepare platform device, but don't register it yet. It's too early,
562 + * malloc (required by device_private_init) is not available yet. */
563 + bcma_nflash_dev.dev.platform_data = &cc->nflash;
564 +
565 + return 0;
566 +}
567 --- a/drivers/bcma/driver_chipcommon_pmu.c
568 +++ b/drivers/bcma/driver_chipcommon_pmu.c
569 @@ -3,7 +3,8 @@
570 * ChipCommon Power Management Unit driver
571 *
572 * Copyright 2009, Michael Buesch <m@bues.ch>
573 - * Copyright 2007, Broadcom Corporation
574 + * Copyright 2007, 2011, Broadcom Corporation
575 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
576 *
577 * Licensed under the GNU/GPL. See COPYING for details.
578 */
579 @@ -12,12 +13,13 @@
580 #include <linux/export.h>
581 #include <linux/bcma/bcma.h>
582
583 -static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
584 +u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
585 {
586 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
587 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
588 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
589 }
590 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
591
592 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
593 {
594 @@ -54,38 +56,19 @@ void bcma_chipco_regctl_maskset(struct b
595 }
596 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
597
598 -static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
599 -{
600 - struct bcma_bus *bus = cc->core->bus;
601 -
602 - switch (bus->chipinfo.id) {
603 - case 0x4313:
604 - case 0x4331:
605 - case 43224:
606 - case 43225:
607 - break;
608 - default:
609 - pr_err("PLL init unknown for device 0x%04X\n",
610 - bus->chipinfo.id);
611 - }
612 -}
613 -
614 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
615 {
616 struct bcma_bus *bus = cc->core->bus;
617 u32 min_msk = 0, max_msk = 0;
618
619 switch (bus->chipinfo.id) {
620 - case 0x4313:
621 + case BCMA_CHIP_ID_BCM4313:
622 min_msk = 0x200D;
623 max_msk = 0xFFFF;
624 break;
625 - case 43224:
626 - case 43225:
627 - break;
628 default:
629 - pr_err("PMU resource config unknown for device 0x%04X\n",
630 - bus->chipinfo.id);
631 + bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
632 + bus->chipinfo.id);
633 }
634
635 /* Set the resource masks. */
636 @@ -93,22 +76,12 @@ static void bcma_pmu_resources_init(stru
637 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
638 if (max_msk)
639 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
640 -}
641 -
642 -void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
643 -{
644 - struct bcma_bus *bus = cc->core->bus;
645
646 - switch (bus->chipinfo.id) {
647 - case 0x4313:
648 - case 0x4331:
649 - case 43224:
650 - case 43225:
651 - break;
652 - default:
653 - pr_err("PMU switch/regulators init unknown for device "
654 - "0x%04X\n", bus->chipinfo.id);
655 - }
656 + /*
657 + * Add some delay; allow resources to come up and settle.
658 + * Delay is required for SoC (early init).
659 + */
660 + mdelay(2);
661 }
662
663 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
664 @@ -122,51 +95,69 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
665 val |= BCMA_CHIPCTL_4331_EXTPA_EN;
666 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
667 val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
668 + else if (bus->chipinfo.rev > 0)
669 + val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
670 } else {
671 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
672 + val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
673 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
674 }
675 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
676 }
677
678 -void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
679 +static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
680 {
681 struct bcma_bus *bus = cc->core->bus;
682
683 switch (bus->chipinfo.id) {
684 - case 0x4313:
685 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
686 + case BCMA_CHIP_ID_BCM4313:
687 + /* enable 12 mA drive strenth for 4313 and set chipControl
688 + register bit 1 */
689 + bcma_chipco_chipctl_maskset(cc, 0,
690 + ~BCMA_CCTRL_4313_12MA_LED_DRIVE,
691 + BCMA_CCTRL_4313_12MA_LED_DRIVE);
692 break;
693 - case 0x4331:
694 - /* BCM4331 workaround is SPROM-related, we put it in sprom.c */
695 + case BCMA_CHIP_ID_BCM4331:
696 + case BCMA_CHIP_ID_BCM43431:
697 + /* Ext PA lines must be enabled for tx on BCM4331 */
698 + bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
699 break;
700 - case 43224:
701 + case BCMA_CHIP_ID_BCM43224:
702 + case BCMA_CHIP_ID_BCM43421:
703 + /* enable 12 mA drive strenth for 43224 and set chipControl
704 + register bit 15 */
705 if (bus->chipinfo.rev == 0) {
706 - pr_err("Workarounds for 43224 rev 0 not fully "
707 - "implemented\n");
708 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
709 + bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
710 + ~BCMA_CCTRL_43224_GPIO_TOGGLE,
711 + BCMA_CCTRL_43224_GPIO_TOGGLE);
712 + bcma_chipco_chipctl_maskset(cc, 0,
713 + ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
714 + BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
715 } else {
716 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
717 + bcma_chipco_chipctl_maskset(cc, 0,
718 + ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
719 + BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
720 }
721 break;
722 - case 43225:
723 - break;
724 default:
725 - pr_err("Workarounds unknown for device 0x%04X\n",
726 - bus->chipinfo.id);
727 + bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
728 + bus->chipinfo.id);
729 }
730 }
731
732 -void bcma_pmu_init(struct bcma_drv_cc *cc)
733 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
734 {
735 u32 pmucap;
736
737 pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
738 cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
739
740 - pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
741 - pmucap);
742 + bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
743 + cc->pmu.rev, pmucap);
744 +}
745
746 +void bcma_pmu_init(struct bcma_drv_cc *cc)
747 +{
748 if (cc->pmu.rev == 1)
749 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
750 ~BCMA_CC_PMU_CTL_NOILPONW);
751 @@ -174,37 +165,31 @@ void bcma_pmu_init(struct bcma_drv_cc *c
752 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
753 BCMA_CC_PMU_CTL_NOILPONW);
754
755 - if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
756 - pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
757 -
758 - bcma_pmu_pll_init(cc);
759 bcma_pmu_resources_init(cc);
760 - bcma_pmu_swreg_init(cc);
761 bcma_pmu_workarounds(cc);
762 }
763
764 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
765 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
766 {
767 struct bcma_bus *bus = cc->core->bus;
768
769 switch (bus->chipinfo.id) {
770 - case 0x4716:
771 - case 0x4748:
772 - case 47162:
773 - case 0x4313:
774 - case 0x5357:
775 - case 0x4749:
776 - case 53572:
777 + case BCMA_CHIP_ID_BCM4716:
778 + case BCMA_CHIP_ID_BCM4748:
779 + case BCMA_CHIP_ID_BCM47162:
780 + case BCMA_CHIP_ID_BCM4313:
781 + case BCMA_CHIP_ID_BCM5357:
782 + case BCMA_CHIP_ID_BCM4749:
783 + case BCMA_CHIP_ID_BCM53572:
784 /* always 20Mhz */
785 return 20000 * 1000;
786 - case 0x5356:
787 - case 0x5300:
788 + case BCMA_CHIP_ID_BCM5356:
789 + case BCMA_CHIP_ID_BCM4706:
790 /* always 25Mhz */
791 return 25000 * 1000;
792 default:
793 - pr_warn("No ALP clock specified for %04X device, "
794 - "pmu rev. %d, using default %d Hz\n",
795 - bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
796 + bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
797 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
798 }
799 return BCMA_CC_PMU_ALP_CLOCK;
800 }
801 @@ -212,7 +197,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
802 /* Find the output of the "m" pll divider given pll controls that start with
803 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
804 */
805 -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
806 +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
807 {
808 u32 tmp, div, ndiv, p1, p2, fc;
809 struct bcma_bus *bus = cc->core->bus;
810 @@ -221,7 +206,8 @@ static u32 bcma_pmu_clock(struct bcma_dr
811
812 BUG_ON(!m || m > 4);
813
814 - if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
815 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
816 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
817 /* Detect failure in clock setting */
818 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
819 if (tmp & 0x40000)
820 @@ -240,60 +226,95 @@ static u32 bcma_pmu_clock(struct bcma_dr
821 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
822
823 /* Do calculation in Mhz */
824 - fc = bcma_pmu_alp_clock(cc) / 1000000;
825 + fc = bcma_pmu_get_alp_clock(cc) / 1000000;
826 fc = (p1 * ndiv * fc) / p2;
827
828 /* Return clock in Hertz */
829 return (fc / div) * 1000000;
830 }
831
832 +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
833 +{
834 + u32 tmp, ndiv, p1div, p2div;
835 + u32 clock;
836 +
837 + BUG_ON(!m || m > 4);
838 +
839 + /* Get N, P1 and P2 dividers to determine CPU clock */
840 + tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
841 + ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
842 + >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
843 + p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
844 + >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
845 + p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
846 + >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
847 +
848 + tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
849 + if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
850 + /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
851 + clock = (25000000 / 4) * ndiv * p2div / p1div;
852 + else
853 + /* Fixed reference clock 25MHz and m = 2 */
854 + clock = (25000000 / 2) * ndiv * p2div / p1div;
855 +
856 + if (m == BCMA_CC_PMU5_MAINPLL_SSB)
857 + clock = clock / 4;
858 +
859 + return clock;
860 +}
861 +
862 /* query bus clock frequency for PMU-enabled chipcommon */
863 -u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
864 +static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
865 {
866 struct bcma_bus *bus = cc->core->bus;
867
868 switch (bus->chipinfo.id) {
869 - case 0x4716:
870 - case 0x4748:
871 - case 47162:
872 - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
873 - BCMA_CC_PMU5_MAINPLL_SSB);
874 - case 0x5356:
875 - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
876 - BCMA_CC_PMU5_MAINPLL_SSB);
877 - case 0x5357:
878 - case 0x4749:
879 - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
880 - BCMA_CC_PMU5_MAINPLL_SSB);
881 - case 0x5300:
882 - return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
883 - BCMA_CC_PMU5_MAINPLL_SSB);
884 - case 53572:
885 + case BCMA_CHIP_ID_BCM4716:
886 + case BCMA_CHIP_ID_BCM4748:
887 + case BCMA_CHIP_ID_BCM47162:
888 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
889 + BCMA_CC_PMU5_MAINPLL_SSB);
890 + case BCMA_CHIP_ID_BCM5356:
891 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
892 + BCMA_CC_PMU5_MAINPLL_SSB);
893 + case BCMA_CHIP_ID_BCM5357:
894 + case BCMA_CHIP_ID_BCM4749:
895 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
896 + BCMA_CC_PMU5_MAINPLL_SSB);
897 + case BCMA_CHIP_ID_BCM4706:
898 + return bcma_pmu_pll_clock_bcm4706(cc,
899 + BCMA_CC_PMU4706_MAINPLL_PLL0,
900 + BCMA_CC_PMU5_MAINPLL_SSB);
901 + case BCMA_CHIP_ID_BCM53572:
902 return 75000000;
903 default:
904 - pr_warn("No backplane clock specified for %04X device, "
905 - "pmu rev. %d, using default %d Hz\n",
906 - bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
907 + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
908 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
909 }
910 return BCMA_CC_PMU_HT_CLOCK;
911 }
912
913 /* query cpu clock frequency for PMU-enabled chipcommon */
914 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
915 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
916 {
917 struct bcma_bus *bus = cc->core->bus;
918
919 - if (bus->chipinfo.id == 53572)
920 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
921 return 300000000;
922
923 + /* New PMUs can have different clock for bus and CPU */
924 if (cc->pmu.rev >= 5) {
925 u32 pll;
926 switch (bus->chipinfo.id) {
927 - case 0x5356:
928 + case BCMA_CHIP_ID_BCM4706:
929 + return bcma_pmu_pll_clock_bcm4706(cc,
930 + BCMA_CC_PMU4706_MAINPLL_PLL0,
931 + BCMA_CC_PMU5_MAINPLL_CPU);
932 + case BCMA_CHIP_ID_BCM5356:
933 pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
934 break;
935 - case 0x5357:
936 - case 0x4749:
937 + case BCMA_CHIP_ID_BCM5357:
938 + case BCMA_CHIP_ID_BCM4749:
939 pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
940 break;
941 default:
942 @@ -301,10 +322,189 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
943 break;
944 }
945
946 - /* TODO: if (bus->chipinfo.id == 0x5300)
947 - return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
948 - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
949 + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
950 + }
951 +
952 + /* On old PMUs CPU has the same clock as the bus */
953 + return bcma_pmu_get_bus_clock(cc);
954 +}
955 +
956 +static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
957 + u32 value)
958 +{
959 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
960 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
961 +}
962 +
963 +void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
964 +{
965 + u32 tmp = 0;
966 + u8 phypll_offset = 0;
967 + u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
968 + u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
969 + struct bcma_bus *bus = cc->core->bus;
970 +
971 + switch (bus->chipinfo.id) {
972 + case BCMA_CHIP_ID_BCM5357:
973 + case BCMA_CHIP_ID_BCM4749:
974 + case BCMA_CHIP_ID_BCM53572:
975 + /* 5357[ab]0, 43236[ab]0, and 6362b0 */
976 +
977 + /* BCM5357 needs to touch PLL1_PLLCTL[02],
978 + so offset PLL0_PLLCTL[02] by 6 */
979 + phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
980 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
981 + bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
982 +
983 + /* RMW only the P1 divider */
984 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
985 + BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
986 + tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
987 + tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
988 + tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
989 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
990 +
991 + /* RMW only the int feedback divider */
992 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
993 + BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
994 + tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
995 + tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
996 + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
997 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
998 +
999 + tmp = 1 << 10;
1000 + break;
1001 +
1002 + case BCMA_CHIP_ID_BCM4331:
1003 + case BCMA_CHIP_ID_BCM43431:
1004 + if (spuravoid == 2) {
1005 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1006 + 0x11500014);
1007 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1008 + 0x0FC00a08);
1009 + } else if (spuravoid == 1) {
1010 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1011 + 0x11500014);
1012 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1013 + 0x0F600a08);
1014 + } else {
1015 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1016 + 0x11100014);
1017 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1018 + 0x03000a08);
1019 + }
1020 + tmp = 1 << 10;
1021 + break;
1022 +
1023 + case BCMA_CHIP_ID_BCM43224:
1024 + case BCMA_CHIP_ID_BCM43225:
1025 + case BCMA_CHIP_ID_BCM43421:
1026 + if (spuravoid == 1) {
1027 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1028 + 0x11500010);
1029 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1030 + 0x000C0C06);
1031 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1032 + 0x0F600a08);
1033 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1034 + 0x00000000);
1035 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1036 + 0x2001E920);
1037 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1038 + 0x88888815);
1039 + } else {
1040 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1041 + 0x11100010);
1042 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1043 + 0x000c0c06);
1044 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1045 + 0x03000a08);
1046 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1047 + 0x00000000);
1048 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1049 + 0x200005c0);
1050 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1051 + 0x88888815);
1052 + }
1053 + tmp = 1 << 10;
1054 + break;
1055 +
1056 + case BCMA_CHIP_ID_BCM4716:
1057 + case BCMA_CHIP_ID_BCM4748:
1058 + case BCMA_CHIP_ID_BCM47162:
1059 + if (spuravoid == 1) {
1060 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1061 + 0x11500060);
1062 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1063 + 0x080C0C06);
1064 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1065 + 0x0F600000);
1066 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1067 + 0x00000000);
1068 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1069 + 0x2001E924);
1070 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1071 + 0x88888815);
1072 + } else {
1073 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1074 + 0x11100060);
1075 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1076 + 0x080c0c06);
1077 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1078 + 0x03000000);
1079 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1080 + 0x00000000);
1081 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1082 + 0x200005c0);
1083 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1084 + 0x88888815);
1085 + }
1086 +
1087 + tmp = 3 << 9;
1088 + break;
1089 +
1090 + case BCMA_CHIP_ID_BCM43227:
1091 + case BCMA_CHIP_ID_BCM43228:
1092 + case BCMA_CHIP_ID_BCM43428:
1093 + /* LCNXN */
1094 + /* PLL Settings for spur avoidance on/off mode,
1095 + no on2 support for 43228A0 */
1096 + if (spuravoid == 1) {
1097 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1098 + 0x01100014);
1099 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1100 + 0x040C0C06);
1101 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1102 + 0x03140A08);
1103 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1104 + 0x00333333);
1105 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1106 + 0x202C2820);
1107 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1108 + 0x88888815);
1109 + } else {
1110 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
1111 + 0x11100014);
1112 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
1113 + 0x040c0c06);
1114 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
1115 + 0x03000a08);
1116 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
1117 + 0x00000000);
1118 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
1119 + 0x200005c0);
1120 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
1121 + 0x88888815);
1122 + }
1123 + tmp = 1 << 10;
1124 + break;
1125 + default:
1126 + bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
1127 + bus->chipinfo.id);
1128 + break;
1129 }
1130
1131 - return bcma_pmu_get_clockcontrol(cc);
1132 + tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
1133 + bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
1134 }
1135 +EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
1136 --- /dev/null
1137 +++ b/drivers/bcma/driver_chipcommon_sflash.c
1138 @@ -0,0 +1,165 @@
1139 +/*
1140 + * Broadcom specific AMBA
1141 + * ChipCommon serial flash interface
1142 + *
1143 + * Licensed under the GNU/GPL. See COPYING for details.
1144 + */
1145 +
1146 +#include <linux/platform_device.h>
1147 +#include <linux/bcma/bcma.h>
1148 +
1149 +#include "bcma_private.h"
1150 +
1151 +static struct resource bcma_sflash_resource = {
1152 + .name = "bcma_sflash",
1153 + .start = BCMA_SOC_FLASH2,
1154 + .end = 0,
1155 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
1156 +};
1157 +
1158 +struct platform_device bcma_sflash_dev = {
1159 + .name = "bcma_sflash",
1160 + .resource = &bcma_sflash_resource,
1161 + .num_resources = 1,
1162 +};
1163 +
1164 +struct bcma_sflash_tbl_e {
1165 + char *name;
1166 + u32 id;
1167 + u32 blocksize;
1168 + u16 numblocks;
1169 +};
1170 +
1171 +static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
1172 + { "M25P20", 0x11, 0x10000, 4, },
1173 + { "M25P40", 0x12, 0x10000, 8, },
1174 +
1175 + { "M25P16", 0x14, 0x10000, 32, },
1176 + { "M25P32", 0x15, 0x10000, 64, },
1177 + { "M25P64", 0x16, 0x10000, 128, },
1178 + { "M25FL128", 0x17, 0x10000, 256, },
1179 + { 0 },
1180 +};
1181 +
1182 +static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
1183 + { "SST25WF512", 1, 0x1000, 16, },
1184 + { "SST25VF512", 0x48, 0x1000, 16, },
1185 + { "SST25WF010", 2, 0x1000, 32, },
1186 + { "SST25VF010", 0x49, 0x1000, 32, },
1187 + { "SST25WF020", 3, 0x1000, 64, },
1188 + { "SST25VF020", 0x43, 0x1000, 64, },
1189 + { "SST25WF040", 4, 0x1000, 128, },
1190 + { "SST25VF040", 0x44, 0x1000, 128, },
1191 + { "SST25VF040B", 0x8d, 0x1000, 128, },
1192 + { "SST25WF080", 5, 0x1000, 256, },
1193 + { "SST25VF080B", 0x8e, 0x1000, 256, },
1194 + { "SST25VF016", 0x41, 0x1000, 512, },
1195 + { "SST25VF032", 0x4a, 0x1000, 1024, },
1196 + { "SST25VF064", 0x4b, 0x1000, 2048, },
1197 + { 0 },
1198 +};
1199 +
1200 +static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
1201 + { "AT45DB011", 0xc, 256, 512, },
1202 + { "AT45DB021", 0x14, 256, 1024, },
1203 + { "AT45DB041", 0x1c, 256, 2048, },
1204 + { "AT45DB081", 0x24, 256, 4096, },
1205 + { "AT45DB161", 0x2c, 512, 4096, },
1206 + { "AT45DB321", 0x34, 512, 8192, },
1207 + { "AT45DB642", 0x3c, 1024, 8192, },
1208 + { 0 },
1209 +};
1210 +
1211 +static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
1212 +{
1213 + int i;
1214 + bcma_cc_write32(cc, BCMA_CC_FLASHCTL,
1215 + BCMA_CC_FLASHCTL_START | opcode);
1216 + for (i = 0; i < 1000; i++) {
1217 + if (!(bcma_cc_read32(cc, BCMA_CC_FLASHCTL) &
1218 + BCMA_CC_FLASHCTL_BUSY))
1219 + return;
1220 + cpu_relax();
1221 + }
1222 + bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
1223 +}
1224 +
1225 +/* Initialize serial flash access */
1226 +int bcma_sflash_init(struct bcma_drv_cc *cc)
1227 +{
1228 + struct bcma_bus *bus = cc->core->bus;
1229 + struct bcma_sflash *sflash = &cc->sflash;
1230 + struct bcma_sflash_tbl_e *e;
1231 + u32 id, id2;
1232 +
1233 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1234 + case BCMA_CC_FLASHT_STSER:
1235 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP);
1236 +
1237 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0);
1238 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
1239 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
1240 +
1241 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1);
1242 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
1243 + id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
1244 +
1245 + switch (id) {
1246 + case 0xbf:
1247 + for (e = bcma_sflash_sst_tbl; e->name; e++) {
1248 + if (e->id == id2)
1249 + break;
1250 + }
1251 + break;
1252 + case 0x13:
1253 + return -ENOTSUPP;
1254 + default:
1255 + for (e = bcma_sflash_st_tbl; e->name; e++) {
1256 + if (e->id == id)
1257 + break;
1258 + }
1259 + break;
1260 + }
1261 + if (!e->name) {
1262 + bcma_err(bus, "Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2);
1263 + return -ENOTSUPP;
1264 + }
1265 +
1266 + break;
1267 + case BCMA_CC_FLASHT_ATSER:
1268 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
1269 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c;
1270 +
1271 + for (e = bcma_sflash_at_tbl; e->name; e++) {
1272 + if (e->id == id)
1273 + break;
1274 + }
1275 + if (!e->name) {
1276 + bcma_err(bus, "Unsupported Atmel serial flash (id: 0x%X)\n", id);
1277 + return -ENOTSUPP;
1278 + }
1279 +
1280 + break;
1281 + default:
1282 + bcma_err(bus, "Unsupported flash type\n");
1283 + return -ENOTSUPP;
1284 + }
1285 +
1286 + sflash->window = BCMA_SOC_FLASH2;
1287 + sflash->blocksize = e->blocksize;
1288 + sflash->numblocks = e->numblocks;
1289 + sflash->size = sflash->blocksize * sflash->numblocks;
1290 + sflash->present = true;
1291 +
1292 + bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
1293 + e->name, sflash->size / 1024, sflash->blocksize,
1294 + sflash->numblocks);
1295 +
1296 + /* Prepare platform device, but don't register it yet. It's too early,
1297 + * malloc (required by device_private_init) is not available yet. */
1298 + bcma_sflash_dev.resource[0].end = bcma_sflash_dev.resource[0].start +
1299 + sflash->size;
1300 + bcma_sflash_dev.dev.platform_data = sflash;
1301 +
1302 + return 0;
1303 +}
1304 --- /dev/null
1305 +++ b/drivers/bcma/driver_gmac_cmn.c
1306 @@ -0,0 +1,14 @@
1307 +/*
1308 + * Broadcom specific AMBA
1309 + * GBIT MAC COMMON Core
1310 + *
1311 + * Licensed under the GNU/GPL. See COPYING for details.
1312 + */
1313 +
1314 +#include "bcma_private.h"
1315 +#include <linux/bcma/bcma.h>
1316 +
1317 +void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc)
1318 +{
1319 + mutex_init(&gc->phy_mutex);
1320 +}
1321 --- /dev/null
1322 +++ b/drivers/bcma/driver_gpio.c
1323 @@ -0,0 +1,98 @@
1324 +/*
1325 + * Broadcom specific AMBA
1326 + * GPIO driver
1327 + *
1328 + * Copyright 2011, Broadcom Corporation
1329 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
1330 + *
1331 + * Licensed under the GNU/GPL. See COPYING for details.
1332 + */
1333 +
1334 +#include <linux/gpio.h>
1335 +#include <linux/export.h>
1336 +#include <linux/bcma/bcma.h>
1337 +
1338 +#include "bcma_private.h"
1339 +
1340 +static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
1341 +{
1342 + return container_of(chip, struct bcma_drv_cc, gpio);
1343 +}
1344 +
1345 +static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1346 +{
1347 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1348 +
1349 + return !!bcma_chipco_gpio_in(cc, 1 << gpio);
1350 +}
1351 +
1352 +static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
1353 + int value)
1354 +{
1355 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1356 +
1357 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
1358 +}
1359 +
1360 +static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1361 +{
1362 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1363 +
1364 + bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
1365 + return 0;
1366 +}
1367 +
1368 +static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
1369 + int value)
1370 +{
1371 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1372 +
1373 + bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
1374 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
1375 + return 0;
1376 +}
1377 +
1378 +static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
1379 +{
1380 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1381 +
1382 + bcma_chipco_gpio_control(cc, 1 << gpio, 0);
1383 + /* clear pulldown */
1384 + bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
1385 + /* Set pullup */
1386 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
1387 +
1388 + return 0;
1389 +}
1390 +
1391 +static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
1392 +{
1393 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1394 +
1395 + /* clear pullup */
1396 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
1397 +}
1398 +
1399 +int bcma_gpio_init(struct bcma_drv_cc *cc)
1400 +{
1401 + struct gpio_chip *chip = &cc->gpio;
1402 +
1403 + chip->label = "bcma_gpio";
1404 + chip->owner = THIS_MODULE;
1405 + chip->request = bcma_gpio_request;
1406 + chip->free = bcma_gpio_free;
1407 + chip->get = bcma_gpio_get_value;
1408 + chip->set = bcma_gpio_set_value;
1409 + chip->direction_input = bcma_gpio_direction_input;
1410 + chip->direction_output = bcma_gpio_direction_output;
1411 + chip->ngpio = 16;
1412 + /* There is just one SoC in one device and its GPIO addresses should be
1413 + * deterministic to address them more easily. The other buses could get
1414 + * a random base number. */
1415 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
1416 + chip->base = 0;
1417 + else
1418 + chip->base = -1;
1419 +
1420 + return gpiochip_add(chip);
1421 +}
1422 --- a/drivers/bcma/driver_mips.c
1423 +++ b/drivers/bcma/driver_mips.c
1424 @@ -22,15 +22,15 @@
1425 /* The 47162a0 hangs when reading MIPS DMP registers registers */
1426 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
1427 {
1428 - return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
1429 - dev->id.id == BCMA_CORE_MIPS_74K;
1430 + return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
1431 + dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
1432 }
1433
1434 /* The 5357b0 hangs when reading USB20H DMP registers */
1435 static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
1436 {
1437 - return (dev->bus->chipinfo.id == 0x5357 ||
1438 - dev->bus->chipinfo.id == 0x4749) &&
1439 + return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
1440 + dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
1441 dev->bus->chipinfo.pkg == 11 &&
1442 dev->id.id == BCMA_CORE_USB20_HOST;
1443 }
1444 @@ -74,11 +74,16 @@ static u32 bcma_core_mips_irqflag(struct
1445 return dev->core_index;
1446 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
1447
1448 - return flag & 0x1F;
1449 + if (flag)
1450 + return flag & 0x1F;
1451 + else
1452 + return 0x3f;
1453 }
1454
1455 /* Get the MIPS IRQ assignment for a specified device.
1456 * If unassigned, 0 is returned.
1457 + * If disabled, 5 is returned.
1458 + * If not supported, 6 is returned.
1459 */
1460 unsigned int bcma_core_mips_irq(struct bcma_device *dev)
1461 {
1462 @@ -87,13 +92,15 @@ unsigned int bcma_core_mips_irq(struct b
1463 unsigned int irq;
1464
1465 irqflag = bcma_core_mips_irqflag(dev);
1466 + if (irqflag == 0x3f)
1467 + return 6;
1468
1469 - for (irq = 1; irq <= 4; irq++)
1470 + for (irq = 0; irq <= 4; irq++)
1471 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
1472 (1 << irqflag))
1473 return irq;
1474
1475 - return 0;
1476 + return 5;
1477 }
1478 EXPORT_SYMBOL(bcma_core_mips_irq);
1479
1480 @@ -114,8 +121,8 @@ static void bcma_core_mips_set_irq(struc
1481 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
1482 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
1483 ~(1 << irqflag));
1484 - else
1485 - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
1486 + else if (oldirq != 5)
1487 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
1488
1489 /* assign the new one */
1490 if (irq == 0) {
1491 @@ -123,17 +130,17 @@ static void bcma_core_mips_set_irq(struc
1492 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
1493 (1 << irqflag));
1494 } else {
1495 - u32 oldirqflag = bcma_read32(mdev,
1496 - BCMA_MIPS_MIPS74K_INTMASK(irq));
1497 - if (oldirqflag) {
1498 + u32 irqinitmask = bcma_read32(mdev,
1499 + BCMA_MIPS_MIPS74K_INTMASK(irq));
1500 + if (irqinitmask) {
1501 struct bcma_device *core;
1502
1503 /* backplane irq line is in use, find out who uses
1504 * it and set user to irq 0
1505 */
1506 - list_for_each_entry_reverse(core, &bus->cores, list) {
1507 + list_for_each_entry(core, &bus->cores, list) {
1508 if ((1 << bcma_core_mips_irqflag(core)) ==
1509 - oldirqflag) {
1510 + irqinitmask) {
1511 bcma_core_mips_set_irq(core, 0);
1512 break;
1513 }
1514 @@ -143,15 +150,31 @@ static void bcma_core_mips_set_irq(struc
1515 1 << irqflag);
1516 }
1517
1518 - pr_info("set_irq: core 0x%04x, irq %d => %d\n",
1519 - dev->id.id, oldirq + 2, irq + 2);
1520 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
1521 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
1522 +}
1523 +
1524 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
1525 + u16 coreid, u8 unit)
1526 +{
1527 + struct bcma_device *core;
1528 +
1529 + core = bcma_find_core_unit(bus, coreid, unit);
1530 + if (!core) {
1531 + bcma_warn(bus,
1532 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
1533 + coreid, unit);
1534 + return;
1535 + }
1536 +
1537 + bcma_core_mips_set_irq(core, irq);
1538 }
1539
1540 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
1541 {
1542 int i;
1543 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1544 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1545 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1546 for (i = 0; i <= 6; i++)
1547 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
1548 printk("\n");
1549 @@ -161,7 +184,7 @@ static void bcma_core_mips_dump_irq(stru
1550 {
1551 struct bcma_device *core;
1552
1553 - list_for_each_entry_reverse(core, &bus->cores, list) {
1554 + list_for_each_entry(core, &bus->cores, list) {
1555 bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
1556 }
1557 }
1558 @@ -171,9 +194,9 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
1559 struct bcma_bus *bus = mcore->core->bus;
1560
1561 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
1562 - return bcma_pmu_get_clockcpu(&bus->drv_cc);
1563 + return bcma_pmu_get_cpu_clock(&bus->drv_cc);
1564
1565 - pr_err("No PMU available, need this to get the cpu clock\n");
1566 + bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
1567 return 0;
1568 }
1569 EXPORT_SYMBOL(bcma_cpu_clock);
1570 @@ -181,76 +204,109 @@ EXPORT_SYMBOL(bcma_cpu_clock);
1571 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
1572 {
1573 struct bcma_bus *bus = mcore->core->bus;
1574 + struct bcma_drv_cc *cc = &bus->drv_cc;
1575
1576 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
1577 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1578 case BCMA_CC_FLASHT_STSER:
1579 case BCMA_CC_FLASHT_ATSER:
1580 - pr_err("Serial flash not supported.\n");
1581 + bcma_debug(bus, "Found serial flash\n");
1582 + bcma_sflash_init(cc);
1583 break;
1584 case BCMA_CC_FLASHT_PARA:
1585 - pr_info("found parallel flash.\n");
1586 - bus->drv_cc.pflash.window = 0x1c000000;
1587 - bus->drv_cc.pflash.window_size = 0x02000000;
1588 + bcma_debug(bus, "Found parallel flash\n");
1589 + cc->pflash.present = true;
1590 + cc->pflash.window = BCMA_SOC_FLASH2;
1591 + cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
1592
1593 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
1594 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
1595 BCMA_CC_FLASH_CFG_DS) == 0)
1596 - bus->drv_cc.pflash.buswidth = 1;
1597 + cc->pflash.buswidth = 1;
1598 else
1599 - bus->drv_cc.pflash.buswidth = 2;
1600 + cc->pflash.buswidth = 2;
1601 break;
1602 default:
1603 - pr_err("flash not supported.\n");
1604 + bcma_err(bus, "Flash type not supported\n");
1605 + }
1606 +
1607 + if (cc->core->id.rev == 38 ||
1608 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
1609 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
1610 + bcma_debug(bus, "Found NAND flash\n");
1611 + bcma_nflash_init(cc);
1612 + }
1613 }
1614 }
1615
1616 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
1617 +{
1618 + struct bcma_bus *bus = mcore->core->bus;
1619 +
1620 + if (mcore->early_setup_done)
1621 + return;
1622 +
1623 + bcma_chipco_serial_init(&bus->drv_cc);
1624 + bcma_core_mips_flash_detect(mcore);
1625 +
1626 + mcore->early_setup_done = true;
1627 +}
1628 +
1629 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
1630 {
1631 struct bcma_bus *bus;
1632 struct bcma_device *core;
1633 bus = mcore->core->bus;
1634
1635 - pr_info("Initializing MIPS core...\n");
1636 + if (mcore->setup_done)
1637 + return;
1638 +
1639 + bcma_debug(bus, "Initializing MIPS core...\n");
1640
1641 - if (!mcore->setup_done)
1642 - mcore->assigned_irqs = 1;
1643 + bcma_core_mips_early_init(mcore);
1644
1645 - /* Assign IRQs to all cores on the bus */
1646 - list_for_each_entry_reverse(core, &bus->cores, list) {
1647 - int mips_irq;
1648 - if (core->irq)
1649 - continue;
1650 -
1651 - mips_irq = bcma_core_mips_irq(core);
1652 - if (mips_irq > 4)
1653 - core->irq = 0;
1654 - else
1655 - core->irq = mips_irq + 2;
1656 - if (core->irq > 5)
1657 - continue;
1658 - switch (core->id.id) {
1659 - case BCMA_CORE_PCI:
1660 - case BCMA_CORE_PCIE:
1661 - case BCMA_CORE_ETHERNET:
1662 - case BCMA_CORE_ETHERNET_GBIT:
1663 - case BCMA_CORE_MAC_GBIT:
1664 - case BCMA_CORE_80211:
1665 - case BCMA_CORE_USB20_HOST:
1666 - /* These devices get their own IRQ line if available,
1667 - * the rest goes on IRQ0
1668 - */
1669 - if (mcore->assigned_irqs <= 4)
1670 - bcma_core_mips_set_irq(core,
1671 - mcore->assigned_irqs++);
1672 - break;
1673 + switch (bus->chipinfo.id) {
1674 + case BCMA_CHIP_ID_BCM4716:
1675 + case BCMA_CHIP_ID_BCM4748:
1676 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1677 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1678 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1679 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
1680 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1681 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1682 + break;
1683 + case BCMA_CHIP_ID_BCM5356:
1684 + case BCMA_CHIP_ID_BCM47162:
1685 + case BCMA_CHIP_ID_BCM53572:
1686 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1687 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1688 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1689 + break;
1690 + case BCMA_CHIP_ID_BCM5357:
1691 + case BCMA_CHIP_ID_BCM4749:
1692 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1693 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1694 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1695 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1696 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1697 + break;
1698 + case BCMA_CHIP_ID_BCM4706:
1699 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
1700 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
1701 + 0);
1702 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
1703 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
1704 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
1705 + 0);
1706 + break;
1707 + default:
1708 + list_for_each_entry(core, &bus->cores, list) {
1709 + core->irq = bcma_core_mips_irq(core) + 2;
1710 }
1711 + bcma_err(bus,
1712 + "Unknown device (0x%x) found, can not configure IRQs\n",
1713 + bus->chipinfo.id);
1714 }
1715 - pr_info("IRQ reconfiguration done\n");
1716 + bcma_debug(bus, "IRQ reconfiguration done\n");
1717 bcma_core_mips_dump_irq(bus);
1718
1719 - if (mcore->setup_done)
1720 - return;
1721 -
1722 - bcma_chipco_serial_init(&bus->drv_cc);
1723 - bcma_core_mips_flash_detect(mcore);
1724 mcore->setup_done = true;
1725 }
1726 --- a/drivers/bcma/driver_pci.c
1727 +++ b/drivers/bcma/driver_pci.c
1728 @@ -2,8 +2,9 @@
1729 * Broadcom specific AMBA
1730 * PCI Core
1731 *
1732 - * Copyright 2005, Broadcom Corporation
1733 + * Copyright 2005, 2011, Broadcom Corporation
1734 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1735 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
1736 *
1737 * Licensed under the GNU/GPL. See COPYING for details.
1738 */
1739 @@ -16,120 +17,124 @@
1740 * R/W ops.
1741 **************************************************/
1742
1743 -static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
1744 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
1745 {
1746 - pcicore_write32(pc, 0x130, address);
1747 - pcicore_read32(pc, 0x130);
1748 - return pcicore_read32(pc, 0x134);
1749 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
1750 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
1751 + return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
1752 }
1753
1754 -#if 0
1755 static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
1756 {
1757 - pcicore_write32(pc, 0x130, address);
1758 - pcicore_read32(pc, 0x130);
1759 - pcicore_write32(pc, 0x134, data);
1760 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
1761 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
1762 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
1763 }
1764 -#endif
1765
1766 static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
1767 {
1768 - const u16 mdio_control = 0x128;
1769 - const u16 mdio_data = 0x12C;
1770 u32 v;
1771 int i;
1772
1773 - v = (1 << 30); /* Start of Transaction */
1774 - v |= (1 << 28); /* Write Transaction */
1775 - v |= (1 << 17); /* Turnaround */
1776 - v |= (0x1F << 18);
1777 + v = BCMA_CORE_PCI_MDIODATA_START;
1778 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
1779 + v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
1780 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
1781 + v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
1782 + BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
1783 + v |= BCMA_CORE_PCI_MDIODATA_TA;
1784 v |= (phy << 4);
1785 - pcicore_write32(pc, mdio_data, v);
1786 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
1787
1788 udelay(10);
1789 for (i = 0; i < 200; i++) {
1790 - v = pcicore_read32(pc, mdio_control);
1791 - if (v & 0x100 /* Trans complete */)
1792 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1793 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1794 break;
1795 - msleep(1);
1796 + usleep_range(1000, 2000);
1797 }
1798 }
1799
1800 static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
1801 {
1802 - const u16 mdio_control = 0x128;
1803 - const u16 mdio_data = 0x12C;
1804 int max_retries = 10;
1805 u16 ret = 0;
1806 u32 v;
1807 int i;
1808
1809 - v = 0x80; /* Enable Preamble Sequence */
1810 - v |= 0x2; /* MDIO Clock Divisor */
1811 - pcicore_write32(pc, mdio_control, v);
1812 + /* enable mdio access to SERDES */
1813 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
1814 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
1815 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
1816
1817 if (pc->core->id.rev >= 10) {
1818 max_retries = 200;
1819 bcma_pcie_mdio_set_phy(pc, device);
1820 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
1821 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
1822 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
1823 + } else {
1824 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
1825 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
1826 }
1827
1828 - v = (1 << 30); /* Start of Transaction */
1829 - v |= (1 << 29); /* Read Transaction */
1830 - v |= (1 << 17); /* Turnaround */
1831 - if (pc->core->id.rev < 10)
1832 - v |= (u32)device << 22;
1833 - v |= (u32)address << 18;
1834 - pcicore_write32(pc, mdio_data, v);
1835 + v = BCMA_CORE_PCI_MDIODATA_START;
1836 + v |= BCMA_CORE_PCI_MDIODATA_READ;
1837 + v |= BCMA_CORE_PCI_MDIODATA_TA;
1838 +
1839 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
1840 /* Wait for the device to complete the transaction */
1841 udelay(10);
1842 for (i = 0; i < max_retries; i++) {
1843 - v = pcicore_read32(pc, mdio_control);
1844 - if (v & 0x100 /* Trans complete */) {
1845 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1846 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
1847 udelay(10);
1848 - ret = pcicore_read32(pc, mdio_data);
1849 + ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
1850 break;
1851 }
1852 - msleep(1);
1853 + usleep_range(1000, 2000);
1854 }
1855 - pcicore_write32(pc, mdio_control, 0);
1856 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1857 return ret;
1858 }
1859
1860 static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
1861 u8 address, u16 data)
1862 {
1863 - const u16 mdio_control = 0x128;
1864 - const u16 mdio_data = 0x12C;
1865 int max_retries = 10;
1866 u32 v;
1867 int i;
1868
1869 - v = 0x80; /* Enable Preamble Sequence */
1870 - v |= 0x2; /* MDIO Clock Divisor */
1871 - pcicore_write32(pc, mdio_control, v);
1872 + /* enable mdio access to SERDES */
1873 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
1874 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
1875 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
1876
1877 if (pc->core->id.rev >= 10) {
1878 max_retries = 200;
1879 bcma_pcie_mdio_set_phy(pc, device);
1880 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
1881 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
1882 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
1883 + } else {
1884 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
1885 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
1886 }
1887
1888 - v = (1 << 30); /* Start of Transaction */
1889 - v |= (1 << 28); /* Write Transaction */
1890 - v |= (1 << 17); /* Turnaround */
1891 - if (pc->core->id.rev < 10)
1892 - v |= (u32)device << 22;
1893 - v |= (u32)address << 18;
1894 + v = BCMA_CORE_PCI_MDIODATA_START;
1895 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
1896 + v |= BCMA_CORE_PCI_MDIODATA_TA;
1897 v |= data;
1898 - pcicore_write32(pc, mdio_data, v);
1899 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
1900 /* Wait for the device to complete the transaction */
1901 udelay(10);
1902 for (i = 0; i < max_retries; i++) {
1903 - v = pcicore_read32(pc, mdio_control);
1904 - if (v & 0x100 /* Trans complete */)
1905 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1906 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1907 break;
1908 - msleep(1);
1909 + usleep_range(1000, 2000);
1910 }
1911 - pcicore_write32(pc, mdio_control, 0);
1912 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1913 }
1914
1915 /**************************************************
1916 @@ -138,88 +143,108 @@ static void bcma_pcie_mdio_write(struct
1917
1918 static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
1919 {
1920 - return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
1921 + u32 tmp;
1922 +
1923 + tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
1924 + if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
1925 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
1926 + BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
1927 + else
1928 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
1929 }
1930
1931 static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
1932 {
1933 - const u8 serdes_pll_device = 0x1D;
1934 - const u8 serdes_rx_device = 0x1F;
1935 u16 tmp;
1936
1937 - bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
1938 - bcma_pcicore_polarity_workaround(pc));
1939 - tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
1940 - if (tmp & 0x4000)
1941 - bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
1942 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
1943 + BCMA_CORE_PCI_SERDES_RX_CTRL,
1944 + bcma_pcicore_polarity_workaround(pc));
1945 + tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
1946 + BCMA_CORE_PCI_SERDES_PLL_CTRL);
1947 + if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
1948 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
1949 + BCMA_CORE_PCI_SERDES_PLL_CTRL,
1950 + tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
1951 +}
1952 +
1953 +static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
1954 +{
1955 + struct bcma_device *core = pc->core;
1956 + u16 val16, core_index;
1957 + uint regoff;
1958 +
1959 + regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
1960 + core_index = (u16)core->core_index;
1961 +
1962 + val16 = pcicore_read16(pc, regoff);
1963 + if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
1964 + != core_index) {
1965 + val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) |
1966 + (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
1967 + pcicore_write16(pc, regoff, val16);
1968 + }
1969 +}
1970 +
1971 +/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
1972 +/* Needs to happen when coming out of 'standby'/'hibernate' */
1973 +static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
1974 +{
1975 + u16 val16;
1976 + uint regoff;
1977 +
1978 + regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);
1979 +
1980 + val16 = pcicore_read16(pc, regoff);
1981 +
1982 + if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
1983 + val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
1984 + pcicore_write16(pc, regoff, val16);
1985 + }
1986 }
1987
1988 /**************************************************
1989 * Init.
1990 **************************************************/
1991
1992 -static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
1993 +static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
1994 {
1995 + bcma_core_pci_fixcfg(pc);
1996 bcma_pcicore_serdes_workaround(pc);
1997 + bcma_core_pci_config_fixup(pc);
1998 }
1999
2000 -static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
2001 -{
2002 - struct bcma_bus *bus = pc->core->bus;
2003 - u16 chipid_top;
2004 -
2005 - chipid_top = (bus->chipinfo.id & 0xFF00);
2006 - if (chipid_top != 0x4700 &&
2007 - chipid_top != 0x5300)
2008 - return false;
2009 -
2010 -#ifdef CONFIG_SSB_DRIVER_PCICORE
2011 - if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
2012 - return false;
2013 -#endif /* CONFIG_SSB_DRIVER_PCICORE */
2014 -
2015 -#if 0
2016 - /* TODO: on BCMA we use address from EROM instead of magic formula */
2017 - u32 tmp;
2018 - return !mips_busprobe32(tmp, (bus->mmio +
2019 - (pc->core->core_index * BCMA_CORE_SIZE)));
2020 -#endif
2021 -
2022 - return true;
2023 -}
2024 -
2025 -void bcma_core_pci_init(struct bcma_drv_pci *pc)
2026 +void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
2027 {
2028 if (pc->setup_done)
2029 return;
2030
2031 - if (bcma_core_pci_is_in_hostmode(pc)) {
2032 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
2033 + pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
2034 + if (pc->hostmode)
2035 bcma_core_pci_hostmode_init(pc);
2036 -#else
2037 - pr_err("Driver compiled without support for hostmode PCI\n");
2038 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
2039 - } else {
2040 - bcma_core_pci_clientmode_init(pc);
2041 - }
2042
2043 - pc->setup_done = true;
2044 + if (!pc->hostmode)
2045 + bcma_core_pci_clientmode_init(pc);
2046 }
2047
2048 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
2049 bool enable)
2050 {
2051 - struct pci_dev *pdev = pc->core->bus->host_pci;
2052 + struct pci_dev *pdev;
2053 u32 coremask, tmp;
2054 int err = 0;
2055
2056 - if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
2057 + if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
2058 /* This bcma device is not on a PCI host-bus. So the IRQs are
2059 * not routed through the PCI core.
2060 * So we must not enable routing through the PCI core. */
2061 goto out;
2062 }
2063
2064 + pdev = pc->core->bus->host_pci;
2065 +
2066 err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
2067 if (err)
2068 goto out;
2069 @@ -236,3 +261,17 @@ out:
2070 return err;
2071 }
2072 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
2073 +
2074 +void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
2075 +{
2076 + u32 w;
2077 +
2078 + w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
2079 + if (extend)
2080 + w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
2081 + else
2082 + w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
2083 + bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
2084 + bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
2085 +}
2086 +EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
2087 --- a/drivers/bcma/driver_pci_host.c
2088 +++ b/drivers/bcma/driver_pci_host.c
2089 @@ -2,13 +2,600 @@
2090 * Broadcom specific AMBA
2091 * PCI Core in hostmode
2092 *
2093 + * Copyright 2005 - 2011, Broadcom Corporation
2094 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
2095 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
2096 + *
2097 * Licensed under the GNU/GPL. See COPYING for details.
2098 */
2099
2100 #include "bcma_private.h"
2101 +#include <linux/pci.h>
2102 +#include <linux/export.h>
2103 #include <linux/bcma/bcma.h>
2104 +#include <asm/paccess.h>
2105 +
2106 +/* Probe a 32bit value on the bus and catch bus exceptions.
2107 + * Returns nonzero on a bus exception.
2108 + * This is MIPS specific */
2109 +#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
2110 +
2111 +/* Assume one-hot slot wiring */
2112 +#define BCMA_PCI_SLOT_MAX 16
2113 +#define PCI_CONFIG_SPACE_SIZE 256
2114 +
2115 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
2116 +{
2117 + struct bcma_bus *bus = pc->core->bus;
2118 + u16 chipid_top;
2119 + u32 tmp;
2120 +
2121 + chipid_top = (bus->chipinfo.id & 0xFF00);
2122 + if (chipid_top != 0x4700 &&
2123 + chipid_top != 0x5300)
2124 + return false;
2125 +
2126 + bcma_core_enable(pc->core, 0);
2127 +
2128 + return !mips_busprobe32(tmp, pc->core->io_addr);
2129 +}
2130 +
2131 +static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
2132 +{
2133 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
2134 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
2135 + return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
2136 +}
2137 +
2138 +static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
2139 + u32 data)
2140 +{
2141 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
2142 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
2143 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
2144 +}
2145 +
2146 +static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
2147 + unsigned int func, unsigned int off)
2148 +{
2149 + u32 addr = 0;
2150 +
2151 + /* Issue config commands only when the data link is up (atleast
2152 + * one external pcie device is present).
2153 + */
2154 + if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
2155 + & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
2156 + goto out;
2157 +
2158 + /* Type 0 transaction */
2159 + /* Slide the PCI window to the appropriate slot */
2160 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
2161 + /* Calculate the address */
2162 + addr = pc->host_controller->host_cfg_addr;
2163 + addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
2164 + addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
2165 + addr |= (off & ~3);
2166 +
2167 +out:
2168 + return addr;
2169 +}
2170
2171 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
2172 +static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
2173 + unsigned int func, unsigned int off,
2174 + void *buf, int len)
2175 {
2176 - pr_err("No support for PCI core in hostmode yet\n");
2177 + int err = -EINVAL;
2178 + u32 addr, val;
2179 + void __iomem *mmio = 0;
2180 +
2181 + WARN_ON(!pc->hostmode);
2182 + if (unlikely(len != 1 && len != 2 && len != 4))
2183 + goto out;
2184 + if (dev == 0) {
2185 + /* we support only two functions on device 0 */
2186 + if (func > 1)
2187 + return -EINVAL;
2188 +
2189 + /* accesses to config registers with offsets >= 256
2190 + * requires indirect access.
2191 + */
2192 + if (off >= PCI_CONFIG_SPACE_SIZE) {
2193 + addr = (func << 12);
2194 + addr |= (off & 0x0FFF);
2195 + val = bcma_pcie_read_config(pc, addr);
2196 + } else {
2197 + addr = BCMA_CORE_PCI_PCICFG0;
2198 + addr |= (func << 8);
2199 + addr |= (off & 0xfc);
2200 + val = pcicore_read32(pc, addr);
2201 + }
2202 + } else {
2203 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
2204 + if (unlikely(!addr))
2205 + goto out;
2206 + err = -ENOMEM;
2207 + mmio = ioremap_nocache(addr, sizeof(val));
2208 + if (!mmio)
2209 + goto out;
2210 +
2211 + if (mips_busprobe32(val, mmio)) {
2212 + val = 0xffffffff;
2213 + goto unmap;
2214 + }
2215 +
2216 + val = readl(mmio);
2217 + }
2218 + val >>= (8 * (off & 3));
2219 +
2220 + switch (len) {
2221 + case 1:
2222 + *((u8 *)buf) = (u8)val;
2223 + break;
2224 + case 2:
2225 + *((u16 *)buf) = (u16)val;
2226 + break;
2227 + case 4:
2228 + *((u32 *)buf) = (u32)val;
2229 + break;
2230 + }
2231 + err = 0;
2232 +unmap:
2233 + if (mmio)
2234 + iounmap(mmio);
2235 +out:
2236 + return err;
2237 +}
2238 +
2239 +static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
2240 + unsigned int func, unsigned int off,
2241 + const void *buf, int len)
2242 +{
2243 + int err = -EINVAL;
2244 + u32 addr = 0, val = 0;
2245 + void __iomem *mmio = 0;
2246 + u16 chipid = pc->core->bus->chipinfo.id;
2247 +
2248 + WARN_ON(!pc->hostmode);
2249 + if (unlikely(len != 1 && len != 2 && len != 4))
2250 + goto out;
2251 + if (dev == 0) {
2252 + /* accesses to config registers with offsets >= 256
2253 + * requires indirect access.
2254 + */
2255 + if (off < PCI_CONFIG_SPACE_SIZE) {
2256 + addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
2257 + addr |= (func << 8);
2258 + addr |= (off & 0xfc);
2259 + mmio = ioremap_nocache(addr, sizeof(val));
2260 + if (!mmio)
2261 + goto out;
2262 + }
2263 + } else {
2264 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
2265 + if (unlikely(!addr))
2266 + goto out;
2267 + err = -ENOMEM;
2268 + mmio = ioremap_nocache(addr, sizeof(val));
2269 + if (!mmio)
2270 + goto out;
2271 +
2272 + if (mips_busprobe32(val, mmio)) {
2273 + val = 0xffffffff;
2274 + goto unmap;
2275 + }
2276 + }
2277 +
2278 + switch (len) {
2279 + case 1:
2280 + val = readl(mmio);
2281 + val &= ~(0xFF << (8 * (off & 3)));
2282 + val |= *((const u8 *)buf) << (8 * (off & 3));
2283 + break;
2284 + case 2:
2285 + val = readl(mmio);
2286 + val &= ~(0xFFFF << (8 * (off & 3)));
2287 + val |= *((const u16 *)buf) << (8 * (off & 3));
2288 + break;
2289 + case 4:
2290 + val = *((const u32 *)buf);
2291 + break;
2292 + }
2293 + if (dev == 0 && !addr) {
2294 + /* accesses to config registers with offsets >= 256
2295 + * requires indirect access.
2296 + */
2297 + addr = (func << 12);
2298 + addr |= (off & 0x0FFF);
2299 + bcma_pcie_write_config(pc, addr, val);
2300 + } else {
2301 + writel(val, mmio);
2302 +
2303 + if (chipid == BCMA_CHIP_ID_BCM4716 ||
2304 + chipid == BCMA_CHIP_ID_BCM4748)
2305 + readl(mmio);
2306 + }
2307 +
2308 + err = 0;
2309 +unmap:
2310 + if (mmio)
2311 + iounmap(mmio);
2312 +out:
2313 + return err;
2314 +}
2315 +
2316 +static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
2317 + unsigned int devfn,
2318 + int reg, int size, u32 *val)
2319 +{
2320 + unsigned long flags;
2321 + int err;
2322 + struct bcma_drv_pci *pc;
2323 + struct bcma_drv_pci_host *pc_host;
2324 +
2325 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
2326 + pc = pc_host->pdev;
2327 +
2328 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
2329 + err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
2330 + PCI_FUNC(devfn), reg, val, size);
2331 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
2332 +
2333 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
2334 +}
2335 +
2336 +static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
2337 + unsigned int devfn,
2338 + int reg, int size, u32 val)
2339 +{
2340 + unsigned long flags;
2341 + int err;
2342 + struct bcma_drv_pci *pc;
2343 + struct bcma_drv_pci_host *pc_host;
2344 +
2345 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
2346 + pc = pc_host->pdev;
2347 +
2348 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
2349 + err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
2350 + PCI_FUNC(devfn), reg, &val, size);
2351 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
2352 +
2353 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
2354 +}
2355 +
2356 +/* return cap_offset if requested capability exists in the PCI config space */
2357 +static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc,
2358 + unsigned int dev,
2359 + unsigned int func, u8 req_cap_id,
2360 + unsigned char *buf, u32 *buflen)
2361 +{
2362 + u8 cap_id;
2363 + u8 cap_ptr = 0;
2364 + u32 bufsize;
2365 + u8 byte_val;
2366 +
2367 + /* check for Header type 0 */
2368 + bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
2369 + sizeof(u8));
2370 + if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
2371 + return cap_ptr;
2372 +
2373 + /* check if the capability pointer field exists */
2374 + bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
2375 + sizeof(u8));
2376 + if (!(byte_val & PCI_STATUS_CAP_LIST))
2377 + return cap_ptr;
2378 +
2379 + /* check if the capability pointer is 0x00 */
2380 + bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
2381 + sizeof(u8));
2382 + if (cap_ptr == 0x00)
2383 + return cap_ptr;
2384 +
2385 + /* loop thr'u the capability list and see if the requested capabilty
2386 + * exists */
2387 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
2388 + while (cap_id != req_cap_id) {
2389 + bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
2390 + sizeof(u8));
2391 + if (cap_ptr == 0x00)
2392 + return cap_ptr;
2393 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
2394 + sizeof(u8));
2395 + }
2396 +
2397 + /* found the caller requested capability */
2398 + if ((buf != NULL) && (buflen != NULL)) {
2399 + u8 cap_data;
2400 +
2401 + bufsize = *buflen;
2402 + if (!bufsize)
2403 + return cap_ptr;
2404 +
2405 + *buflen = 0;
2406 +
2407 + /* copy the cpability data excluding cap ID and next ptr */
2408 + cap_data = cap_ptr + 2;
2409 + if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE)
2410 + bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
2411 + *buflen = bufsize;
2412 + while (bufsize--) {
2413 + bcma_extpci_read_config(pc, dev, func, cap_data, buf,
2414 + sizeof(u8));
2415 + cap_data++;
2416 + buf++;
2417 + }
2418 + }
2419 +
2420 + return cap_ptr;
2421 +}
2422 +
2423 +/* If the root port is capable of returning Config Request
2424 + * Retry Status (CRS) Completion Status to software then
2425 + * enable the feature.
2426 + */
2427 +static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
2428 +{
2429 + struct bcma_bus *bus = pc->core->bus;
2430 + u8 cap_ptr, root_ctrl, root_cap, dev;
2431 + u16 val16;
2432 + int i;
2433 +
2434 + cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
2435 + NULL);
2436 + root_cap = cap_ptr + PCI_EXP_RTCAP;
2437 + bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
2438 + if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
2439 + /* Enable CRS software visibility */
2440 + root_ctrl = cap_ptr + PCI_EXP_RTCTL;
2441 + val16 = PCI_EXP_RTCTL_CRSSVE;
2442 + bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
2443 + sizeof(u16));
2444 +
2445 + /* Initiate a configuration request to read the vendor id
2446 + * field of the device function's config space header after
2447 + * 100 ms wait time from the end of Reset. If the device is
2448 + * not done with its internal initialization, it must at
2449 + * least return a completion TLP, with a completion status
2450 + * of "Configuration Request Retry Status (CRS)". The root
2451 + * complex must complete the request to the host by returning
2452 + * a read-data value of 0001h for the Vendor ID field and
2453 + * all 1s for any additional bytes included in the request.
2454 + * Poll using the config reads for max wait time of 1 sec or
2455 + * until we receive the successful completion status. Repeat
2456 + * the procedure for all the devices.
2457 + */
2458 + for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
2459 + for (i = 0; i < 100000; i++) {
2460 + bcma_extpci_read_config(pc, dev, 0,
2461 + PCI_VENDOR_ID, &val16,
2462 + sizeof(val16));
2463 + if (val16 != 0x1)
2464 + break;
2465 + udelay(10);
2466 + }
2467 + if (val16 == 0x1)
2468 + bcma_err(bus, "PCI: Broken device in slot %d\n",
2469 + dev);
2470 + }
2471 + }
2472 +}
2473 +
2474 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
2475 +{
2476 + struct bcma_bus *bus = pc->core->bus;
2477 + struct bcma_drv_pci_host *pc_host;
2478 + u32 tmp;
2479 + u32 pci_membase_1G;
2480 + unsigned long io_map_base;
2481 +
2482 + bcma_info(bus, "PCIEcore in host mode found\n");
2483 +
2484 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
2485 + bcma_info(bus, "This PCIE core is disabled and not working\n");
2486 + return;
2487 + }
2488 +
2489 + pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
2490 + if (!pc_host) {
2491 + bcma_err(bus, "can not allocate memory");
2492 + return;
2493 + }
2494 +
2495 + pc->host_controller = pc_host;
2496 + pc_host->pci_controller.io_resource = &pc_host->io_resource;
2497 + pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
2498 + pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
2499 + pc_host->pdev = pc;
2500 +
2501 + pci_membase_1G = BCMA_SOC_PCI_DMA;
2502 + pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
2503 +
2504 + pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
2505 + pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
2506 +
2507 + pc_host->mem_resource.name = "BCMA PCIcore external memory",
2508 + pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
2509 + pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
2510 + pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
2511 +
2512 + pc_host->io_resource.name = "BCMA PCIcore external I/O",
2513 + pc_host->io_resource.start = 0x100;
2514 + pc_host->io_resource.end = 0x7FF;
2515 + pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
2516 +
2517 + /* Reset RC */
2518 + usleep_range(3000, 5000);
2519 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
2520 + usleep_range(1000, 2000);
2521 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
2522 + BCMA_CORE_PCI_CTL_RST_OE);
2523 +
2524 + /* 64 MB I/O access window. On 4716, use
2525 + * sbtopcie0 to access the device registers. We
2526 + * can't use address match 2 (1 GB window) region
2527 + * as mips can't generate 64-bit address on the
2528 + * backplane.
2529 + */
2530 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 ||
2531 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
2532 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
2533 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
2534 + BCMA_SOC_PCI_MEM_SZ - 1;
2535 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2536 + BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
2537 + } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
2538 + tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
2539 + tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
2540 + tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
2541 + if (pc->core->core_unit == 0) {
2542 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
2543 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
2544 + BCMA_SOC_PCI_MEM_SZ - 1;
2545 + pc_host->io_resource.start = 0x100;
2546 + pc_host->io_resource.end = 0x47F;
2547 + pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
2548 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2549 + tmp | BCMA_SOC_PCI_MEM);
2550 + } else if (pc->core->core_unit == 1) {
2551 + pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
2552 + pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
2553 + BCMA_SOC_PCI_MEM_SZ - 1;
2554 + pc_host->io_resource.start = 0x480;
2555 + pc_host->io_resource.end = 0x7FF;
2556 + pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
2557 + pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
2558 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2559 + tmp | BCMA_SOC_PCI1_MEM);
2560 + }
2561 + } else
2562 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
2563 + BCMA_CORE_PCI_SBTOPCI_IO);
2564 +
2565 + /* 64 MB configuration access window */
2566 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
2567 +
2568 + /* 1 GB memory access window */
2569 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
2570 + BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
2571 +
2572 +
2573 + /* As per PCI Express Base Spec 1.1 we need to wait for
2574 + * at least 100 ms from the end of a reset (cold/warm/hot)
2575 + * before issuing configuration requests to PCI Express
2576 + * devices.
2577 + */
2578 + msleep(100);
2579 +
2580 + bcma_core_pci_enable_crs(pc);
2581 +
2582 + /* Enable PCI bridge BAR0 memory & master access */
2583 + tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
2584 + bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
2585 +
2586 + /* Enable PCI interrupts */
2587 + pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
2588 +
2589 + /* Ok, ready to run, register it to the system.
2590 + * The following needs change, if we want to port hostmode
2591 + * to non-MIPS platform. */
2592 + io_map_base = (unsigned long)ioremap_nocache(pc_host->mem_resource.start,
2593 + resource_size(&pc_host->mem_resource));
2594 + pc_host->pci_controller.io_map_base = io_map_base;
2595 + set_io_port_base(pc_host->pci_controller.io_map_base);
2596 + /* Give some time to the PCI controller to configure itself with the new
2597 + * values. Not waiting at this point causes crashes of the machine. */
2598 + usleep_range(10000, 15000);
2599 + register_pci_controller(&pc_host->pci_controller);
2600 + return;
2601 +}
2602 +
2603 +/* Early PCI fixup for a device on the PCI-core bridge. */
2604 +static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
2605 +{
2606 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2607 + /* This is not a device on the PCI-core bridge. */
2608 + return;
2609 + }
2610 + if (PCI_SLOT(dev->devfn) != 0)
2611 + return;
2612 +
2613 + pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
2614 +
2615 + /* Enable PCI bridge bus mastering and memory space */
2616 + pci_set_master(dev);
2617 + if (pcibios_enable_device(dev, ~0) < 0) {
2618 + pr_err("PCI: BCMA bridge enable failed\n");
2619 + return;
2620 + }
2621 +
2622 + /* Enable PCI bridge BAR1 prefetch and burst */
2623 + pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
2624 +}
2625 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
2626 +
2627 +/* Early PCI fixup for all PCI-cores to set the correct memory address. */
2628 +static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
2629 +{
2630 + struct resource *res;
2631 + int pos, err;
2632 +
2633 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2634 + /* This is not a device on the PCI-core bridge. */
2635 + return;
2636 + }
2637 + if (PCI_SLOT(dev->devfn) == 0)
2638 + return;
2639 +
2640 + pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
2641 +
2642 + for (pos = 0; pos < 6; pos++) {
2643 + res = &dev->resource[pos];
2644 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
2645 + err = pci_assign_resource(dev, pos);
2646 + if (err)
2647 + pr_err("PCI: Problem fixing up the addresses on %s\n",
2648 + pci_name(dev));
2649 + }
2650 + }
2651 +}
2652 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
2653 +
2654 +/* This function is called when doing a pci_enable_device().
2655 + * We must first check if the device is a device on the PCI-core bridge. */
2656 +int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
2657 +{
2658 + struct bcma_drv_pci_host *pc_host;
2659 +
2660 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2661 + /* This is not a device on the PCI-core bridge. */
2662 + return -ENODEV;
2663 + }
2664 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
2665 + pci_ops);
2666 +
2667 + pr_info("PCI: Fixing up device %s\n", pci_name(dev));
2668 +
2669 + /* Fix up interrupt lines */
2670 + dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
2671 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
2672 +
2673 + return 0;
2674 +}
2675 +EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
2676 +
2677 +/* PCI device IRQ mapping. */
2678 +int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
2679 +{
2680 + struct bcma_drv_pci_host *pc_host;
2681 +
2682 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
2683 + /* This is not a device on the PCI-core bridge. */
2684 + return -ENODEV;
2685 + }
2686 +
2687 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
2688 + pci_ops);
2689 + return bcma_core_mips_irq(pc_host->pdev->core) + 2;
2690 }
2691 +EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
2692 --- a/drivers/bcma/host_pci.c
2693 +++ b/drivers/bcma/host_pci.c
2694 @@ -18,7 +18,7 @@ static void bcma_host_pci_switch_core(st
2695 pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
2696 core->wrap);
2697 core->bus->mapped_core = core;
2698 - pr_debug("Switched to core: 0x%X\n", core->id.id);
2699 + bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id);
2700 }
2701
2702 /* Provides access to the requested core. Returns base offset that has to be
2703 @@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct
2704 }
2705
2706 #ifdef CONFIG_BCMA_BLOCKIO
2707 -void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
2708 - size_t count, u16 offset, u8 reg_width)
2709 +static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
2710 + size_t count, u16 offset, u8 reg_width)
2711 {
2712 void __iomem *addr = core->bus->mmio + offset;
2713 if (core->bus->mapped_core != core)
2714 @@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm
2715 }
2716 }
2717
2718 -void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
2719 - size_t count, u16 offset, u8 reg_width)
2720 +static void bcma_host_pci_block_write(struct bcma_device *core,
2721 + const void *buffer, size_t count,
2722 + u16 offset, u8 reg_width)
2723 {
2724 void __iomem *addr = core->bus->mmio + offset;
2725 if (core->bus->mapped_core != core)
2726 @@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc
2727 iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
2728 }
2729
2730 -const struct bcma_host_ops bcma_host_pci_ops = {
2731 +static const struct bcma_host_ops bcma_host_pci_ops = {
2732 .read8 = bcma_host_pci_read8,
2733 .read16 = bcma_host_pci_read16,
2734 .read32 = bcma_host_pci_read32,
2735 @@ -154,8 +155,8 @@ const struct bcma_host_ops bcma_host_pci
2736 .awrite32 = bcma_host_pci_awrite32,
2737 };
2738
2739 -static int bcma_host_pci_probe(struct pci_dev *dev,
2740 - const struct pci_device_id *id)
2741 +static int __devinit bcma_host_pci_probe(struct pci_dev *dev,
2742 + const struct pci_device_id *id)
2743 {
2744 struct bcma_bus *bus;
2745 int err = -ENOMEM;
2746 @@ -188,7 +189,7 @@ static int bcma_host_pci_probe(struct pc
2747
2748 /* SSB needed additional powering up, do we have any AMBA PCI cards? */
2749 if (!pci_is_pcie(dev))
2750 - pr_err("PCI card detected, report problems.\n");
2751 + bcma_err(bus, "PCI card detected, report problems.\n");
2752
2753 /* Map MMIO */
2754 err = -ENOMEM;
2755 @@ -201,6 +202,9 @@ static int bcma_host_pci_probe(struct pc
2756 bus->hosttype = BCMA_HOSTTYPE_PCI;
2757 bus->ops = &bcma_host_pci_ops;
2758
2759 + bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
2760 + bus->boardinfo.type = bus->host_pci->subsystem_device;
2761 +
2762 /* Register */
2763 err = bcma_bus_register(bus);
2764 if (err)
2765 @@ -222,7 +226,7 @@ err_kfree_bus:
2766 return err;
2767 }
2768
2769 -static void bcma_host_pci_remove(struct pci_dev *dev)
2770 +static void __devexit bcma_host_pci_remove(struct pci_dev *dev)
2771 {
2772 struct bcma_bus *bus = pci_get_drvdata(dev);
2773
2774 @@ -234,7 +238,7 @@ static void bcma_host_pci_remove(struct
2775 pci_set_drvdata(dev, NULL);
2776 }
2777
2778 -#ifdef CONFIG_PM
2779 +#ifdef CONFIG_PM_SLEEP
2780 static int bcma_host_pci_suspend(struct device *dev)
2781 {
2782 struct pci_dev *pdev = to_pci_dev(dev);
2783 @@ -257,17 +261,20 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
2784 bcma_host_pci_resume);
2785 #define BCMA_PM_OPS (&bcma_pm_ops)
2786
2787 -#else /* CONFIG_PM */
2788 +#else /* CONFIG_PM_SLEEP */
2789
2790 #define BCMA_PM_OPS NULL
2791
2792 -#endif /* CONFIG_PM */
2793 +#endif /* CONFIG_PM_SLEEP */
2794
2795 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
2796 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
2797 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
2798 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
2799 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
2800 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
2801 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
2802 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
2803 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
2804 { 0, },
2805 };
2806 @@ -277,7 +284,7 @@ static struct pci_driver bcma_pci_bridge
2807 .name = "bcma-pci-bridge",
2808 .id_table = bcma_pci_bridge_tbl,
2809 .probe = bcma_host_pci_probe,
2810 - .remove = bcma_host_pci_remove,
2811 + .remove = __devexit_p(bcma_host_pci_remove),
2812 .driver.pm = BCMA_PM_OPS,
2813 };
2814
2815 --- a/drivers/bcma/host_soc.c
2816 +++ b/drivers/bcma/host_soc.c
2817 @@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc
2818 writel(value, core->io_wrap + offset);
2819 }
2820
2821 -const struct bcma_host_ops bcma_host_soc_ops = {
2822 +static const struct bcma_host_ops bcma_host_soc_ops = {
2823 .read8 = bcma_host_soc_read8,
2824 .read16 = bcma_host_soc_read16,
2825 .read32 = bcma_host_soc_read32,
2826 --- a/drivers/bcma/main.c
2827 +++ b/drivers/bcma/main.c
2828 @@ -7,12 +7,19 @@
2829
2830 #include "bcma_private.h"
2831 #include <linux/module.h>
2832 +#include <linux/platform_device.h>
2833 #include <linux/bcma/bcma.h>
2834 #include <linux/slab.h>
2835
2836 MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
2837 MODULE_LICENSE("GPL");
2838
2839 +/* contains the number the next bus should get. */
2840 +static unsigned int bcma_bus_next_num = 0;
2841 +
2842 +/* bcma_buses_mutex locks the bcma_bus_next_num */
2843 +static DEFINE_MUTEX(bcma_buses_mutex);
2844 +
2845 static int bcma_bus_match(struct device *dev, struct device_driver *drv);
2846 static int bcma_device_probe(struct device *dev);
2847 static int bcma_device_remove(struct device *dev);
2848 @@ -55,7 +62,14 @@ static struct bus_type bcma_bus_type = {
2849 .dev_attrs = bcma_device_attrs,
2850 };
2851
2852 -static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
2853 +static u16 bcma_cc_core_id(struct bcma_bus *bus)
2854 +{
2855 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
2856 + return BCMA_CORE_4706_CHIPCOMMON;
2857 + return BCMA_CORE_CHIPCOMMON;
2858 +}
2859 +
2860 +struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
2861 {
2862 struct bcma_device *core;
2863
2864 @@ -65,6 +79,19 @@ static struct bcma_device *bcma_find_cor
2865 }
2866 return NULL;
2867 }
2868 +EXPORT_SYMBOL_GPL(bcma_find_core);
2869 +
2870 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
2871 + u8 unit)
2872 +{
2873 + struct bcma_device *core;
2874 +
2875 + list_for_each_entry(core, &bus->cores, list) {
2876 + if (core->id.id == coreid && core->core_unit == unit)
2877 + return core;
2878 + }
2879 + return NULL;
2880 +}
2881
2882 static void bcma_release_core_dev(struct device *dev)
2883 {
2884 @@ -84,16 +111,18 @@ static int bcma_register_cores(struct bc
2885 list_for_each_entry(core, &bus->cores, list) {
2886 /* We support that cores ourself */
2887 switch (core->id.id) {
2888 + case BCMA_CORE_4706_CHIPCOMMON:
2889 case BCMA_CORE_CHIPCOMMON:
2890 case BCMA_CORE_PCI:
2891 case BCMA_CORE_PCIE:
2892 case BCMA_CORE_MIPS_74K:
2893 + case BCMA_CORE_4706_MAC_GBIT_COMMON:
2894 continue;
2895 }
2896
2897 core->dev.release = bcma_release_core_dev;
2898 core->dev.bus = &bcma_bus_type;
2899 - dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id);
2900 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
2901
2902 switch (bus->hosttype) {
2903 case BCMA_HOSTTYPE_PCI:
2904 @@ -111,41 +140,90 @@ static int bcma_register_cores(struct bc
2905
2906 err = device_register(&core->dev);
2907 if (err) {
2908 - pr_err("Could not register dev for core 0x%03X\n",
2909 - core->id.id);
2910 + bcma_err(bus,
2911 + "Could not register dev for core 0x%03X\n",
2912 + core->id.id);
2913 continue;
2914 }
2915 core->dev_registered = true;
2916 dev_id++;
2917 }
2918
2919 +#ifdef CONFIG_BCMA_SFLASH
2920 + if (bus->drv_cc.sflash.present) {
2921 + err = platform_device_register(&bcma_sflash_dev);
2922 + if (err)
2923 + bcma_err(bus, "Error registering serial flash\n");
2924 + }
2925 +#endif
2926 +
2927 +#ifdef CONFIG_BCMA_NFLASH
2928 + if (bus->drv_cc.nflash.present) {
2929 + err = platform_device_register(&bcma_nflash_dev);
2930 + if (err)
2931 + bcma_err(bus, "Error registering NAND flash\n");
2932 + }
2933 +#endif
2934 + err = bcma_gpio_init(&bus->drv_cc);
2935 + if (err == -ENOTSUPP)
2936 + bcma_debug(bus, "GPIO driver not activated\n");
2937 + else if (err)
2938 + bcma_err(bus, "Error registering GPIO driver: %i\n", err);
2939 +
2940 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
2941 + err = bcma_chipco_watchdog_register(&bus->drv_cc);
2942 + if (err)
2943 + bcma_err(bus, "Error registering watchdog driver\n");
2944 + }
2945 +
2946 return 0;
2947 }
2948
2949 static void bcma_unregister_cores(struct bcma_bus *bus)
2950 {
2951 - struct bcma_device *core;
2952 + struct bcma_device *core, *tmp;
2953
2954 - list_for_each_entry(core, &bus->cores, list) {
2955 + list_for_each_entry_safe(core, tmp, &bus->cores, list) {
2956 + list_del(&core->list);
2957 if (core->dev_registered)
2958 device_unregister(&core->dev);
2959 }
2960 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
2961 + platform_device_unregister(bus->drv_cc.watchdog);
2962 }
2963
2964 -int bcma_bus_register(struct bcma_bus *bus)
2965 +int __devinit bcma_bus_register(struct bcma_bus *bus)
2966 {
2967 int err;
2968 struct bcma_device *core;
2969
2970 + mutex_lock(&bcma_buses_mutex);
2971 + bus->num = bcma_bus_next_num++;
2972 + mutex_unlock(&bcma_buses_mutex);
2973 +
2974 /* Scan for devices (cores) */
2975 err = bcma_bus_scan(bus);
2976 if (err) {
2977 - pr_err("Failed to scan: %d\n", err);
2978 + bcma_err(bus, "Failed to scan: %d\n", err);
2979 return -1;
2980 }
2981
2982 + /* Early init CC core */
2983 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
2984 + if (core) {
2985 + bus->drv_cc.core = core;
2986 + bcma_core_chipcommon_early_init(&bus->drv_cc);
2987 + }
2988 +
2989 + /* Try to get SPROM */
2990 + err = bcma_sprom_get(bus);
2991 + if (err == -ENOENT) {
2992 + bcma_err(bus, "No SPROM available\n");
2993 + } else if (err)
2994 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
2995 +
2996 /* Init CC core */
2997 - core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
2998 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
2999 if (core) {
3000 bus->drv_cc.core = core;
3001 bcma_core_chipcommon_init(&bus->drv_cc);
3002 @@ -159,30 +237,47 @@ int bcma_bus_register(struct bcma_bus *b
3003 }
3004
3005 /* Init PCIE core */
3006 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
3007 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
3008 if (core) {
3009 - bus->drv_pci.core = core;
3010 - bcma_core_pci_init(&bus->drv_pci);
3011 + bus->drv_pci[0].core = core;
3012 + bcma_core_pci_init(&bus->drv_pci[0]);
3013 }
3014
3015 - /* Try to get SPROM */
3016 - err = bcma_sprom_get(bus);
3017 - if (err == -ENOENT) {
3018 - pr_err("No SPROM available\n");
3019 - } else if (err)
3020 - pr_err("Failed to get SPROM: %d\n", err);
3021 + /* Init PCIE core */
3022 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
3023 + if (core) {
3024 + bus->drv_pci[1].core = core;
3025 + bcma_core_pci_init(&bus->drv_pci[1]);
3026 + }
3027 +
3028 + /* Init GBIT MAC COMMON core */
3029 + core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
3030 + if (core) {
3031 + bus->drv_gmac_cmn.core = core;
3032 + bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
3033 + }
3034
3035 /* Register found cores */
3036 bcma_register_cores(bus);
3037
3038 - pr_info("Bus registered\n");
3039 + bcma_info(bus, "Bus registered\n");
3040
3041 return 0;
3042 }
3043
3044 void bcma_bus_unregister(struct bcma_bus *bus)
3045 {
3046 + struct bcma_device *cores[3];
3047 +
3048 + cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
3049 + cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
3050 + cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
3051 +
3052 bcma_unregister_cores(bus);
3053 +
3054 + kfree(cores[2]);
3055 + kfree(cores[1]);
3056 + kfree(cores[0]);
3057 }
3058
3059 int __init bcma_bus_early_register(struct bcma_bus *bus,
3060 @@ -196,14 +291,14 @@ int __init bcma_bus_early_register(struc
3061 bcma_init_bus(bus);
3062
3063 match.manuf = BCMA_MANUF_BCM;
3064 - match.id = BCMA_CORE_CHIPCOMMON;
3065 + match.id = bcma_cc_core_id(bus);
3066 match.class = BCMA_CL_SIM;
3067 match.rev = BCMA_ANY_REV;
3068
3069 /* Scan for chip common core */
3070 err = bcma_bus_scan_early(bus, &match, core_cc);
3071 if (err) {
3072 - pr_err("Failed to scan for common core: %d\n", err);
3073 + bcma_err(bus, "Failed to scan for common core: %d\n", err);
3074 return -1;
3075 }
3076
3077 @@ -215,25 +310,25 @@ int __init bcma_bus_early_register(struc
3078 /* Scan for mips core */
3079 err = bcma_bus_scan_early(bus, &match, core_mips);
3080 if (err) {
3081 - pr_err("Failed to scan for mips core: %d\n", err);
3082 + bcma_err(bus, "Failed to scan for mips core: %d\n", err);
3083 return -1;
3084 }
3085
3086 - /* Init CC core */
3087 - core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
3088 + /* Early init CC core */
3089 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
3090 if (core) {
3091 bus->drv_cc.core = core;
3092 - bcma_core_chipcommon_init(&bus->drv_cc);
3093 + bcma_core_chipcommon_early_init(&bus->drv_cc);
3094 }
3095
3096 - /* Init MIPS core */
3097 + /* Early init MIPS core */
3098 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
3099 if (core) {
3100 bus->drv_mips.core = core;
3101 - bcma_core_mips_init(&bus->drv_mips);
3102 + bcma_core_mips_early_init(&bus->drv_mips);
3103 }
3104
3105 - pr_info("Early bus registered\n");
3106 + bcma_info(bus, "Early bus registered\n");
3107
3108 return 0;
3109 }
3110 @@ -259,8 +354,7 @@ int bcma_bus_resume(struct bcma_bus *bus
3111 struct bcma_device *core;
3112
3113 /* Init CC core */
3114 - core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
3115 - if (core) {
3116 + if (bus->drv_cc.core) {
3117 bus->drv_cc.setup_done = false;
3118 bcma_core_chipcommon_init(&bus->drv_cc);
3119 }
3120 --- a/drivers/bcma/scan.c
3121 +++ b/drivers/bcma/scan.c
3122 @@ -19,15 +19,27 @@ struct bcma_device_id_name {
3123 u16 id;
3124 const char *name;
3125 };
3126 -struct bcma_device_id_name bcma_device_names[] = {
3127 +
3128 +static const struct bcma_device_id_name bcma_arm_device_names[] = {
3129 + { BCMA_CORE_4706_MAC_GBIT_COMMON, "BCM4706 GBit MAC Common" },
3130 + { BCMA_CORE_ARM_1176, "ARM 1176" },
3131 + { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
3132 + { BCMA_CORE_ARM_CM3, "ARM CM3" },
3133 +};
3134 +
3135 +static const struct bcma_device_id_name bcma_bcm_device_names[] = {
3136 { BCMA_CORE_OOB_ROUTER, "OOB Router" },
3137 + { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
3138 + { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
3139 + { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
3140 + { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
3141 + { BCMA_CORE_ALTA, "ALTA (I2S)" },
3142 { BCMA_CORE_INVALID, "Invalid" },
3143 { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
3144 { BCMA_CORE_ILINE20, "ILine 20" },
3145 { BCMA_CORE_SRAM, "SRAM" },
3146 { BCMA_CORE_SDRAM, "SDRAM" },
3147 { BCMA_CORE_PCI, "PCI" },
3148 - { BCMA_CORE_MIPS, "MIPS" },
3149 { BCMA_CORE_ETHERNET, "Fast Ethernet" },
3150 { BCMA_CORE_V90, "V90" },
3151 { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
3152 @@ -44,7 +56,6 @@ struct bcma_device_id_name bcma_device_n
3153 { BCMA_CORE_PHY_A, "PHY A" },
3154 { BCMA_CORE_PHY_B, "PHY B" },
3155 { BCMA_CORE_PHY_G, "PHY G" },
3156 - { BCMA_CORE_MIPS_3302, "MIPS 3302" },
3157 { BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
3158 { BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
3159 { BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
3160 @@ -58,15 +69,11 @@ struct bcma_device_id_name bcma_device_n
3161 { BCMA_CORE_PHY_N, "PHY N" },
3162 { BCMA_CORE_SRAM_CTL, "SRAM Controller" },
3163 { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
3164 - { BCMA_CORE_ARM_1176, "ARM 1176" },
3165 - { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
3166 { BCMA_CORE_PHY_LP, "PHY LP" },
3167 { BCMA_CORE_PMU, "PMU" },
3168 { BCMA_CORE_PHY_SSN, "PHY SSN" },
3169 { BCMA_CORE_SDIO_DEV, "SDIO Device" },
3170 - { BCMA_CORE_ARM_CM3, "ARM CM3" },
3171 { BCMA_CORE_PHY_HT, "PHY HT" },
3172 - { BCMA_CORE_MIPS_74K, "MIPS 74K" },
3173 { BCMA_CORE_MAC_GBIT, "GBit MAC" },
3174 { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
3175 { BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
3176 @@ -79,16 +86,41 @@ struct bcma_device_id_name bcma_device_n
3177 { BCMA_CORE_SHIM, "SHIM" },
3178 { BCMA_CORE_DEFAULT, "Default" },
3179 };
3180 -const char *bcma_device_name(struct bcma_device_id *id)
3181 +
3182 +static const struct bcma_device_id_name bcma_mips_device_names[] = {
3183 + { BCMA_CORE_MIPS, "MIPS" },
3184 + { BCMA_CORE_MIPS_3302, "MIPS 3302" },
3185 + { BCMA_CORE_MIPS_74K, "MIPS 74K" },
3186 +};
3187 +
3188 +static const char *bcma_device_name(const struct bcma_device_id *id)
3189 {
3190 - int i;
3191 + const struct bcma_device_id_name *names;
3192 + int size, i;
3193
3194 - if (id->manuf == BCMA_MANUF_BCM) {
3195 - for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
3196 - if (bcma_device_names[i].id == id->id)
3197 - return bcma_device_names[i].name;
3198 - }
3199 + /* search manufacturer specific names */
3200 + switch (id->manuf) {
3201 + case BCMA_MANUF_ARM:
3202 + names = bcma_arm_device_names;
3203 + size = ARRAY_SIZE(bcma_arm_device_names);
3204 + break;
3205 + case BCMA_MANUF_BCM:
3206 + names = bcma_bcm_device_names;
3207 + size = ARRAY_SIZE(bcma_bcm_device_names);
3208 + break;
3209 + case BCMA_MANUF_MIPS:
3210 + names = bcma_mips_device_names;
3211 + size = ARRAY_SIZE(bcma_mips_device_names);
3212 + break;
3213 + default:
3214 + return "UNKNOWN";
3215 }
3216 +
3217 + for (i = 0; i < size; i++) {
3218 + if (names[i].id == id->id)
3219 + return names[i].name;
3220 + }
3221 +
3222 return "UNKNOWN";
3223 }
3224
3225 @@ -212,6 +244,17 @@ static struct bcma_device *bcma_find_cor
3226 return NULL;
3227 }
3228
3229 +static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid)
3230 +{
3231 + struct bcma_device *core;
3232 +
3233 + list_for_each_entry_reverse(core, &bus->cores, list) {
3234 + if (core->id.id == coreid)
3235 + return core;
3236 + }
3237 + return NULL;
3238 +}
3239 +
3240 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
3241 struct bcma_device_id *match, int core_num,
3242 struct bcma_device *core)
3243 @@ -252,11 +295,15 @@ static int bcma_get_next_core(struct bcm
3244
3245 /* check if component is a core at all */
3246 if (wrappers[0] + wrappers[1] == 0) {
3247 - /* we could save addrl of the router
3248 - if (cid == BCMA_CORE_OOB_ROUTER)
3249 - */
3250 - bcma_erom_skip_component(bus, eromptr);
3251 - return -ENXIO;
3252 + /* Some specific cores don't need wrappers */
3253 + switch (core->id.id) {
3254 + case BCMA_CORE_4706_MAC_GBIT_COMMON:
3255 + /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
3256 + break;
3257 + default:
3258 + bcma_erom_skip_component(bus, eromptr);
3259 + return -ENXIO;
3260 + }
3261 }
3262
3263 if (bcma_erom_is_bridge(bus, eromptr)) {
3264 @@ -286,6 +333,23 @@ static int bcma_get_next_core(struct bcm
3265 return -EILSEQ;
3266 }
3267
3268 + /* First Slave Address Descriptor should be port 0:
3269 + * the main register space for the core
3270 + */
3271 + tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
3272 + if (tmp <= 0) {
3273 + /* Try again to see if it is a bridge */
3274 + tmp = bcma_erom_get_addr_desc(bus, eromptr,
3275 + SCAN_ADDR_TYPE_BRIDGE, 0);
3276 + if (tmp <= 0) {
3277 + return -EILSEQ;
3278 + } else {
3279 + bcma_info(bus, "Bridge found\n");
3280 + return -ENXIO;
3281 + }
3282 + }
3283 + core->addr = tmp;
3284 +
3285 /* get & parse slave ports */
3286 for (i = 0; i < ports[1]; i++) {
3287 for (j = 0; ; j++) {
3288 @@ -298,7 +362,7 @@ static int bcma_get_next_core(struct bcm
3289 break;
3290 } else {
3291 if (i == 0 && j == 0)
3292 - core->addr = tmp;
3293 + core->addr1 = tmp;
3294 }
3295 }
3296 }
3297 @@ -353,6 +417,7 @@ static int bcma_get_next_core(struct bcm
3298 void bcma_init_bus(struct bcma_bus *bus)
3299 {
3300 s32 tmp;
3301 + struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
3302
3303 if (bus->init_done)
3304 return;
3305 @@ -363,9 +428,12 @@ void bcma_init_bus(struct bcma_bus *bus)
3306 bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
3307
3308 tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
3309 - bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
3310 - bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
3311 - bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
3312 + chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
3313 + chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
3314 + chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
3315 + bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
3316 + chipinfo->id, chipinfo->rev, chipinfo->pkg);
3317 +
3318 bus->init_done = true;
3319 }
3320
3321 @@ -392,9 +460,12 @@ int bcma_bus_scan(struct bcma_bus *bus)
3322 bcma_scan_switch_core(bus, erombase);
3323
3324 while (eromptr < eromend) {
3325 + struct bcma_device *other_core;
3326 struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
3327 - if (!core)
3328 - return -ENOMEM;
3329 + if (!core) {
3330 + err = -ENOMEM;
3331 + goto out;
3332 + }
3333 INIT_LIST_HEAD(&core->list);
3334 core->bus = bus;
3335
3336 @@ -409,25 +480,28 @@ int bcma_bus_scan(struct bcma_bus *bus)
3337 } else if (err == -ESPIPE) {
3338 break;
3339 }
3340 - return err;
3341 + goto out;
3342 }
3343
3344 core->core_index = core_num++;
3345 bus->nr_cores++;
3346 + other_core = bcma_find_core_reverse(bus, core->id.id);
3347 + core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
3348
3349 - pr_info("Core %d found: %s "
3350 - "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3351 - core->core_index, bcma_device_name(&core->id),
3352 - core->id.manuf, core->id.id, core->id.rev,
3353 - core->id.class);
3354 + bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3355 + core->core_index, bcma_device_name(&core->id),
3356 + core->id.manuf, core->id.id, core->id.rev,
3357 + core->id.class);
3358
3359 - list_add(&core->list, &bus->cores);
3360 + list_add_tail(&core->list, &bus->cores);
3361 }
3362
3363 + err = 0;
3364 +out:
3365 if (bus->hosttype == BCMA_HOSTTYPE_SOC)
3366 iounmap(eromptr);
3367
3368 - return 0;
3369 + return err;
3370 }
3371
3372 int __init bcma_bus_scan_early(struct bcma_bus *bus,
3373 @@ -467,21 +541,21 @@ int __init bcma_bus_scan_early(struct bc
3374 else if (err == -ESPIPE)
3375 break;
3376 else if (err < 0)
3377 - return err;
3378 + goto out;
3379
3380 core->core_index = core_num++;
3381 bus->nr_cores++;
3382 - pr_info("Core %d found: %s "
3383 - "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3384 - core->core_index, bcma_device_name(&core->id),
3385 - core->id.manuf, core->id.id, core->id.rev,
3386 - core->id.class);
3387 + bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
3388 + core->core_index, bcma_device_name(&core->id),
3389 + core->id.manuf, core->id.id, core->id.rev,
3390 + core->id.class);
3391
3392 - list_add(&core->list, &bus->cores);
3393 + list_add_tail(&core->list, &bus->cores);
3394 err = 0;
3395 break;
3396 }
3397
3398 +out:
3399 if (bus->hosttype == BCMA_HOSTTYPE_SOC)
3400 iounmap(eromptr);
3401
3402 --- a/drivers/bcma/scan.h
3403 +++ b/drivers/bcma/scan.h
3404 @@ -27,7 +27,7 @@
3405 #define SCAN_CIB_NMW 0x0007C000
3406 #define SCAN_CIB_NMW_SHIFT 14
3407 #define SCAN_CIB_NSW 0x00F80000
3408 -#define SCAN_CIB_NSW_SHIFT 17
3409 +#define SCAN_CIB_NSW_SHIFT 19
3410 #define SCAN_CIB_REV 0xFF000000
3411 #define SCAN_CIB_REV_SHIFT 24
3412
3413 --- a/drivers/bcma/sprom.c
3414 +++ b/drivers/bcma/sprom.c
3415 @@ -2,6 +2,8 @@
3416 * Broadcom specific AMBA
3417 * SPROM reading
3418 *
3419 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
3420 + *
3421 * Licensed under the GNU/GPL. See COPYING for details.
3422 */
3423
3424 @@ -14,7 +16,57 @@
3425 #include <linux/dma-mapping.h>
3426 #include <linux/slab.h>
3427
3428 -#define SPOFF(offset) ((offset) / sizeof(u16))
3429 +static int(*get_fallback_sprom)(struct bcma_bus *dev, struct ssb_sprom *out);
3430 +
3431 +/**
3432 + * bcma_arch_register_fallback_sprom - Registers a method providing a
3433 + * fallback SPROM if no SPROM is found.
3434 + *
3435 + * @sprom_callback: The callback function.
3436 + *
3437 + * With this function the architecture implementation may register a
3438 + * callback handler which fills the SPROM data structure. The fallback is
3439 + * used for PCI based BCMA devices, where no valid SPROM can be found
3440 + * in the shadow registers and to provide the SPROM for SoCs where BCMA is
3441 + * to controll the system bus.
3442 + *
3443 + * This function is useful for weird architectures that have a half-assed
3444 + * BCMA device hardwired to their PCI bus.
3445 + *
3446 + * This function is available for architecture code, only. So it is not
3447 + * exported.
3448 + */
3449 +int bcma_arch_register_fallback_sprom(int (*sprom_callback)(struct bcma_bus *bus,
3450 + struct ssb_sprom *out))
3451 +{
3452 + if (get_fallback_sprom)
3453 + return -EEXIST;
3454 + get_fallback_sprom = sprom_callback;
3455 +
3456 + return 0;
3457 +}
3458 +
3459 +static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus,
3460 + struct ssb_sprom *out)
3461 +{
3462 + int err;
3463 +
3464 + if (!get_fallback_sprom) {
3465 + err = -ENOENT;
3466 + goto fail;
3467 + }
3468 +
3469 + err = get_fallback_sprom(bus, out);
3470 + if (err)
3471 + goto fail;
3472 +
3473 + bcma_debug(bus, "Using SPROM revision %d provided by platform.\n",
3474 + bus->sprom.revision);
3475 + return 0;
3476 +fail:
3477 + bcma_warn(bus, "Using fallback SPROM failed (err %d)\n", err);
3478 + return err;
3479 +}
3480
3481 /**************************************************
3482 * R/W ops.
3483 @@ -124,10 +176,37 @@ static int bcma_sprom_valid(const u16 *s
3484 * SPROM extraction.
3485 **************************************************/
3486
3487 +#define SPOFF(offset) ((offset) / sizeof(u16))
3488 +
3489 +#define SPEX(_field, _offset, _mask, _shift) \
3490 + bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
3491 +
3492 +#define SPEX32(_field, _offset, _mask, _shift) \
3493 + bus->sprom._field = ((((u32)sprom[SPOFF((_offset)+2)] << 16 | \
3494 + sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))
3495 +
3496 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
3497 + do { \
3498 + SPEX(_field[0], _offset + 0, _mask, _shift); \
3499 + SPEX(_field[1], _offset + 2, _mask, _shift); \
3500 + SPEX(_field[2], _offset + 4, _mask, _shift); \
3501 + SPEX(_field[3], _offset + 6, _mask, _shift); \
3502 + SPEX(_field[4], _offset + 8, _mask, _shift); \
3503 + SPEX(_field[5], _offset + 10, _mask, _shift); \
3504 + SPEX(_field[6], _offset + 12, _mask, _shift); \
3505 + SPEX(_field[7], _offset + 14, _mask, _shift); \
3506 + } while (0)
3507 +
3508 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
3509 {
3510 - u16 v;
3511 + u16 v, o;
3512 int i;
3513 + u16 pwr_info_offset[] = {
3514 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
3515 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
3516 + };
3517 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
3518 + ARRAY_SIZE(bus->sprom.core_pwr_info));
3519
3520 bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
3521 SSB_SPROM_REVISION_REV;
3522 @@ -137,107 +216,390 @@ static void bcma_sprom_extract_r8(struct
3523 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
3524 }
3525
3526 - bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)];
3527 + SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
3528 +
3529 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
3530 + SSB_SPROM4_TXPID2G0_SHIFT);
3531 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G1,
3532 + SSB_SPROM4_TXPID2G1_SHIFT);
3533 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G2,
3534 + SSB_SPROM4_TXPID2G2_SHIFT);
3535 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G3,
3536 + SSB_SPROM4_TXPID2G3_SHIFT);
3537 +
3538 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL0,
3539 + SSB_SPROM4_TXPID5GL0_SHIFT);
3540 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL1,
3541 + SSB_SPROM4_TXPID5GL1_SHIFT);
3542 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL2,
3543 + SSB_SPROM4_TXPID5GL2_SHIFT);
3544 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL3,
3545 + SSB_SPROM4_TXPID5GL3_SHIFT);
3546 +
3547 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G0,
3548 + SSB_SPROM4_TXPID5G0_SHIFT);
3549 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G1,
3550 + SSB_SPROM4_TXPID5G1_SHIFT);
3551 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G2,
3552 + SSB_SPROM4_TXPID5G2_SHIFT);
3553 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G3,
3554 + SSB_SPROM4_TXPID5G3_SHIFT);
3555 +
3556 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH0,
3557 + SSB_SPROM4_TXPID5GH0_SHIFT);
3558 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH1,
3559 + SSB_SPROM4_TXPID5GH1_SHIFT);
3560 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH2,
3561 + SSB_SPROM4_TXPID5GH2_SHIFT);
3562 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH3,
3563 + SSB_SPROM4_TXPID5GH3_SHIFT);
3564 +
3565 + SPEX(boardflags_lo, SSB_SPROM8_BFLLO, ~0, 0);
3566 + SPEX(boardflags_hi, SSB_SPROM8_BFLHI, ~0, 0);
3567 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, ~0, 0);
3568 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, ~0, 0);
3569 +
3570 + SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
3571 + SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
3572 +
3573 + /* Extract cores power info info */
3574 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
3575 + o = pwr_info_offset[i];
3576 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
3577 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
3578 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
3579 + SSB_SPROM8_2G_MAXP, 0);
3580 +
3581 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
3582 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
3583 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
3584 +
3585 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
3586 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
3587 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
3588 + SSB_SPROM8_5G_MAXP, 0);
3589 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
3590 + SSB_SPROM8_5GH_MAXP, 0);
3591 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
3592 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
3593 +
3594 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
3595 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
3596 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
3597 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
3598 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
3599 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
3600 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
3601 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
3602 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
3603 + }
3604
3605 - bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
3606 - SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT;
3607 - bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
3608 - SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT;
3609 - bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
3610 - SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT;
3611 - bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
3612 - SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT;
3613 -
3614 - bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
3615 - SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT;
3616 - bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
3617 - SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT;
3618 - bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
3619 - SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT;
3620 - bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
3621 - SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT;
3622 -
3623 - bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
3624 - SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT;
3625 - bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
3626 - SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT;
3627 - bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
3628 - SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT;
3629 - bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
3630 - SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT;
3631 -
3632 - bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
3633 - SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT;
3634 - bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
3635 - SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT;
3636 - bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
3637 - SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT;
3638 - bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
3639 - SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT;
3640 -
3641 - bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
3642 - bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
3643 - bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
3644 - bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
3645 -
3646 - bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
3647 -
3648 - bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3649 - SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
3650 - bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3651 - SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
3652 - bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3653 - SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
3654 - bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3655 - SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
3656 - bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3657 - SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
3658 -
3659 - bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3660 - SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
3661 - bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3662 - SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
3663 - bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3664 - SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
3665 - bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3666 - SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
3667 - bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3668 - SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
3669 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TSSIPOS,
3670 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
3671 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_EXTPA_GAIN,
3672 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
3673 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_PDET_RANGE,
3674 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
3675 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TR_ISO,
3676 + SSB_SROM8_FEM_TR_ISO_SHIFT);
3677 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_ANTSWLUT,
3678 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
3679 +
3680 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TSSIPOS,
3681 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
3682 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_EXTPA_GAIN,
3683 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
3684 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_PDET_RANGE,
3685 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
3686 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TR_ISO,
3687 + SSB_SROM8_FEM_TR_ISO_SHIFT);
3688 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_ANTSWLUT,
3689 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
3690 +
3691 + SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
3692 + SSB_SPROM8_ANTAVAIL_A_SHIFT);
3693 + SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
3694 + SSB_SPROM8_ANTAVAIL_BG_SHIFT);
3695 + SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
3696 + SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
3697 + SSB_SPROM8_ITSSI_BG_SHIFT);
3698 + SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
3699 + SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
3700 + SSB_SPROM8_ITSSI_A_SHIFT);
3701 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
3702 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
3703 + SSB_SPROM8_MAXP_AL_SHIFT);
3704 + SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
3705 + SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
3706 + SSB_SPROM8_GPIOA_P1_SHIFT);
3707 + SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
3708 + SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
3709 + SSB_SPROM8_GPIOB_P3_SHIFT);
3710 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
3711 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
3712 + SSB_SPROM8_TRI5G_SHIFT);
3713 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
3714 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
3715 + SSB_SPROM8_TRI5GH_SHIFT);
3716 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G,
3717 + SSB_SPROM8_RXPO2G_SHIFT);
3718 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
3719 + SSB_SPROM8_RXPO5G_SHIFT);
3720 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
3721 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
3722 + SSB_SPROM8_RSSISMC2G_SHIFT);
3723 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
3724 + SSB_SPROM8_RSSISAV2G_SHIFT);
3725 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
3726 + SSB_SPROM8_BXA2G_SHIFT);
3727 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
3728 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
3729 + SSB_SPROM8_RSSISMC5G_SHIFT);
3730 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
3731 + SSB_SPROM8_RSSISAV5G_SHIFT);
3732 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
3733 + SSB_SPROM8_BXA5G_SHIFT);
3734 +
3735 + SPEX(pa0b0, SSB_SPROM8_PA0B0, ~0, 0);
3736 + SPEX(pa0b1, SSB_SPROM8_PA0B1, ~0, 0);
3737 + SPEX(pa0b2, SSB_SPROM8_PA0B2, ~0, 0);
3738 + SPEX(pa1b0, SSB_SPROM8_PA1B0, ~0, 0);
3739 + SPEX(pa1b1, SSB_SPROM8_PA1B1, ~0, 0);
3740 + SPEX(pa1b2, SSB_SPROM8_PA1B2, ~0, 0);
3741 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, ~0, 0);
3742 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, ~0, 0);
3743 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, ~0, 0);
3744 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, ~0, 0);
3745 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, ~0, 0);
3746 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, ~0, 0);
3747 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, ~0, 0);
3748 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, ~0, 0);
3749 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, ~0, 0);
3750 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, ~0, 0);
3751 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
3752 +
3753 + /* Extract the antenna gain values. */
3754 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
3755 + SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
3756 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
3757 + SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
3758 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
3759 + SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
3760 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
3761 + SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
3762 +
3763 + SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
3764 + SSB_SPROM8_LEDDC_ON_SHIFT);
3765 + SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
3766 + SSB_SPROM8_LEDDC_OFF_SHIFT);
3767 +
3768 + SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
3769 + SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
3770 + SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
3771 + SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
3772 + SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
3773 + SSB_SPROM8_TXRXC_SWITCH_SHIFT);
3774 +
3775 + SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
3776 +
3777 + SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
3778 + SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
3779 + SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
3780 + SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
3781 +
3782 + SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
3783 + SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
3784 + SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
3785 + SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
3786 + SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
3787 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
3788 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
3789 + SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
3790 + SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
3791 + SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
3792 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
3793 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
3794 + SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
3795 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
3796 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
3797 + SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
3798 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
3799 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
3800 + SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
3801 + SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
3802 +
3803 + SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
3804 + SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
3805 + SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
3806 + SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
3807 +
3808 + SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
3809 + SSB_SPROM8_THERMAL_TRESH_SHIFT);
3810 + SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
3811 + SSB_SPROM8_THERMAL_OFFSET_SHIFT);
3812 + SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
3813 + SSB_SPROM8_TEMPDELTA_PHYCAL,
3814 + SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
3815 + SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
3816 + SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
3817 + SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
3818 + SSB_SPROM8_TEMPDELTA_HYSTERESIS,
3819 + SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
3820 +}
3821 +
3822 +/*
3823 + * Indicates the presence of external SPROM.
3824 + */
3825 +static bool bcma_sprom_ext_available(struct bcma_bus *bus)
3826 +{
3827 + u32 chip_status;
3828 + u32 srom_control;
3829 + u32 present_mask;
3830 +
3831 + if (bus->drv_cc.core->id.rev >= 31) {
3832 + if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
3833 + return false;
3834 +
3835 + srom_control = bcma_read32(bus->drv_cc.core,
3836 + BCMA_CC_SROM_CONTROL);
3837 + return srom_control & BCMA_CC_SROM_CONTROL_PRESENT;
3838 + }
3839 +
3840 + /* older chipcommon revisions use chip status register */
3841 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
3842 + switch (bus->chipinfo.id) {
3843 + case BCMA_CHIP_ID_BCM4313:
3844 + present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT;
3845 + break;
3846 +
3847 + case BCMA_CHIP_ID_BCM4331:
3848 + present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT;
3849 + break;
3850 +
3851 + default:
3852 + return true;
3853 + }
3854 +
3855 + return chip_status & present_mask;
3856 +}
3857 +
3858 +/*
3859 + * Indicates that on-chip OTP memory is present and enabled.
3860 + */
3861 +static bool bcma_sprom_onchip_available(struct bcma_bus *bus)
3862 +{
3863 + u32 chip_status;
3864 + u32 otpsize = 0;
3865 + bool present;
3866 +
3867 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
3868 + switch (bus->chipinfo.id) {
3869 + case BCMA_CHIP_ID_BCM4313:
3870 + present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT;
3871 + break;
3872 +
3873 + case BCMA_CHIP_ID_BCM4331:
3874 + present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
3875 + break;
3876 +
3877 + case BCMA_CHIP_ID_BCM43224:
3878 + case BCMA_CHIP_ID_BCM43225:
3879 + /* for these chips OTP is always available */
3880 + present = true;
3881 + break;
3882 + case BCMA_CHIP_ID_BCM43227:
3883 + case BCMA_CHIP_ID_BCM43228:
3884 + case BCMA_CHIP_ID_BCM43428:
3885 + present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT;
3886 + break;
3887 + default:
3888 + present = false;
3889 + break;
3890 + }
3891 +
3892 + if (present) {
3893 + otpsize = bus->drv_cc.capabilities & BCMA_CC_CAP_OTPS;
3894 + otpsize >>= BCMA_CC_CAP_OTPS_SHIFT;
3895 + }
3896 +
3897 + return otpsize != 0;
3898 +}
3899 +
3900 +/*
3901 + * Verify OTP is filled and determine the byte
3902 + * offset where SPROM data is located.
3903 + *
3904 + * On error, returns 0; byte offset otherwise.
3905 + */
3906 +static int bcma_sprom_onchip_offset(struct bcma_bus *bus)
3907 +{
3908 + struct bcma_device *cc = bus->drv_cc.core;
3909 + u32 offset;
3910 +
3911 + /* verify OTP status */
3912 + if ((bcma_read32(cc, BCMA_CC_OTPS) & BCMA_CC_OTPS_GU_PROG_HW) == 0)
3913 + return 0;
3914 +
3915 + /* obtain bit offset from otplayout register */
3916 + offset = (bcma_read32(cc, BCMA_CC_OTPL) & BCMA_CC_OTPL_GURGN_OFFSET);
3917 + return BCMA_CC_SPROM + (offset >> 3);
3918 }
3919
3920 int bcma_sprom_get(struct bcma_bus *bus)
3921 {
3922 - u16 offset;
3923 + u16 offset = BCMA_CC_SPROM;
3924 u16 *sprom;
3925 int err = 0;
3926
3927 if (!bus->drv_cc.core)
3928 return -EOPNOTSUPP;
3929
3930 - if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
3931 - return -ENOENT;
3932 + if (!bcma_sprom_ext_available(bus)) {
3933 + bool sprom_onchip;
3934 +
3935 + /*
3936 + * External SPROM takes precedence so check
3937 + * on-chip OTP only when no external SPROM
3938 + * is present.
3939 + */
3940 + sprom_onchip = bcma_sprom_onchip_available(bus);
3941 + if (sprom_onchip) {
3942 + /* determine offset */
3943 + offset = bcma_sprom_onchip_offset(bus);
3944 + }
3945 + if (!offset || !sprom_onchip) {
3946 + /*
3947 + * Maybe there is no SPROM on the device?
3948 + * Now we ask the arch code if there is some sprom
3949 + * available for this device in some other storage.
3950 + */
3951 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
3952 + return err;
3953 + }
3954 + }
3955
3956 sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
3957 GFP_KERNEL);
3958 if (!sprom)
3959 return -ENOMEM;
3960
3961 - if (bus->chipinfo.id == 0x4331)
3962 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
3963 + bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
3964 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
3965
3966 - /* Most cards have SPROM moved by additional offset 0x30 (48 dwords).
3967 - * According to brcm80211 this applies to cards with PCIe rev >= 6
3968 - * TODO: understand this condition and use it */
3969 - offset = (bus->chipinfo.id == 0x4331) ? BCMA_CC_SPROM :
3970 - BCMA_CC_SPROM_PCIE6;
3971 + bcma_debug(bus, "SPROM offset 0x%x\n", offset);
3972 bcma_sprom_read(bus, offset, sprom);
3973
3974 - if (bus->chipinfo.id == 0x4331)
3975 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
3976 + bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
3977 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
3978
3979 err = bcma_sprom_valid(sprom);
3980 - if (err)
3981 + if (err) {
3982 + bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
3983 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
3984 goto out;
3985 + }
3986
3987 bcma_sprom_extract_r8(bus, sprom);
3988
3989 --- a/include/linux/bcma/bcma.h
3990 +++ b/include/linux/bcma/bcma.h
3991 @@ -7,9 +7,10 @@
3992 #include <linux/bcma/bcma_driver_chipcommon.h>
3993 #include <linux/bcma/bcma_driver_pci.h>
3994 #include <linux/bcma/bcma_driver_mips.h>
3995 +#include <linux/bcma/bcma_driver_gmac_cmn.h>
3996 #include <linux/ssb/ssb.h> /* SPROM sharing */
3997
3998 -#include "bcma_regs.h"
3999 +#include <linux/bcma/bcma_regs.h>
4000
4001 struct bcma_device;
4002 struct bcma_bus;
4003 @@ -26,6 +27,11 @@ struct bcma_chipinfo {
4004 u8 pkg;
4005 };
4006
4007 +struct bcma_boardinfo {
4008 + u16 vendor;
4009 + u16 type;
4010 +};
4011 +
4012 enum bcma_clkmode {
4013 BCMA_CLKMODE_FAST,
4014 BCMA_CLKMODE_DYNAMIC,
4015 @@ -65,6 +71,13 @@ struct bcma_host_ops {
4016
4017 /* Core-ID values. */
4018 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
4019 +#define BCMA_CORE_4706_CHIPCOMMON 0x500
4020 +#define BCMA_CORE_4706_SOC_RAM 0x50E
4021 +#define BCMA_CORE_4706_MAC_GBIT 0x52D
4022 +#define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
4023 +#define BCMA_CORE_ALTA 0x534 /* I2S core */
4024 +#define BCMA_CORE_4706_MAC_GBIT_COMMON 0x5DC
4025 +#define BCMA_CORE_DDR23_PHY 0x5DD
4026 #define BCMA_CORE_INVALID 0x700
4027 #define BCMA_CORE_CHIPCOMMON 0x800
4028 #define BCMA_CORE_ILINE20 0x801
4029 @@ -125,6 +138,41 @@ struct bcma_host_ops {
4030
4031 #define BCMA_MAX_NR_CORES 16
4032
4033 +/* Chip IDs of PCIe devices */
4034 +#define BCMA_CHIP_ID_BCM4313 0x4313
4035 +#define BCMA_CHIP_ID_BCM43224 43224
4036 +#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
4037 +#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
4038 +#define BCMA_CHIP_ID_BCM43225 43225
4039 +#define BCMA_CHIP_ID_BCM43227 43227
4040 +#define BCMA_CHIP_ID_BCM43228 43228
4041 +#define BCMA_CHIP_ID_BCM43421 43421
4042 +#define BCMA_CHIP_ID_BCM43428 43428
4043 +#define BCMA_CHIP_ID_BCM43431 43431
4044 +#define BCMA_CHIP_ID_BCM43460 43460
4045 +#define BCMA_CHIP_ID_BCM4331 0x4331
4046 +#define BCMA_CHIP_ID_BCM6362 0x6362
4047 +#define BCMA_CHIP_ID_BCM4360 0x4360
4048 +#define BCMA_CHIP_ID_BCM4352 0x4352
4049 +
4050 +/* Chip IDs of SoCs */
4051 +#define BCMA_CHIP_ID_BCM4706 0x5300
4052 +#define BCMA_PKG_ID_BCM4706L 1
4053 +#define BCMA_CHIP_ID_BCM4716 0x4716
4054 +#define BCMA_PKG_ID_BCM4716 8
4055 +#define BCMA_PKG_ID_BCM4717 9
4056 +#define BCMA_PKG_ID_BCM4718 10
4057 +#define BCMA_CHIP_ID_BCM47162 47162
4058 +#define BCMA_CHIP_ID_BCM4748 0x4748
4059 +#define BCMA_CHIP_ID_BCM4749 0x4749
4060 +#define BCMA_CHIP_ID_BCM5356 0x5356
4061 +#define BCMA_CHIP_ID_BCM5357 0x5357
4062 +#define BCMA_PKG_ID_BCM5358 9
4063 +#define BCMA_PKG_ID_BCM47186 10
4064 +#define BCMA_PKG_ID_BCM5357 11
4065 +#define BCMA_CHIP_ID_BCM53572 53572
4066 +#define BCMA_PKG_ID_BCM47188 9
4067 +
4068 struct bcma_device {
4069 struct bcma_bus *bus;
4070 struct bcma_device_id id;
4071 @@ -136,8 +184,10 @@ struct bcma_device {
4072 bool dev_registered;
4073
4074 u8 core_index;
4075 + u8 core_unit;
4076
4077 u32 addr;
4078 + u32 addr1;
4079 u32 wrap;
4080
4081 void __iomem *io_addr;
4082 @@ -175,6 +225,12 @@ int __bcma_driver_register(struct bcma_d
4083
4084 extern void bcma_driver_unregister(struct bcma_driver *drv);
4085
4086 +/* Set a fallback SPROM.
4087 + * See kdoc at the function definition for complete documentation. */
4088 +extern int bcma_arch_register_fallback_sprom(
4089 + int (*sprom_callback)(struct bcma_bus *bus,
4090 + struct ssb_sprom *out));
4091 +
4092 struct bcma_bus {
4093 /* The MMIO area. */
4094 void __iomem *mmio;
4095 @@ -191,14 +247,18 @@ struct bcma_bus {
4096
4097 struct bcma_chipinfo chipinfo;
4098
4099 + struct bcma_boardinfo boardinfo;
4100 +
4101 struct bcma_device *mapped_core;
4102 struct list_head cores;
4103 u8 nr_cores;
4104 u8 init_done:1;
4105 + u8 num;
4106
4107 struct bcma_drv_cc drv_cc;
4108 - struct bcma_drv_pci drv_pci;
4109 + struct bcma_drv_pci drv_pci[2];
4110 struct bcma_drv_mips drv_mips;
4111 + struct bcma_drv_gmac_cmn drv_gmac_cmn;
4112
4113 /* We decided to share SPROM struct with SSB as long as we do not need
4114 * any hacks for BCMA. This simplifies drivers code. */
4115 @@ -282,6 +342,7 @@ static inline void bcma_maskset16(struct
4116 bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
4117 }
4118
4119 +extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
4120 extern bool bcma_core_is_enabled(struct bcma_device *core);
4121 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
4122 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
4123 @@ -289,6 +350,7 @@ extern void bcma_core_set_clockmode(stru
4124 enum bcma_clkmode clkmode);
4125 extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
4126 bool on);
4127 +extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
4128 #define BCMA_DMA_TRANSLATION_MASK 0xC0000000
4129 #define BCMA_DMA_TRANSLATION_NONE 0x00000000
4130 #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
4131 --- a/include/linux/bcma/bcma_driver_chipcommon.h
4132 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
4133 @@ -1,6 +1,9 @@
4134 #ifndef LINUX_BCMA_DRIVER_CC_H_
4135 #define LINUX_BCMA_DRIVER_CC_H_
4136
4137 +#include <linux/platform_device.h>
4138 +#include <linux/gpio.h>
4139 +
4140 /** ChipCommon core registers. **/
4141 #define BCMA_CC_ID 0x0000
4142 #define BCMA_CC_ID_ID 0x0000FFFF
4143 @@ -24,7 +27,7 @@
4144 #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
4145 #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
4146 #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
4147 -#define BCMA_CC_FLASHT_NFLASH 0x00000200
4148 +#define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */
4149 #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
4150 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
4151 #define BCMA_PLLTYPE_NONE 0x00000000
4152 @@ -45,6 +48,7 @@
4153 #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
4154 #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
4155 #define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
4156 +#define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */
4157 #define BCMA_CC_CORECTL 0x0008
4158 #define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
4159 #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
4160 @@ -56,6 +60,9 @@
4161 #define BCMA_CC_OTPS_HW_PROTECT 0x00000001
4162 #define BCMA_CC_OTPS_SW_PROTECT 0x00000002
4163 #define BCMA_CC_OTPS_CID_PROTECT 0x00000004
4164 +#define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */
4165 +#define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8
4166 +#define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */
4167 #define BCMA_CC_OTPC 0x0014 /* OTP control */
4168 #define BCMA_CC_OTPC_RECWAIT 0xFF000000
4169 #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
4170 @@ -72,6 +79,8 @@
4171 #define BCMA_CC_OTPP_READ 0x40000000
4172 #define BCMA_CC_OTPP_START 0x80000000
4173 #define BCMA_CC_OTPP_BUSY 0x80000000
4174 +#define BCMA_CC_OTPL 0x001C /* OTP layout */
4175 +#define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
4176 #define BCMA_CC_IRQSTAT 0x0020
4177 #define BCMA_CC_IRQMASK 0x0024
4178 #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
4179 @@ -79,6 +88,22 @@
4180 #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
4181 #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
4182 #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
4183 +#define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
4184 +#define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
4185 +#define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
4186 +#define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
4187 +#define BCMA_CC_CHIPST_43228_ILP_DIV_EN 0x00000001
4188 +#define BCMA_CC_CHIPST_43228_OTP_PRESENT 0x00000002
4189 +#define BCMA_CC_CHIPST_43228_SERDES_REFCLK_PADSEL 0x00000004
4190 +#define BCMA_CC_CHIPST_43228_SDIO_MODE 0x00000008
4191 +#define BCMA_CC_CHIPST_43228_SDIO_OTP_PRESENT 0x00000010
4192 +#define BCMA_CC_CHIPST_43228_SDIO_RESET 0x00000020
4193 +#define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
4194 +#define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
4195 +#define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
4196 +#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
4197 +#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
4198 +#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
4199 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
4200 #define BCMA_CC_JCMD_START 0x80000000
4201 #define BCMA_CC_JCMD_BUSY 0x80000000
4202 @@ -108,10 +133,58 @@
4203 #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
4204 #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
4205 #define BCMA_CC_FLASHCTL 0x0040
4206 +/* Start/busy bit in flashcontrol */
4207 +#define BCMA_CC_FLASHCTL_OPCODE 0x000000ff
4208 +#define BCMA_CC_FLASHCTL_ACTION 0x00000700
4209 +#define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
4210 #define BCMA_CC_FLASHCTL_START 0x80000000
4211 #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
4212 +/* Flashcontrol action + opcodes for ST flashes */
4213 +#define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
4214 +#define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
4215 +#define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
4216 +#define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
4217 +#define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
4218 +#define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */
4219 +#define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */
4220 +#define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */
4221 +#define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
4222 +#define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */
4223 +#define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
4224 +#define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
4225 +/* Flashcontrol action + opcodes for Atmel flashes */
4226 +#define BCMA_CC_FLASHCTL_AT_READ 0x07e8
4227 +#define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2
4228 +#define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7
4229 +#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384
4230 +#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387
4231 +#define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283
4232 +#define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286
4233 +#define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288
4234 +#define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289
4235 +#define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281
4236 +#define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250
4237 +#define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
4238 +#define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
4239 +#define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253
4240 +#define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255
4241 +#define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260
4242 +#define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261
4243 +#define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
4244 +#define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
4245 #define BCMA_CC_FLASHADDR 0x0044
4246 #define BCMA_CC_FLASHDATA 0x0048
4247 +/* Status register bits for ST flashes */
4248 +#define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */
4249 +#define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */
4250 +#define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */
4251 +#define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2
4252 +#define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */
4253 +/* Status register bits for Atmel flashes */
4254 +#define BCMA_CC_FLASHDATA_AT_READY 0x80
4255 +#define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40
4256 +#define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38
4257 +#define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3
4258 #define BCMA_CC_BCAST_ADDR 0x0050
4259 #define BCMA_CC_BCAST_DATA 0x0054
4260 #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
4261 @@ -181,6 +254,45 @@
4262 #define BCMA_CC_FLASH_CFG 0x0128
4263 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
4264 #define BCMA_CC_FLASH_WAITCNT 0x012C
4265 +#define BCMA_CC_SROM_CONTROL 0x0190
4266 +#define BCMA_CC_SROM_CONTROL_START 0x80000000
4267 +#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
4268 +#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
4269 +#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
4270 +#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
4271 +#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
4272 +#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
4273 +#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
4274 +#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
4275 +#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
4276 +#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
4277 +#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
4278 +#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
4279 +#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
4280 +#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
4281 +/* Block 0x140 - 0x190 registers are chipset specific */
4282 +#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
4283 +#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
4284 +#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
4285 +#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
4286 +#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
4287 +#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
4288 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
4289 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
4290 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
4291 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
4292 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
4293 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
4294 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
4295 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
4296 +/* NAND flash registers for BCM4706 (corerev = 31) */
4297 +#define BCMA_CC_NFLASH_CTL 0x01A0
4298 +#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
4299 +#define BCMA_CC_NFLASH_CONF 0x01A4
4300 +#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
4301 +#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
4302 +#define BCMA_CC_NFLASH_DATA 0x01B0
4303 +#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
4304 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
4305 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
4306 #define BCMA_CC_UART0_DATA 0x0300
4307 @@ -240,7 +352,60 @@
4308 #define BCMA_CC_PLLCTL_ADDR 0x0660
4309 #define BCMA_CC_PLLCTL_DATA 0x0664
4310 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
4311 -#define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */
4312 +/* NAND flash MLC controller registers (corerev >= 38) */
4313 +#define BCMA_CC_NAND_REVISION 0x0C00
4314 +#define BCMA_CC_NAND_CMD_START 0x0C04
4315 +#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
4316 +#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
4317 +#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
4318 +#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
4319 +#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
4320 +#define BCMA_CC_NAND_SPARE_RD0 0x0C20
4321 +#define BCMA_CC_NAND_SPARE_RD4 0x0C24
4322 +#define BCMA_CC_NAND_SPARE_RD8 0x0C28
4323 +#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
4324 +#define BCMA_CC_NAND_SPARE_WR0 0x0C30
4325 +#define BCMA_CC_NAND_SPARE_WR4 0x0C34
4326 +#define BCMA_CC_NAND_SPARE_WR8 0x0C38
4327 +#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
4328 +#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
4329 +#define BCMA_CC_NAND_CONFIG 0x0C48
4330 +#define BCMA_CC_NAND_TIMING_1 0x0C50
4331 +#define BCMA_CC_NAND_TIMING_2 0x0C54
4332 +#define BCMA_CC_NAND_SEMAPHORE 0x0C58
4333 +#define BCMA_CC_NAND_DEVID 0x0C60
4334 +#define BCMA_CC_NAND_DEVID_X 0x0C64
4335 +#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
4336 +#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
4337 +#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
4338 +#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
4339 +#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
4340 +#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
4341 +#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
4342 +#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
4343 +#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
4344 +#define BCMA_CC_NAND_READ_ADDR 0x0C94
4345 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
4346 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
4347 +#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
4348 +#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
4349 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
4350 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
4351 +#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
4352 +#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
4353 +#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
4354 +#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
4355 +#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
4356 +#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
4357 +#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
4358 +#define BCMA_CC_NAND_SPARE_RD16 0x0D30
4359 +#define BCMA_CC_NAND_SPARE_RD20 0x0D34
4360 +#define BCMA_CC_NAND_SPARE_RD24 0x0D38
4361 +#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
4362 +#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
4363 +#define BCMA_CC_NAND_CACHE_DATA 0x0D44
4364 +#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
4365 +#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
4366
4367 /* Divider allocation in 4716/47162/5356 */
4368 #define BCMA_CC_PMU5_MAINPLL_CPU 1
4369 @@ -256,6 +421,15 @@
4370
4371 /* 4706 PMU */
4372 #define BCMA_CC_PMU4706_MAINPLL_PLL0 0
4373 +#define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */
4374 +#define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000
4375 +#define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16
4376 +#define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000
4377 +#define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12
4378 +#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8
4379 +#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3
4380 +#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
4381 +#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
4382
4383 /* ALP clock on pre-PMU chips */
4384 #define BCMA_CC_PMU_ALP_CLOCK 20000000
4385 @@ -284,6 +458,19 @@
4386 #define BCMA_CC_PPL_PCHI_OFF 5
4387 #define BCMA_CC_PPL_PCHI_MASK 0x0000003f
4388
4389 +#define BCMA_CC_PMU_PLL_CTL0 0
4390 +#define BCMA_CC_PMU_PLL_CTL1 1
4391 +#define BCMA_CC_PMU_PLL_CTL2 2
4392 +#define BCMA_CC_PMU_PLL_CTL3 3
4393 +#define BCMA_CC_PMU_PLL_CTL4 4
4394 +#define BCMA_CC_PMU_PLL_CTL5 5
4395 +
4396 +#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
4397 +#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20
4398 +
4399 +#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
4400 +#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
4401 +
4402 /* BCM4331 ChipControl numbers. */
4403 #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
4404 #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
4405 @@ -297,9 +484,25 @@
4406 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
4407 #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
4408 #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
4409 +#define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */
4410 #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
4411 #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
4412
4413 +/* 43224 chip-specific ChipControl register bits */
4414 +#define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
4415 +#define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
4416 +#define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
4417 +
4418 +/* 4313 Chip specific ChipControl register bits */
4419 +#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
4420 +
4421 +/* BCM5357 ChipControl register bits */
4422 +#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
4423 +#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
4424 +#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
4425 +#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
4426 +#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
4427 +
4428 /* Data for the PMU, if available.
4429 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
4430 */
4431 @@ -310,11 +513,35 @@ struct bcma_chipcommon_pmu {
4432
4433 #ifdef CONFIG_BCMA_DRIVER_MIPS
4434 struct bcma_pflash {
4435 + bool present;
4436 u8 buswidth;
4437 u32 window;
4438 u32 window_size;
4439 };
4440
4441 +#ifdef CONFIG_BCMA_SFLASH
4442 +struct bcma_sflash {
4443 + bool present;
4444 + u32 window;
4445 + u32 blocksize;
4446 + u16 numblocks;
4447 + u32 size;
4448 +
4449 + struct mtd_info *mtd;
4450 +};
4451 +#endif
4452 +
4453 +#ifdef CONFIG_BCMA_NFLASH
4454 +struct mtd_info;
4455 +
4456 +struct bcma_nflash {
4457 + bool present;
4458 + bool boot; /* This is the flash the SoC boots from */
4459 +
4460 + struct mtd_info *mtd;
4461 +};
4462 +#endif
4463 +
4464 struct bcma_serial_port {
4465 void *regs;
4466 unsigned long clockspeed;
4467 @@ -330,15 +557,30 @@ struct bcma_drv_cc {
4468 u32 capabilities;
4469 u32 capabilities_ext;
4470 u8 setup_done:1;
4471 + u8 early_setup_done:1;
4472 /* Fast Powerup Delay constant */
4473 u16 fast_pwrup_delay;
4474 struct bcma_chipcommon_pmu pmu;
4475 #ifdef CONFIG_BCMA_DRIVER_MIPS
4476 struct bcma_pflash pflash;
4477 +#ifdef CONFIG_BCMA_SFLASH
4478 + struct bcma_sflash sflash;
4479 +#endif
4480 +#ifdef CONFIG_BCMA_NFLASH
4481 + struct bcma_nflash nflash;
4482 +#endif
4483
4484 int nr_serial_ports;
4485 struct bcma_serial_port serial_ports[4];
4486 #endif /* CONFIG_BCMA_DRIVER_MIPS */
4487 + u32 ticks_per_ms;
4488 + struct platform_device *watchdog;
4489 +
4490 + /* Lock for GPIO register access. */
4491 + spinlock_t gpio_lock;
4492 +#ifdef CONFIG_BCMA_DRIVER_GPIO
4493 + struct gpio_chip gpio;
4494 +#endif
4495 };
4496
4497 /* Register access */
4498 @@ -355,14 +597,14 @@ struct bcma_drv_cc {
4499 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
4500
4501 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
4502 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
4503
4504 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
4505 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
4506
4507 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
4508
4509 -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
4510 - u32 ticks);
4511 +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
4512
4513 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
4514
4515 @@ -375,9 +617,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
4516 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
4517 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
4518 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
4519 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
4520 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
4521
4522 /* PMU support */
4523 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
4524 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
4525
4526 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
4527 u32 value);
4528 @@ -387,5 +632,6 @@ extern void bcma_chipco_chipctl_maskset(
4529 u32 offset, u32 mask, u32 set);
4530 extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
4531 u32 offset, u32 mask, u32 set);
4532 +extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
4533
4534 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
4535 --- /dev/null
4536 +++ b/include/linux/bcma/bcma_driver_gmac_cmn.h
4537 @@ -0,0 +1,100 @@
4538 +#ifndef LINUX_BCMA_DRIVER_GMAC_CMN_H_
4539 +#define LINUX_BCMA_DRIVER_GMAC_CMN_H_
4540 +
4541 +#include <linux/types.h>
4542 +
4543 +#define BCMA_GMAC_CMN_STAG0 0x000
4544 +#define BCMA_GMAC_CMN_STAG1 0x004
4545 +#define BCMA_GMAC_CMN_STAG2 0x008
4546 +#define BCMA_GMAC_CMN_STAG3 0x00C
4547 +#define BCMA_GMAC_CMN_PARSER_CTL 0x020
4548 +#define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
4549 +#define BCMA_GMAC_CMN_PHY_ACCESS 0x100
4550 +#define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
4551 +#define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
4552 +#define BCMA_GMAC_CMN_PA_ADDR_SHIFT 16
4553 +#define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
4554 +#define BCMA_GMAC_CMN_PA_REG_SHIFT 24
4555 +#define BCMA_GMAC_CMN_PA_WRITE 0x20000000
4556 +#define BCMA_GMAC_CMN_PA_START 0x40000000
4557 +#define BCMA_GMAC_CMN_PHY_CTL 0x104
4558 +#define BCMA_GMAC_CMN_PC_EPA_MASK 0x0000001f
4559 +#define BCMA_GMAC_CMN_PC_MCT_MASK 0x007f0000
4560 +#define BCMA_GMAC_CMN_PC_MCT_SHIFT 16
4561 +#define BCMA_GMAC_CMN_PC_MTE 0x00800000
4562 +#define BCMA_GMAC_CMN_GMAC0_RGMII_CTL 0x110
4563 +#define BCMA_GMAC_CMN_CFP_ACCESS 0x200
4564 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA0 0x210
4565 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA1 0x214
4566 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA2 0x218
4567 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA3 0x21C
4568 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA4 0x220
4569 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA5 0x224
4570 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA6 0x228
4571 +#define BCMA_GMAC_CMN_CFP_TCAM_DATA7 0x22C
4572 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK0 0x230
4573 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK1 0x234
4574 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK2 0x238
4575 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK3 0x23C
4576 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK4 0x240
4577 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK5 0x244
4578 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK6 0x248
4579 +#define BCMA_GMAC_CMN_CFP_TCAM_MASK7 0x24C
4580 +#define BCMA_GMAC_CMN_CFP_ACTION_DATA 0x250
4581 +#define BCMA_GMAC_CMN_TCAM_BIST_CTL 0x2A0
4582 +#define BCMA_GMAC_CMN_TCAM_BIST_STATUS 0x2A4
4583 +#define BCMA_GMAC_CMN_TCAM_CMP_STATUS 0x2A8
4584 +#define BCMA_GMAC_CMN_TCAM_DISABLE 0x2AC
4585 +#define BCMA_GMAC_CMN_TCAM_TEST_CTL 0x2F0
4586 +#define BCMA_GMAC_CMN_UDF_0_A3_A0 0x300
4587 +#define BCMA_GMAC_CMN_UDF_0_A7_A4 0x304
4588 +#define BCMA_GMAC_CMN_UDF_0_A8 0x308
4589 +#define BCMA_GMAC_CMN_UDF_1_A3_A0 0x310
4590 +#define BCMA_GMAC_CMN_UDF_1_A7_A4 0x314
4591 +#define BCMA_GMAC_CMN_UDF_1_A8 0x318
4592 +#define BCMA_GMAC_CMN_UDF_2_A3_A0 0x320
4593 +#define BCMA_GMAC_CMN_UDF_2_A7_A4 0x324
4594 +#define BCMA_GMAC_CMN_UDF_2_A8 0x328
4595 +#define BCMA_GMAC_CMN_UDF_0_B3_B0 0x330
4596 +#define BCMA_GMAC_CMN_UDF_0_B7_B4 0x334
4597 +#define BCMA_GMAC_CMN_UDF_0_B8 0x338
4598 +#define BCMA_GMAC_CMN_UDF_1_B3_B0 0x340
4599 +#define BCMA_GMAC_CMN_UDF_1_B7_B4 0x344
4600 +#define BCMA_GMAC_CMN_UDF_1_B8 0x348
4601 +#define BCMA_GMAC_CMN_UDF_2_B3_B0 0x350
4602 +#define BCMA_GMAC_CMN_UDF_2_B7_B4 0x354
4603 +#define BCMA_GMAC_CMN_UDF_2_B8 0x358
4604 +#define BCMA_GMAC_CMN_UDF_0_C3_C0 0x360
4605 +#define BCMA_GMAC_CMN_UDF_0_C7_C4 0x364
4606 +#define BCMA_GMAC_CMN_UDF_0_C8 0x368
4607 +#define BCMA_GMAC_CMN_UDF_1_C3_C0 0x370
4608 +#define BCMA_GMAC_CMN_UDF_1_C7_C4 0x374
4609 +#define BCMA_GMAC_CMN_UDF_1_C8 0x378
4610 +#define BCMA_GMAC_CMN_UDF_2_C3_C0 0x380
4611 +#define BCMA_GMAC_CMN_UDF_2_C7_C4 0x384
4612 +#define BCMA_GMAC_CMN_UDF_2_C8 0x388
4613 +#define BCMA_GMAC_CMN_UDF_0_D3_D0 0x390
4614 +#define BCMA_GMAC_CMN_UDF_0_D7_D4 0x394
4615 +#define BCMA_GMAC_CMN_UDF_0_D11_D8 0x394
4616 +
4617 +struct bcma_drv_gmac_cmn {
4618 + struct bcma_device *core;
4619 +
4620 + /* Drivers accessing BCMA_GMAC_CMN_PHY_ACCESS and
4621 + * BCMA_GMAC_CMN_PHY_CTL need to take that mutex first. */
4622 + struct mutex phy_mutex;
4623 +};
4624 +
4625 +/* Register access */
4626 +#define gmac_cmn_read16(gc, offset) bcma_read16((gc)->core, offset)
4627 +#define gmac_cmn_read32(gc, offset) bcma_read32((gc)->core, offset)
4628 +#define gmac_cmn_write16(gc, offset, val) bcma_write16((gc)->core, offset, val)
4629 +#define gmac_cmn_write32(gc, offset, val) bcma_write32((gc)->core, offset, val)
4630 +
4631 +#ifdef CONFIG_BCMA_DRIVER_GMAC_CMN
4632 +extern void __devinit bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc);
4633 +#else
4634 +static inline void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) { }
4635 +#endif
4636 +
4637 +#endif /* LINUX_BCMA_DRIVER_GMAC_CMN_H_ */
4638 --- a/include/linux/bcma/bcma_driver_mips.h
4639 +++ b/include/linux/bcma/bcma_driver_mips.h
4640 @@ -35,13 +35,15 @@ struct bcma_device;
4641 struct bcma_drv_mips {
4642 struct bcma_device *core;
4643 u8 setup_done:1;
4644 - unsigned int assigned_irqs;
4645 + u8 early_setup_done:1;
4646 };
4647
4648 #ifdef CONFIG_BCMA_DRIVER_MIPS
4649 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
4650 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
4651 #else
4652 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
4653 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
4654 #endif
4655
4656 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
4657 --- a/include/linux/bcma/bcma_driver_pci.h
4658 +++ b/include/linux/bcma/bcma_driver_pci.h
4659 @@ -53,11 +53,47 @@ struct pci_dev;
4660 #define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
4661 #define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
4662 #define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
4663 +#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
4664 +#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
4665 +#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */
4666 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
4667 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2
4668 +#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
4669 +#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
4670 +#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */
4671 +#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */
4672 +#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */
4673 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
4674 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
4675 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
4676 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
4677 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
4678 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
4679 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
4680 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
4681 +#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */
4682 +#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */
4683 +#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */
4684 +#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
4685 +#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
4686 +#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
4687 +#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
4688 +#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
4689 +#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */
4690 +#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */
4691 +#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */
4692 #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
4693 #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
4694 #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
4695 #define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
4696 #define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
4697 +#define BCMA_CORE_PCI_SPROM_PI_OFFSET 0 /* first word */
4698 +#define BCMA_CORE_PCI_SPROM_PI_MASK 0xf000 /* bit 15:12 */
4699 +#define BCMA_CORE_PCI_SPROM_PI_SHIFT 12 /* bit 15:12 */
4700 +#define BCMA_CORE_PCI_SPROM_MISC_CONFIG 5 /* word 5 */
4701 +#define BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
4702 +#define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
4703 +#define BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800 /* bit 11 */
4704
4705 /* SBtoPCIx */
4706 #define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
4707 @@ -72,20 +108,118 @@ struct pci_dev;
4708 #define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
4709 #define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
4710
4711 +/* PCIE protocol PHY diagnostic registers */
4712 +#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */
4713 +#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */
4714 +#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */
4715 +#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
4716 +#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
4717 +#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
4718 +#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
4719 +#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */
4720 +#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */
4721 +#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */
4722 +#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
4723 +#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
4724 +#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */
4725 +#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
4726 +#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
4727 +#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
4728 +#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
4729 +
4730 +/* PCIE protocol DLLP diagnostic registers */
4731 +#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */
4732 +#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */
4733 +#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */
4734 +#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)
4735 +#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
4736 +#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
4737 +#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
4738 +#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
4739 +#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
4740 +#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */
4741 +#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
4742 +#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
4743 +#define BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */
4744 +#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
4745 +#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
4746 +#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
4747 +#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
4748 +#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
4749 +#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
4750 +#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */
4751 +#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
4752 +#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */
4753 +#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */
4754 +#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
4755 +
4756 +/* SERDES RX registers */
4757 +#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */
4758 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
4759 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
4760 +#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */
4761 +#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */
4762 +#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */
4763 +
4764 +/* SERDES PLL registers */
4765 +#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */
4766 +#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
4767 +
4768 /* PCIcore specific boardflags */
4769 #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
4770
4771 +/* PCIE Config space accessing MACROS */
4772 +#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */
4773 +#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */
4774 +#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */
4775 +#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */
4776 +
4777 +#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */
4778 +#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */
4779 +#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
4780 +#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
4781 +
4782 +/* PCIE Root Capability Register bits (Host mode only) */
4783 +#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
4784 +
4785 +struct bcma_drv_pci;
4786 +
4787 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
4788 +struct bcma_drv_pci_host {
4789 + struct bcma_drv_pci *pdev;
4790 +
4791 + u32 host_cfg_addr;
4792 + spinlock_t cfgspace_lock;
4793 +
4794 + struct pci_controller pci_controller;
4795 + struct pci_ops pci_ops;
4796 + struct resource mem_resource;
4797 + struct resource io_resource;
4798 +};
4799 +#endif
4800 +
4801 struct bcma_drv_pci {
4802 struct bcma_device *core;
4803 u8 setup_done:1;
4804 + u8 hostmode:1;
4805 +
4806 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
4807 + struct bcma_drv_pci_host *host_controller;
4808 +#endif
4809 };
4810
4811 /* Register access */
4812 +#define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)
4813 #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
4814 +#define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)
4815 #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
4816
4817 -extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
4818 +extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc);
4819 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
4820 struct bcma_device *core, bool enable);
4821 +extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
4822 +
4823 +extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
4824 +extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
4825
4826 #endif /* LINUX_BCMA_DRIVER_PCI_H_ */
4827 --- a/include/linux/bcma/bcma_regs.h
4828 +++ b/include/linux/bcma/bcma_regs.h
4829 @@ -11,11 +11,13 @@
4830 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
4831 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
4832 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
4833 +#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8
4834 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
4835 #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
4836 #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
4837 #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
4838 #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
4839 +#define BCMA_CLKCTLST_EXTRESST_SHIFT 24
4840 /* Is there any BCM4328 on BCMA bus? */
4841 #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
4842 #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
4843 @@ -56,4 +58,36 @@
4844 #define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
4845 #define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
4846
4847 +/* SiliconBackplane Address Map.
4848 + * All regions may not exist on all chips.
4849 + */
4850 +#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */
4851 +#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
4852 +#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024)
4853 +#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
4854 +#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
4855 +#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */
4856 +
4857 +
4858 +#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
4859 +#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */
4860 +#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
4861 +#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2
4862 + * (2 ZettaBytes), low 32 bits
4863 + */
4864 +#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2
4865 + * (2 ZettaBytes), high 32 bits
4866 + */
4867 +
4868 +#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
4869 +#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
4870 +#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2
4871 + * (2 ZettaBytes), high 32 bits
4872 + */
4873 +
4874 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
4875 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
4876 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
4877 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
4878 +
4879 #endif /* LINUX_BCMA_REGS_H_ */
4880 --- a/drivers/net/wireless/b43/main.c
4881 +++ b/drivers/net/wireless/b43/main.c
4882 @@ -4618,7 +4618,7 @@ static int b43_wireless_core_init(struct
4883 switch (dev->dev->bus_type) {
4884 #ifdef CONFIG_B43_BCMA
4885 case B43_BUS_BCMA:
4886 - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4887 + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
4888 dev->dev->bdev, true);
4889 break;
4890 #endif
4891 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
4892 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
4893 @@ -533,7 +533,7 @@ ai_buscore_setup(struct si_info *sii, st
4894
4895 /* fixup necessary chip/core configurations */
4896 if (!sii->pch) {
4897 - sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci.core);
4898 + sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci[0].core);
4899 if (sii->pch == NULL)
4900 return false;
4901 }
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