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generic: add detach callback to struct phy_driver
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.6 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -48,12 +48,12 @@ config BCMA_DRIVER_MIPS
4
5 config BCMA_SFLASH
6 bool
7 - depends on BCMA_DRIVER_MIPS && BROKEN
8 + depends on BCMA_DRIVER_MIPS
9 default y
10
11 config BCMA_NFLASH
12 bool
13 - depends on BCMA_DRIVER_MIPS && BROKEN
14 + depends on BCMA_DRIVER_MIPS
15 default y
16
17 config BCMA_DRIVER_GMAC_CMN
18 @@ -65,6 +65,14 @@ config BCMA_DRIVER_GMAC_CMN
19
20 If unsure, say N
21
22 +config BCMA_DRIVER_GPIO
23 + bool "BCMA GPIO driver"
24 + depends on BCMA && GPIOLIB
25 + help
26 + Driver to provide access to the GPIO pins of the bcma bus.
27 +
28 + If unsure, say N
29 +
30 config BCMA_DEBUG
31 bool "BCMA debugging"
32 depends on BCMA
33 --- a/drivers/bcma/Makefile
34 +++ b/drivers/bcma/Makefile
35 @@ -6,6 +6,7 @@ bcma-y += driver_pci.o
36 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
37 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
38 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
39 +bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o
40 bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
41 bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
42 obj-$(CONFIG_BCMA) += bcma.o
43 --- a/drivers/bcma/bcma_private.h
44 +++ b/drivers/bcma/bcma_private.h
45 @@ -31,6 +31,8 @@ int __init bcma_bus_early_register(struc
46 int bcma_bus_suspend(struct bcma_bus *bus);
47 int bcma_bus_resume(struct bcma_bus *bus);
48 #endif
49 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
50 + u8 unit);
51
52 /* scan.c */
53 int bcma_bus_scan(struct bcma_bus *bus);
54 @@ -48,12 +50,13 @@ void bcma_chipco_serial_init(struct bcma
55 #endif /* CONFIG_BCMA_DRIVER_MIPS */
56
57 /* driver_chipcommon_pmu.c */
58 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
59 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
60 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
61 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
62
63 #ifdef CONFIG_BCMA_SFLASH
64 /* driver_chipcommon_sflash.c */
65 int bcma_sflash_init(struct bcma_drv_cc *cc);
66 +extern struct platform_device bcma_sflash_dev;
67 #else
68 static inline int bcma_sflash_init(struct bcma_drv_cc *cc)
69 {
70 @@ -65,6 +68,7 @@ static inline int bcma_sflash_init(struc
71 #ifdef CONFIG_BCMA_NFLASH
72 /* driver_chipcommon_nflash.c */
73 int bcma_nflash_init(struct bcma_drv_cc *cc);
74 +extern struct platform_device bcma_nflash_dev;
75 #else
76 static inline int bcma_nflash_init(struct bcma_drv_cc *cc)
77 {
78 @@ -82,9 +86,21 @@ extern void __exit bcma_host_pci_exit(vo
79 /* driver_pci.c */
80 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
81
82 +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
83 +
84 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
85 bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
86 void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
87 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
88
89 +#ifdef CONFIG_BCMA_DRIVER_GPIO
90 +/* driver_gpio.c */
91 +int bcma_gpio_init(struct bcma_drv_cc *cc);
92 +#else
93 +static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
94 +{
95 + return -ENOTSUPP;
96 +}
97 +#endif /* CONFIG_BCMA_DRIVER_GPIO */
98 +
99 #endif
100 --- a/drivers/bcma/core.c
101 +++ b/drivers/bcma/core.c
102 @@ -65,7 +65,7 @@ void bcma_core_set_clockmode(struct bcma
103 switch (clkmode) {
104 case BCMA_CLKMODE_FAST:
105 bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
106 - udelay(64);
107 + usleep_range(64, 300);
108 for (i = 0; i < 1500; i++) {
109 if (bcma_read32(core, BCMA_CLKCTLST) &
110 BCMA_CLKCTLST_HAVEHT) {
111 --- a/drivers/bcma/driver_chipcommon.c
112 +++ b/drivers/bcma/driver_chipcommon.c
113 @@ -4,12 +4,15 @@
114 *
115 * Copyright 2005, Broadcom Corporation
116 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
117 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
118 *
119 * Licensed under the GNU/GPL. See COPYING for details.
120 */
121
122 #include "bcma_private.h"
123 +#include <linux/bcm47xx_wdt.h>
124 #include <linux/export.h>
125 +#include <linux/platform_device.h>
126 #include <linux/bcma/bcma.h>
127
128 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
129 @@ -22,20 +25,119 @@ static inline u32 bcma_cc_write32_masked
130 return value;
131 }
132
133 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
134 +static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
135 {
136 - u32 leddc_on = 10;
137 - u32 leddc_off = 90;
138 + if (cc->capabilities & BCMA_CC_CAP_PMU)
139 + return bcma_pmu_get_alp_clock(cc);
140
141 - if (cc->setup_done)
142 + return 20000000;
143 +}
144 +
145 +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
146 +{
147 + struct bcma_bus *bus = cc->core->bus;
148 + u32 nb;
149 +
150 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
151 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
152 + nb = 32;
153 + else if (cc->core->id.rev < 26)
154 + nb = 16;
155 + else
156 + nb = (cc->core->id.rev >= 37) ? 32 : 24;
157 + } else {
158 + nb = 28;
159 + }
160 + if (nb == 32)
161 + return 0xffffffff;
162 + else
163 + return (1 << nb) - 1;
164 +}
165 +
166 +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
167 + u32 ticks)
168 +{
169 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
170 +
171 + return bcma_chipco_watchdog_timer_set(cc, ticks);
172 +}
173 +
174 +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
175 + u32 ms)
176 +{
177 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
178 + u32 ticks;
179 +
180 + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
181 + return ticks / cc->ticks_per_ms;
182 +}
183 +
184 +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
185 +{
186 + struct bcma_bus *bus = cc->core->bus;
187 +
188 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
189 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
190 + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
191 + return bcma_chipco_get_alp_clock(cc) / 4000;
192 + else
193 + /* based on 32KHz ILP clock */
194 + return 32;
195 + } else {
196 + return bcma_chipco_get_alp_clock(cc) / 1000;
197 + }
198 +}
199 +
200 +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
201 +{
202 + struct bcm47xx_wdt wdt = {};
203 + struct platform_device *pdev;
204 +
205 + wdt.driver_data = cc;
206 + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
207 + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
208 + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
209 +
210 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
211 + cc->core->bus->num, &wdt,
212 + sizeof(wdt));
213 + if (IS_ERR(pdev))
214 + return PTR_ERR(pdev);
215 +
216 + cc->watchdog = pdev;
217 +
218 + return 0;
219 +}
220 +
221 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
222 +{
223 + if (cc->early_setup_done)
224 return;
225
226 + spin_lock_init(&cc->gpio_lock);
227 +
228 if (cc->core->id.rev >= 11)
229 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
230 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
231 if (cc->core->id.rev >= 35)
232 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
233
234 + if (cc->capabilities & BCMA_CC_CAP_PMU)
235 + bcma_pmu_early_init(cc);
236 +
237 + cc->early_setup_done = true;
238 +}
239 +
240 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
241 +{
242 + u32 leddc_on = 10;
243 + u32 leddc_off = 90;
244 +
245 + if (cc->setup_done)
246 + return;
247 +
248 + bcma_core_chipcommon_early_init(cc);
249 +
250 if (cc->core->id.rev >= 20) {
251 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
252 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
253 @@ -56,15 +158,33 @@ void bcma_core_chipcommon_init(struct bc
254 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
255 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
256 }
257 + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
258
259 cc->setup_done = true;
260 }
261
262 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
263 -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
264 +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
265 {
266 - /* instant NMI */
267 - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
268 + u32 maxt;
269 + enum bcma_clkmode clkmode;
270 +
271 + maxt = bcma_chipco_watchdog_get_max_timer(cc);
272 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
273 + if (ticks == 1)
274 + ticks = 2;
275 + else if (ticks > maxt)
276 + ticks = maxt;
277 + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
278 + } else {
279 + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
280 + bcma_core_set_clockmode(cc->core, clkmode);
281 + if (ticks > maxt)
282 + ticks = maxt;
283 + /* instant NMI */
284 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
285 + }
286 + return ticks;
287 }
288
289 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
290 @@ -84,28 +204,97 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
291
292 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
293 {
294 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
295 + unsigned long flags;
296 + u32 res;
297 +
298 + spin_lock_irqsave(&cc->gpio_lock, flags);
299 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
300 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
301 +
302 + return res;
303 }
304
305 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
306 {
307 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
308 + unsigned long flags;
309 + u32 res;
310 +
311 + spin_lock_irqsave(&cc->gpio_lock, flags);
312 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
313 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
314 +
315 + return res;
316 }
317
318 +/*
319 + * If the bit is set to 0, chipcommon controlls this GPIO,
320 + * if the bit is set to 1, it is used by some part of the chip and not our code.
321 + */
322 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
323 {
324 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
325 + unsigned long flags;
326 + u32 res;
327 +
328 + spin_lock_irqsave(&cc->gpio_lock, flags);
329 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
330 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
331 +
332 + return res;
333 }
334 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
335
336 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
337 {
338 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
339 + unsigned long flags;
340 + u32 res;
341 +
342 + spin_lock_irqsave(&cc->gpio_lock, flags);
343 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
344 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
345 +
346 + return res;
347 }
348
349 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
350 {
351 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
352 + unsigned long flags;
353 + u32 res;
354 +
355 + spin_lock_irqsave(&cc->gpio_lock, flags);
356 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
357 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
358 +
359 + return res;
360 +}
361 +
362 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
363 +{
364 + unsigned long flags;
365 + u32 res;
366 +
367 + if (cc->core->id.rev < 20)
368 + return 0;
369 +
370 + spin_lock_irqsave(&cc->gpio_lock, flags);
371 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
372 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
373 +
374 + return res;
375 +}
376 +
377 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
378 +{
379 + unsigned long flags;
380 + u32 res;
381 +
382 + if (cc->core->id.rev < 20)
383 + return 0;
384 +
385 + spin_lock_irqsave(&cc->gpio_lock, flags);
386 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
387 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
388 +
389 + return res;
390 }
391
392 #ifdef CONFIG_BCMA_DRIVER_MIPS
393 @@ -118,8 +307,7 @@ void bcma_chipco_serial_init(struct bcma
394 struct bcma_serial_port *ports = cc->serial_ports;
395
396 if (ccrev >= 11 && ccrev != 15) {
397 - /* Fixed ALP clock */
398 - baud_base = bcma_pmu_alp_clock(cc);
399 + baud_base = bcma_chipco_get_alp_clock(cc);
400 if (ccrev >= 21) {
401 /* Turn off UART clock before switching clocksource. */
402 bcma_cc_write32(cc, BCMA_CC_CORECTL,
403 --- a/drivers/bcma/driver_chipcommon_nflash.c
404 +++ b/drivers/bcma/driver_chipcommon_nflash.c
405 @@ -5,15 +5,40 @@
406 * Licensed under the GNU/GPL. See COPYING for details.
407 */
408
409 +#include <linux/platform_device.h>
410 #include <linux/bcma/bcma.h>
411 -#include <linux/bcma/bcma_driver_chipcommon.h>
412 -#include <linux/delay.h>
413
414 #include "bcma_private.h"
415
416 +struct platform_device bcma_nflash_dev = {
417 + .name = "bcma_nflash",
418 + .num_resources = 0,
419 +};
420 +
421 /* Initialize NAND flash access */
422 int bcma_nflash_init(struct bcma_drv_cc *cc)
423 {
424 - bcma_err(cc->core->bus, "NAND flash support is broken\n");
425 + struct bcma_bus *bus = cc->core->bus;
426 +
427 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
428 + cc->core->id.rev != 0x38) {
429 + bcma_err(bus, "NAND flash on unsupported board!\n");
430 + return -ENOTSUPP;
431 + }
432 +
433 + if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) {
434 + bcma_err(bus, "NAND flash not present according to ChipCommon\n");
435 + return -ENODEV;
436 + }
437 +
438 + cc->nflash.present = true;
439 + if (cc->core->id.rev == 38 &&
440 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
441 + cc->nflash.boot = true;
442 +
443 + /* Prepare platform device, but don't register it yet. It's too early,
444 + * malloc (required by device_private_init) is not available yet. */
445 + bcma_nflash_dev.dev.platform_data = &cc->nflash;
446 +
447 return 0;
448 }
449 --- a/drivers/bcma/driver_chipcommon_pmu.c
450 +++ b/drivers/bcma/driver_chipcommon_pmu.c
451 @@ -13,12 +13,13 @@
452 #include <linux/export.h>
453 #include <linux/bcma/bcma.h>
454
455 -static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
456 +u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
457 {
458 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
459 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
460 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
461 }
462 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
463
464 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
465 {
466 @@ -76,7 +77,10 @@ static void bcma_pmu_resources_init(stru
467 if (max_msk)
468 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
469
470 - /* Add some delay; allow resources to come up and settle. */
471 + /*
472 + * Add some delay; allow resources to come up and settle.
473 + * Delay is required for SoC (early init).
474 + */
475 mdelay(2);
476 }
477
478 @@ -101,7 +105,7 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
479 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
480 }
481
482 -void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
483 +static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
484 {
485 struct bcma_bus *bus = cc->core->bus;
486
487 @@ -141,7 +145,7 @@ void bcma_pmu_workarounds(struct bcma_dr
488 }
489 }
490
491 -void bcma_pmu_init(struct bcma_drv_cc *cc)
492 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
493 {
494 u32 pmucap;
495
496 @@ -150,7 +154,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
497
498 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
499 cc->pmu.rev, pmucap);
500 +}
501
502 +void bcma_pmu_init(struct bcma_drv_cc *cc)
503 +{
504 if (cc->pmu.rev == 1)
505 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
506 ~BCMA_CC_PMU_CTL_NOILPONW);
507 @@ -162,7 +169,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
508 bcma_pmu_workarounds(cc);
509 }
510
511 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
512 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
513 {
514 struct bcma_bus *bus = cc->core->bus;
515
516 @@ -190,7 +197,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
517 /* Find the output of the "m" pll divider given pll controls that start with
518 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
519 */
520 -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
521 +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
522 {
523 u32 tmp, div, ndiv, p1, p2, fc;
524 struct bcma_bus *bus = cc->core->bus;
525 @@ -219,14 +226,14 @@ static u32 bcma_pmu_clock(struct bcma_dr
526 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
527
528 /* Do calculation in Mhz */
529 - fc = bcma_pmu_alp_clock(cc) / 1000000;
530 + fc = bcma_pmu_get_alp_clock(cc) / 1000000;
531 fc = (p1 * ndiv * fc) / p2;
532
533 /* Return clock in Hertz */
534 return (fc / div) * 1000000;
535 }
536
537 -static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
538 +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
539 {
540 u32 tmp, ndiv, p1div, p2div;
541 u32 clock;
542 @@ -257,7 +264,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
543 }
544
545 /* query bus clock frequency for PMU-enabled chipcommon */
546 -u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
547 +static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
548 {
549 struct bcma_bus *bus = cc->core->bus;
550
551 @@ -265,40 +272,42 @@ u32 bcma_pmu_get_clockcontrol(struct bcm
552 case BCMA_CHIP_ID_BCM4716:
553 case BCMA_CHIP_ID_BCM4748:
554 case BCMA_CHIP_ID_BCM47162:
555 - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
556 - BCMA_CC_PMU5_MAINPLL_SSB);
557 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
558 + BCMA_CC_PMU5_MAINPLL_SSB);
559 case BCMA_CHIP_ID_BCM5356:
560 - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
561 - BCMA_CC_PMU5_MAINPLL_SSB);
562 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
563 + BCMA_CC_PMU5_MAINPLL_SSB);
564 case BCMA_CHIP_ID_BCM5357:
565 case BCMA_CHIP_ID_BCM4749:
566 - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
567 - BCMA_CC_PMU5_MAINPLL_SSB);
568 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
569 + BCMA_CC_PMU5_MAINPLL_SSB);
570 case BCMA_CHIP_ID_BCM4706:
571 - return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
572 - BCMA_CC_PMU5_MAINPLL_SSB);
573 + return bcma_pmu_pll_clock_bcm4706(cc,
574 + BCMA_CC_PMU4706_MAINPLL_PLL0,
575 + BCMA_CC_PMU5_MAINPLL_SSB);
576 case BCMA_CHIP_ID_BCM53572:
577 return 75000000;
578 default:
579 - bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
580 + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
581 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
582 }
583 return BCMA_CC_PMU_HT_CLOCK;
584 }
585
586 /* query cpu clock frequency for PMU-enabled chipcommon */
587 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
588 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
589 {
590 struct bcma_bus *bus = cc->core->bus;
591
592 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
593 return 300000000;
594
595 + /* New PMUs can have different clock for bus and CPU */
596 if (cc->pmu.rev >= 5) {
597 u32 pll;
598 switch (bus->chipinfo.id) {
599 case BCMA_CHIP_ID_BCM4706:
600 - return bcma_pmu_clock_bcm4706(cc,
601 + return bcma_pmu_pll_clock_bcm4706(cc,
602 BCMA_CC_PMU4706_MAINPLL_PLL0,
603 BCMA_CC_PMU5_MAINPLL_CPU);
604 case BCMA_CHIP_ID_BCM5356:
605 @@ -313,10 +322,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
606 break;
607 }
608
609 - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
610 + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
611 }
612
613 - return bcma_pmu_get_clockcontrol(cc);
614 + /* On old PMUs CPU has the same clock as the bus */
615 + return bcma_pmu_get_bus_clock(cc);
616 }
617
618 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
619 --- a/drivers/bcma/driver_chipcommon_sflash.c
620 +++ b/drivers/bcma/driver_chipcommon_sflash.c
621 @@ -5,15 +5,161 @@
622 * Licensed under the GNU/GPL. See COPYING for details.
623 */
624
625 +#include <linux/platform_device.h>
626 #include <linux/bcma/bcma.h>
627 -#include <linux/bcma/bcma_driver_chipcommon.h>
628 -#include <linux/delay.h>
629
630 #include "bcma_private.h"
631
632 +static struct resource bcma_sflash_resource = {
633 + .name = "bcma_sflash",
634 + .start = BCMA_SOC_FLASH2,
635 + .end = 0,
636 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
637 +};
638 +
639 +struct platform_device bcma_sflash_dev = {
640 + .name = "bcma_sflash",
641 + .resource = &bcma_sflash_resource,
642 + .num_resources = 1,
643 +};
644 +
645 +struct bcma_sflash_tbl_e {
646 + char *name;
647 + u32 id;
648 + u32 blocksize;
649 + u16 numblocks;
650 +};
651 +
652 +static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
653 + { "M25P20", 0x11, 0x10000, 4, },
654 + { "M25P40", 0x12, 0x10000, 8, },
655 +
656 + { "M25P16", 0x14, 0x10000, 32, },
657 + { "M25P32", 0x15, 0x10000, 64, },
658 + { "M25P64", 0x16, 0x10000, 128, },
659 + { "M25FL128", 0x17, 0x10000, 256, },
660 + { 0 },
661 +};
662 +
663 +static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
664 + { "SST25WF512", 1, 0x1000, 16, },
665 + { "SST25VF512", 0x48, 0x1000, 16, },
666 + { "SST25WF010", 2, 0x1000, 32, },
667 + { "SST25VF010", 0x49, 0x1000, 32, },
668 + { "SST25WF020", 3, 0x1000, 64, },
669 + { "SST25VF020", 0x43, 0x1000, 64, },
670 + { "SST25WF040", 4, 0x1000, 128, },
671 + { "SST25VF040", 0x44, 0x1000, 128, },
672 + { "SST25VF040B", 0x8d, 0x1000, 128, },
673 + { "SST25WF080", 5, 0x1000, 256, },
674 + { "SST25VF080B", 0x8e, 0x1000, 256, },
675 + { "SST25VF016", 0x41, 0x1000, 512, },
676 + { "SST25VF032", 0x4a, 0x1000, 1024, },
677 + { "SST25VF064", 0x4b, 0x1000, 2048, },
678 + { 0 },
679 +};
680 +
681 +static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
682 + { "AT45DB011", 0xc, 256, 512, },
683 + { "AT45DB021", 0x14, 256, 1024, },
684 + { "AT45DB041", 0x1c, 256, 2048, },
685 + { "AT45DB081", 0x24, 256, 4096, },
686 + { "AT45DB161", 0x2c, 512, 4096, },
687 + { "AT45DB321", 0x34, 512, 8192, },
688 + { "AT45DB642", 0x3c, 1024, 8192, },
689 + { 0 },
690 +};
691 +
692 +static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
693 +{
694 + int i;
695 + bcma_cc_write32(cc, BCMA_CC_FLASHCTL,
696 + BCMA_CC_FLASHCTL_START | opcode);
697 + for (i = 0; i < 1000; i++) {
698 + if (!(bcma_cc_read32(cc, BCMA_CC_FLASHCTL) &
699 + BCMA_CC_FLASHCTL_BUSY))
700 + return;
701 + cpu_relax();
702 + }
703 + bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
704 +}
705 +
706 /* Initialize serial flash access */
707 int bcma_sflash_init(struct bcma_drv_cc *cc)
708 {
709 - bcma_err(cc->core->bus, "Serial flash support is broken\n");
710 + struct bcma_bus *bus = cc->core->bus;
711 + struct bcma_sflash *sflash = &cc->sflash;
712 + struct bcma_sflash_tbl_e *e;
713 + u32 id, id2;
714 +
715 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
716 + case BCMA_CC_FLASHT_STSER:
717 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP);
718 +
719 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0);
720 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
721 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
722 +
723 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1);
724 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
725 + id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
726 +
727 + switch (id) {
728 + case 0xbf:
729 + for (e = bcma_sflash_sst_tbl; e->name; e++) {
730 + if (e->id == id2)
731 + break;
732 + }
733 + break;
734 + case 0x13:
735 + return -ENOTSUPP;
736 + default:
737 + for (e = bcma_sflash_st_tbl; e->name; e++) {
738 + if (e->id == id)
739 + break;
740 + }
741 + break;
742 + }
743 + if (!e->name) {
744 + bcma_err(bus, "Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2);
745 + return -ENOTSUPP;
746 + }
747 +
748 + break;
749 + case BCMA_CC_FLASHT_ATSER:
750 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
751 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c;
752 +
753 + for (e = bcma_sflash_at_tbl; e->name; e++) {
754 + if (e->id == id)
755 + break;
756 + }
757 + if (!e->name) {
758 + bcma_err(bus, "Unsupported Atmel serial flash (id: 0x%X)\n", id);
759 + return -ENOTSUPP;
760 + }
761 +
762 + break;
763 + default:
764 + bcma_err(bus, "Unsupported flash type\n");
765 + return -ENOTSUPP;
766 + }
767 +
768 + sflash->window = BCMA_SOC_FLASH2;
769 + sflash->blocksize = e->blocksize;
770 + sflash->numblocks = e->numblocks;
771 + sflash->size = sflash->blocksize * sflash->numblocks;
772 + sflash->present = true;
773 +
774 + bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
775 + e->name, sflash->size / 1024, sflash->blocksize,
776 + sflash->numblocks);
777 +
778 + /* Prepare platform device, but don't register it yet. It's too early,
779 + * malloc (required by device_private_init) is not available yet. */
780 + bcma_sflash_dev.resource[0].end = bcma_sflash_dev.resource[0].start +
781 + sflash->size;
782 + bcma_sflash_dev.dev.platform_data = sflash;
783 +
784 return 0;
785 }
786 --- /dev/null
787 +++ b/drivers/bcma/driver_gpio.c
788 @@ -0,0 +1,98 @@
789 +/*
790 + * Broadcom specific AMBA
791 + * GPIO driver
792 + *
793 + * Copyright 2011, Broadcom Corporation
794 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
795 + *
796 + * Licensed under the GNU/GPL. See COPYING for details.
797 + */
798 +
799 +#include <linux/gpio.h>
800 +#include <linux/export.h>
801 +#include <linux/bcma/bcma.h>
802 +
803 +#include "bcma_private.h"
804 +
805 +static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
806 +{
807 + return container_of(chip, struct bcma_drv_cc, gpio);
808 +}
809 +
810 +static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
811 +{
812 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
813 +
814 + return !!bcma_chipco_gpio_in(cc, 1 << gpio);
815 +}
816 +
817 +static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
818 + int value)
819 +{
820 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
821 +
822 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
823 +}
824 +
825 +static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
826 +{
827 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
828 +
829 + bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
830 + return 0;
831 +}
832 +
833 +static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
834 + int value)
835 +{
836 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
837 +
838 + bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
839 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
840 + return 0;
841 +}
842 +
843 +static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
844 +{
845 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
846 +
847 + bcma_chipco_gpio_control(cc, 1 << gpio, 0);
848 + /* clear pulldown */
849 + bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
850 + /* Set pullup */
851 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
852 +
853 + return 0;
854 +}
855 +
856 +static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
857 +{
858 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
859 +
860 + /* clear pullup */
861 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
862 +}
863 +
864 +int bcma_gpio_init(struct bcma_drv_cc *cc)
865 +{
866 + struct gpio_chip *chip = &cc->gpio;
867 +
868 + chip->label = "bcma_gpio";
869 + chip->owner = THIS_MODULE;
870 + chip->request = bcma_gpio_request;
871 + chip->free = bcma_gpio_free;
872 + chip->get = bcma_gpio_get_value;
873 + chip->set = bcma_gpio_set_value;
874 + chip->direction_input = bcma_gpio_direction_input;
875 + chip->direction_output = bcma_gpio_direction_output;
876 + chip->ngpio = 16;
877 + /* There is just one SoC in one device and its GPIO addresses should be
878 + * deterministic to address them more easily. The other buses could get
879 + * a random base number. */
880 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
881 + chip->base = 0;
882 + else
883 + chip->base = -1;
884 +
885 + return gpiochip_add(chip);
886 +}
887 --- a/drivers/bcma/driver_mips.c
888 +++ b/drivers/bcma/driver_mips.c
889 @@ -74,11 +74,16 @@ static u32 bcma_core_mips_irqflag(struct
890 return dev->core_index;
891 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
892
893 - return flag & 0x1F;
894 + if (flag)
895 + return flag & 0x1F;
896 + else
897 + return 0x3f;
898 }
899
900 /* Get the MIPS IRQ assignment for a specified device.
901 * If unassigned, 0 is returned.
902 + * If disabled, 5 is returned.
903 + * If not supported, 6 is returned.
904 */
905 unsigned int bcma_core_mips_irq(struct bcma_device *dev)
906 {
907 @@ -87,13 +92,15 @@ unsigned int bcma_core_mips_irq(struct b
908 unsigned int irq;
909
910 irqflag = bcma_core_mips_irqflag(dev);
911 + if (irqflag == 0x3f)
912 + return 6;
913
914 - for (irq = 1; irq <= 4; irq++)
915 + for (irq = 0; irq <= 4; irq++)
916 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
917 (1 << irqflag))
918 return irq;
919
920 - return 0;
921 + return 5;
922 }
923 EXPORT_SYMBOL(bcma_core_mips_irq);
924
925 @@ -114,8 +121,8 @@ static void bcma_core_mips_set_irq(struc
926 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
927 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
928 ~(1 << irqflag));
929 - else
930 - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
931 + else if (oldirq != 5)
932 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
933
934 /* assign the new one */
935 if (irq == 0) {
936 @@ -123,9 +130,9 @@ static void bcma_core_mips_set_irq(struc
937 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
938 (1 << irqflag));
939 } else {
940 - u32 oldirqflag = bcma_read32(mdev,
941 - BCMA_MIPS_MIPS74K_INTMASK(irq));
942 - if (oldirqflag) {
943 + u32 irqinitmask = bcma_read32(mdev,
944 + BCMA_MIPS_MIPS74K_INTMASK(irq));
945 + if (irqinitmask) {
946 struct bcma_device *core;
947
948 /* backplane irq line is in use, find out who uses
949 @@ -133,7 +140,7 @@ static void bcma_core_mips_set_irq(struc
950 */
951 list_for_each_entry(core, &bus->cores, list) {
952 if ((1 << bcma_core_mips_irqflag(core)) ==
953 - oldirqflag) {
954 + irqinitmask) {
955 bcma_core_mips_set_irq(core, 0);
956 break;
957 }
958 @@ -143,15 +150,31 @@ static void bcma_core_mips_set_irq(struc
959 1 << irqflag);
960 }
961
962 - bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
963 - dev->id.id, oldirq + 2, irq + 2);
964 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
965 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
966 +}
967 +
968 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
969 + u16 coreid, u8 unit)
970 +{
971 + struct bcma_device *core;
972 +
973 + core = bcma_find_core_unit(bus, coreid, unit);
974 + if (!core) {
975 + bcma_warn(bus,
976 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
977 + coreid, unit);
978 + return;
979 + }
980 +
981 + bcma_core_mips_set_irq(core, irq);
982 }
983
984 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
985 {
986 int i;
987 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
988 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
989 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
990 for (i = 0; i <= 6; i++)
991 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
992 printk("\n");
993 @@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
994 struct bcma_bus *bus = mcore->core->bus;
995
996 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
997 - return bcma_pmu_get_clockcpu(&bus->drv_cc);
998 + return bcma_pmu_get_cpu_clock(&bus->drv_cc);
999
1000 bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
1001 return 0;
1002 @@ -181,85 +204,109 @@ EXPORT_SYMBOL(bcma_cpu_clock);
1003 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
1004 {
1005 struct bcma_bus *bus = mcore->core->bus;
1006 + struct bcma_drv_cc *cc = &bus->drv_cc;
1007
1008 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
1009 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1010 case BCMA_CC_FLASHT_STSER:
1011 case BCMA_CC_FLASHT_ATSER:
1012 bcma_debug(bus, "Found serial flash\n");
1013 - bcma_sflash_init(&bus->drv_cc);
1014 + bcma_sflash_init(cc);
1015 break;
1016 case BCMA_CC_FLASHT_PARA:
1017 bcma_debug(bus, "Found parallel flash\n");
1018 - bus->drv_cc.pflash.window = 0x1c000000;
1019 - bus->drv_cc.pflash.window_size = 0x02000000;
1020 + cc->pflash.present = true;
1021 + cc->pflash.window = BCMA_SOC_FLASH2;
1022 + cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
1023
1024 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
1025 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
1026 BCMA_CC_FLASH_CFG_DS) == 0)
1027 - bus->drv_cc.pflash.buswidth = 1;
1028 + cc->pflash.buswidth = 1;
1029 else
1030 - bus->drv_cc.pflash.buswidth = 2;
1031 + cc->pflash.buswidth = 2;
1032 break;
1033 default:
1034 bcma_err(bus, "Flash type not supported\n");
1035 }
1036
1037 - if (bus->drv_cc.core->id.rev == 38 ||
1038 + if (cc->core->id.rev == 38 ||
1039 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
1040 - if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
1041 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
1042 bcma_debug(bus, "Found NAND flash\n");
1043 - bcma_nflash_init(&bus->drv_cc);
1044 + bcma_nflash_init(cc);
1045 }
1046 }
1047 }
1048
1049 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
1050 +{
1051 + struct bcma_bus *bus = mcore->core->bus;
1052 +
1053 + if (mcore->early_setup_done)
1054 + return;
1055 +
1056 + bcma_chipco_serial_init(&bus->drv_cc);
1057 + bcma_core_mips_flash_detect(mcore);
1058 +
1059 + mcore->early_setup_done = true;
1060 +}
1061 +
1062 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
1063 {
1064 struct bcma_bus *bus;
1065 struct bcma_device *core;
1066 bus = mcore->core->bus;
1067
1068 - bcma_info(bus, "Initializing MIPS core...\n");
1069 + if (mcore->setup_done)
1070 + return;
1071
1072 - if (!mcore->setup_done)
1073 - mcore->assigned_irqs = 1;
1074 + bcma_debug(bus, "Initializing MIPS core...\n");
1075
1076 - /* Assign IRQs to all cores on the bus */
1077 - list_for_each_entry(core, &bus->cores, list) {
1078 - int mips_irq;
1079 - if (core->irq)
1080 - continue;
1081 -
1082 - mips_irq = bcma_core_mips_irq(core);
1083 - if (mips_irq > 4)
1084 - core->irq = 0;
1085 - else
1086 - core->irq = mips_irq + 2;
1087 - if (core->irq > 5)
1088 - continue;
1089 - switch (core->id.id) {
1090 - case BCMA_CORE_PCI:
1091 - case BCMA_CORE_PCIE:
1092 - case BCMA_CORE_ETHERNET:
1093 - case BCMA_CORE_ETHERNET_GBIT:
1094 - case BCMA_CORE_MAC_GBIT:
1095 - case BCMA_CORE_80211:
1096 - case BCMA_CORE_USB20_HOST:
1097 - /* These devices get their own IRQ line if available,
1098 - * the rest goes on IRQ0
1099 - */
1100 - if (mcore->assigned_irqs <= 4)
1101 - bcma_core_mips_set_irq(core,
1102 - mcore->assigned_irqs++);
1103 - break;
1104 + bcma_core_mips_early_init(mcore);
1105 +
1106 + switch (bus->chipinfo.id) {
1107 + case BCMA_CHIP_ID_BCM4716:
1108 + case BCMA_CHIP_ID_BCM4748:
1109 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1110 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1111 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1112 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
1113 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1114 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1115 + break;
1116 + case BCMA_CHIP_ID_BCM5356:
1117 + case BCMA_CHIP_ID_BCM47162:
1118 + case BCMA_CHIP_ID_BCM53572:
1119 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1120 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1121 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1122 + break;
1123 + case BCMA_CHIP_ID_BCM5357:
1124 + case BCMA_CHIP_ID_BCM4749:
1125 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1126 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1127 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1128 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1129 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1130 + break;
1131 + case BCMA_CHIP_ID_BCM4706:
1132 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
1133 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
1134 + 0);
1135 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
1136 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
1137 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
1138 + 0);
1139 + break;
1140 + default:
1141 + list_for_each_entry(core, &bus->cores, list) {
1142 + core->irq = bcma_core_mips_irq(core) + 2;
1143 }
1144 + bcma_err(bus,
1145 + "Unknown device (0x%x) found, can not configure IRQs\n",
1146 + bus->chipinfo.id);
1147 }
1148 - bcma_info(bus, "IRQ reconfiguration done\n");
1149 + bcma_debug(bus, "IRQ reconfiguration done\n");
1150 bcma_core_mips_dump_irq(bus);
1151
1152 - if (mcore->setup_done)
1153 - return;
1154 -
1155 - bcma_chipco_serial_init(&bus->drv_cc);
1156 - bcma_core_mips_flash_detect(mcore);
1157 mcore->setup_done = true;
1158 }
1159 --- a/drivers/bcma/driver_pci.c
1160 +++ b/drivers/bcma/driver_pci.c
1161 @@ -51,7 +51,7 @@ static void bcma_pcie_mdio_set_phy(struc
1162 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1163 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1164 break;
1165 - msleep(1);
1166 + usleep_range(1000, 2000);
1167 }
1168 }
1169
1170 @@ -92,7 +92,7 @@ static u16 bcma_pcie_mdio_read(struct bc
1171 ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
1172 break;
1173 }
1174 - msleep(1);
1175 + usleep_range(1000, 2000);
1176 }
1177 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1178 return ret;
1179 @@ -132,7 +132,7 @@ static void bcma_pcie_mdio_write(struct
1180 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1181 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1182 break;
1183 - msleep(1);
1184 + usleep_range(1000, 2000);
1185 }
1186 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1187 }
1188 --- a/drivers/bcma/driver_pci_host.c
1189 +++ b/drivers/bcma/driver_pci_host.c
1190 @@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
1191 chipid_top != 0x5300)
1192 return false;
1193
1194 - if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1195 - bcma_info(bus, "This PCI core is disabled and not working\n");
1196 - return false;
1197 - }
1198 -
1199 bcma_core_enable(pc->core, 0);
1200
1201 return !mips_busprobe32(tmp, pc->core->io_addr);
1202 @@ -396,6 +391,11 @@ void __devinit bcma_core_pci_hostmode_in
1203
1204 bcma_info(bus, "PCIEcore in host mode found\n");
1205
1206 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1207 + bcma_info(bus, "This PCIE core is disabled and not working\n");
1208 + return;
1209 + }
1210 +
1211 pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
1212 if (!pc_host) {
1213 bcma_err(bus, "can not allocate memory");
1214 @@ -425,9 +425,9 @@ void __devinit bcma_core_pci_hostmode_in
1215 pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
1216
1217 /* Reset RC */
1218 - udelay(3000);
1219 + usleep_range(3000, 5000);
1220 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
1221 - udelay(1000);
1222 + usleep_range(1000, 2000);
1223 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
1224 BCMA_CORE_PCI_CTL_RST_OE);
1225
1226 @@ -452,6 +452,8 @@ void __devinit bcma_core_pci_hostmode_in
1227 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1228 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1229 BCMA_SOC_PCI_MEM_SZ - 1;
1230 + pc_host->io_resource.start = 0x100;
1231 + pc_host->io_resource.end = 0x47F;
1232 pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
1233 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1234 tmp | BCMA_SOC_PCI_MEM);
1235 @@ -459,6 +461,8 @@ void __devinit bcma_core_pci_hostmode_in
1236 pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
1237 pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
1238 BCMA_SOC_PCI_MEM_SZ - 1;
1239 + pc_host->io_resource.start = 0x480;
1240 + pc_host->io_resource.end = 0x7FF;
1241 pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
1242 pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
1243 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1244 @@ -481,7 +485,7 @@ void __devinit bcma_core_pci_hostmode_in
1245 * before issuing configuration requests to PCI Express
1246 * devices.
1247 */
1248 - udelay(100000);
1249 + msleep(100);
1250
1251 bcma_core_pci_enable_crs(pc);
1252
1253 @@ -501,7 +505,7 @@ void __devinit bcma_core_pci_hostmode_in
1254 set_io_port_base(pc_host->pci_controller.io_map_base);
1255 /* Give some time to the PCI controller to configure itself with the new
1256 * values. Not waiting at this point causes crashes of the machine. */
1257 - mdelay(10);
1258 + usleep_range(10000, 15000);
1259 register_pci_controller(&pc_host->pci_controller);
1260 return;
1261 }
1262 @@ -534,7 +538,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_
1263 static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
1264 {
1265 struct resource *res;
1266 - int pos;
1267 + int pos, err;
1268
1269 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1270 /* This is not a device on the PCI-core bridge. */
1271 @@ -547,8 +551,12 @@ static void bcma_core_pci_fixup_addresse
1272
1273 for (pos = 0; pos < 6; pos++) {
1274 res = &dev->resource[pos];
1275 - if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
1276 - pci_assign_resource(dev, pos);
1277 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
1278 + err = pci_assign_resource(dev, pos);
1279 + if (err)
1280 + pr_err("PCI: Problem fixing up the addresses on %s\n",
1281 + pci_name(dev));
1282 + }
1283 }
1284 }
1285 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
1286 --- a/drivers/bcma/host_pci.c
1287 +++ b/drivers/bcma/host_pci.c
1288 @@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct
1289 }
1290
1291 #ifdef CONFIG_BCMA_BLOCKIO
1292 -void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
1293 - size_t count, u16 offset, u8 reg_width)
1294 +static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
1295 + size_t count, u16 offset, u8 reg_width)
1296 {
1297 void __iomem *addr = core->bus->mmio + offset;
1298 if (core->bus->mapped_core != core)
1299 @@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm
1300 }
1301 }
1302
1303 -void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
1304 - size_t count, u16 offset, u8 reg_width)
1305 +static void bcma_host_pci_block_write(struct bcma_device *core,
1306 + const void *buffer, size_t count,
1307 + u16 offset, u8 reg_width)
1308 {
1309 void __iomem *addr = core->bus->mmio + offset;
1310 if (core->bus->mapped_core != core)
1311 @@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc
1312 iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
1313 }
1314
1315 -const struct bcma_host_ops bcma_host_pci_ops = {
1316 +static const struct bcma_host_ops bcma_host_pci_ops = {
1317 .read8 = bcma_host_pci_read8,
1318 .read16 = bcma_host_pci_read16,
1319 .read32 = bcma_host_pci_read32,
1320 @@ -237,7 +238,7 @@ static void __devexit bcma_host_pci_remo
1321 pci_set_drvdata(dev, NULL);
1322 }
1323
1324 -#ifdef CONFIG_PM
1325 +#ifdef CONFIG_PM_SLEEP
1326 static int bcma_host_pci_suspend(struct device *dev)
1327 {
1328 struct pci_dev *pdev = to_pci_dev(dev);
1329 @@ -260,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
1330 bcma_host_pci_resume);
1331 #define BCMA_PM_OPS (&bcma_pm_ops)
1332
1333 -#else /* CONFIG_PM */
1334 +#else /* CONFIG_PM_SLEEP */
1335
1336 #define BCMA_PM_OPS NULL
1337
1338 -#endif /* CONFIG_PM */
1339 +#endif /* CONFIG_PM_SLEEP */
1340
1341 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
1342 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
1343 @@ -272,6 +273,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
1344 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
1345 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
1346 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
1347 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
1348 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
1349 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
1350 { 0, },
1351 --- a/drivers/bcma/host_soc.c
1352 +++ b/drivers/bcma/host_soc.c
1353 @@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc
1354 writel(value, core->io_wrap + offset);
1355 }
1356
1357 -const struct bcma_host_ops bcma_host_soc_ops = {
1358 +static const struct bcma_host_ops bcma_host_soc_ops = {
1359 .read8 = bcma_host_soc_read8,
1360 .read16 = bcma_host_soc_read16,
1361 .read32 = bcma_host_soc_read32,
1362 --- a/drivers/bcma/main.c
1363 +++ b/drivers/bcma/main.c
1364 @@ -7,6 +7,7 @@
1365
1366 #include "bcma_private.h"
1367 #include <linux/module.h>
1368 +#include <linux/platform_device.h>
1369 #include <linux/bcma/bcma.h>
1370 #include <linux/slab.h>
1371
1372 @@ -80,6 +81,18 @@ struct bcma_device *bcma_find_core(struc
1373 }
1374 EXPORT_SYMBOL_GPL(bcma_find_core);
1375
1376 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1377 + u8 unit)
1378 +{
1379 + struct bcma_device *core;
1380 +
1381 + list_for_each_entry(core, &bus->cores, list) {
1382 + if (core->id.id == coreid && core->core_unit == unit)
1383 + return core;
1384 + }
1385 + return NULL;
1386 +}
1387 +
1388 static void bcma_release_core_dev(struct device *dev)
1389 {
1390 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1391 @@ -136,6 +149,33 @@ static int bcma_register_cores(struct bc
1392 dev_id++;
1393 }
1394
1395 +#ifdef CONFIG_BCMA_SFLASH
1396 + if (bus->drv_cc.sflash.present) {
1397 + err = platform_device_register(&bcma_sflash_dev);
1398 + if (err)
1399 + bcma_err(bus, "Error registering serial flash\n");
1400 + }
1401 +#endif
1402 +
1403 +#ifdef CONFIG_BCMA_NFLASH
1404 + if (bus->drv_cc.nflash.present) {
1405 + err = platform_device_register(&bcma_nflash_dev);
1406 + if (err)
1407 + bcma_err(bus, "Error registering NAND flash\n");
1408 + }
1409 +#endif
1410 + err = bcma_gpio_init(&bus->drv_cc);
1411 + if (err == -ENOTSUPP)
1412 + bcma_debug(bus, "GPIO driver not activated\n");
1413 + else if (err)
1414 + bcma_err(bus, "Error registering GPIO driver: %i\n", err);
1415 +
1416 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
1417 + err = bcma_chipco_watchdog_register(&bus->drv_cc);
1418 + if (err)
1419 + bcma_err(bus, "Error registering watchdog driver\n");
1420 + }
1421 +
1422 return 0;
1423 }
1424
1425 @@ -148,6 +188,8 @@ static void bcma_unregister_cores(struct
1426 if (core->dev_registered)
1427 device_unregister(&core->dev);
1428 }
1429 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
1430 + platform_device_unregister(bus->drv_cc.watchdog);
1431 }
1432
1433 int __devinit bcma_bus_register(struct bcma_bus *bus)
1434 @@ -166,6 +208,20 @@ int __devinit bcma_bus_register(struct b
1435 return -1;
1436 }
1437
1438 + /* Early init CC core */
1439 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
1440 + if (core) {
1441 + bus->drv_cc.core = core;
1442 + bcma_core_chipcommon_early_init(&bus->drv_cc);
1443 + }
1444 +
1445 + /* Try to get SPROM */
1446 + err = bcma_sprom_get(bus);
1447 + if (err == -ENOENT) {
1448 + bcma_err(bus, "No SPROM available\n");
1449 + } else if (err)
1450 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
1451 +
1452 /* Init CC core */
1453 core = bcma_find_core(bus, bcma_cc_core_id(bus));
1454 if (core) {
1455 @@ -181,10 +237,17 @@ int __devinit bcma_bus_register(struct b
1456 }
1457
1458 /* Init PCIE core */
1459 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
1460 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
1461 + if (core) {
1462 + bus->drv_pci[0].core = core;
1463 + bcma_core_pci_init(&bus->drv_pci[0]);
1464 + }
1465 +
1466 + /* Init PCIE core */
1467 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
1468 if (core) {
1469 - bus->drv_pci.core = core;
1470 - bcma_core_pci_init(&bus->drv_pci);
1471 + bus->drv_pci[1].core = core;
1472 + bcma_core_pci_init(&bus->drv_pci[1]);
1473 }
1474
1475 /* Init GBIT MAC COMMON core */
1476 @@ -194,13 +257,6 @@ int __devinit bcma_bus_register(struct b
1477 bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
1478 }
1479
1480 - /* Try to get SPROM */
1481 - err = bcma_sprom_get(bus);
1482 - if (err == -ENOENT) {
1483 - bcma_err(bus, "No SPROM available\n");
1484 - } else if (err)
1485 - bcma_err(bus, "Failed to get SPROM: %d\n", err);
1486 -
1487 /* Register found cores */
1488 bcma_register_cores(bus);
1489
1490 @@ -211,7 +267,17 @@ int __devinit bcma_bus_register(struct b
1491
1492 void bcma_bus_unregister(struct bcma_bus *bus)
1493 {
1494 + struct bcma_device *cores[3];
1495 +
1496 + cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1497 + cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
1498 + cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
1499 +
1500 bcma_unregister_cores(bus);
1501 +
1502 + kfree(cores[2]);
1503 + kfree(cores[1]);
1504 + kfree(cores[0]);
1505 }
1506
1507 int __init bcma_bus_early_register(struct bcma_bus *bus,
1508 @@ -248,18 +314,18 @@ int __init bcma_bus_early_register(struc
1509 return -1;
1510 }
1511
1512 - /* Init CC core */
1513 + /* Early init CC core */
1514 core = bcma_find_core(bus, bcma_cc_core_id(bus));
1515 if (core) {
1516 bus->drv_cc.core = core;
1517 - bcma_core_chipcommon_init(&bus->drv_cc);
1518 + bcma_core_chipcommon_early_init(&bus->drv_cc);
1519 }
1520
1521 - /* Init MIPS core */
1522 + /* Early init MIPS core */
1523 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1524 if (core) {
1525 bus->drv_mips.core = core;
1526 - bcma_core_mips_init(&bus->drv_mips);
1527 + bcma_core_mips_early_init(&bus->drv_mips);
1528 }
1529
1530 bcma_info(bus, "Early bus registered\n");
1531 --- a/drivers/bcma/sprom.c
1532 +++ b/drivers/bcma/sprom.c
1533 @@ -507,7 +507,9 @@ static bool bcma_sprom_onchip_available(
1534 /* for these chips OTP is always available */
1535 present = true;
1536 break;
1537 + case BCMA_CHIP_ID_BCM43227:
1538 case BCMA_CHIP_ID_BCM43228:
1539 + case BCMA_CHIP_ID_BCM43428:
1540 present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT;
1541 break;
1542 default:
1543 @@ -593,8 +595,11 @@ int bcma_sprom_get(struct bcma_bus *bus)
1544 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
1545
1546 err = bcma_sprom_valid(sprom);
1547 - if (err)
1548 + if (err) {
1549 + bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
1550 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
1551 goto out;
1552 + }
1553
1554 bcma_sprom_extract_r8(bus, sprom);
1555
1556 --- a/include/linux/bcma/bcma.h
1557 +++ b/include/linux/bcma/bcma.h
1558 @@ -10,7 +10,7 @@
1559 #include <linux/bcma/bcma_driver_gmac_cmn.h>
1560 #include <linux/ssb/ssb.h> /* SPROM sharing */
1561
1562 -#include "bcma_regs.h"
1563 +#include <linux/bcma/bcma_regs.h>
1564
1565 struct bcma_device;
1566 struct bcma_bus;
1567 @@ -157,6 +157,7 @@ struct bcma_host_ops {
1568
1569 /* Chip IDs of SoCs */
1570 #define BCMA_CHIP_ID_BCM4706 0x5300
1571 +#define BCMA_PKG_ID_BCM4706L 1
1572 #define BCMA_CHIP_ID_BCM4716 0x4716
1573 #define BCMA_PKG_ID_BCM4716 8
1574 #define BCMA_PKG_ID_BCM4717 9
1575 @@ -166,7 +167,11 @@ struct bcma_host_ops {
1576 #define BCMA_CHIP_ID_BCM4749 0x4749
1577 #define BCMA_CHIP_ID_BCM5356 0x5356
1578 #define BCMA_CHIP_ID_BCM5357 0x5357
1579 +#define BCMA_PKG_ID_BCM5358 9
1580 +#define BCMA_PKG_ID_BCM47186 10
1581 +#define BCMA_PKG_ID_BCM5357 11
1582 #define BCMA_CHIP_ID_BCM53572 53572
1583 +#define BCMA_PKG_ID_BCM47188 9
1584
1585 struct bcma_device {
1586 struct bcma_bus *bus;
1587 @@ -251,7 +256,7 @@ struct bcma_bus {
1588 u8 num;
1589
1590 struct bcma_drv_cc drv_cc;
1591 - struct bcma_drv_pci drv_pci;
1592 + struct bcma_drv_pci drv_pci[2];
1593 struct bcma_drv_mips drv_mips;
1594 struct bcma_drv_gmac_cmn drv_gmac_cmn;
1595
1596 @@ -345,6 +350,7 @@ extern void bcma_core_set_clockmode(stru
1597 enum bcma_clkmode clkmode);
1598 extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
1599 bool on);
1600 +extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
1601 #define BCMA_DMA_TRANSLATION_MASK 0xC0000000
1602 #define BCMA_DMA_TRANSLATION_NONE 0x00000000
1603 #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
1604 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1605 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1606 @@ -1,6 +1,9 @@
1607 #ifndef LINUX_BCMA_DRIVER_CC_H_
1608 #define LINUX_BCMA_DRIVER_CC_H_
1609
1610 +#include <linux/platform_device.h>
1611 +#include <linux/gpio.h>
1612 +
1613 /** ChipCommon core registers. **/
1614 #define BCMA_CC_ID 0x0000
1615 #define BCMA_CC_ID_ID 0x0000FFFF
1616 @@ -100,6 +103,7 @@
1617 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
1618 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
1619 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
1620 +#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
1621 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
1622 #define BCMA_CC_JCMD_START 0x80000000
1623 #define BCMA_CC_JCMD_BUSY 0x80000000
1624 @@ -266,6 +270,29 @@
1625 #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
1626 #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
1627 #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
1628 +/* Block 0x140 - 0x190 registers are chipset specific */
1629 +#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
1630 +#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
1631 +#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
1632 +#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
1633 +#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
1634 +#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
1635 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
1636 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
1637 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
1638 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
1639 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
1640 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
1641 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
1642 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
1643 +/* NAND flash registers for BCM4706 (corerev = 31) */
1644 +#define BCMA_CC_NFLASH_CTL 0x01A0
1645 +#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
1646 +#define BCMA_CC_NFLASH_CONF 0x01A4
1647 +#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
1648 +#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
1649 +#define BCMA_CC_NFLASH_DATA 0x01B0
1650 +#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
1651 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
1652 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
1653 #define BCMA_CC_UART0_DATA 0x0300
1654 @@ -325,6 +352,60 @@
1655 #define BCMA_CC_PLLCTL_ADDR 0x0660
1656 #define BCMA_CC_PLLCTL_DATA 0x0664
1657 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
1658 +/* NAND flash MLC controller registers (corerev >= 38) */
1659 +#define BCMA_CC_NAND_REVISION 0x0C00
1660 +#define BCMA_CC_NAND_CMD_START 0x0C04
1661 +#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
1662 +#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
1663 +#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
1664 +#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
1665 +#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
1666 +#define BCMA_CC_NAND_SPARE_RD0 0x0C20
1667 +#define BCMA_CC_NAND_SPARE_RD4 0x0C24
1668 +#define BCMA_CC_NAND_SPARE_RD8 0x0C28
1669 +#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
1670 +#define BCMA_CC_NAND_SPARE_WR0 0x0C30
1671 +#define BCMA_CC_NAND_SPARE_WR4 0x0C34
1672 +#define BCMA_CC_NAND_SPARE_WR8 0x0C38
1673 +#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
1674 +#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
1675 +#define BCMA_CC_NAND_CONFIG 0x0C48
1676 +#define BCMA_CC_NAND_TIMING_1 0x0C50
1677 +#define BCMA_CC_NAND_TIMING_2 0x0C54
1678 +#define BCMA_CC_NAND_SEMAPHORE 0x0C58
1679 +#define BCMA_CC_NAND_DEVID 0x0C60
1680 +#define BCMA_CC_NAND_DEVID_X 0x0C64
1681 +#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
1682 +#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
1683 +#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
1684 +#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
1685 +#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
1686 +#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
1687 +#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
1688 +#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
1689 +#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
1690 +#define BCMA_CC_NAND_READ_ADDR 0x0C94
1691 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
1692 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
1693 +#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
1694 +#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
1695 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
1696 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
1697 +#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
1698 +#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
1699 +#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
1700 +#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
1701 +#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
1702 +#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
1703 +#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
1704 +#define BCMA_CC_NAND_SPARE_RD16 0x0D30
1705 +#define BCMA_CC_NAND_SPARE_RD20 0x0D34
1706 +#define BCMA_CC_NAND_SPARE_RD24 0x0D38
1707 +#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
1708 +#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
1709 +#define BCMA_CC_NAND_CACHE_DATA 0x0D44
1710 +#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
1711 +#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
1712
1713 /* Divider allocation in 4716/47162/5356 */
1714 #define BCMA_CC_PMU5_MAINPLL_CPU 1
1715 @@ -415,6 +496,13 @@
1716 /* 4313 Chip specific ChipControl register bits */
1717 #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
1718
1719 +/* BCM5357 ChipControl register bits */
1720 +#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
1721 +#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
1722 +#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
1723 +#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
1724 +#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
1725 +
1726 /* Data for the PMU, if available.
1727 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
1728 */
1729 @@ -425,11 +513,35 @@ struct bcma_chipcommon_pmu {
1730
1731 #ifdef CONFIG_BCMA_DRIVER_MIPS
1732 struct bcma_pflash {
1733 + bool present;
1734 u8 buswidth;
1735 u32 window;
1736 u32 window_size;
1737 };
1738
1739 +#ifdef CONFIG_BCMA_SFLASH
1740 +struct bcma_sflash {
1741 + bool present;
1742 + u32 window;
1743 + u32 blocksize;
1744 + u16 numblocks;
1745 + u32 size;
1746 +
1747 + struct mtd_info *mtd;
1748 +};
1749 +#endif
1750 +
1751 +#ifdef CONFIG_BCMA_NFLASH
1752 +struct mtd_info;
1753 +
1754 +struct bcma_nflash {
1755 + bool present;
1756 + bool boot; /* This is the flash the SoC boots from */
1757 +
1758 + struct mtd_info *mtd;
1759 +};
1760 +#endif
1761 +
1762 struct bcma_serial_port {
1763 void *regs;
1764 unsigned long clockspeed;
1765 @@ -445,15 +557,30 @@ struct bcma_drv_cc {
1766 u32 capabilities;
1767 u32 capabilities_ext;
1768 u8 setup_done:1;
1769 + u8 early_setup_done:1;
1770 /* Fast Powerup Delay constant */
1771 u16 fast_pwrup_delay;
1772 struct bcma_chipcommon_pmu pmu;
1773 #ifdef CONFIG_BCMA_DRIVER_MIPS
1774 struct bcma_pflash pflash;
1775 +#ifdef CONFIG_BCMA_SFLASH
1776 + struct bcma_sflash sflash;
1777 +#endif
1778 +#ifdef CONFIG_BCMA_NFLASH
1779 + struct bcma_nflash nflash;
1780 +#endif
1781
1782 int nr_serial_ports;
1783 struct bcma_serial_port serial_ports[4];
1784 #endif /* CONFIG_BCMA_DRIVER_MIPS */
1785 + u32 ticks_per_ms;
1786 + struct platform_device *watchdog;
1787 +
1788 + /* Lock for GPIO register access. */
1789 + spinlock_t gpio_lock;
1790 +#ifdef CONFIG_BCMA_DRIVER_GPIO
1791 + struct gpio_chip gpio;
1792 +#endif
1793 };
1794
1795 /* Register access */
1796 @@ -470,14 +597,14 @@ struct bcma_drv_cc {
1797 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
1798
1799 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
1800 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
1801
1802 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
1803 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
1804
1805 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
1806
1807 -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
1808 - u32 ticks);
1809 +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
1810
1811 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
1812
1813 @@ -490,9 +617,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
1814 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
1815 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
1816 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
1817 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
1818 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
1819
1820 /* PMU support */
1821 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
1822 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
1823
1824 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
1825 u32 value);
1826 --- a/include/linux/bcma/bcma_driver_mips.h
1827 +++ b/include/linux/bcma/bcma_driver_mips.h
1828 @@ -35,13 +35,15 @@ struct bcma_device;
1829 struct bcma_drv_mips {
1830 struct bcma_device *core;
1831 u8 setup_done:1;
1832 - unsigned int assigned_irqs;
1833 + u8 early_setup_done:1;
1834 };
1835
1836 #ifdef CONFIG_BCMA_DRIVER_MIPS
1837 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
1838 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
1839 #else
1840 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
1841 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
1842 #endif
1843
1844 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
1845 --- a/include/linux/bcma/bcma_regs.h
1846 +++ b/include/linux/bcma/bcma_regs.h
1847 @@ -11,11 +11,13 @@
1848 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1849 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1850 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
1851 +#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8
1852 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
1853 #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
1854 #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
1855 #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
1856 #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
1857 +#define BCMA_CLKCTLST_EXTRESST_SHIFT 24
1858 /* Is there any BCM4328 on BCMA bus? */
1859 #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
1860 #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
1861 @@ -83,4 +85,9 @@
1862 * (2 ZettaBytes), high 32 bits
1863 */
1864
1865 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
1866 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
1867 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
1868 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
1869 +
1870 #endif /* LINUX_BCMA_REGS_H_ */
1871 --- a/drivers/net/wireless/b43/main.c
1872 +++ b/drivers/net/wireless/b43/main.c
1873 @@ -4622,7 +4622,7 @@ static int b43_wireless_core_init(struct
1874 switch (dev->dev->bus_type) {
1875 #ifdef CONFIG_B43_BCMA
1876 case B43_BUS_BCMA:
1877 - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
1878 + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
1879 dev->dev->bdev, true);
1880 break;
1881 #endif
1882 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1883 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1884 @@ -695,7 +695,7 @@ void ai_pci_up(struct si_pub *sih)
1885 sii = container_of(sih, struct si_info, pub);
1886
1887 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1888 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
1889 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
1890 }
1891
1892 /* Unconfigure and/or apply various WARs when going down */
1893 @@ -706,7 +706,7 @@ void ai_pci_down(struct si_pub *sih)
1894 sii = container_of(sih, struct si_info, pub);
1895
1896 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1897 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
1898 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
1899 }
1900
1901 /* Enable BT-COEX & Ex-PA for 4313 */
1902 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
1903 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
1904 @@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_
1905 * Configure pci/pcmcia here instead of in brcms_c_attach()
1906 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1907 */
1908 - bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
1909 + bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
1910 true);
1911
1912 /*
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