projects / openwrt / svn-archive / archive.git / blob
? search:


dec684239f7687250b1449ef1b43b180b6a07eff
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.7 / 020-ssb_update.patch
1 --- a/arch/mips/bcm47xx/nvram.c
2 +++ b/arch/mips/bcm47xx/nvram.c
3 @@ -43,8 +43,8 @@ static void early_nvram_init(void)
4 #ifdef CONFIG_BCM47XX_SSB
5 case BCM47XX_BUS_TYPE_SSB:
6 mcore_ssb = &bcm47xx_bus.ssb.mipscore;
7 - base = mcore_ssb->flash_window;
8 - lim = mcore_ssb->flash_window_size;
9 + base = mcore_ssb->pflash.window;
10 + lim = mcore_ssb->pflash.window_size;
11 break;
12 #endif
13 #ifdef CONFIG_BCM47XX_BCMA
14 --- a/arch/mips/bcm47xx/wgt634u.c
15 +++ b/arch/mips/bcm47xx/wgt634u.c
16 @@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
17 SSB_CHIPCO_IRQ_GPIO);
18 }
19
20 - wgt634u_flash_data.width = mcore->flash_buswidth;
21 - wgt634u_flash_resource.start = mcore->flash_window;
22 - wgt634u_flash_resource.end = mcore->flash_window
23 - + mcore->flash_window_size
24 + wgt634u_flash_data.width = mcore->pflash.buswidth;
25 + wgt634u_flash_resource.start = mcore->pflash.window;
26 + wgt634u_flash_resource.end = mcore->pflash.window
27 + + mcore->pflash.window_size
28 - 1;
29 return platform_add_devices(wgt634u_devices,
30 ARRAY_SIZE(wgt634u_devices));
31 --- a/drivers/ssb/Kconfig
32 +++ b/drivers/ssb/Kconfig
33 @@ -136,6 +136,11 @@ config SSB_DRIVER_MIPS
34
35 If unsure, say N
36
37 +config SSB_SFLASH
38 + bool "SSB serial flash support"
39 + depends on SSB_DRIVER_MIPS && BROKEN
40 + default y
41 +
42 # Assumption: We are on embedded, if we compile the MIPS core.
43 config SSB_EMBEDDED
44 bool
45 @@ -160,4 +165,12 @@ config SSB_DRIVER_GIGE
46
47 If unsure, say N
48
49 +config SSB_DRIVER_GPIO
50 + bool "SSB GPIO driver"
51 + depends on SSB && GPIOLIB
52 + help
53 + Driver to provide access to the GPIO pins on the bus.
54 +
55 + If unsure, say N
56 +
57 endmenu
58 --- a/drivers/ssb/Makefile
59 +++ b/drivers/ssb/Makefile
60 @@ -11,10 +11,12 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
61 # built-in drivers
62 ssb-y += driver_chipcommon.o
63 ssb-y += driver_chipcommon_pmu.o
64 +ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o
65 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
66 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
67 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
68 ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o
69 +ssb-$(CONFIG_SSB_DRIVER_GPIO) += driver_gpio.o
70
71 # b43 pci-ssb-bridge driver
72 # Not strictly a part of SSB, but kept here for convenience
73 --- a/drivers/ssb/b43_pci_bridge.c
74 +++ b/drivers/ssb/b43_pci_bridge.c
75 @@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
76 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
77 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
78 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
79 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
80 { 0, },
81 };
82 MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
83 --- a/drivers/ssb/driver_chipcommon.c
84 +++ b/drivers/ssb/driver_chipcommon.c
85 @@ -4,6 +4,7 @@
86 *
87 * Copyright 2005, Broadcom Corporation
88 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
89 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
90 *
91 * Licensed under the GNU/GPL. See COPYING for details.
92 */
93 @@ -12,6 +13,7 @@
94 #include <linux/ssb/ssb_regs.h>
95 #include <linux/export.h>
96 #include <linux/pci.h>
97 +#include <linux/bcm47xx_wdt.h>
98
99 #include "ssb_private.h"
100
101 @@ -280,10 +282,76 @@ static void calc_fast_powerup_delay(stru
102 cc->fast_pwrup_delay = tmp;
103 }
104
105 +static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
106 +{
107 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
108 + return ssb_pmu_get_alp_clock(cc);
109 +
110 + return 20000000;
111 +}
112 +
113 +static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
114 +{
115 + u32 nb;
116 +
117 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
118 + if (cc->dev->id.revision < 26)
119 + nb = 16;
120 + else
121 + nb = (cc->dev->id.revision >= 37) ? 32 : 24;
122 + } else {
123 + nb = 28;
124 + }
125 + if (nb == 32)
126 + return 0xffffffff;
127 + else
128 + return (1 << nb) - 1;
129 +}
130 +
131 +u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
132 +{
133 + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
134 +
135 + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
136 + return 0;
137 +
138 + return ssb_chipco_watchdog_timer_set(cc, ticks);
139 +}
140 +
141 +u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
142 +{
143 + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
144 + u32 ticks;
145 +
146 + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
147 + return 0;
148 +
149 + ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
150 + return ticks / cc->ticks_per_ms;
151 +}
152 +
153 +static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
154 +{
155 + struct ssb_bus *bus = cc->dev->bus;
156 +
157 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
158 + /* based on 32KHz ILP clock */
159 + return 32;
160 + } else {
161 + if (cc->dev->id.revision < 18)
162 + return ssb_clockspeed(bus) / 1000;
163 + else
164 + return ssb_chipco_alp_clock(cc) / 1000;
165 + }
166 +}
167 +
168 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
169 {
170 if (!cc->dev)
171 return; /* We don't have a ChipCommon */
172 +
173 + spin_lock_init(&cc->gpio_lock);
174 +
175 if (cc->dev->id.revision >= 11)
176 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
177 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
178 @@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip
179 chipco_powercontrol_init(cc);
180 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
181 calc_fast_powerup_delay(cc);
182 +
183 + if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
184 + cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
185 + cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
186 + }
187 }
188
189 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
190 @@ -395,10 +468,27 @@ void ssb_chipco_timing_init(struct ssb_c
191 }
192
193 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
194 -void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
195 +u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
196 {
197 - /* instant NMI */
198 - chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
199 + u32 maxt;
200 + enum ssb_clkmode clkmode;
201 +
202 + maxt = ssb_chipco_watchdog_get_max_timer(cc);
203 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
204 + if (ticks == 1)
205 + ticks = 2;
206 + else if (ticks > maxt)
207 + ticks = maxt;
208 + chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
209 + } else {
210 + clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
211 + ssb_chipco_set_clockmode(cc, clkmode);
212 + if (ticks > maxt)
213 + ticks = maxt;
214 + /* instant NMI */
215 + chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
216 + }
217 + return ticks;
218 }
219
220 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
221 @@ -418,28 +508,93 @@ u32 ssb_chipco_gpio_in(struct ssb_chipco
222
223 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
224 {
225 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
226 + unsigned long flags;
227 + u32 res = 0;
228 +
229 + spin_lock_irqsave(&cc->gpio_lock, flags);
230 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
231 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
232 +
233 + return res;
234 }
235
236 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
237 {
238 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
239 + unsigned long flags;
240 + u32 res = 0;
241 +
242 + spin_lock_irqsave(&cc->gpio_lock, flags);
243 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
244 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
245 +
246 + return res;
247 }
248
249 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
250 {
251 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
252 + unsigned long flags;
253 + u32 res = 0;
254 +
255 + spin_lock_irqsave(&cc->gpio_lock, flags);
256 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
257 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
258 +
259 + return res;
260 }
261 EXPORT_SYMBOL(ssb_chipco_gpio_control);
262
263 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
264 {
265 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
266 + unsigned long flags;
267 + u32 res = 0;
268 +
269 + spin_lock_irqsave(&cc->gpio_lock, flags);
270 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
271 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
272 +
273 + return res;
274 }
275
276 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
277 {
278 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
279 + unsigned long flags;
280 + u32 res = 0;
281 +
282 + spin_lock_irqsave(&cc->gpio_lock, flags);
283 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
284 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
285 +
286 + return res;
287 +}
288 +
289 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
290 +{
291 + unsigned long flags;
292 + u32 res = 0;
293 +
294 + if (cc->dev->id.revision < 20)
295 + return 0xffffffff;
296 +
297 + spin_lock_irqsave(&cc->gpio_lock, flags);
298 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
299 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
300 +
301 + return res;
302 +}
303 +
304 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
305 +{
306 + unsigned long flags;
307 + u32 res = 0;
308 +
309 + if (cc->dev->id.revision < 20)
310 + return 0xffffffff;
311 +
312 + spin_lock_irqsave(&cc->gpio_lock, flags);
313 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
314 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
315 +
316 + return res;
317 }
318
319 #ifdef CONFIG_SSB_SERIAL
320 @@ -473,12 +628,7 @@ int ssb_chipco_serial_init(struct ssb_ch
321 chipco_read32(cc, SSB_CHIPCO_CORECTL)
322 | SSB_CHIPCO_CORECTL_UARTCLK0);
323 } else if ((ccrev >= 11) && (ccrev != 15)) {
324 - /* Fixed ALP clock */
325 - baud_base = 20000000;
326 - if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
327 - /* FIXME: baud_base is different for devices with a PMU */
328 - SSB_WARN_ON(1);
329 - }
330 + baud_base = ssb_chipco_alp_clock(cc);
331 div = 1;
332 if (ccrev >= 21) {
333 /* Turn off UART clock before switching clocksource. */
334 --- a/drivers/ssb/driver_chipcommon_pmu.c
335 +++ b/drivers/ssb/driver_chipcommon_pmu.c
336 @@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
337 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
338 }
339 break;
340 + case 43222:
341 + break;
342 default:
343 ssb_printk(KERN_ERR PFX
344 "ERROR: PLL init unknown for device %04X\n",
345 @@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
346 min_msk = 0xCBB;
347 break;
348 case 0x4322:
349 + case 43222:
350 /* We keep the default settings:
351 * min_msk = 0xCBB
352 * max_msk = 0x7FFFF
353 @@ -615,6 +618,33 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
354 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
355 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
356
357 +static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
358 +{
359 + u32 crystalfreq;
360 + const struct pmu0_plltab_entry *e = NULL;
361 +
362 + crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
363 + SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
364 + e = pmu0_plltab_find_entry(crystalfreq);
365 + BUG_ON(!e);
366 + return e->freq * 1000;
367 +}
368 +
369 +u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
370 +{
371 + struct ssb_bus *bus = cc->dev->bus;
372 +
373 + switch (bus->chip_id) {
374 + case 0x5354:
375 + ssb_pmu_get_alp_clock_clk0(cc);
376 + default:
377 + ssb_printk(KERN_ERR PFX
378 + "ERROR: PMU alp clock unknown for device %04X\n",
379 + bus->chip_id);
380 + return 0;
381 + }
382 +}
383 +
384 u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
385 {
386 struct ssb_bus *bus = cc->dev->bus;
387 --- /dev/null
388 +++ b/drivers/ssb/driver_chipcommon_sflash.c
389 @@ -0,0 +1,18 @@
390 +/*
391 + * Sonics Silicon Backplane
392 + * ChipCommon serial flash interface
393 + *
394 + * Licensed under the GNU/GPL. See COPYING for details.
395 + */
396 +
397 +#include <linux/ssb/ssb.h>
398 +
399 +#include "ssb_private.h"
400 +
401 +/* Initialize serial flash access */
402 +int ssb_sflash_init(struct ssb_chipcommon *cc)
403 +{
404 + pr_err("Serial flash support is not implemented yet!\n");
405 +
406 + return -ENOTSUPP;
407 +}
408 --- a/drivers/ssb/driver_extif.c
409 +++ b/drivers/ssb/driver_extif.c
410 @@ -112,10 +112,37 @@ void ssb_extif_get_clockcontrol(struct s
411 *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
412 }
413
414 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
415 - u32 ticks)
416 +u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
417 {
418 + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
419 +
420 + return ssb_extif_watchdog_timer_set(extif, ticks);
421 +}
422 +
423 +u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
424 +{
425 + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
426 + u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
427 +
428 + ticks = ssb_extif_watchdog_timer_set(extif, ticks);
429 +
430 + return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
431 +}
432 +
433 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
434 +{
435 + if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
436 + ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
437 extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
438 +
439 + return ticks;
440 +}
441 +
442 +void ssb_extif_init(struct ssb_extif *extif)
443 +{
444 + if (!extif->dev)
445 + return; /* We don't have a Extif core */
446 + spin_lock_init(&extif->gpio_lock);
447 }
448
449 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
450 @@ -125,22 +152,50 @@ u32 ssb_extif_gpio_in(struct ssb_extif *
451
452 u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
453 {
454 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
455 + unsigned long flags;
456 + u32 res = 0;
457 +
458 + spin_lock_irqsave(&extif->gpio_lock, flags);
459 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
460 mask, value);
461 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
462 +
463 + return res;
464 }
465
466 u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
467 {
468 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
469 + unsigned long flags;
470 + u32 res = 0;
471 +
472 + spin_lock_irqsave(&extif->gpio_lock, flags);
473 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
474 mask, value);
475 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
476 +
477 + return res;
478 }
479
480 u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
481 {
482 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
483 + unsigned long flags;
484 + u32 res = 0;
485 +
486 + spin_lock_irqsave(&extif->gpio_lock, flags);
487 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
488 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
489 +
490 + return res;
491 }
492
493 u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
494 {
495 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
496 + unsigned long flags;
497 + u32 res = 0;
498 +
499 + spin_lock_irqsave(&extif->gpio_lock, flags);
500 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
501 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
502 +
503 + return res;
504 }
505 --- /dev/null
506 +++ b/drivers/ssb/driver_gpio.c
507 @@ -0,0 +1,176 @@
508 +/*
509 + * Sonics Silicon Backplane
510 + * GPIO driver
511 + *
512 + * Copyright 2011, Broadcom Corporation
513 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
514 + *
515 + * Licensed under the GNU/GPL. See COPYING for details.
516 + */
517 +
518 +#include <linux/gpio.h>
519 +#include <linux/export.h>
520 +#include <linux/ssb/ssb.h>
521 +
522 +#include "ssb_private.h"
523 +
524 +static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip)
525 +{
526 + return container_of(chip, struct ssb_bus, gpio);
527 +}
528 +
529 +static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio)
530 +{
531 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
532 +
533 + return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio);
534 +}
535 +
536 +static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio,
537 + int value)
538 +{
539 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
540 +
541 + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
542 +}
543 +
544 +static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip,
545 + unsigned gpio)
546 +{
547 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
548 +
549 + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0);
550 + return 0;
551 +}
552 +
553 +static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip,
554 + unsigned gpio, int value)
555 +{
556 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
557 +
558 + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio);
559 + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
560 + return 0;
561 +}
562 +
563 +static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio)
564 +{
565 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
566 +
567 + ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0);
568 + /* clear pulldown */
569 + ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0);
570 + /* Set pullup */
571 + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio);
572 +
573 + return 0;
574 +}
575 +
576 +static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio)
577 +{
578 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
579 +
580 + /* clear pullup */
581 + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
582 +}
583 +
584 +static int ssb_gpio_chipco_init(struct ssb_bus *bus)
585 +{
586 + struct gpio_chip *chip = &bus->gpio;
587 +
588 + chip->label = "ssb_chipco_gpio";
589 + chip->owner = THIS_MODULE;
590 + chip->request = ssb_gpio_chipco_request;
591 + chip->free = ssb_gpio_chipco_free;
592 + chip->get = ssb_gpio_chipco_get_value;
593 + chip->set = ssb_gpio_chipco_set_value;
594 + chip->direction_input = ssb_gpio_chipco_direction_input;
595 + chip->direction_output = ssb_gpio_chipco_direction_output;
596 + chip->ngpio = 16;
597 + /* There is just one SoC in one device and its GPIO addresses should be
598 + * deterministic to address them more easily. The other buses could get
599 + * a random base number. */
600 + if (bus->bustype == SSB_BUSTYPE_SSB)
601 + chip->base = 0;
602 + else
603 + chip->base = -1;
604 +
605 + return gpiochip_add(chip);
606 +}
607 +
608 +#ifdef CONFIG_SSB_DRIVER_EXTIF
609 +
610 +static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio)
611 +{
612 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
613 +
614 + return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio);
615 +}
616 +
617 +static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio,
618 + int value)
619 +{
620 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
621 +
622 + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
623 +}
624 +
625 +static int ssb_gpio_extif_direction_input(struct gpio_chip *chip,
626 + unsigned gpio)
627 +{
628 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
629 +
630 + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0);
631 + return 0;
632 +}
633 +
634 +static int ssb_gpio_extif_direction_output(struct gpio_chip *chip,
635 + unsigned gpio, int value)
636 +{
637 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
638 +
639 + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio);
640 + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
641 + return 0;
642 +}
643 +
644 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
645 +{
646 + struct gpio_chip *chip = &bus->gpio;
647 +
648 + chip->label = "ssb_extif_gpio";
649 + chip->owner = THIS_MODULE;
650 + chip->get = ssb_gpio_extif_get_value;
651 + chip->set = ssb_gpio_extif_set_value;
652 + chip->direction_input = ssb_gpio_extif_direction_input;
653 + chip->direction_output = ssb_gpio_extif_direction_output;
654 + chip->ngpio = 5;
655 + /* There is just one SoC in one device and its GPIO addresses should be
656 + * deterministic to address them more easily. The other buses could get
657 + * a random base number. */
658 + if (bus->bustype == SSB_BUSTYPE_SSB)
659 + chip->base = 0;
660 + else
661 + chip->base = -1;
662 +
663 + return gpiochip_add(chip);
664 +}
665 +
666 +#else
667 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
668 +{
669 + return -ENOTSUPP;
670 +}
671 +#endif
672 +
673 +int ssb_gpio_init(struct ssb_bus *bus)
674 +{
675 + if (ssb_chipco_available(&bus->chipco))
676 + return ssb_gpio_chipco_init(bus);
677 + else if (ssb_extif_available(&bus->extif))
678 + return ssb_gpio_extif_init(bus);
679 + else
680 + SSB_WARN_ON(1);
681 +
682 + return -1;
683 +}
684 --- a/drivers/ssb/driver_mipscore.c
685 +++ b/drivers/ssb/driver_mipscore.c
686 @@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
687 {
688 struct ssb_bus *bus = mcore->dev->bus;
689
690 - if (bus->extif.dev)
691 + if (ssb_extif_available(&bus->extif))
692 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
693 - else if (bus->chipco.dev)
694 + else if (ssb_chipco_available(&bus->chipco))
695 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
696 else
697 mcore->nr_serial_ports = 0;
698 @@ -191,10 +191,11 @@ static void ssb_mips_flash_detect(struct
699 struct ssb_bus *bus = mcore->dev->bus;
700
701 /* When there is no chipcommon on the bus there is 4MB flash */
702 - if (!bus->chipco.dev) {
703 - mcore->flash_buswidth = 2;
704 - mcore->flash_window = SSB_FLASH1;
705 - mcore->flash_window_size = SSB_FLASH1_SZ;
706 + if (!ssb_chipco_available(&bus->chipco)) {
707 + mcore->pflash.present = true;
708 + mcore->pflash.buswidth = 2;
709 + mcore->pflash.window = SSB_FLASH1;
710 + mcore->pflash.window_size = SSB_FLASH1_SZ;
711 return;
712 }
713
714 @@ -202,17 +203,19 @@ static void ssb_mips_flash_detect(struct
715 switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
716 case SSB_CHIPCO_FLASHT_STSER:
717 case SSB_CHIPCO_FLASHT_ATSER:
718 - pr_err("Serial flash not supported\n");
719 + pr_debug("Found serial flash\n");
720 + ssb_sflash_init(&bus->chipco);
721 break;
722 case SSB_CHIPCO_FLASHT_PARA:
723 pr_debug("Found parallel flash\n");
724 - mcore->flash_window = SSB_FLASH2;
725 - mcore->flash_window_size = SSB_FLASH2_SZ;
726 + mcore->pflash.present = true;
727 + mcore->pflash.window = SSB_FLASH2;
728 + mcore->pflash.window_size = SSB_FLASH2_SZ;
729 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
730 & SSB_CHIPCO_CFG_DS16) == 0)
731 - mcore->flash_buswidth = 1;
732 + mcore->pflash.buswidth = 1;
733 else
734 - mcore->flash_buswidth = 2;
735 + mcore->pflash.buswidth = 2;
736 break;
737 }
738 }
739 @@ -225,9 +228,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
740 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
741 return ssb_pmu_get_cpu_clock(&bus->chipco);
742
743 - if (bus->extif.dev) {
744 + if (ssb_extif_available(&bus->extif)) {
745 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
746 - } else if (bus->chipco.dev) {
747 + } else if (ssb_chipco_available(&bus->chipco)) {
748 ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
749 } else
750 return 0;
751 @@ -263,9 +266,9 @@ void ssb_mipscore_init(struct ssb_mipsco
752 hz = 100000000;
753 ns = 1000000000 / hz;
754
755 - if (bus->extif.dev)
756 + if (ssb_extif_available(&bus->extif))
757 ssb_extif_timing_init(&bus->extif, ns);
758 - else if (bus->chipco.dev)
759 + else if (ssb_chipco_available(&bus->chipco))
760 ssb_chipco_timing_init(&bus->chipco, ns);
761
762 /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
763 --- a/drivers/ssb/embedded.c
764 +++ b/drivers/ssb/embedded.c
765 @@ -4,11 +4,13 @@
766 *
767 * Copyright 2005-2008, Broadcom Corporation
768 * Copyright 2006-2008, Michael Buesch <m@bues.ch>
769 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
770 *
771 * Licensed under the GNU/GPL. See COPYING for details.
772 */
773
774 #include <linux/export.h>
775 +#include <linux/platform_device.h>
776 #include <linux/ssb/ssb.h>
777 #include <linux/ssb/ssb_embedded.h>
778 #include <linux/ssb/ssb_driver_pci.h>
779 @@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
780 }
781 EXPORT_SYMBOL(ssb_watchdog_timer_set);
782
783 +int ssb_watchdog_register(struct ssb_bus *bus)
784 +{
785 + struct bcm47xx_wdt wdt = {};
786 + struct platform_device *pdev;
787 +
788 + if (ssb_chipco_available(&bus->chipco)) {
789 + wdt.driver_data = &bus->chipco;
790 + wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
791 + wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
792 + wdt.max_timer_ms = bus->chipco.max_timer_ms;
793 + } else if (ssb_extif_available(&bus->extif)) {
794 + wdt.driver_data = &bus->extif;
795 + wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
796 + wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
797 + wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
798 + } else {
799 + return -ENODEV;
800 + }
801 +
802 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
803 + bus->busnumber, &wdt,
804 + sizeof(wdt));
805 + if (IS_ERR(pdev)) {
806 + ssb_dprintk(KERN_INFO PFX
807 + "can not register watchdog device, err: %li\n",
808 + PTR_ERR(pdev));
809 + return PTR_ERR(pdev);
810 + }
811 +
812 + bus->watchdog = pdev;
813 + return 0;
814 +}
815 +
816 u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
817 {
818 unsigned long flags;
819 --- a/drivers/ssb/main.c
820 +++ b/drivers/ssb/main.c
821 @@ -13,6 +13,7 @@
822 #include <linux/delay.h>
823 #include <linux/io.h>
824 #include <linux/module.h>
825 +#include <linux/platform_device.h>
826 #include <linux/ssb/ssb.h>
827 #include <linux/ssb/ssb_regs.h>
828 #include <linux/ssb/ssb_driver_gige.h>
829 @@ -433,6 +434,11 @@ static void ssb_devices_unregister(struc
830 if (sdev->dev)
831 device_unregister(sdev->dev);
832 }
833 +
834 +#ifdef CONFIG_SSB_EMBEDDED
835 + if (bus->bustype == SSB_BUSTYPE_SSB)
836 + platform_device_unregister(bus->watchdog);
837 +#endif
838 }
839
840 void ssb_bus_unregister(struct ssb_bus *bus)
841 @@ -561,6 +567,8 @@ static int __devinit ssb_attach_queued_b
842 if (err)
843 goto error;
844 ssb_pcicore_init(&bus->pcicore);
845 + if (bus->bustype == SSB_BUSTYPE_SSB)
846 + ssb_watchdog_register(bus);
847 ssb_bus_may_powerdown(bus);
848
849 err = ssb_devices_register(bus);
850 @@ -796,7 +804,14 @@ static int __devinit ssb_bus_register(st
851 if (err)
852 goto err_pcmcia_exit;
853 ssb_chipcommon_init(&bus->chipco);
854 + ssb_extif_init(&bus->extif);
855 ssb_mipscore_init(&bus->mipscore);
856 + err = ssb_gpio_init(bus);
857 + if (err == -ENOTSUPP)
858 + ssb_dprintk(KERN_DEBUG PFX "GPIO driver not activated\n");
859 + else if (err)
860 + ssb_dprintk(KERN_ERR PFX
861 + "Error registering GPIO driver: %i\n", err);
862 err = ssb_fetch_invariants(bus, get_invariants);
863 if (err) {
864 ssb_bus_may_powerdown(bus);
865 @@ -1118,8 +1133,7 @@ static u32 ssb_tmslow_reject_bitmask(str
866 case SSB_IDLOW_SSBREV_27: /* same here */
867 return SSB_TMSLOW_REJECT; /* this is a guess */
868 default:
869 - printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
870 - WARN_ON(1);
871 + WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
872 }
873 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
874 }
875 --- a/drivers/ssb/ssb_private.h
876 +++ b/drivers/ssb/ssb_private.h
877 @@ -3,6 +3,7 @@
878
879 #include <linux/ssb/ssb.h>
880 #include <linux/types.h>
881 +#include <linux/bcm47xx_wdt.h>
882
883
884 #define PFX "ssb: "
885 @@ -210,5 +211,63 @@ static inline void b43_pci_ssb_bridge_ex
886 /* driver_chipcommon_pmu.c */
887 extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
888 extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
889 +extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
890 +
891 +extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
892 + u32 ticks);
893 +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
894 +
895 +/* driver_chipcommon_sflash.c */
896 +#ifdef CONFIG_SSB_SFLASH
897 +int ssb_sflash_init(struct ssb_chipcommon *cc);
898 +#else
899 +static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
900 +{
901 + pr_err("Serial flash not supported\n");
902 + return 0;
903 +}
904 +#endif /* CONFIG_SSB_SFLASH */
905 +
906 +#ifdef CONFIG_SSB_DRIVER_EXTIF
907 +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
908 +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
909 +#else
910 +static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
911 + u32 ticks)
912 +{
913 + return 0;
914 +}
915 +static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
916 + u32 ms)
917 +{
918 + return 0;
919 +}
920 +#endif
921 +
922 +#ifdef CONFIG_SSB_EMBEDDED
923 +extern int ssb_watchdog_register(struct ssb_bus *bus);
924 +#else /* CONFIG_SSB_EMBEDDED */
925 +static inline int ssb_watchdog_register(struct ssb_bus *bus)
926 +{
927 + return 0;
928 +}
929 +#endif /* CONFIG_SSB_EMBEDDED */
930 +
931 +#ifdef CONFIG_SSB_DRIVER_EXTIF
932 +extern void ssb_extif_init(struct ssb_extif *extif);
933 +#else
934 +static inline void ssb_extif_init(struct ssb_extif *extif)
935 +{
936 +}
937 +#endif
938 +
939 +#ifdef CONFIG_SSB_DRIVER_GPIO
940 +extern int ssb_gpio_init(struct ssb_bus *bus);
941 +#else /* CONFIG_SSB_DRIVER_GPIO */
942 +static inline int ssb_gpio_init(struct ssb_bus *bus)
943 +{
944 + return -ENOTSUPP;
945 +}
946 +#endif /* CONFIG_SSB_DRIVER_GPIO */
947
948 #endif /* LINUX_SSB_PRIVATE_H_ */
949 --- a/include/linux/ssb/ssb.h
950 +++ b/include/linux/ssb/ssb.h
951 @@ -6,8 +6,10 @@
952 #include <linux/types.h>
953 #include <linux/spinlock.h>
954 #include <linux/pci.h>
955 +#include <linux/gpio.h>
956 #include <linux/mod_devicetable.h>
957 #include <linux/dma-mapping.h>
958 +#include <linux/platform_device.h>
959
960 #include <linux/ssb/ssb_regs.h>
961
962 @@ -432,7 +434,11 @@ struct ssb_bus {
963 #ifdef CONFIG_SSB_EMBEDDED
964 /* Lock for GPIO register access. */
965 spinlock_t gpio_lock;
966 + struct platform_device *watchdog;
967 #endif /* EMBEDDED */
968 +#ifdef CONFIG_SSB_DRIVER_GPIO
969 + struct gpio_chip gpio;
970 +#endif /* DRIVER_GPIO */
971
972 /* Internal-only stuff follows. Do not touch. */
973 struct list_head list;
974 --- a/include/linux/ssb/ssb_driver_chipcommon.h
975 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
976 @@ -590,7 +590,10 @@ struct ssb_chipcommon {
977 u32 status;
978 /* Fast Powerup Delay constant */
979 u16 fast_pwrup_delay;
980 + spinlock_t gpio_lock;
981 struct ssb_chipcommon_pmu pmu;
982 + u32 ticks_per_ms;
983 + u32 max_timer_ms;
984 };
985
986 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
987 @@ -630,8 +633,7 @@ enum ssb_clkmode {
988 extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
989 enum ssb_clkmode mode);
990
991 -extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
992 - u32 ticks);
993 +extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
994
995 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
996
997 @@ -644,6 +646,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi
998 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
999 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
1000 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
1001 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value);
1002 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value);
1003
1004 #ifdef CONFIG_SSB_SERIAL
1005 extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
1006 --- a/include/linux/ssb/ssb_driver_extif.h
1007 +++ b/include/linux/ssb/ssb_driver_extif.h
1008 @@ -152,12 +152,16 @@
1009 /* watchdog */
1010 #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
1011
1012 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
1013 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
1014 + / (SSB_EXTIF_WATCHDOG_CLK / 1000))
1015
1016
1017 #ifdef CONFIG_SSB_DRIVER_EXTIF
1018
1019 struct ssb_extif {
1020 struct ssb_device *dev;
1021 + spinlock_t gpio_lock;
1022 };
1023
1024 static inline bool ssb_extif_available(struct ssb_extif *extif)
1025 @@ -171,8 +175,7 @@ extern void ssb_extif_get_clockcontrol(s
1026 extern void ssb_extif_timing_init(struct ssb_extif *extif,
1027 unsigned long ns);
1028
1029 -extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
1030 - u32 ticks);
1031 +extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
1032
1033 /* Extif GPIO pin access */
1034 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
1035 @@ -205,10 +208,52 @@ void ssb_extif_get_clockcontrol(struct s
1036 }
1037
1038 static inline
1039 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
1040 - u32 ticks)
1041 +void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
1042 {
1043 }
1044
1045 +static inline
1046 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
1047 +{
1048 + return 0;
1049 +}
1050 +
1051 +static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
1052 +{
1053 + return 0;
1054 +}
1055 +
1056 +static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
1057 + u32 value)
1058 +{
1059 + return 0;
1060 +}
1061 +
1062 +static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
1063 + u32 value)
1064 +{
1065 + return 0;
1066 +}
1067 +
1068 +static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
1069 + u32 value)
1070 +{
1071 + return 0;
1072 +}
1073 +
1074 +static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
1075 + u32 value)
1076 +{
1077 + return 0;
1078 +}
1079 +
1080 +#ifdef CONFIG_SSB_SERIAL
1081 +static inline int ssb_extif_serial_init(struct ssb_extif *extif,
1082 + struct ssb_serial_port *ports)
1083 +{
1084 + return 0;
1085 +}
1086 +#endif /* CONFIG_SSB_SERIAL */
1087 +
1088 #endif /* CONFIG_SSB_DRIVER_EXTIF */
1089 #endif /* LINUX_SSB_EXTIFCORE_H_ */
1090 --- a/include/linux/ssb/ssb_driver_mips.h
1091 +++ b/include/linux/ssb/ssb_driver_mips.h
1092 @@ -13,6 +13,12 @@ struct ssb_serial_port {
1093 unsigned int reg_shift;
1094 };
1095
1096 +struct ssb_pflash {
1097 + bool present;
1098 + u8 buswidth;
1099 + u32 window;
1100 + u32 window_size;
1101 +};
1102
1103 struct ssb_mipscore {
1104 struct ssb_device *dev;
1105 @@ -20,9 +26,7 @@ struct ssb_mipscore {
1106 int nr_serial_ports;
1107 struct ssb_serial_port serial_ports[4];
1108
1109 - u8 flash_buswidth;
1110 - u32 flash_window;
1111 - u32 flash_window_size;
1112 + struct ssb_pflash pflash;
1113 };
1114
1115 extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
1116 --- a/include/linux/ssb/ssb_regs.h
1117 +++ b/include/linux/ssb/ssb_regs.h
1118 @@ -485,7 +485,7 @@
1119 #define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
1120 #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
1121 #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
1122 -#define SSB_SPROM8_TEMPDELTA 0x00BA
1123 +#define SSB_SPROM8_TEMPDELTA 0x00BC
1124 #define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
1125 #define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
1126 #define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
1127 --- /dev/null
1128 +++ b/include/linux/bcm47xx_wdt.h
1129 @@ -0,0 +1,19 @@
1130 +#ifndef LINUX_BCM47XX_WDT_H_
1131 +#define LINUX_BCM47XX_WDT_H_
1132 +
1133 +#include <linux/types.h>
1134 +
1135 +
1136 +struct bcm47xx_wdt {
1137 + u32 (*timer_set)(struct bcm47xx_wdt *, u32);
1138 + u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
1139 + u32 max_timer_ms;
1140 +
1141 + void *driver_data;
1142 +};
1143 +
1144 +static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
1145 +{
1146 + return wdt->driver_data;
1147 +}
1148 +#endif /* LINUX_BCM47XX_WDT_H_ */
OpenWrt SVN history