target/linux/generic/patches-3.9/025-bcma_backport.patch

   1 --- a/drivers/bcma/core.c
   2 +++ b/drivers/bcma/core.c
   3 @@ -104,7 +104,13 @@ void bcma_core_pll_ctl(struct bcma_devic
   4                 if (i)
   5                         bcma_err(core->bus, "PLL enable timeout\n");
   6         } else {
   7 -               bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
   8 +               /*
   9 +                * Mask the PLL but don't wait for it to be disabled. PLL may be
  10 +                * shared between cores and will be still up if there is another
  11 +                * core using it.
  12 +                */
  13 +               bcma_mask32(core, BCMA_CLKCTLST, ~req);
  14 +               bcma_read32(core, BCMA_CLKCTLST);
  15         }
  16  }
  17  EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
  18 --- a/drivers/bcma/driver_chipcommon.c
  19 +++ b/drivers/bcma/driver_chipcommon.c
  20 @@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked
  21         return value;
  22  }
  23
  24 -static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
  25 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
  26  {
  27         if (cc->capabilities & BCMA_CC_CAP_PMU)
  28                 return bcma_pmu_get_alp_clock(cc);
  29
  30         return 20000000;
  31  }
  32 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
  33
  34  static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
  35  {
  36 @@ -213,6 +214,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv
  37
  38         return res;
  39  }
  40 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
  41
  42  u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
  43  {
  44 @@ -225,6 +227,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
  45
  46         return res;
  47  }
  48 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
  49
  50  /*
  51   * If the bit is set to 0, chipcommon controlls this GPIO,
  52 --- a/drivers/bcma/driver_chipcommon_pmu.c
  53 +++ b/drivers/bcma/driver_chipcommon_pmu.c
  54 @@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d
  55         struct bcma_bus *bus = cc->core->bus;
  56
  57         switch (bus->chipinfo.id) {
  58 +       case BCMA_CHIP_ID_BCM4313:
  59 +       case BCMA_CHIP_ID_BCM43224:
  60 +       case BCMA_CHIP_ID_BCM43225:
  61 +       case BCMA_CHIP_ID_BCM43227:
  62 +       case BCMA_CHIP_ID_BCM43228:
  63 +       case BCMA_CHIP_ID_BCM4331:
  64 +       case BCMA_CHIP_ID_BCM43421:
  65 +       case BCMA_CHIP_ID_BCM43428:
  66 +       case BCMA_CHIP_ID_BCM43431:
  67         case BCMA_CHIP_ID_BCM4716:
  68 -       case BCMA_CHIP_ID_BCM4748:
  69         case BCMA_CHIP_ID_BCM47162:
  70 -       case BCMA_CHIP_ID_BCM4313:
  71 -       case BCMA_CHIP_ID_BCM5357:
  72 +       case BCMA_CHIP_ID_BCM4748:
  73         case BCMA_CHIP_ID_BCM4749:
  74 +       case BCMA_CHIP_ID_BCM5357:
  75         case BCMA_CHIP_ID_BCM53572:
  76 +       case BCMA_CHIP_ID_BCM6362:
  77                 /* always 20Mhz */
  78                 return 20000 * 1000;
  79 -       case BCMA_CHIP_ID_BCM5356:
  80         case BCMA_CHIP_ID_BCM4706:
  81 +       case BCMA_CHIP_ID_BCM5356:
  82                 /* always 25Mhz */
  83                 return 25000 * 1000;
  84 +       case BCMA_CHIP_ID_BCM43460:
  85 +       case BCMA_CHIP_ID_BCM4352:
  86 +       case BCMA_CHIP_ID_BCM4360:
  87 +               if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
  88 +                       return 40000 * 1000;
  89 +               else
  90 +                       return 20000 * 1000;
  91         default:
  92                 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
  93                           bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
  94 @@ -373,7 +389,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
  95                 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
  96                 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
  97
  98 -               tmp = 1 << 10;
  99 +               tmp = BCMA_CC_PMU_CTL_PLL_UPD;
 100                 break;
 101
 102         case BCMA_CHIP_ID_BCM4331:
 103 @@ -394,7 +410,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
 104                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
 105                                                      0x03000a08);
 106                 }
 107 -               tmp = 1 << 10;
 108 +               tmp = BCMA_CC_PMU_CTL_PLL_UPD;
 109                 break;
 110
 111         case BCMA_CHIP_ID_BCM43224:
 112 @@ -427,7 +443,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
 113                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 114                                                      0x88888815);
 115                 }
 116 -               tmp = 1 << 10;
 117 +               tmp = BCMA_CC_PMU_CTL_PLL_UPD;
 118                 break;
 119
 120         case BCMA_CHIP_ID_BCM4716:
 121 @@ -461,7 +477,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
 122                                                      0x88888815);
 123                 }
 124
 125 -               tmp = 3 << 9;
 126 +               tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
 127                 break;
 128
 129         case BCMA_CHIP_ID_BCM43227:
 130 @@ -497,7 +513,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
 131                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 132                                                      0x88888815);
 133                 }
 134 -               tmp = 1 << 10;
 135 +               tmp = BCMA_CC_PMU_CTL_PLL_UPD;
 136                 break;
 137         default:
 138                 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
 139 --- a/drivers/bcma/main.c
 140 +++ b/drivers/bcma/main.c
 141 @@ -120,6 +120,11 @@ static int bcma_register_cores(struct bc
 142                         continue;
 143                 }
 144
 145 +               /* Only first GMAC core on BCM4706 is connected and working */
 146 +               if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
 147 +                   core->core_unit > 0)
 148 +                       continue;
 149 +
 150                 core->dev.release = bcma_release_core_dev;
 151                 core->dev.bus = &bcma_bus_type;
 152                 dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
 153 --- a/drivers/bcma/scan.c
 154 +++ b/drivers/bcma/scan.c
 155 @@ -137,19 +137,19 @@ static void bcma_scan_switch_core(struct
 156                                        addr);
 157  }
 158
 159 -static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
 160 +static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr)
 161  {
 162         u32 ent = readl(*eromptr);
 163         (*eromptr)++;
 164         return ent;
 165  }
 166
 167 -static void bcma_erom_push_ent(u32 **eromptr)
 168 +static void bcma_erom_push_ent(u32 __iomem **eromptr)
 169  {
 170         (*eromptr)--;
 171  }
 172
 173 -static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
 174 +static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr)
 175  {
 176         u32 ent = bcma_erom_get_ent(bus, eromptr);
 177         if (!(ent & SCAN_ER_VALID))
 178 @@ -159,14 +159,14 @@ static s32 bcma_erom_get_ci(struct bcma_
 179         return ent;
 180  }
 181
 182 -static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
 183 +static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr)
 184  {
 185         u32 ent = bcma_erom_get_ent(bus, eromptr);
 186         bcma_erom_push_ent(eromptr);
 187         return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
 188  }
 189
 190 -static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
 191 +static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr)
 192  {
 193         u32 ent = bcma_erom_get_ent(bus, eromptr);
 194         bcma_erom_push_ent(eromptr);
 195 @@ -175,7 +175,7 @@ static bool bcma_erom_is_bridge(struct b
 196                 ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
 197  }
 198
 199 -static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
 200 +static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr)
 201  {
 202         u32 ent;
 203         while (1) {
 204 @@ -189,7 +189,7 @@ static void bcma_erom_skip_component(str
 205         bcma_erom_push_ent(eromptr);
 206  }
 207
 208 -static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
 209 +static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr)
 210  {
 211         u32 ent = bcma_erom_get_ent(bus, eromptr);
 212         if (!(ent & SCAN_ER_VALID))
 213 @@ -199,7 +199,7 @@ static s32 bcma_erom_get_mst_port(struct
 214         return ent;
 215  }
 216
 217 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
 218 +static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
 219                                   u32 type, u8 port)
 220  {
 221         u32 addrl, addrh, sizel, sizeh = 0;
 222 --- a/drivers/bcma/sprom.c
 223 +++ b/drivers/bcma/sprom.c
 224 @@ -217,6 +217,7 @@ static void bcma_sprom_extract_r8(struct
 225         }
 226
 227         SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
 228 +       SPEX(board_type, SSB_SPROM1_SPID, ~0, 0);
 229
 230         SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
 231              SSB_SPROM4_TXPID2G0_SHIFT);
 232 --- a/include/linux/bcma/bcma.h
 233 +++ b/include/linux/bcma/bcma.h
 234 @@ -134,6 +134,7 @@ struct bcma_host_ops {
 235  #define BCMA_CORE_I2S                  0x834
 236  #define BCMA_CORE_SDR_DDR1_MEM_CTL     0x835   /* SDR/DDR1 memory controller core */
 237  #define BCMA_CORE_SHIM                 0x837   /* SHIM component in ubus/6362 */
 238 +#define BCMA_CORE_ARM_CR4              0x83e
 239  #define BCMA_CORE_DEFAULT              0xFFF
 240
 241  #define BCMA_MAX_NR_CORES              16
 242 @@ -173,6 +174,60 @@ struct bcma_host_ops {
 243  #define BCMA_CHIP_ID_BCM53572  53572
 244  #define  BCMA_PKG_ID_BCM47188  9
 245
 246 +/* Board types (on PCI usually equals to the subsystem dev id) */
 247 +/* BCM4313 */
 248 +#define BCMA_BOARD_TYPE_BCM94313BU     0X050F
 249 +#define BCMA_BOARD_TYPE_BCM94313HM     0X0510
 250 +#define BCMA_BOARD_TYPE_BCM94313EPA    0X0511
 251 +#define BCMA_BOARD_TYPE_BCM94313HMG    0X051C
 252 +/* BCM4716 */
 253 +#define BCMA_BOARD_TYPE_BCM94716NR2    0X04CD
 254 +/* BCM43224 */
 255 +#define BCMA_BOARD_TYPE_BCM943224X21   0X056E
 256 +#define BCMA_BOARD_TYPE_BCM943224X21_FCC       0X00D1
 257 +#define BCMA_BOARD_TYPE_BCM943224X21B  0X00E9
 258 +#define BCMA_BOARD_TYPE_BCM943224M93   0X008B
 259 +#define BCMA_BOARD_TYPE_BCM943224M93A  0X0090
 260 +#define BCMA_BOARD_TYPE_BCM943224X16   0X0093
 261 +#define BCMA_BOARD_TYPE_BCM94322X9     0X008D
 262 +#define BCMA_BOARD_TYPE_BCM94322M35E   0X008E
 263 +/* BCM43228 */
 264 +#define BCMA_BOARD_TYPE_BCM943228BU8   0X0540
 265 +#define BCMA_BOARD_TYPE_BCM943228BU9   0X0541
 266 +#define BCMA_BOARD_TYPE_BCM943228BU    0X0542
 267 +#define BCMA_BOARD_TYPE_BCM943227HM4L  0X0543
 268 +#define BCMA_BOARD_TYPE_BCM943227HMB   0X0544
 269 +#define BCMA_BOARD_TYPE_BCM943228HM4L  0X0545
 270 +#define BCMA_BOARD_TYPE_BCM943228SD    0X0573
 271 +/* BCM4331 */
 272 +#define BCMA_BOARD_TYPE_BCM94331X19    0X00D6
 273 +#define BCMA_BOARD_TYPE_BCM94331X28    0X00E4
 274 +#define BCMA_BOARD_TYPE_BCM94331X28B   0X010E
 275 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX      0X00E4
 276 +#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC
 277 +#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED
 278 +#define BCMA_BOARD_TYPE_BCM94331X29B   0X00EF
 279 +#define BCMA_BOARD_TYPE_BCM94331CSAX   0X00EF
 280 +#define BCMA_BOARD_TYPE_BCM94331X19C   0X00F5
 281 +#define BCMA_BOARD_TYPE_BCM94331X33    0X00F4
 282 +#define BCMA_BOARD_TYPE_BCM94331BU     0X0523
 283 +#define BCMA_BOARD_TYPE_BCM94331S9BU   0X0524
 284 +#define BCMA_BOARD_TYPE_BCM94331MC     0X0525
 285 +#define BCMA_BOARD_TYPE_BCM94331MCI    0X0526
 286 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT4        0X0527
 287 +#define BCMA_BOARD_TYPE_BCM94331HM     0X0574
 288 +#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL       0X059B
 289 +#define BCMA_BOARD_TYPE_BCM94331MCH5   0X05A9
 290 +#define BCMA_BOARD_TYPE_BCM94331CS     0X05C6
 291 +#define BCMA_BOARD_TYPE_BCM94331CD     0X05DA
 292 +/* BCM53572 */
 293 +#define BCMA_BOARD_TYPE_BCM953572BU    0X058D
 294 +#define BCMA_BOARD_TYPE_BCM953572NR2   0X058E
 295 +#define BCMA_BOARD_TYPE_BCM947188NR2   0X058F
 296 +#define BCMA_BOARD_TYPE_BCM953572SDRNR2        0X0590
 297 +/* BCM43142 */
 298 +#define BCMA_BOARD_TYPE_BCM943142HM    0X05E0
 299 +
 300  struct bcma_device {
 301         struct bcma_bus *bus;
 302         struct bcma_device_id id;
 303 --- a/include/linux/bcma/bcma_driver_chipcommon.h
 304 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
 305 @@ -104,6 +104,7 @@
 306  #define  BCMA_CC_CHIPST_4706_MIPS_BENDIAN      BIT(3) /* 0: little, 1: big endian */
 307  #define  BCMA_CC_CHIPST_4706_PCIE1_DISABLE     BIT(5) /* PCIE1 enable strap pin */
 308  #define  BCMA_CC_CHIPST_5357_NAND_BOOT         BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
 309 +#define  BCMA_CC_CHIPST_4360_XTAL_40MZ         0x00000001
 310  #define BCMA_CC_JCMD                   0x0030          /* Rev >= 10 only */
 311  #define  BCMA_CC_JCMD_START            0x80000000
 312  #define  BCMA_CC_JCMD_BUSY             0x80000000
 313 @@ -315,6 +316,9 @@
 314  #define BCMA_CC_PMU_CTL                        0x0600 /* PMU control */
 315  #define  BCMA_CC_PMU_CTL_ILP_DIV       0xFFFF0000 /* ILP div mask */
 316  #define  BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
 317 +#define  BCMA_CC_PMU_CTL_RES           0x00006000 /* reset control mask */
 318 +#define  BCMA_CC_PMU_CTL_RES_SHIFT     13
 319 +#define  BCMA_CC_PMU_CTL_RES_RELOAD    0x2     /* reload POR values */
 320  #define  BCMA_CC_PMU_CTL_PLL_UPD       0x00000400
 321  #define  BCMA_CC_PMU_CTL_NOILPONW      0x00000200 /* No ILP on wait */
 322  #define  BCMA_CC_PMU_CTL_HTREQEN       0x00000100 /* HT req enable */
 323 @@ -607,6 +611,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
 324
 325  extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
 326
 327 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
 328 +
 329  void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
 330
 331  u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
 332 --- a/include/linux/bcma/bcma_regs.h
 333 +++ b/include/linux/bcma/bcma_regs.h
 334 @@ -37,6 +37,7 @@
 335  #define  BCMA_IOST_BIST_DONE           0x8000
 336  #define BCMA_RESET_CTL                 0x0800
 337  #define  BCMA_RESET_CTL_RESET          0x0001
 338 +#define BCMA_RESET_ST                  0x0804
 339
 340  /* BCMA PCI config space registers. */
 341  #define BCMA_PCI_PMCSR                 0x44