target/linux/ifxmips/files/arch/mips/ifxmips/clock.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; either version 2 of the License, or
   5  *   (at your option) any later version.
   6  *
   7  *   This program is distributed in the hope that it will be useful,
   8  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  *   GNU General Public License for more details.
  11  *
  12  *   You should have received a copy of the GNU General Public License
  13  *   along with this program; if not, write to the Free Software
  14  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  15  *
  16  *   Copyright (C) 2007 Xu Liang, infineon
  17  *   Copyright (C) 2008 John Crispin <blogic@openwrt.org>
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/version.h>
  23 #include <linux/types.h>
  24 #include <linux/fs.h>
  25 #include <linux/miscdevice.h>
  26 #include <linux/init.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/unistd.h>
  29 #include <linux/errno.h>
  30
  31 #include <asm/irq.h>
  32 #include <asm/div64.h>
  33
  34 #include <ifxmips.h>
  35 #include <ifxmips_cgu.h>
  36
  37 static unsigned int cgu_get_pll0_fdiv(void);
  38 unsigned int ifxmips_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
  39
  40 #define DDR_HZ ifxmips_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3]
  41
  42 static inline unsigned int get_input_clock(int pll)
  43 {
  44         switch (pll) {
  45         case 0:
  46                 if (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & CGU_PLL0_SRC)
  47                         return BASIS_INPUT_CRYSTAL_USB;
  48                 else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
  49                         return BASIC_INPUT_CLOCK_FREQUENCY_1;
  50                 else
  51                         return BASIC_INPUT_CLOCK_FREQUENCY_2;
  52         case 1:
  53                 if (CGU_PLL1_SRC)
  54                         return BASIS_INPUT_CRYSTAL_USB;
  55                 else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
  56                         return BASIC_INPUT_CLOCK_FREQUENCY_1;
  57                 else
  58                         return BASIC_INPUT_CLOCK_FREQUENCY_2;
  59         case 2:
  60                 switch (CGU_PLL2_SRC) {
  61                 case 0:
  62                         return cgu_get_pll0_fdiv();
  63                 case 1:
  64                         return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
  65                                 BASIC_INPUT_CLOCK_FREQUENCY_1 :
  66                                 BASIC_INPUT_CLOCK_FREQUENCY_2;
  67                 case 2:
  68                         return BASIS_INPUT_CRYSTAL_USB;
  69                 }
  70         default:
  71                 return 0;
  72         }
  73 }
  74
  75 static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
  76 {
  77         u64 res, clock = get_input_clock(pll);
  78
  79         res = num * clock;
  80         do_div(res, den);
  81         return res;
  82 }
  83
  84 static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
  85         unsigned int K)
  86 {
  87         unsigned int num = ((N + 1) << 10) + K;
  88         unsigned int den = (M + 1) << 10;
  89
  90         return cal_dsm(pll, num, den);
  91 }
  92
  93 static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
  94         unsigned int K)
  95 {
  96         unsigned int num = ((N + 1) << 11) + K + 512;
  97         unsigned int den = (M + 1) << 11;
  98
  99         return cal_dsm(pll, num, den);
 100 }
 101
 102 static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
 103         unsigned int K)
 104 {
 105         unsigned int num = K >= 512 ?
 106                 ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
 107         unsigned int den = (M + 1) << 12;
 108
 109         return cal_dsm(pll, num, den);
 110 }
 111
 112 static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
 113         unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
 114 {
 115         if (!dsmsel)
 116                 return mash_dsm(pll, M, N, K);
 117         else if (!phase_div_en)
 118                 return mash_dsm(pll, M, N, K);
 119         else
 120                 return ssff_dsm_2(pll, M, N, K);
 121 }
 122
 123 static inline unsigned int cgu_get_pll0_fosc(void)
 124 {
 125         if (CGU_PLL0_BYPASS)
 126                 return get_input_clock(0);
 127         else
 128                 return !CGU_PLL0_CFG_FRAC_EN
 129                         ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
 130                                 CGU_PLL0_PHASE_DIVIDER_ENABLE)
 131                         : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
 132                                 CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
 133 }
 134
 135 static unsigned int cgu_get_pll0_fdiv(void)
 136 {
 137         unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
 138         return (cgu_get_pll0_fosc() + (div >> 1)) / div;
 139 }
 140
 141 unsigned int cgu_get_io_region_clock(void)
 142 {
 143         unsigned int ret = cgu_get_pll0_fosc();
 144         switch (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
 145         default:
 146         case 0:
 147                 return (ret + 1) / 2;
 148         case 1:
 149                 return (ret * 2 + 2) / 5;
 150         case 2:
 151                 return (ret + 1) / 3;
 152         case 3:
 153                 return (ret + 2) / 4;
 154         }
 155 }
 156
 157 void cgu_setup_pci_clk(int external_clock)
 158 {
 159         /* set clock to 33Mhz */
 160         ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000,
 161                 IFXMIPS_CGU_IFCCR);
 162         ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000,
 163                 IFXMIPS_CGU_IFCCR);
 164         if (external_clock) {
 165                 ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~(1 << 16),
 166                         IFXMIPS_CGU_IFCCR);
 167                 ifxmips_w32((1 << 30), IFXMIPS_CGU_PCICR);
 168         } else {
 169                 ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16),
 170                         IFXMIPS_CGU_IFCCR);
 171                 ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
 172         }
 173 }
 174
 175 unsigned int cgu_get_fpi_bus_clock(int fpi)
 176 {
 177         unsigned int ret = cgu_get_io_region_clock();
 178         if ((fpi == 2) && (ifxmips_r32(IFXMIPS_CGU_SYS) & CGU_SYS_FPI_SEL))
 179                 ret >>= 1;
 180         return ret;
 181 }
 182 EXPORT_SYMBOL(cgu_get_fpi_bus_clock);
 183
 184 unsigned int ifxmips_get_cpu_hz(void)
 185 {
 186         unsigned int ddr_clock = DDR_HZ;
 187         switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc) {
 188         case 0:
 189                 return CLOCK_333M;
 190         case 4:
 191                 return ddr_clock;
 192         }
 193         return ddr_clock << 1;
 194 }
 195 EXPORT_SYMBOL(ifxmips_get_cpu_hz);
 196
 197 unsigned int ifxmips_get_fpi_hz(void)
 198 {
 199         unsigned int ddr_clock = DDR_HZ;
 200         if (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
 201                 return ddr_clock >> 1;
 202         return ddr_clock;
 203 }
 204 EXPORT_SYMBOL(ifxmips_get_fpi_hz);