target/linux/ifxmips/files/arch/mips/ifxmips/clock.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; either version 2 of the License, or
   5  *   (at your option) any later version.
   6  *
   7  *   This program is distributed in the hope that it will be useful,
   8  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  *   GNU General Public License for more details.
  11  *
  12  *   You should have received a copy of the GNU General Public License
  13  *   along with this program; if not, write to the Free Software
  14  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  15  *
  16  *   Copyright (C) 2007 Xu Liang, infineon
  17  *   Copyright (C) 2008 John Crispin <blogic@openwrt.org>
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/version.h>
  23 #include <linux/types.h>
  24 #include <linux/fs.h>
  25 #include <linux/miscdevice.h>
  26 #include <linux/init.h>
  27 #include <asm/uaccess.h>
  28 #include <asm/unistd.h>
  29 #include <asm/irq.h>
  30 #include <asm/div64.h>
  31 #include <linux/errno.h>
  32 #include <asm/ifxmips/ifxmips.h>
  33
  34 #define BASIC_INPUT_CLOCK_FREQUENCY_1   35328000
  35 #define BASIC_INPUT_CLOCK_FREQUENCY_2   36000000
  36
  37 #define BASIS_INPUT_CRYSTAL_USB         12000000
  38
  39 #define GET_BITS(x, msb, lsb)           (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
  40
  41
  42 #define CGU_PLL0_PHASE_DIVIDER_ENABLE   (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 31))
  43 #define CGU_PLL0_BYPASS                 (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 30))
  44 #define CGU_PLL0_CFG_DSMSEL             (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 28))
  45 #define CGU_PLL0_CFG_FRAC_EN            (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 27))
  46 #define CGU_PLL1_SRC                    (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 31))
  47 #define CGU_PLL1_BYPASS                 (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 30))
  48 #define CGU_PLL1_CFG_DSMSEL             (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 28))
  49 #define CGU_PLL1_CFG_FRAC_EN            (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 27))
  50 #define CGU_PLL2_PHASE_DIVIDER_ENABLE   (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 20))
  51 #define CGU_PLL2_BYPASS                 (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 19))
  52 #define CGU_SYS_FPI_SEL                 (1 << 6)
  53 #define CGU_SYS_DDR_SEL                 0x3
  54 #define CGU_PLL0_SRC                    (1 << 29)
  55
  56 #define CGU_PLL0_CFG_PLLK               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17)
  57 #define CGU_PLL0_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6)
  58 #define CGU_PLL0_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2)
  59 #define CGU_PLL1_CFG_PLLK               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17)
  60 #define CGU_PLL1_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6)
  61 #define CGU_PLL1_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2)
  62 #define CGU_PLL2_SRC                    GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17)
  63 #define CGU_PLL2_CFG_INPUT_DIV          GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13)
  64 #define CGU_PLL2_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6)
  65 #define CGU_PLL2_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2)
  66 #define CGU_IF_CLK_PCI_CLK              GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20)
  67
  68 static unsigned int cgu_get_pll0_fdiv(void);
  69 unsigned int ifxmips_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
  70
  71 #define DDR_HZ ifxmips_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3]
  72
  73
  74 static inline unsigned int
  75 get_input_clock(int pll)
  76 {
  77         switch(pll)
  78         {
  79         case 0:
  80                 if(ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & CGU_PLL0_SRC)
  81                         return BASIS_INPUT_CRYSTAL_USB;
  82                 else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
  83                         return BASIC_INPUT_CLOCK_FREQUENCY_1;
  84                 else
  85                         return BASIC_INPUT_CLOCK_FREQUENCY_2;
  86         case 1:
  87                 if(CGU_PLL1_SRC)
  88                         return BASIS_INPUT_CRYSTAL_USB;
  89                 else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
  90                         return BASIC_INPUT_CLOCK_FREQUENCY_1;
  91                 else
  92                         return BASIC_INPUT_CLOCK_FREQUENCY_2;
  93         case 2:
  94                 switch(CGU_PLL2_SRC)
  95                 {
  96                 case 0:
  97                         return cgu_get_pll0_fdiv();
  98                 case 1:
  99                         return CGU_PLL2_PHASE_DIVIDER_ENABLE ? BASIC_INPUT_CLOCK_FREQUENCY_1 : BASIC_INPUT_CLOCK_FREQUENCY_2;
 100                 case 2:
 101                         return BASIS_INPUT_CRYSTAL_USB;
 102                 }
 103         default:
 104                 return 0;
 105         }
 106 }
 107
 108 static inline unsigned int
 109 cal_dsm(int pll, unsigned int num, unsigned int den)
 110 {
 111         u64 res, clock = get_input_clock(pll);
 112
 113         res = num * clock;
 114         do_div(res, den);
 115         return res;
 116 }
 117
 118 static inline unsigned int
 119 mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K)
 120 {
 121         unsigned int num = ((N + 1) << 10) + K;
 122         unsigned int den = (M + 1) << 10;
 123
 124         return cal_dsm(pll, num, den);
 125 }
 126
 127 static inline unsigned int
 128 ssff_dsm_1(int pll, unsigned int M,     unsigned int N, unsigned int K)
 129 {
 130         unsigned int num = ((N + 1) << 11) + K + 512;
 131         unsigned int den = (M + 1) << 11;
 132
 133         return cal_dsm(pll, num, den);
 134 }
 135
 136 static inline unsigned int
 137 ssff_dsm_2(int pll, unsigned int M,     unsigned int N, unsigned int K)
 138 {
 139         unsigned int num = K >= 512 ?
 140                 ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
 141         unsigned int den = (M + 1) << 12;
 142
 143         return cal_dsm(pll, num, den);
 144 }
 145
 146 static inline unsigned int
 147 dsm(int pll, unsigned int M, unsigned int N, unsigned int K,
 148         unsigned int dsmsel, unsigned int phase_div_en)
 149 {
 150         if(!dsmsel)
 151                 return mash_dsm(pll, M, N, K);
 152         else if(!phase_div_en)
 153                 return mash_dsm(pll, M, N, K);
 154         else
 155                 return ssff_dsm_2(pll, M, N, K);
 156 }
 157
 158 static inline unsigned int
 159 cgu_get_pll0_fosc(void)
 160 {
 161         if(CGU_PLL0_BYPASS)
 162                 return get_input_clock(0);
 163         else
 164                 return !CGU_PLL0_CFG_FRAC_EN
 165                         ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
 166                                 CGU_PLL0_PHASE_DIVIDER_ENABLE)
 167                         : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
 168                                 CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
 169 }
 170
 171 static unsigned int
 172 cgu_get_pll0_fdiv(void)
 173 {
 174         register unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
 175         return (cgu_get_pll0_fosc() + (div >> 1)) / div;
 176 }
 177
 178 unsigned int
 179 cgu_get_io_region_clock(void)
 180 {
 181         register unsigned int ret = cgu_get_pll0_fosc();
 182         switch(ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL)
 183         {
 184         default:
 185         case 0:
 186                 return (ret + 1) / 2;
 187         case 1:
 188                 return (ret * 2 + 2) / 5;
 189         case 2:
 190                 return (ret + 1) / 3;
 191         case 3:
 192                 return (ret + 2) / 4;
 193         }
 194 }
 195
 196 unsigned int
 197 cgu_get_fpi_bus_clock(int fpi)
 198 {
 199         register unsigned int ret = cgu_get_io_region_clock();
 200         if((fpi == 2) && (ifxmips_r32(IFXMIPS_CGU_SYS) & CGU_SYS_FPI_SEL))
 201                 ret >>= 1;
 202         return ret;
 203 }
 204
 205 void cgu_setup_pci_clk(int external_clock)
 206 {
 207         //set clock to 33Mhz
 208         ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
 209         ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
 210         if(external_clock)
 211         {
 212                 ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~ (1 << 16), IFXMIPS_CGU_IFCCR);
 213                 ifxmips_w32((1 << 30), IFXMIPS_CGU_PCICR);
 214         } else {
 215                 ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
 216                 ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
 217         }
 218 }
 219
 220 unsigned int
 221 ifxmips_get_cpu_hz(void)
 222 {
 223         unsigned int ddr_clock = DDR_HZ;
 224         switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
 225         {
 226         case 0:
 227                 return CLOCK_333M;
 228         case 4:
 229                 return ddr_clock;
 230         }
 231         return ddr_clock << 1;
 232 }
 233 EXPORT_SYMBOL(ifxmips_get_cpu_hz);
 234
 235 unsigned int
 236 ifxmips_get_fpi_hz(void)
 237 {
 238         unsigned int ddr_clock = DDR_HZ;
 239         if(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
 240                 return ddr_clock >> 1;
 241         return ddr_clock;
 242 }
 243 EXPORT_SYMBOL(ifxmips_get_fpi_hz);