projects / openwrt / svn-archive / archive.git / blob
? search:


9f5c0047a5f15214cbe9af80a71a1fe59373a062
[openwrt/svn-archive/archive.git] / target / linux / ifxmips / files / drivers / char / ifxmips_ssc.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) 2006 infineon
17 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
18 *
19 */
20
21 // ### TO DO: general issues:
22 // - power management
23 // - interrupt handling (direct/indirect)
24 // - pin/mux-handling (just overall concept due to project dependency)
25 // - multiple instances capability
26 // - slave functionality
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/signal.h>
31 #include <linux/sched.h>
32 #include <linux/timer.h>
33 #include <linux/interrupt.h>
34 #include <linux/major.h>
35 #include <linux/string.h>
36 #include <linux/fs.h>
37 #include <linux/fcntl.h>
38 #include <linux/ptrace.h>
39 #include <linux/mm.h>
40 #include <linux/ioport.h>
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/spinlock.h>
44 #include <linux/slab.h>
45
46 #include <asm/system.h>
47 #include <asm/io.h>
48 #include <asm/irq.h>
49 #include <asm/uaccess.h>
50 #include <asm/bitops.h>
51
52 #include <linux/types.h>
53 #include <linux/kernel.h>
54 #include <linux/version.h>
55
56 #include <asm/ifxmips/ifxmips.h>
57 #include <asm/ifxmips/ifxmips_irq.h>
58 #include <asm/ifxmips/ifx_ssc_defines.h>
59 #include <asm/ifxmips/ifx_ssc.h>
60
61 #ifdef SSC_FRAME_INT_ENABLE
62 #undef SSC_FRAME_INT_ENABLE
63 #endif
64
65 #define not_yet
66
67 #define SPI_VINETIC
68
69
70
71 /* allow the user to set the major device number */
72 static int maj = 0;
73
74 /*
75 * This is the per-channel data structure containing pointers, flags
76 * and variables for the port. This driver supports a maximum of PORT_CNT.
77 * isp is allocated in ifx_ssc_init() based on the chip version.
78 */
79 static struct ifx_ssc_port *isp;
80
81 /* prototypes for fops */
82 static ssize_t ifx_ssc_read (struct file *, char *, size_t, loff_t *);
83 static ssize_t ifx_ssc_write (struct file *, const char *, size_t, loff_t *);
84 //static unsigned int ifx_ssc_poll(struct file *, struct poll_table_struct *);
85 int ifx_ssc_ioctl (struct inode *, struct file *, unsigned int,
86 unsigned long);
87 int ifx_ssc_open (struct inode *, struct file *);
88 int ifx_ssc_close (struct inode *, struct file *);
89
90 /* other forward declarations */
91 static unsigned int ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info);
92 static void tx_int (struct ifx_ssc_port *);
93
94 extern unsigned int ifxmips_get_fpi_hz (void);
95 extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
96
97 static struct file_operations ifx_ssc_fops = {
98 .owner = THIS_MODULE,
99 .read = ifx_ssc_read,
100 .write = ifx_ssc_write,
101 .ioctl = ifx_ssc_ioctl,
102 .open = ifx_ssc_open,
103 .release = ifx_ssc_close,
104 };
105
106 static inline unsigned int
107 ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info)
108 {
109 unsigned int rmc;
110
111 rmc = (readl(IFXMIPS_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
112 if (rmc == 0)
113 {
114 printk ("ifx_ssc_get_kernel_clk rmc==0 \n");
115 return 0;
116 }
117 return ifxmips_get_fpi_hz () / rmc;
118 }
119
120 #ifndef not_yet
121 #ifdef IFX_SSC_INT_USE_BH
122 /*
123 * This routine is used by the interrupt handler to schedule
124 * processing in the software interrupt portion of the driver
125 * (also known as the "bottom half"). This can be called any
126 * number of times for any channel without harm.
127 */
128 static inline void
129 ifx_ssc_sched_event (struct ifx_ssc_port *info, int event)
130 {
131 info->event |= 1 << event; /* remember what kind of event and who */
132 queue_task (&info->tqueue, &tq_cyclades); /* it belongs to */
133 mark_bh (CYCLADES_BH); /* then trigger event */
134 }
135
136 static void
137 do_softint (void *private_)
138 {
139 struct ifx_ssc_port *info = (struct ifx_ssc_port *) private_;
140
141 if (test_and_clear_bit (Cy_EVENT_HANGUP, &info->event))
142 {
143 wake_up_interruptible (&info->open_wait);
144 info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CALLOUT_ACTIVE);
145 }
146
147 if (test_and_clear_bit (Cy_EVENT_OPEN_WAKEUP, &info->event))
148 wake_up_interruptible (&info->open_wait);
149
150 if (test_and_clear_bit (Cy_EVENT_DELTA_WAKEUP, &info->event))
151 wake_up_interruptible (&info->delta_msr_wait);
152
153 if (test_and_clear_bit (Cy_EVENT_WRITE_WAKEUP, &info->event))
154 wake_up_interruptible (&tty->write_wait);
155 #ifdef Z_WAKE
156 if (test_and_clear_bit (Cy_EVENT_SHUTDOWN_WAKEUP, &info->event))
157 wake_up_interruptible (&info->shutdown_wait);
158 #endif
159 }
160 #endif
161 #endif
162
163 inline static void
164 rx_int (struct ifx_ssc_port *info)
165 {
166 int fifo_fill_lev, bytes_in_buf, i;
167 unsigned long tmp_val;
168 unsigned long *tmp_ptr;
169 unsigned int rx_valid_cnt;
170 /* number of words waiting in the RX FIFO */
171 fifo_fill_lev = (readl(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
172 bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr;
173 // transfer with 32 bits per entry
174 while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) {
175 tmp_ptr = (unsigned long *) info->rxbuf_ptr;
176 *tmp_ptr = readl(IFXMIPS_SSC_RB);
177 info->rxbuf_ptr += 4;
178 info->stats.rxBytes += 4;
179 fifo_fill_lev--;
180 bytes_in_buf -= 4;
181 }
182
183 // now do the rest as mentioned in STATE.RXBV
184 while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) {
185 rx_valid_cnt = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
186 if (rx_valid_cnt == 0)
187 break;
188
189 if (rx_valid_cnt > bytes_in_buf)
190 rx_valid_cnt = bytes_in_buf;
191
192 tmp_val = readl(IFXMIPS_SSC_RB);
193
194 for (i = 0; i < rx_valid_cnt; i++)
195 {
196 *info->rxbuf_ptr = (tmp_val >> (8 * (rx_valid_cnt - i - 1))) & 0xff;
197 bytes_in_buf--;
198 info->rxbuf_ptr++;
199 }
200 info->stats.rxBytes += rx_valid_cnt;
201 }
202
203 // check if transfer is complete
204 if (info->rxbuf_ptr >= info->rxbuf_end)
205 {
206 disable_irq(info->rxirq);
207 wake_up_interruptible (&info->rwait);
208 } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (readl(IFXMIPS_SSC_RXCNT) == 0))
209 {
210 if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE)
211 writel((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
212 else
213 writel(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
214 }
215 }
216
217 inline static void
218 tx_int (struct ifx_ssc_port *info)
219 {
220
221 int fifo_space, fill, i;
222 fifo_space = ((readl(IFXMIPS_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
223 - ((readl(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
224
225 if (fifo_space == 0)
226 return;
227
228 fill = info->txbuf_end - info->txbuf_ptr;
229
230 if (fill > fifo_space * 4)
231 fill = fifo_space * 4;
232
233 for (i = 0; i < fill / 4; i++)
234 {
235 // at first 32 bit access
236 writel(*(UINT32 *) info->txbuf_ptr, IFXMIPS_SSC_TB);
237 info->txbuf_ptr += 4;
238 }
239
240 fifo_space -= fill / 4;
241 info->stats.txBytes += fill & ~0x3;
242 fill &= 0x3;
243 if ((fifo_space > 0) & (fill > 1))
244 {
245 // trailing 16 bit access
246 WRITE_PERIPHERAL_REGISTER_16 (*(UINT16 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
247 info->txbuf_ptr += 2;
248 info->stats.txBytes += 2;
249 fifo_space--;
250 fill -= 2;
251 }
252
253 if ((fifo_space > 0) & (fill > 0))
254 {
255 // trailing 8 bit access
256 WRITE_PERIPHERAL_REGISTER_8 (*(UINT8 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
257 info->txbuf_ptr++;
258 info->stats.txBytes++;
259 }
260
261 // check if transmission complete
262 if (info->txbuf_ptr >= info->txbuf_end)
263 {
264 disable_irq(info->txirq);
265 kfree (info->txbuf);
266 info->txbuf = NULL;
267 }
268
269 }
270
271 irqreturn_t
272 ifx_ssc_rx_int (int irq, void *dev_id)
273 {
274 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
275 rx_int (info);
276
277 return IRQ_HANDLED;
278 }
279
280 irqreturn_t
281 ifx_ssc_tx_int (int irq, void *dev_id)
282 {
283 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
284 tx_int (info);
285
286 return IRQ_HANDLED;
287 }
288
289 irqreturn_t
290 ifx_ssc_err_int (int irq, void *dev_id)
291 {
292 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
293 unsigned int state;
294 unsigned int write_back = 0;
295 unsigned long flags;
296
297 local_irq_save (flags);
298 state = readl(IFXMIPS_SSC_STATE);
299
300 if ((state & IFX_SSC_STATE_RX_UFL) != 0) {
301 info->stats.rxUnErr++;
302 write_back |= IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR;
303 }
304
305 if ((state & IFX_SSC_STATE_RX_OFL) != 0) {
306 info->stats.rxOvErr++;
307 write_back |= IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR;
308 }
309
310 if ((state & IFX_SSC_STATE_TX_OFL) != 0) {
311 info->stats.txOvErr++;
312 write_back |= IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR;
313 }
314
315 if ((state & IFX_SSC_STATE_TX_UFL) != 0) {
316 info->stats.txUnErr++;
317 write_back |= IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR;
318 }
319
320 if ((state & IFX_SSC_STATE_MODE_ERR) != 0) {
321 info->stats.modeErr++;
322 write_back |= IFX_SSC_WHBSTATE_CLR_MODE_ERROR;
323 }
324
325 if (write_back)
326 writel(write_back, IFXMIPS_SSC_WHBSTATE);
327
328 local_irq_restore (flags);
329
330 return IRQ_HANDLED;
331 }
332
333 static void
334 ifx_ssc_abort (struct ifx_ssc_port *info)
335 {
336 unsigned long flags;
337 bool enabled;
338
339 local_irq_save (flags);
340
341 disable_irq(info->rxirq);
342 disable_irq(info->txirq);
343 disable_irq(info->errirq);
344
345 local_irq_restore (flags);
346
347 // disable SSC (also aborts a receive request!)
348 // ### TO DO: Perhaps it's better to abort after the receiption of a
349 // complete word. The disable cuts the transmission immediatly and
350 // releases the chip selects. This could result in unpredictable
351 // behavior of connected external devices!
352 enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
353 writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
354
355 // flush fifos
356 writel(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_TXFCON);
357 writel(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_RXFCON);
358
359 // free txbuf
360 if (info->txbuf != NULL)
361 {
362 kfree (info->txbuf);
363 info->txbuf = NULL;
364 }
365
366 // wakeup read process
367 if (info->rxbuf != NULL)
368 wake_up_interruptible (&info->rwait);
369
370 // clear pending int's
371 mask_and_ack_ifxmips_irq(info->rxirq);
372 mask_and_ack_ifxmips_irq(info->txirq);
373 mask_and_ack_ifxmips_irq(info->errirq);
374
375 // clear error flags
376 writel(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
377
378 if (enabled)
379 writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
380
381 }
382
383 /*
384 * This routine is called whenever a port is opened. It enforces
385 * exclusive opening of a port and enables interrupts, etc.
386 */
387 int
388 ifx_ssc_open (struct inode *inode, struct file *filp)
389 {
390 struct ifx_ssc_port *info;
391 int line;
392 int from_kernel = 0;
393
394 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1)) {
395 from_kernel = 1;
396 line = (int) inode;
397 } else {
398 line = MINOR (filp->f_dentry->d_inode->i_rdev);
399 filp->f_op = &ifx_ssc_fops;
400 }
401
402 /* don't open more minor devices than we can support */
403 if (line < 0 || line >= PORT_CNT)
404 return -ENXIO;
405
406 info = &isp[line];
407
408 /* exclusive open */
409 if (info->port_is_open != 0)
410 return -EBUSY;
411 info->port_is_open++;
412
413 disable_irq(info->rxirq);
414 disable_irq(info->txirq);
415 disable_irq(info->errirq);
416
417 /* Flush and enable TX/RX FIFO */
418 writel((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
419 writel((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
420
421 /* logically flush the software FIFOs */
422 info->rxbuf_ptr = 0;
423 info->txbuf_ptr = 0;
424
425 /* clear all error bits */
426 writel(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
427
428 // clear pending interrupts
429 mask_and_ack_ifxmips_irq(info->rxirq);
430 mask_and_ack_ifxmips_irq(info->txirq);
431 mask_and_ack_ifxmips_irq(info->errirq);
432
433 writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
434
435 return 0;
436 }
437 EXPORT_SYMBOL(ifx_ssc_open);
438
439 int
440 ifx_ssc_close (struct inode *inode, struct file *filp)
441 {
442 struct ifx_ssc_port *info;
443 int idx;
444
445 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1))
446 idx = (int) inode;
447 else
448 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
449
450 if (idx < 0 || idx >= PORT_CNT)
451 return -ENXIO;
452
453 info = &isp[idx];
454 if (!info)
455 return -ENXIO;
456
457 writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
458
459 ifx_ssc_abort(info);
460
461 info->port_is_open--;
462
463 return 0;
464 }
465 EXPORT_SYMBOL(ifx_ssc_close);
466
467 static ssize_t
468 ifx_ssc_read_helper_poll (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel)
469 {
470 ssize_t ret_val;
471 unsigned long flags;
472
473 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
474 return -EFAULT;
475 local_irq_save (flags);
476 info->rxbuf_ptr = info->rxbuf;
477 info->rxbuf_end = info->rxbuf + len;
478 local_irq_restore (flags);
479 /* Vinetic driver always works in IFX_SSC_MODE_RXTX */
480 /* TXRX in poll mode */
481 while (info->rxbuf_ptr < info->rxbuf_end)
482 {
483 if (info->txbuf_ptr < info->txbuf_end)
484 tx_int (info);
485
486 rx_int (info);
487 };
488
489 ret_val = info->rxbuf_ptr - info->rxbuf;
490
491 return ret_val;
492 }
493
494 static ssize_t
495 ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel)
496 {
497 ssize_t ret_val;
498 unsigned long flags;
499 DECLARE_WAITQUEUE (wait, current);
500
501 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
502 return -EFAULT;
503
504 local_irq_save (flags);
505 info->rxbuf_ptr = info->rxbuf;
506 info->rxbuf_end = info->rxbuf + len;
507
508 if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX)
509 {
510 if ((info->txbuf == NULL) || (info->txbuf != info->txbuf_ptr) || (info->txbuf_end != len + info->txbuf))
511 {
512 local_irq_restore (flags);
513 printk ("IFX SSC - %s: write must be called before calling " "read in combined RX/TX!\n", __func__);
514 return -EFAULT;
515 }
516
517 local_irq_restore(flags);
518 tx_int (info);
519
520 if (info->txbuf_ptr < info->txbuf_end)
521 enable_irq(info->txirq);
522
523 enable_irq(info->rxirq);
524 } else {
525 local_irq_restore(flags);
526 if (readl(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
527 return -EBUSY;
528 enable_irq(info->rxirq);
529 if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
530 writel(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
531 else
532 writel(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
533 }
534
535 __add_wait_queue (&info->rwait, &wait);
536 set_current_state (TASK_INTERRUPTIBLE);
537
538 do {
539 local_irq_save (flags);
540 if (info->rxbuf_ptr >= info->rxbuf_end)
541 break;
542
543 local_irq_restore (flags);
544
545 if (signal_pending (current))
546 {
547 ret_val = -ERESTARTSYS;
548 goto out;
549 }
550 schedule();
551 } while (1);
552
553 ret_val = info->rxbuf_ptr - info->rxbuf;
554 local_irq_restore (flags);
555
556 out:
557 current->state = TASK_RUNNING;
558 __remove_wait_queue (&info->rwait, &wait);
559
560 return (ret_val);
561 }
562
563 static ssize_t
564 ifx_ssc_write_helper (struct ifx_ssc_port *info, const char *buf,
565 size_t len, int from_kernel)
566 {
567 if (info->opts.modeRxTx == IFX_SSC_MODE_RX)
568 return -EFAULT;
569
570 info->txbuf_ptr = info->txbuf;
571 info->txbuf_end = len + info->txbuf;
572 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
573 {
574 tx_int (info);
575 if (info->txbuf_ptr < info->txbuf_end)
576 {
577 enable_irq(info->txirq);
578 }
579 }
580
581 return len;
582 }
583
584 ssize_t
585 ifx_ssc_kread (int port, char *kbuf, size_t len)
586 {
587 struct ifx_ssc_port *info;
588 ssize_t ret_val;
589
590 if (port < 0 || port >= PORT_CNT)
591 return -ENXIO;
592
593 if (len == 0)
594 return 0;
595
596 info = &isp[port];
597
598 if (info->rxbuf != NULL)
599 {
600 printk ("SSC device busy\n");
601 return -EBUSY;
602 }
603
604 info->rxbuf = kbuf;
605 if (info->rxbuf == NULL)
606 {
607 printk ("SSC device error\n");
608 return -EINVAL;
609 }
610
611 ret_val = ifx_ssc_read_helper_poll (info, kbuf, len, 1);
612 info->rxbuf = NULL;
613
614 disable_irq(info->rxirq);
615
616 return ret_val;
617 }
618 EXPORT_SYMBOL(ifx_ssc_kread);
619
620 ssize_t
621 ifx_ssc_kwrite (int port, const char *kbuf, size_t len)
622 {
623 struct ifx_ssc_port *info;
624 ssize_t ret_val;
625
626 if (port < 0 || port >= PORT_CNT)
627 return -ENXIO;
628
629 if (len == 0)
630 return 0;
631
632 info = &isp[port];
633
634 // check if transmission in progress
635 if (info->txbuf != NULL)
636 return -EBUSY;
637
638 info->txbuf = (char *) kbuf;
639
640 ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 1);
641
642 if (ret_val < 0)
643 info->txbuf = NULL;
644
645 return ret_val;
646 }
647 EXPORT_SYMBOL(ifx_ssc_kwrite);
648
649 static ssize_t
650 ifx_ssc_read (struct file *filp, char *ubuf, size_t len, loff_t * off)
651 {
652 ssize_t ret_val;
653 int idx;
654 struct ifx_ssc_port *info;
655
656 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
657 info = &isp[idx];
658
659 if (info->rxbuf != NULL)
660 return -EBUSY;
661
662 info->rxbuf = kmalloc (len + 3, GFP_KERNEL);
663 if (info->rxbuf == NULL)
664 return -ENOMEM;
665
666 ret_val = ifx_ssc_read_helper (info, info->rxbuf, len, 0);
667 if (copy_to_user ((void *) ubuf, info->rxbuf, ret_val) != 0)
668 ret_val = -EFAULT;
669
670 disable_irq(info->rxirq);
671
672 kfree (info->rxbuf);
673 info->rxbuf = NULL;
674
675 return (ret_val);
676 }
677
678 static ssize_t
679 ifx_ssc_write (struct file *filp, const char *ubuf, size_t len, loff_t * off)
680 {
681 int idx;
682 struct ifx_ssc_port *info;
683 int ret_val;
684
685 if (len == 0)
686 return (0);
687
688 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
689 info = &isp[idx];
690
691 if (info->txbuf != NULL)
692 return -EBUSY;
693
694 info->txbuf = kmalloc (len + 3, GFP_KERNEL);
695 if (info->txbuf == NULL)
696 return -ENOMEM;
697
698 ret_val = copy_from_user (info->txbuf, ubuf, len);
699 if (ret_val == 0)
700 ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 0);
701 else
702 ret_val = -EFAULT;
703
704 if (ret_val < 0)
705 {
706 kfree (info->txbuf);
707 info->txbuf = NULL;
708 }
709
710 return (ret_val);
711 }
712
713 static struct ifx_ssc_frm_status *
714 ifx_ssc_frm_status_get (struct ifx_ssc_port *info)
715 {
716 unsigned long tmp;
717
718 tmp = readl(IFXMIPS_SSC_SFSTAT);
719 info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0;
720 info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
721 info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
722 info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET;
723 tmp = readl(IFXMIPS_SSC_SFCON);
724 info->frm_status.EnIntAfterData = (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0;
725 info->frm_status.EnIntAfterPause = (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0;
726
727 return &info->frm_status;
728 }
729
730
731 static struct ifx_ssc_frm_opts *
732 ifx_ssc_frm_control_get (struct ifx_ssc_port *info)
733 {
734 unsigned long tmp;
735
736 tmp = readl(IFXMIPS_SSC_SFCON);
737 info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0;
738 info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
739 info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
740 info->frm_opts.IdleData = (tmp & IFX_SSC_SFCON_PAUSE_DATA_MASK) >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
741 info->frm_opts.IdleClock = (tmp & IFX_SSC_SFCON_PAUSE_CLOCK_MASK) >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
742 info->frm_opts.StopAfterPause = (tmp & IFX_SSC_SFCON_STOP_AFTER_PAUSE) > 0;
743
744 return &info->frm_opts;
745 }
746
747 static int
748 ifx_ssc_frm_control_set (struct ifx_ssc_port *info)
749 {
750 unsigned long tmp;
751
752 // check parameters
753 if ((info->frm_opts.DataLength > IFX_SSC_SFCON_DATA_LENGTH_MAX)
754 || (info->frm_opts.DataLength < 1)
755 || (info->frm_opts.PauseLength > IFX_SSC_SFCON_PAUSE_LENGTH_MAX)
756 || (info->frm_opts.PauseLength < 1)
757 || (info->frm_opts.IdleData & ~(IFX_SSC_SFCON_PAUSE_DATA_MASK >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET))
758 || (info->frm_opts.IdleClock & ~(IFX_SSC_SFCON_PAUSE_CLOCK_MASK >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET)))
759 return -EINVAL;
760
761 // read interrupt bits (they're not changed here)
762 tmp = readl(IFXMIPS_SSC_SFCON) &
763 (IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE);
764
765 // set all values with respect to it's bit position (for data and pause
766 // length set N-1)
767 tmp = (info->frm_opts.DataLength - 1) << IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
768 tmp |= (info->frm_opts.PauseLength - 1) << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
769 tmp |= info->frm_opts.IdleData << IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
770 tmp |= info->frm_opts.IdleClock << IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
771 tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE;
772 tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE;
773
774 writel(tmp, IFXMIPS_SSC_SFCON);
775
776 return 0;
777 }
778
779 static int
780 ifx_ssc_rxtx_mode_set (struct ifx_ssc_port *info, unsigned int val)
781 {
782 unsigned long tmp;
783
784 if (!(info) || (val & ~(IFX_SSC_MODE_MASK)))
785 return -EINVAL;
786
787 if ((readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)
788 || (readl(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
789 return -EBUSY;
790
791 tmp = (readl(IFXMIPS_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
792 writel(tmp, IFXMIPS_SSC_SFCON);
793 info->opts.modeRxTx = val;
794
795 return 0;
796 }
797
798 static int
799 ifx_ssc_sethwopts (struct ifx_ssc_port *info)
800 {
801 unsigned long flags, bits;
802 struct ifx_ssc_hwopts *opts = &info->opts;
803
804 if ((opts->dataWidth < IFX_SSC_MIN_DATA_WIDTH)
805 || (opts->dataWidth > IFX_SSC_MAX_DATA_WIDTH))
806 return -EINVAL;
807
808 bits = (opts->dataWidth - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET;
809 bits |= IFX_SSC_CON_ENABLE_BYTE_VALID;
810
811 if (opts->rxOvErrDetect)
812 bits |= IFX_SSC_CON_RX_OFL_CHECK;
813 if (opts->rxUndErrDetect)
814 bits |= IFX_SSC_CON_RX_UFL_CHECK;
815 if (opts->txOvErrDetect)
816 bits |= IFX_SSC_CON_TX_OFL_CHECK;
817 if (opts->txUndErrDetect)
818 bits |= IFX_SSC_CON_TX_UFL_CHECK;
819 if (opts->loopBack)
820 bits |= IFX_SSC_CON_LOOPBACK_MODE;
821 if (opts->echoMode)
822 bits |= IFX_SSC_CON_ECHO_MODE_ON;
823 if (opts->headingControl)
824 bits |= IFX_SSC_CON_MSB_FIRST;
825 if (opts->clockPhase)
826 bits |= IFX_SSC_CON_LATCH_THEN_SHIFT;
827 if (opts->clockPolarity)
828 bits |= IFX_SSC_CON_CLOCK_FALL;
829
830 switch (opts->modeRxTx)
831 {
832 case IFX_SSC_MODE_TX:
833 bits |= IFX_SSC_CON_RX_OFF;
834 break;
835 case IFX_SSC_MODE_RX:
836 bits |= IFX_SSC_CON_TX_OFF;
837 break;
838 }
839
840 local_irq_save (flags);
841
842 writel(bits, IFXMIPS_SSC_CON);
843 writel((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
844 (info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), IFXMIPS_SSC_GPOCON);
845
846 writel(info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, IFXMIPS_SSC_WHBGPOSTAT);
847
848 //master mode
849 if (opts->masterSelect)
850 writel(IFX_SSC_WHBSTATE_SET_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
851 else
852 writel(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
853
854 // init serial framing
855 writel(0, IFXMIPS_SSC_SFCON);
856 /* set up the port pins */
857 //check for general requirements to switch (external) pad/pin characteristics
858 /* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
859 /* p0.15 SPI_CS1(EEPROM), P0.13 SPI_CS3, */
860 /* Set p0.15 to alternative 01, others to 00 (In/OUT) */
861 *(IFXMIPS_GPIO_P0_DIR) = (*IFXMIPS_GPIO_P0_DIR) | (0xA000);
862 *(IFXMIPS_GPIO_P0_ALTSEL0) = (((*IFXMIPS_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000)));
863 *(IFXMIPS_GPIO_P0_ALTSEL1) = (((*IFXMIPS_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000)));
864 *(IFXMIPS_GPIO_P0_OD) = (*IFXMIPS_GPIO_P0_OD) | 0xA000;
865
866 /* p1.6 SPI_CS2(SFLASH), p1.0 SPI_DIN, p1.1 SPI_DOUT, p1.2 SPI_CLK */
867 *(IFXMIPS_GPIO_P1_DIR) = ((*IFXMIPS_GPIO_P1_DIR) | (0x46)) & (~1);
868 *(IFXMIPS_GPIO_P1_ALTSEL0) = ((*IFXMIPS_GPIO_P1_ALTSEL0) | (0x47));
869 *(IFXMIPS_GPIO_P1_ALTSEL1) = (*IFXMIPS_GPIO_P1_ALTSEL1) & (~0x47);
870 *(IFXMIPS_GPIO_P1_OD) = (*IFXMIPS_GPIO_P1_OD) | 0x0046;
871
872 /*CS3 */
873 /*TODO: CS4 CS5 CS6 */
874 *IFXMIPS_GPIO_P0_OUT = ((*IFXMIPS_GPIO_P0_OUT) | 0x2000);
875
876 local_irq_restore (flags);
877
878 return 0;
879 }
880
881 static int
882 ifx_ssc_set_baud (struct ifx_ssc_port *info, unsigned int baud)
883 {
884 unsigned int ifx_ssc_clock;
885 unsigned int br;
886 unsigned long flags;
887 bool enabled;
888 int retval = 0;
889
890 ifx_ssc_clock = ifx_ssc_get_kernel_clk(info);
891 if (ifx_ssc_clock == 0)
892 {
893 retval = -EINVAL;
894 goto out;
895 }
896
897 local_irq_save (flags);
898
899 enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
900 writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
901
902 br = (((ifx_ssc_clock >> 1) + baud / 2) / baud) - 1;
903 wmb();
904
905 if (br > 0xffff || ((br == 0) &&
906 ((readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
907 local_irq_restore (flags);
908 printk ("%s: invalid baudrate %u\n", __func__, baud);
909 return -EINVAL;
910 }
911
912 writel(br, IFXMIPS_SSC_BR);
913
914 if (enabled)
915 writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
916
917 local_irq_restore(flags);
918
919 out:
920 return retval;
921 }
922
923 static int
924 ifx_ssc_hwinit (struct ifx_ssc_port *info)
925 {
926 unsigned long flags;
927 bool enabled;
928
929 enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
930 writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
931
932 if (ifx_ssc_sethwopts (info) < 0)
933 {
934 printk ("%s: setting the hardware options failed\n", __func__);
935 return -EINVAL;
936 }
937
938 if (ifx_ssc_set_baud (info, info->baud) < 0)
939 {
940 printk ("%s: setting the baud rate failed\n", __func__);
941 return -EINVAL;
942 }
943
944 local_irq_save (flags);
945
946 /* TX FIFO */
947 writel((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
948 /* RX FIFO */
949 writel((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
950
951 local_irq_restore (flags);
952
953 if (enabled)
954 writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
955
956 return 0;
957 }
958
959 int
960 ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data)
961 {
962 struct ifx_ssc_port *info;
963 int line, ret_val = 0;
964 unsigned long flags;
965 unsigned long tmp;
966 int from_kernel = 0;
967
968 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1))
969 {
970 from_kernel = 1;
971 line = (int) inode;
972 } else {
973 line = MINOR (filp->f_dentry->d_inode->i_rdev);
974 }
975
976 if (line < 0 || line >= PORT_CNT)
977 return -ENXIO;
978
979 info = &isp[line];
980
981 switch (cmd)
982 {
983 case IFX_SSC_STATS_READ:
984 /* data must be a pointer to a struct ifx_ssc_statistics */
985 if (from_kernel)
986 memcpy ((void *) data, (void *) &info->stats,
987 sizeof (struct ifx_ssc_statistics));
988 else if (copy_to_user ((void *) data,
989 (void *) &info->stats,
990 sizeof (struct ifx_ssc_statistics)))
991 ret_val = -EFAULT;
992 break;
993 case IFX_SSC_STATS_RESET:
994 /* just resets the statistics counters */
995 memset ((void *) &info->stats, 0,
996 sizeof (struct ifx_ssc_statistics));
997 break;
998 case IFX_SSC_BAUD_SET:
999 /* if the buffers are not empty then the port is */
1000 /* busy and we shouldn't change things on-the-fly! */
1001 if (!info->txbuf || !info->rxbuf ||
1002 (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)) {
1003 ret_val = -EBUSY;
1004 break;
1005 }
1006 /* misuse flags */
1007 if (from_kernel)
1008 flags = *((unsigned long *) data);
1009 else if (copy_from_user ((void *) &flags,
1010 (void *) data, sizeof (flags))) {
1011 ret_val = -EFAULT;
1012 break;
1013 }
1014 if (flags == 0) {
1015 ret_val = -EINVAL;
1016 break;
1017 }
1018 if (ifx_ssc_set_baud (info, flags) < 0) {
1019 ret_val = -EINVAL;
1020 break;
1021 }
1022 info->baud = flags;
1023 break;
1024 case IFX_SSC_BAUD_GET:
1025 if (from_kernel)
1026 *((unsigned int *) data) = info->baud;
1027 else if (copy_to_user ((void *) data,
1028 (void *) &info->baud,
1029 sizeof (unsigned long)))
1030 ret_val = -EFAULT;
1031 break;
1032 case IFX_SSC_RXTX_MODE_SET:
1033 if (from_kernel)
1034 tmp = *((unsigned long *) data);
1035 else if (copy_from_user ((void *) &tmp,
1036 (void *) data, sizeof (tmp))) {
1037 ret_val = -EFAULT;
1038 break;
1039 }
1040 ret_val = ifx_ssc_rxtx_mode_set (info, tmp);
1041 break;
1042 case IFX_SSC_RXTX_MODE_GET:
1043 tmp = readl(IFXMIPS_SSC_CON) &
1044 (~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF));
1045 if (from_kernel)
1046 *((unsigned int *) data) = tmp;
1047 else if (copy_to_user ((void *) data,
1048 (void *) &tmp, sizeof (tmp)))
1049 ret_val = -EFAULT;
1050 break;
1051
1052 case IFX_SSC_ABORT:
1053 ifx_ssc_abort (info);
1054 break;
1055
1056 case IFX_SSC_GPO_OUT_SET:
1057 if (from_kernel)
1058 tmp = *((unsigned long *) data);
1059 else if (copy_from_user ((void *) &tmp,
1060 (void *) data, sizeof (tmp))) {
1061 ret_val = -EFAULT;
1062 break;
1063 }
1064 if (tmp > IFX_SSC_MAX_GPO_OUT)
1065 ret_val = -EINVAL;
1066 else
1067 writel(1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
1068 IFXMIPS_SSC_WHBGPOSTAT);
1069 break;
1070 case IFX_SSC_GPO_OUT_CLR:
1071 if (from_kernel)
1072 tmp = *((unsigned long *) data);
1073 else if (copy_from_user ((void *) &tmp, (void *) data, sizeof (tmp))) {
1074 ret_val = -EFAULT;
1075 break;
1076 }
1077 if (tmp > IFX_SSC_MAX_GPO_OUT)
1078 ret_val = -EINVAL;
1079 else {
1080 writel(1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
1081 IFXMIPS_SSC_WHBGPOSTAT);
1082 }
1083 break;
1084 case IFX_SSC_GPO_OUT_GET:
1085 tmp = readl(IFXMIPS_SSC_GPOSTAT);
1086 if (from_kernel)
1087 *((unsigned int *) data) = tmp;
1088 else if (copy_to_user ((void *) data,
1089 (void *) &tmp, sizeof (tmp)))
1090 ret_val = -EFAULT;
1091 break;
1092 case IFX_SSC_FRM_STATUS_GET:
1093 ifx_ssc_frm_status_get (info);
1094 if (from_kernel)
1095 memcpy ((void *) data, (void *) &info->frm_status,
1096 sizeof (struct ifx_ssc_frm_status));
1097 else if (copy_to_user ((void *) data,
1098 (void *) &info->frm_status,
1099 sizeof (struct ifx_ssc_frm_status)))
1100 ret_val = -EFAULT;
1101 break;
1102 case IFX_SSC_FRM_CONTROL_GET:
1103 ifx_ssc_frm_control_get (info);
1104 if (from_kernel)
1105 memcpy ((void *) data, (void *) &info->frm_opts,
1106 sizeof (struct ifx_ssc_frm_opts));
1107 else if (copy_to_user ((void *) data,
1108 (void *) &info->frm_opts,
1109 sizeof (struct ifx_ssc_frm_opts)))
1110 ret_val = -EFAULT;
1111 break;
1112 case IFX_SSC_FRM_CONTROL_SET:
1113 if (from_kernel)
1114 memcpy ((void *) &info->frm_opts, (void *) data,
1115 sizeof (struct ifx_ssc_frm_opts));
1116 else if (copy_to_user ((void *) &info->frm_opts,
1117 (void *) data,
1118 sizeof (struct ifx_ssc_frm_opts))) {
1119 ret_val = -EFAULT;
1120 break;
1121 }
1122 ret_val = ifx_ssc_frm_control_set (info);
1123 break;
1124 case IFX_SSC_HWOPTS_SET:
1125 /* data must be a pointer to a struct ifx_ssc_hwopts */
1126 /* if the buffers are not empty then the port is */
1127 /* busy and we shouldn't change things on-the-fly! */
1128 if (!info->txbuf || !info->rxbuf ||
1129 (readl(IFXMIPS_SSC_STATE)
1130 & IFX_SSC_STATE_BUSY)) {
1131 ret_val = -EBUSY;
1132 break;
1133 }
1134 if (from_kernel)
1135 memcpy ((void *) &info->opts, (void *) data,
1136 sizeof (struct ifx_ssc_hwopts));
1137 else if (copy_from_user ((void *) &info->opts,
1138 (void *) data, sizeof(struct ifx_ssc_hwopts))) {
1139 ret_val = -EFAULT;
1140 break;
1141 }
1142 if (ifx_ssc_hwinit (info) < 0) {
1143 ret_val = -EIO;
1144 }
1145 break;
1146 case IFX_SSC_HWOPTS_GET:
1147 /* data must be a pointer to a struct ifx_ssc_hwopts */
1148 if (from_kernel)
1149 memcpy ((void *) data, (void *) &info->opts,
1150 sizeof (struct ifx_ssc_hwopts));
1151 else if (copy_to_user ((void *) data,
1152 (void *) &info->opts,
1153 sizeof (struct ifx_ssc_hwopts)))
1154 ret_val = -EFAULT;
1155 break;
1156 default:
1157 ret_val = -ENOIOCTLCMD;
1158 }
1159
1160 return ret_val;
1161 }
1162 EXPORT_SYMBOL(ifx_ssc_ioctl);
1163
1164 int __init
1165 ifx_ssc_init (void)
1166 {
1167 struct ifx_ssc_port *info;
1168 int i, nbytes;
1169 unsigned long flags;
1170 int ret_val;
1171
1172 ret_val = -ENOMEM;
1173 nbytes = PORT_CNT * sizeof(struct ifx_ssc_port);
1174 isp = (struct ifx_ssc_port*)kmalloc(nbytes, GFP_KERNEL);
1175
1176 if (isp == NULL)
1177 {
1178 printk("%s: no memory for isp\n", __func__);
1179 return (ret_val);
1180 }
1181 memset(isp, 0, nbytes);
1182
1183 ret_val = -ENXIO;
1184 if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0)
1185 {
1186 printk ("Unable to register major %d for the Infineon SSC\n", maj);
1187 if (maj == 0)
1188 {
1189 goto errout;
1190 } else {
1191 maj = 0;
1192 if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0)
1193 {
1194 printk ("Unable to register major %d for the Infineon SSC\n", maj);
1195 goto errout;
1196 }
1197 }
1198 }
1199
1200 if (maj == 0)
1201 maj = i;
1202
1203 /* set default values in ifx_ssc_port */
1204 for (i = 0; i < PORT_CNT; i++) {
1205 info = &isp[i];
1206 info->port_nr = i;
1207 /* default values for the HwOpts */
1208 info->opts.AbortErrDetect = IFX_SSC_DEF_ABRT_ERR_DETECT;
1209 info->opts.rxOvErrDetect = IFX_SSC_DEF_RO_ERR_DETECT;
1210 info->opts.rxUndErrDetect = IFX_SSC_DEF_RU_ERR_DETECT;
1211 info->opts.txOvErrDetect = IFX_SSC_DEF_TO_ERR_DETECT;
1212 info->opts.txUndErrDetect = IFX_SSC_DEF_TU_ERR_DETECT;
1213 info->opts.loopBack = IFX_SSC_DEF_LOOP_BACK;
1214 info->opts.echoMode = IFX_SSC_DEF_ECHO_MODE;
1215 info->opts.idleValue = IFX_SSC_DEF_IDLE_DATA;
1216 info->opts.clockPolarity = IFX_SSC_DEF_CLOCK_POLARITY;
1217 info->opts.clockPhase = IFX_SSC_DEF_CLOCK_PHASE;
1218 info->opts.headingControl = IFX_SSC_DEF_HEADING_CONTROL;
1219 info->opts.dataWidth = IFX_SSC_DEF_DATA_WIDTH;
1220 info->opts.modeRxTx = IFX_SSC_DEF_MODE_RXTX;
1221 info->opts.gpoCs = IFX_SSC_DEF_GPO_CS;
1222 info->opts.gpoInv = IFX_SSC_DEF_GPO_INV;
1223 info->opts.masterSelect = IFX_SSC_DEF_MASTERSLAVE;
1224 info->baud = IFX_SSC_DEF_BAUDRATE;
1225 info->rxbuf = NULL;
1226 info->txbuf = NULL;
1227 /* values specific to SSC1 */
1228 if (i == 0) {
1229 info->mapbase = IFXMIPS_SSC_BASE_ADDR;
1230 info->txirq = IFXMIPS_SSC_TIR;
1231 info->rxirq = IFXMIPS_SSC_RIR;
1232 info->errirq = IFXMIPS_SSC_EIR;
1233 }
1234
1235 writel(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, IFXMIPS_SSC_CLC);
1236
1237 init_waitqueue_head (&info->rwait);
1238
1239 local_irq_save (flags);
1240
1241 // init serial framing register
1242 writel(IFX_SSC_DEF_SFCON, IFXMIPS_SSC_SFCON);
1243
1244 ret_val = request_irq(info->txirq, ifx_ssc_tx_int, SA_INTERRUPT, "ifx_ssc_tx", info);
1245 if (ret_val)
1246 {
1247 printk("%s: unable to get irq %d\n", __func__, info->txirq);
1248 local_irq_restore(flags);
1249 goto errout;
1250 }
1251
1252 ret_val = request_irq(info->rxirq, ifx_ssc_rx_int, SA_INTERRUPT, "ifx_ssc_rx", info);
1253 if (ret_val)
1254 {
1255 printk ("%s: unable to get irq %d\n", __func__, info->rxirq);
1256 local_irq_restore (flags);
1257 goto irqerr;
1258 }
1259
1260 ret_val = request_irq(info->errirq, ifx_ssc_err_int, SA_INTERRUPT,"ifx_ssc_err", info);
1261 if (ret_val)
1262 {
1263 printk ("%s: unable to get irq %d\n", __func__, info->errirq);
1264 local_irq_restore (flags);
1265 goto irqerr;
1266 }
1267 writel(IFX_SSC_DEF_IRNEN, IFXMIPS_SSC_IRN);
1268
1269 enable_irq(info->txirq);
1270 enable_irq(info->rxirq);
1271 enable_irq(info->errirq);
1272
1273 local_irq_restore (flags);
1274 }
1275
1276 for (i = 0; i < PORT_CNT; i++) {
1277 info = &isp[i];
1278 if (ifx_ssc_hwinit (info) < 0)
1279 {
1280 printk ("%s: hardware init failed for port %d\n", __func__, i);
1281 goto irqerr;
1282 }
1283 }
1284
1285
1286 return 0;
1287
1288 irqerr:
1289 free_irq(isp[0].txirq, &isp[0]);
1290 free_irq(isp[0].rxirq, &isp[0]);
1291 free_irq(isp[0].errirq, &isp[0]);
1292 errout:
1293 kfree (isp);
1294 return (ret_val);
1295 }
1296
1297 void
1298 ifx_ssc_cleanup_module (void)
1299 {
1300 int i;
1301
1302 for (i = 0; i < PORT_CNT; i++) {
1303 writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
1304 free_irq(isp[i].txirq, &isp[i]);
1305 free_irq(isp[i].rxirq, &isp[i]);
1306 free_irq(isp[i].errirq, &isp[i]);
1307 }
1308 kfree (isp);
1309 }
1310
1311 module_init(ifx_ssc_init);
1312 module_exit(ifx_ssc_cleanup_module);
1313
1314
1315 inline int
1316 ifx_ssc_cs_low (u32 pin)
1317 {
1318 int ret = 0;
1319 if ((ret = ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_CLR, (unsigned long) &pin)))
1320 printk ("clear CS %d fails\n", pin);
1321 wmb ();
1322
1323 return ret;
1324 }
1325 EXPORT_SYMBOL(ifx_ssc_cs_low);
1326
1327 inline int
1328 ifx_ssc_cs_high (u32 pin)
1329 {
1330 int ret = 0;
1331 if ((ret = ifx_ssc_ioctl((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_SET, (unsigned long) &pin)))
1332 printk ("set CS %d fails\n", pin);
1333 wmb ();
1334
1335 return ret;
1336 }
1337 EXPORT_SYMBOL(ifx_ssc_cs_high);
1338
1339 static int
1340 ssc_session (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
1341 {
1342 int ret = 0;
1343
1344 char *ssc_tx_buf = NULL;
1345 char *ssc_rx_buf = NULL;
1346 int eff_size = 0;
1347 u8 mode = 0;
1348
1349 if (tx_buf == NULL && tx_len == 0 && rx_buf == NULL && rx_len == 0) {
1350 printk ("invalid parameters\n");
1351 ret = -EINVAL;
1352 goto ssc_session_exit;
1353 }
1354 else if (tx_buf == NULL || tx_len == 0) {
1355 if (rx_buf != NULL && rx_len != 0) {
1356 mode = IFX_SSC_MODE_RX;
1357 }
1358 else {
1359 printk ("invalid parameters\n");
1360 ret = -EINVAL;
1361 goto ssc_session_exit;
1362 }
1363 }
1364 else if (rx_buf == NULL || rx_len == 0) {
1365 if (tx_buf != NULL && tx_len != 0) {
1366 mode = IFX_SSC_MODE_TX;
1367 }
1368 else {
1369 printk ("invalid parameters\n");
1370 ret = -EINVAL;
1371 goto ssc_session_exit;
1372 }
1373 }
1374 else {
1375 mode = IFX_SSC_MODE_RXTX;
1376 }
1377
1378 if (mode == IFX_SSC_MODE_RXTX) {
1379 eff_size = tx_len + rx_len;
1380 }
1381 else if (mode == IFX_SSC_MODE_RX) {
1382 eff_size = rx_len;
1383 }
1384 else {
1385 eff_size = tx_len;
1386 }
1387
1388 //4 bytes alignment, required by driver
1389 /* change by TaiCheng */
1390 //if (in_irq()){
1391 if (1) {
1392 ssc_tx_buf =
1393 (char *) kmalloc (sizeof (char) *
1394 ((eff_size + 3) & (~3)),
1395 GFP_ATOMIC);
1396 ssc_rx_buf =
1397 (char *) kmalloc (sizeof (char) *
1398 ((eff_size + 3) & (~3)),
1399 GFP_ATOMIC);
1400 }
1401 else {
1402 ssc_tx_buf =
1403 (char *) kmalloc (sizeof (char) *
1404 ((eff_size + 3) & (~3)),
1405 GFP_KERNEL);
1406 ssc_rx_buf =
1407 (char *) kmalloc (sizeof (char) *
1408 ((eff_size + 3) & (~3)),
1409 GFP_KERNEL);
1410 }
1411 if (ssc_tx_buf == NULL || ssc_rx_buf == NULL) {
1412 printk ("no memory for size of %d\n", eff_size);
1413 ret = -ENOMEM;
1414 goto ssc_session_exit;
1415 }
1416 memset ((void *) ssc_tx_buf, 0, eff_size);
1417 memset ((void *) ssc_rx_buf, 0, eff_size);
1418
1419 if (tx_len > 0) {
1420 memcpy (ssc_tx_buf, tx_buf, tx_len);
1421 }
1422
1423 ret = ifx_ssc_kwrite (0, ssc_tx_buf, eff_size);
1424
1425 if (ret > 0) {
1426 ssc_tx_buf = NULL; //should be freed by ifx_ssc_kwrite
1427 }
1428
1429 if (ret != eff_size) {
1430 printk ("ifx_ssc_write return %d\n", ret);
1431 goto ssc_session_exit;
1432 }
1433 ret = ifx_ssc_kread (0, ssc_rx_buf, eff_size);
1434 if (ret != eff_size) {
1435 printk ("ifx_ssc_read return %d\n", ret);
1436 goto ssc_session_exit;
1437 }
1438
1439 memcpy (rx_buf, ssc_rx_buf + tx_len, rx_len);
1440
1441 if (mode == IFX_SSC_MODE_TX) {
1442 ret = tx_len;
1443 }
1444 else {
1445 ret = rx_len;
1446 }
1447 ssc_session_exit:
1448
1449 if (ssc_tx_buf != NULL)
1450 kfree (ssc_tx_buf);
1451 if (ssc_rx_buf != NULL)
1452 kfree (ssc_rx_buf);
1453
1454 if (ret < 0) {
1455 printk ("ssc session fails\n");
1456 }
1457 return ret;
1458 }
1459
1460 int
1461 ifx_ssc_txrx (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
1462 {
1463 return ssc_session(tx_buf, tx_len, rx_buf, rx_len);
1464 }
1465 EXPORT_SYMBOL(ifx_ssc_txrx);
1466
1467 int
1468 ifx_ssc_tx (char *tx_buf, u32 tx_len)
1469 {
1470 return ssc_session(tx_buf, tx_len, NULL, 0);
1471 }
1472 EXPORT_SYMBOL(ifx_ssc_tx);
1473
1474 int
1475 ifx_ssc_rx (char *rx_buf, u32 rx_len)
1476 {
1477 return ssc_session(NULL, 0, rx_buf, rx_len);
1478 }
1479 EXPORT_SYMBOL(ifx_ssc_rx);
1480
1481 MODULE_LICENSE("GPL");
1482 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1483 MODULE_DESCRIPTION("ifxmips ssc driver");
1484
OpenWrt SVN history