3 /******************************************************************************
4 Copyright (c) 2002, Infineon Technologies. All rights reserved.
7 Because the program is licensed free of charge, there is no warranty for
8 the program, to the extent permitted by applicable law. Except when
9 otherwise stated in writing the copyright holders and/or other parties
10 provide the program "as is" without warranty of any kind, either
11 expressed or implied, including, but not limited to, the implied
12 warranties of merchantability and fitness for a particular purpose. The
13 entire risk as to the quality and performance of the program is with
14 you. should the program prove defective, you assume the cost of all
15 necessary servicing, repair or correction.
17 In no event unless required by applicable law or agreed to in writing
18 will any copyright holder, or any other party who may modify and/or
19 redistribute the program as permitted above, be liable to you for
20 damages, including any general, special, incidental or consequential
21 damages arising out of the use or inability to use the program
22 (including but not limited to loss of data or data being rendered
23 inaccurate or losses sustained by you or third parties or a failure of
24 the program to operate with any other programs), even if such holder or
25 other party has been advised of the possibility of such damages.
26 ******************************************************************************/
28 /***********************************************************************/
29 /* Module : WDT register address and bits */
30 /***********************************************************************/
32 #define BOARD_SYSTEM_TYPE "DANUBE"
34 #define DANUBE_BIU_WDT (KSEG1+0x1F880000)
36 /***Watchdog Timer Control Register ***/
37 #define DANUBE_BIU_WDT_CR ((volatile u32*)(DANUBE_BIU_WDT + 0x03F0))
38 #define DANUBE_BIU_WDT_CR_GEN (1 << 31)
39 #define DANUBE_BIU_WDT_CR_DSEN (1 << 30)
40 #define DANUBE_BIU_WDT_CR_LPEN (1 << 29)
41 #define DANUBE_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1))
42 #define DANUBE_BIU_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26)
43 #define DANUBE_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
44 #define DANUBE_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24)
45 #define DANUBE_BIU_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1))
46 #define DANUBE_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16)
47 #define DANUBE_BIU_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1))
48 #define DANUBE_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
50 /***Watchdog Timer Status Register***/
51 #define DANUBE_BIU_WDT_SR ((volatile u32*)(DANUBE_BIU_WDT + 0x03F8))
52 #define DANUBE_BIU_WDT_SR_EN (1 << 31)
53 #define DANUBE_BIU_WDT_SR_AE (1 << 30)
54 #define DANUBE_BIU_WDT_SR_PRW (1 << 29)
55 #define DANUBE_BIU_WDT_SR_EXP (1 << 28)
56 #define DANUBE_BIU_WDT_SR_PWD (1 << 27)
57 #define DANUBE_BIU_WDT_SR_DS (1 << 26)
58 #define DANUBE_BIU_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1))
59 #define DANUBE_BIU_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
61 /***********************************************************************/
62 /* Module : PMU register address and bits */
63 /***********************************************************************/
65 #define DANUBE_PMU (KSEG1+0x1F102000)
67 /* PMU Power down Control Register */
68 #define DANUBE_PMU_PWDCR ((volatile u32*)(DANUBE_PMU+0x001C))
69 #define DANUBE_PMU_PWDCR_GPT (1 << 12)
70 #define DANUBE_PMU_PWDCR_FPI (1 << 14)
73 /* PMU Status Register */
74 #define DANUBE_PMU_SR ((volatile u32*)(DANUBE_PMU+0x0020))
76 #define DANUBE_PMU_DMA_SHIFT 5
77 #define DANUBE_PMU_PPE_SHIFT 13
78 #define DANUBE_PMU_SDIO_SHIFT 16
79 #define DANUBE_PMU_ETOP_SHIFT 22
80 #define DANUBE_PMU_ENET0_SHIFT 24
81 #define DANUBE_PMU_ENET1_SHIFT 25
83 /***********************************************************************/
84 /* Module : RCU register address and bits */
85 /***********************************************************************/
86 #define DANUBE_RCU_BASE_ADDR (0xBF203000)
88 #define DANUBE_RCU_REQ (0x0010 + DANUBE_RCU_BASE_ADDR) /* will remove this, pls use DANUBE_RCU_RST_REQ */
90 #define DANUBE_RCU_RST_REQ ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x0010))
91 #define DANUBE_RCU_RST_STAT ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x0014))
92 #define DANUBE_RST_ALL (0x40000000)
94 /***Reset Request Register***/
95 #define DANUBE_RCU_RST_REQ_CPU0 (1 << 31)
96 #define DANUBE_RCU_RST_REQ_CPU1 (1 << 3)
97 #define DANUBE_RCU_RST_REQ_CPUSUB (1 << 29)
98 #define DANUBE_RCU_RST_REQ_HRST (1 << 28)
99 #define DANUBE_RCU_RST_REQ_WDT0 (1 << 27)
100 #define DANUBE_RCU_RST_REQ_WDT1 (1 << 26)
101 #define DANUBE_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1))
102 #define DANUBE_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23)
103 #define DANUBE_RCU_RST_REQ_SWTBOOT (1 << 22)
104 #define DANUBE_RCU_RST_REQ_DMA (1 << 21)
105 #define DANUBE_RCU_RST_REQ_ARC_JTAG (1 << 20)
106 #define DANUBE_RCU_RST_REQ_ETHPHY0 (1 << 19)
107 #define DANUBE_RCU_RST_REQ_CPU0_BR (1 << 18)
109 #define DANBUE_RCU_RST_REQ_AFE (1 << 11)
110 #define DANBUE_RCU_RST_REQ_DFE (1 << 7)
112 /* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */
113 #define DANUBE_RCU_RST_REQ_ALL DANUBE_RST_ALL
115 #define DANUBE_RCU_STAT (0x0014 + DANUBE_RCU_BASE_ADDR)
116 #define DANUBE_RCU_RST_SR ( (volatile u32 *)(DANUBE_RCU_STAT)) /* will remove this, pls use DANUBE_RCU_RST_STAT */
118 /*#define DANUBE_RCU_MON (0x0030 + DANUBE_RCU_BASE_ADDR) */
120 /***********************************************************************/
121 /* Module : BCU register address and bits */
122 /***********************************************************************/
124 #define DANUBE_BCU_BASE_ADDR (KSEG1+0x1E100000)
126 /***BCU Control Register (0010H)***/
127 #define DANUBE_BCU_CON ((volatile u32*)(0x0010 + DANUBE_BCU_BASE_ADDR))
128 #define DANUBE_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24)
129 #define DANUBE_BCU_BCU_CON_SPE (1 << 19)
130 #define DANUBE_BCU_BCU_CON_PSE (1 << 18)
131 #define DANUBE_BCU_BCU_CON_DBG (1 << 16)
132 #define DANUBE_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0)
134 /***BCU Error Control Capture Register (0020H)***/
135 #define DANUBE_BCU_ECON ((volatile u32*)(0x0020 + DANUBE_BCU_BASE_ADDR))
136 #define DANUBE_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24)
137 #define DANUBE_BCU_BCU_ECON_RDN (1 << 23)
138 #define DANUBE_BCU_BCU_ECON_WRN (1 << 22)
139 #define DANUBE_BCU_BCU_ECON_SVM (1 << 21)
140 #define DANUBE_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19)
141 #define DANUBE_BCU_BCU_ECON_ABT (1 << 18)
142 #define DANUBE_BCU_BCU_ECON_RDY (1 << 17)
143 #define DANUBE_BCU_BCU_ECON_TOUT (1 << 16)
144 #define DANUBE_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0)
145 #define DANUBE_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28)
147 /***BCU Error Address Capture Register (0024 H)***/
148 #define DANUBE_BCU_EADD ((volatile u32*)(0x0024 + DANUBE_BCU_BASE_ADDR))
150 /***BCU Error Data Capture Register (0028H)***/
151 #define DANUBE_BCU_EDAT ((volatile u32*)(0x0028 + DANUBE_BCU_BASE_ADDR))
152 #define DANUBE_BCU_IRNEN ((volatile u32*)(0x00F4 + DANUBE_BCU_BASE_ADDR))
153 #define DANUBE_BCU_IRNICR ((volatile u32*)(0x00F8 + DANUBE_BCU_BASE_ADDR))
154 #define DANUBE_BCU_IRNCR ((volatile u32*)(0x00FC + DANUBE_BCU_BASE_ADDR))
156 /***********************************************************************/
157 /* Module : MBC register address and bits */
158 /***********************************************************************/
160 #define DANUBE_MBC (0xBF103000)
161 /***********************************************************************/
163 /***Mailbox CPU Configuration Register***/
164 #define DANUBE_MBC_MBC_CFG ((volatile u32*)(DANUBE_MBC+ 0x0080))
165 #define DANUBE_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6)
166 #define DANUBE_MBC_MBC_CFG_RES (1 << 5)
167 #define DANUBE_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1)
168 #define DANUBE_MBC_MBC_CFG_SIZE (1 << 0)
170 /***Mailbox CPU Interrupt Status Register***/
171 #define DANUBE_MBC_MBC_ISR ((volatile u32*)(DANUBE_MBC+ 0x0084))
172 #define DANUBE_MBC_MBC_ISR_B3DA (1 << 31)
173 #define DANUBE_MBC_MBC_ISR_B2DA (1 << 30)
174 #define DANUBE_MBC_MBC_ISR_B1E (1 << 29)
175 #define DANUBE_MBC_MBC_ISR_B0E (1 << 28)
176 #define DANUBE_MBC_MBC_ISR_WDT (1 << 27)
177 #define DANUBE_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
179 /***Mailbox CPU Mask Register***/
180 #define DANUBE_MBC_MBC_MSK ((volatile u32*)(DANUBE_MBC+ 0x0088))
181 #define DANUBE_MBC_MBC_MSK_B3DA (1 << 31)
182 #define DANUBE_MBC_MBC_MSK_B2DA (1 << 30)
183 #define DANUBE_MBC_MBC_MSK_B1E (1 << 29)
184 #define DANUBE_MBC_MBC_MSK_B0E (1 << 28)
185 #define DANUBE_MBC_MBC_MSK_WDT (1 << 27)
186 #define DANUBE_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
188 /***Mailbox CPU Mask 01 Register***/
189 #define DANUBE_MBC_MBC_MSK01 ((volatile u32*)(DANUBE_MBC+ 0x008C))
190 #define DANUBE_MBC_MBC_MSK01_B3DA (1 << 31)
191 #define DANUBE_MBC_MBC_MSK01_B2DA (1 << 30)
192 #define DANUBE_MBC_MBC_MSK01_B1E (1 << 29)
193 #define DANUBE_MBC_MBC_MSK01_B0E (1 << 28)
194 #define DANUBE_MBC_MBC_MSK01_WDT (1 << 27)
195 #define DANUBE_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
197 /***Mailbox CPU Mask 10 Register***/
198 #define DANUBE_MBC_MBC_MSK10 ((volatile u32*)(DANUBE_MBC+ 0x0090))
199 #define DANUBE_MBC_MBC_MSK10_B3DA (1 << 31)
200 #define DANUBE_MBC_MBC_MSK10_B2DA (1 << 30)
201 #define DANUBE_MBC_MBC_MSK10_B1E (1 << 29)
202 #define DANUBE_MBC_MBC_MSK10_B0E (1 << 28)
203 #define DANUBE_MBC_MBC_MSK10_WDT (1 << 27)
204 #define DANUBE_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
206 /***Mailbox CPU Short Command Register***/
207 #define DANUBE_MBC_MBC_CMD ((volatile u32*)(DANUBE_MBC+ 0x0094))
208 #define DANUBE_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0)
210 /***Mailbox CPU Input Data of Buffer 0***/
211 #define DANUBE_MBC_MBC_ID0 ((volatile u32*)(DANUBE_MBC+ 0x0000))
212 #define DANUBE_MBC_MBC_ID0_INDATA
214 /***Mailbox CPU Input Data of Buffer 1***/
215 #define DANUBE_MBC_MBC_ID1 ((volatile u32*)(DANUBE_MBC+ 0x0020))
216 #define DANUBE_MBC_MBC_ID1_INDATA
218 /***Mailbox CPU Output Data of Buffer 2***/
219 #define DANUBE_MBC_MBC_OD2 ((volatile u32*)(DANUBE_MBC+ 0x0040))
220 #define DANUBE_MBC_MBC_OD2_OUTDATA
222 /***Mailbox CPU Output Data of Buffer 3***/
223 #define DANUBE_MBC_MBC_OD3 ((volatile u32*)(DANUBE_MBC+ 0x0060))
224 #define DANUBE_MBC_MBC_OD3_OUTDATA
226 /***Mailbox CPU Control Register of Buffer 0***/
227 #define DANUBE_MBC_MBC_CR0 ((volatile u32*)(DANUBE_MBC+ 0x0004))
228 #define DANUBE_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
230 /***Mailbox CPU Control Register of Buffer 1***/
231 #define DANUBE_MBC_MBC_CR1 ((volatile u32*)(DANUBE_MBC+ 0x0024))
232 #define DANUBE_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
234 /***Mailbox CPU Control Register of Buffer 2***/
235 #define DANUBE_MBC_MBC_CR2 ((volatile u32*)(DANUBE_MBC+ 0x0044))
236 #define DANUBE_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
238 /***Mailbox CPU Control Register of Buffer 3***/
239 #define DANUBE_MBC_MBC_CR3 ((volatile u32*)(DANUBE_MBC+ 0x0064))
240 #define DANUBE_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
242 /***Mailbox CPU Free Space of Buffer 0***/
243 #define DANUBE_MBC_MBC_FS0 ((volatile u32*)(DANUBE_MBC+ 0x0008))
244 #define DANUBE_MBC_MBC_FS0_FS
246 /***Mailbox CPU Free Space of Buffer 1***/
247 #define DANUBE_MBC_MBC_FS1 ((volatile u32*)(DANUBE_MBC+ 0x0028))
248 #define DANUBE_MBC_MBC_FS1_FS
250 /***Mailbox CPU Free Space of Buffer 2***/
251 #define DANUBE_MBC_MBC_FS2 ((volatile u32*)(DANUBE_MBC+ 0x0048))
252 #define DANUBE_MBC_MBC_FS2_FS
254 /***Mailbox CPU Free Space of Buffer 3***/
255 #define DANUBE_MBC_MBC_FS3 ((volatile u32*)(DANUBE_MBC+ 0x0068))
256 #define DANUBE_MBC_MBC_FS3_FS
258 /***Mailbox CPU Data Available in Buffer 0***/
259 #define DANUBE_MBC_MBC_DA0 ((volatile u32*)(DANUBE_MBC+ 0x000C))
260 #define DANUBE_MBC_MBC_DA0_DA
262 /***Mailbox CPU Data Available in Buffer 1***/
263 #define DANUBE_MBC_MBC_DA1 ((volatile u32*)(DANUBE_MBC+ 0x002C))
264 #define DANUBE_MBC_MBC_DA1_DA
266 /***Mailbox CPU Data Available in Buffer 2***/
267 #define DANUBE_MBC_MBC_DA2 ((volatile u32*)(DANUBE_MBC+ 0x004C))
268 #define DANUBE_MBC_MBC_DA2_DA
270 /***Mailbox CPU Data Available in Buffer 3***/
271 #define DANUBE_MBC_MBC_DA3 ((volatile u32*)(DANUBE_MBC+ 0x006C))
272 #define DANUBE_MBC_MBC_DA3_DA
274 /***Mailbox CPU Input Absolute Pointer of Buffer 0***/
275 #define DANUBE_MBC_MBC_IABS0 ((volatile u32*)(DANUBE_MBC+ 0x0010))
276 #define DANUBE_MBC_MBC_IABS0_IABS
278 /***Mailbox CPU Input Absolute Pointer of Buffer 1***/
279 #define DANUBE_MBC_MBC_IABS1 ((volatile u32*)(DANUBE_MBC+ 0x0030))
280 #define DANUBE_MBC_MBC_IABS1_IABS
282 /***Mailbox CPU Input Absolute Pointer of Buffer 2***/
283 #define DANUBE_MBC_MBC_IABS2 ((volatile u32*)(DANUBE_MBC+ 0x0050))
284 #define DANUBE_MBC_MBC_IABS2_IABS
286 /***Mailbox CPU Input Absolute Pointer of Buffer 3***/
287 #define DANUBE_MBC_MBC_IABS3 ((volatile u32*)(DANUBE_MBC+ 0x0070))
288 #define DANUBE_MBC_MBC_IABS3_IABS
290 /***Mailbox CPU Input Temporary Pointer of Buffer 0***/
291 #define DANUBE_MBC_MBC_ITMP0 ((volatile u32*)(DANUBE_MBC+ 0x0014))
292 #define DANUBE_MBC_MBC_ITMP0_ITMP
294 /***Mailbox CPU Input Temporary Pointer of Buffer 1***/
295 #define DANUBE_MBC_MBC_ITMP1 ((volatile u32*)(DANUBE_MBC+ 0x0034))
296 #define DANUBE_MBC_MBC_ITMP1_ITMP
298 /***Mailbox CPU Input Temporary Pointer of Buffer 2***/
299 #define DANUBE_MBC_MBC_ITMP2 ((volatile u32*)(DANUBE_MBC+ 0x0054))
300 #define DANUBE_MBC_MBC_ITMP2_ITMP
302 /***Mailbox CPU Input Temporary Pointer of Buffer 3***/
303 #define DANUBE_MBC_MBC_ITMP3 ((volatile u32*)(DANUBE_MBC+ 0x0074))
304 #define DANUBE_MBC_MBC_ITMP3_ITMP
306 /***Mailbox CPU Output Absolute Pointer of Buffer 0***/
307 #define DANUBE_MBC_MBC_OABS0 ((volatile u32*)(DANUBE_MBC+ 0x0018))
308 #define DANUBE_MBC_MBC_OABS0_OABS
310 /***Mailbox CPU Output Absolute Pointer of Buffer 1***/
311 #define DANUBE_MBC_MBC_OABS1 ((volatile u32*)(DANUBE_MBC+ 0x0038))
312 #define DANUBE_MBC_MBC_OABS1_OABS
314 /***Mailbox CPU Output Absolute Pointer of Buffer 2***/
315 #define DANUBE_MBC_MBC_OABS2 ((volatile u32*)(DANUBE_MBC+ 0x0058))
316 #define DANUBE_MBC_MBC_OABS2_OABS
318 /***Mailbox CPU Output Absolute Pointer of Buffer 3***/
319 #define DANUBE_MBC_MBC_OABS3 ((volatile u32*)(DANUBE_MBC+ 0x0078))
320 #define DANUBE_MBC_MBC_OABS3_OABS
322 /***Mailbox CPU Output Temporary Pointer of Buffer 0***/
323 #define DANUBE_MBC_MBC_OTMP0 ((volatile u32*)(DANUBE_MBC+ 0x001C))
324 #define DANUBE_MBC_MBC_OTMP0_OTMP
326 /***Mailbox CPU Output Temporary Pointer of Buffer 1***/
327 #define DANUBE_MBC_MBC_OTMP1 ((volatile u32*)(DANUBE_MBC+ 0x003C))
328 #define DANUBE_MBC_MBC_OTMP1_OTMP
330 /***Mailbox CPU Output Temporary Pointer of Buffer 2***/
331 #define DANUBE_MBC_MBC_OTMP2 ((volatile u32*)(DANUBE_MBC+ 0x005C))
332 #define DANUBE_MBC_MBC_OTMP2_OTMP
334 /***Mailbox CPU Output Temporary Pointer of Buffer 3***/
335 #define DANUBE_MBC_MBC_OTMP3 ((volatile u32*)(DANUBE_MBC+ 0x007C))
336 #define DANUBE_MBC_MBC_OTMP3_OTMP
338 /***DSP Control Register***/
339 #define DANUBE_MBC_DCTRL ((volatile u32*)(DANUBE_MBC+ 0x00A0))
340 #define DANUBE_MBC_DCTRL_BA (1 << 0)
341 #define DANUBE_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1)
342 #define DANUBE_MBC_DCTRL_IDL (1 << 4)
343 #define DANUBE_MBC_DCTRL_RES (1 << 15)
345 /***DSP Status Register***/
346 #define DANUBE_MBC_DSTA ((volatile u32*)(DANUBE_MBC+ 0x00A4))
347 #define DANUBE_MBC_DSTA_IDLE (1 << 0)
348 #define DANUBE_MBC_DSTA_PD (1 << 1)
350 /***DSP Test 1 Register***/
351 #define DANUBE_MBC_DTST1 ((volatile u32*)(DANUBE_MBC+ 0x00A8))
352 #define DANUBE_MBC_DTST1_ABORT (1 << 0)
353 #define DANUBE_MBC_DTST1_HWF32 (1 << 1)
354 #define DANUBE_MBC_DTST1_HWF4M (1 << 2)
355 #define DANUBE_MBC_DTST1_HWFOP (1 << 3)
357 /***********************************************************************/
358 /* Module : MEI register address and bits */
359 /***********************************************************************/
360 #define MEI_SPACE_ACCESS 0xBE116000
362 /*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/
363 #define MEI_DATA_XFR ((volatile u32*)(0x0000 + MEI_SPACE_ACCESS))
364 #define MEI_VERSION ((volatile u32*)(0x0004 + MEI_SPACE_ACCESS))
365 #define MEI_ARC_GP_STAT ((volatile u32*)(0x0008 + MEI_SPACE_ACCESS))
366 #define MEI_DATA_XFR_STAT ((volatile u32*)(0x000C + MEI_SPACE_ACCESS))
367 #define MEI_XFR_ADDR ((volatile u32*)(0x0010 + MEI_SPACE_ACCESS))
368 #define MEI_MAX_WAIT ((volatile u32*)(0x0014 + MEI_SPACE_ACCESS))
369 #define MEI_TO_ARC_INT ((volatile u32*)(0x0018 + MEI_SPACE_ACCESS))
370 #define ARC_TO_MEI_INT ((volatile u32*)(0x001C + MEI_SPACE_ACCESS))
371 #define ARC_TO_MEI_INT_MASK ((volatile u32*)(0x0020 + MEI_SPACE_ACCESS))
372 #define MEI_DEBUG_WAD ((volatile u32*)(0x0024 + MEI_SPACE_ACCESS))
373 #define MEI_DEBUG_RAD ((volatile u32*)(0x0028 + MEI_SPACE_ACCESS))
374 #define MEI_DEBUG_DATA ((volatile u32*)(0x002C + MEI_SPACE_ACCESS))
375 #define MEI_DEBUG_DEC ((volatile u32*)(0x0030 + MEI_SPACE_ACCESS))
376 #define MEI_CONFIG ((volatile u32*)(0x0034 + MEI_SPACE_ACCESS))
377 #define MEI_RST_CONTROL ((volatile u32*)(0x0038 + MEI_SPACE_ACCESS))
378 #define MEI_DBG_MASTER ((volatile u32*)(0x003C + MEI_SPACE_ACCESS))
379 #define MEI_CLK_CONTROL ((volatile u32*)(0x0040 + MEI_SPACE_ACCESS))
380 #define MEI_BIST_CONTROL ((volatile u32*)(0x0044 + MEI_SPACE_ACCESS))
381 #define MEI_BIST_STAT ((volatile u32*)(0x0048 + MEI_SPACE_ACCESS))
382 #define MEI_XDATA_BASE_SH ((volatile u32*)(0x004c + MEI_SPACE_ACCESS))
383 #define MEI_XDATA_BASE ((volatile u32*)(0x0050 + MEI_SPACE_ACCESS))
384 #define MEI_XMEM_BAR_BASE ((volatile u32*)(0x0054 + MEI_SPACE_ACCESS))
385 #define MEI_XMEM_BAR0 ((volatile u32*)(0x0054 + MEI_SPACE_ACCESS))
386 #define MEI_XMEM_BAR1 ((volatile u32*)(0x0058 + MEI_SPACE_ACCESS))
387 #define MEI_XMEM_BAR2 ((volatile u32*)(0x005C + MEI_SPACE_ACCESS))
388 #define MEI_XMEM_BAR3 ((volatile u32*)(0x0060 + MEI_SPACE_ACCESS))
389 #define MEI_XMEM_BAR4 ((volatile u32*)(0x0064 + MEI_SPACE_ACCESS))
390 #define MEI_XMEM_BAR5 ((volatile u32*)(0x0068 + MEI_SPACE_ACCESS))
391 #define MEI_XMEM_BAR6 ((volatile u32*)(0x006C + MEI_SPACE_ACCESS)))
392 #define MEI_XMEM_BAR7 ((volatile u32*)(0x0070 + MEI_SPACE_ACCESS))
393 #define MEI_XMEM_BAR8 ((volatile u32*)(0x0074 + MEI_SPACE_ACCESS))
394 #define MEI_XMEM_BAR9 ((volatile u32*)(0x0078 + MEI_SPACE_ACCESS))
395 #define MEI_XMEM_BAR10 ((volatile u32*)(0x007C + MEI_SPACE_ACCESS))
396 #define MEI_XMEM_BAR11 ((volatile u32*)(0x0080 + MEI_SPACE_ACCESS))
397 #define MEI_XMEM_BAR12 ((volatile u32*)(0x0084 + MEI_SPACE_ACCESS))
398 #define MEI_XMEM_BAR13 ((volatile u32*)(0x0088 + MEI_SPACE_ACCESS))
399 #define MEI_XMEM_BAR14 ((volatile u32*)(0x008C + MEI_SPACE_ACCESS))
400 #define MEI_XMEM_BAR15 ((volatile u32*)(0x0090 + MEI_SPACE_ACCESS))
401 #define MEI_XMEM_BAR16 ((volatile u32*)(0x0094 + MEI_SPACE_ACCESS))
403 /***********************************************************************/
404 /* Module : SSC1 register address and bits */
405 /***********************************************************************/
407 #define DANUBE_SSC1 (KSEG1+0x1e100800)
408 /***********************************************************************/
409 /***SSC Clock Control Register***/
410 #define DANUBE_SSC_CLC (0x0000)
411 #define DANUBE_SSC_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8)
412 #define DANUBE_SSC_CLC_DISS (1 << 1)
413 #define DANUBE_SSC_CLC_DISR (1 << 0)
414 /***SSC Port Input Selection Register***/
415 #define DANUBE_SSC_PISEL (0x0004)
416 /***SSC Identification Register***/
417 #define DANUBE_SSC_ID (0x0008)
418 /***Control Register (Programming Mode)***/
419 #define DANUBE_SSC_CON (0x0010)
420 #define DANUBE_SSC_CON_RUEN (1 << 12)
421 #define DANUBE_SSC_CON_TUEN (1 << 11)
422 #define DANUBE_SSC_CON_AEN (1 << 10)
423 #define DANUBE_SSC_CON_REN (1 << 9)
424 #define DANUBE_SSC_CON_TEN (1 << 8)
425 #define DANUBE_SSC_CON_LB (1 << 7)
426 #define DANUBE_SSC_CON_PO (1 << 6)
427 #define DANUBE_SSC_CON_PH (1 << 5)
428 #define DANUBE_SSC_CON_HB (1 << 4)
429 #define DANUBE_SSC_CON_BM(value) (((( 1 << 5) - 1) & (value)) << 16)
430 #define DANUBE_SSC_CON_RX_OFF (1 << 1)
431 #define DANUBE_SSC_CON_TX_OFF (1 << 0)
432 /***SCC Status Register***/
433 #define DANUBE_SSC_STATE (0x0014)
434 #define DANUBE_SSC_STATE_EN (1 << 0)
435 #define DANUBE_SSC_STATE_MS (1 << 1)
436 #define DANUBE_SSC_STATE_BSY (1 << 13)
437 #define DANUBE_SSC_STATE_RUE (1 << 12)
438 #define DANUBE_SSC_STATE_TUE (1 << 11)
439 #define DANUBE_SSC_STATE_AE (1 << 10)
440 #define DANUBE_SSC_STATE_RE (1 << 9)
441 #define DANUBE_SSC_STATE_TE (1 << 8)
442 #define DANUBE_SSC_STATE_BC(value) (((( 1 << 5) - 1) & (value)) << 16)
443 /***SSC Write Hardware Modified Control Register***/
444 #define DANUBE_SSC_WHBSTATE ( 0x0018)
445 #define DANUBE_SSC_WHBSTATE_SETBE (1 << 15)
446 #define DANUBE_SSC_WHBSTATE_SETPE (1 << 14)
447 #define DANUBE_SSC_WHBSTATE_SETRE (1 << 13)
448 #define DANUBE_SSC_WHBSTATE_SETTE (1 << 12)
449 #define DANUBE_SSC_WHBSTATE_CLRBE (1 << 11)
450 #define DANUBE_SSC_WHBSTATE_CLRPE (1 << 10)
451 #define DANUBE_SSC_WHBSTATE_CLRRE (1 << 9)
452 #define DANUBE_SSC_WHBSTATE_CLRTE (1 << 8)
453 /***SSC Transmitter Buffer Register***/
454 #define DANUBE_SSC_TB (0x0020)
455 #define DANUBE_SSC_TB_TB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0)
456 /***SSC Receiver Buffer Register***/
457 #define DANUBE_SSC_RB (0x0024)
458 #define DANUBE_SSC_RB_RB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0)
459 /***SSC Receive FIFO Control Register***/
460 #define DANUBE_SSC_RXFCON (0x0030)
461 #define DANUBE_SSC_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
462 #define DANUBE_SSC_RXFCON_RXTMEN (1 << 2)
463 #define DANUBE_SSC_RXFCON_RXFLU (1 << 1)
464 #define DANUBE_SSC_RXFCON_RXFEN (1 << 0)
465 /***SSC Transmit FIFO Control Register***/
466 #define DANUBE_SSC_TXFCON ( 0x0034)
467 #define DANUBE_SSC_TXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
468 #define DANUBE_SSC_TXFCON_TXTMEN (1 << 2)
469 #define DANUBE_SSC_TXFCON_TXFLU (1 << 1)
470 #define DANUBE_SSC_TXFCON_TXFEN (1 << 0)
471 /***SSC FIFO Status Register***/
472 #define DANUBE_SSC_FSTAT (0x0038)
473 #define DANUBE_SSC_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8)
474 #define DANUBE_SSC_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0)
475 /***SSC Baudrate Timer Reload Register***/
476 #define DANUBE_SSC_BR (0x0040)
477 #define DANUBE_SSC_BR_BR_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0)
478 #define DANUBE_SSC_BRSTAT (0x0044)
479 #define DANUBE_SSC_SFCON (0x0060)
480 #define DANUBE_SSC_SFSTAT (0x0064)
481 #define DANUBE_SSC_GPOCON (0x0070)
482 #define DANUBE_SSC_GPOSTAT (0x0074)
483 #define DANUBE_SSC_WHBGPOSTAT (0x0078)
484 #define DANUBE_SSC_RXREQ (0x0080)
485 #define DANUBE_SSC_RXCNT (0x0084)
486 /*DMA Registers in Bus Clock Domain*/
487 #define DANUBE_SSC_DMA_CON (0x00EC)
488 /*interrupt Node Registers in Bus Clock Domain*/
489 #define DANUBE_SSC_IRNEN (0x00F4)
490 #define DANUBE_SSC_IRNCR (0x00F8)
491 #define DANUBE_SSC_IRNICR (0x00FC)
492 #define DANUBE_SSC_IRN_FIR 0x8
493 #define DANUBE_SSC_IRN_EIR 0x4
494 #define DANUBE_SSC_IRN_RIR 0x2
495 #define DANUBE_SSC_IRN_TIR 0x1
497 #define DANUBE_SSC1_CLC ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CLC))
498 #define DANUBE_SSC1_ID ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_ID))
499 #define DANUBE_SSC1_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CON))
500 #define DANUBE_SSC1_STATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_STATE))
501 #define DANUBE_SSC1_WHBSTATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBSTATE))
502 #define DANUBE_SSC1_TB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TB))
503 #define DANUBE_SSC1_RB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RB))
504 #define DANUBE_SSC1_FSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_FSTAT))
505 #define DANUBE_SSC1_PISEL ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_PISEL))
506 #define DANUBE_SSC1_RXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXFCON))
507 #define DANUBE_SSC1_TXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TXFCON))
508 #define DANUBE_SSC1_BR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BR))
509 #define DANUBE_SSC1_BRSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BRSTAT))
510 #define DANUBE_SSC1_SFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFCON))
511 #define DANUBE_SSC1_SFSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFSTAT))
512 #define DANUBE_SSC1_GPOCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOCON))
513 #define DANUBE_SSC1_GPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOSTAT))
514 #define DANUBE_SSC1_WHBGPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBGPOSTAT))
515 #define DANUBE_SSC1_RXREQ ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXREQ))
516 #define DANUBE_SSC1_RXCNT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXCNT))
517 #define DANUBE_SSC1_DMA_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_DMA_CON))
518 #define DANUBE_SSC1_IRNEN ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNEN))
519 #define DANUBE_SSC1_IRNICR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNICR))
520 #define DANUBE_SSC1_IRNCR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNCR))
522 /***********************************************************************/
523 /* Module : GPIO register address and bits */
524 /***********************************************************************/
525 #define DANUBE_GPIO (0xBE100B00)
526 /***Port 0 Data Output Register (0010H)***/
527 #define DANUBE_GPIO_P0_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0010))
528 /***Port 1 Data Output Register (0040H)***/
529 #define DANUBE_GPIO_P1_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0040))
530 /***Port 0 Data Input Register (0014H)***/
531 #define DANUBE_GPIO_P0_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0014))
532 /***Port 1 Data Input Register (0044H)***/
533 #define DANUBE_GPIO_P1_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0044))
534 /***Port 0 Direction Register (0018H)***/
535 #define DANUBE_GPIO_P0_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0018))
536 /***Port 1 Direction Register (0048H)***/
537 #define DANUBE_GPIO_P1_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0048))
538 /***Port 0 Alternate Function Select Register 0 (001C H) ***/
539 #define DANUBE_GPIO_P0_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x001C))
540 /***Port 1 Alternate Function Select Register 0 (004C H) ***/
541 #define DANUBE_GPIO_P1_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x004C))
542 /***Port 0 Alternate Function Select Register 1 (0020 H) ***/
543 #define DANUBE_GPIO_P0_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0020))
544 /***Port 1 Alternate Function Select Register 0 (0050 H) ***/
545 #define DANUBE_GPIO_P1_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0050))
546 /***Port 0 Open Drain Control Register (0024H)***/
547 #define DANUBE_GPIO_P0_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0024))
548 /***Port 1 Open Drain Control Register (0054H)***/
549 #define DANUBE_GPIO_P1_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0054))
550 /***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/
551 #define DANUBE_GPIO_P0_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0028))
552 /***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/
553 #define DANUBE_GPIO_P1_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0058))
554 /***Port 0 Pull Up/Pull Down Select Register (002C H)***/
555 #define DANUBE_GPIO_P0_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x002C))
556 /***Port 1 Pull Up/Pull Down Select Register (005C H)***/
557 #define DANUBE_GPIO_P1_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x005C))
558 /***Port 0 Pull Up Device Enable Register (0030 H)***/
559 #define DANUBE_GPIO_P0_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0030))
560 /***Port 1 Pull Up Device Enable Register (0060 H)***/
561 #define DANUBE_GPIO_P1_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0060))
562 /***********************************************************************/
563 /* Module : CGU register address and bits */
564 /***********************************************************************/
566 #define DANUBE_CGU (0xBF103000)
567 /***********************************************************************/
568 /***CGU Clock PLL0 ***/
569 #define DANUBE_CGU_PLL0_CFG ((volatile u32*)(DANUBE_CGU+ 0x0004))
570 /***CGU Clock PLL1 ***/
571 #define DANUBE_CGU_PLL1_CFG ((volatile u32*)(DANUBE_CGU+ 0x0008))
572 /***CGU Clock SYS Mux Register***/
573 #define DANUBE_CGU_SYS ((volatile u32*)(DANUBE_CGU+ 0x0010))
574 /***CGU Interface Clock Control Register***/
575 #define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018))
576 /***CGU PCI Clock Control Register**/
577 #define DANUBE_CGU_PCICR ((volatile u32*)(DANUBE_CGU+ 0x0034))
578 #define CLOCK_60M 60000000
579 #define CLOCK_83M 83333333
580 #define CLOCK_111M 111111111
581 #define CLOCK_133M 133333333
582 #define CLOCK_167M 166666667
583 #define CLOCK_333M 333333333
585 /***********************************************************************/
586 /* Module : MCD register address and bits */
587 /***********************************************************************/
588 #define DANUBE_MCD (KSEG1+0x1F106000)
590 /***Manufacturer Identification Register***/
591 #define DANUBE_MCD_MANID ((volatile u32*)(DANUBE_MCD+ 0x0024))
592 #define DANUBE_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5)
594 /***Chip Identification Register***/
595 #define DANUBE_MCD_CHIPID ((volatile u32*)(DANUBE_MCD+ 0x0028))
596 #define DANUBE_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
597 #define DANUBE_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
598 #define DANUBE_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1))
599 #define DANUBE_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
600 #define DANUBE_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1))
601 #define DANUBE_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1)
603 #define DANUBE_CHIPID_STANDARD 0x00EB
604 #define DANUBE_CHIPID_YANGTSE 0x00ED
606 /***Redesign Tracing Identification Register***/
607 #define DANUBE_MCD_RTID ((volatile u32*)(DANUBE_MCD+ 0x002C))
608 #define DANUBE_MCD_RTID_LC (1 << 15)
609 #define DANUBE_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0)
611 /***********************************************************************/
612 /* Module : EBU register address and bits */
613 /***********************************************************************/
615 #define DANUBE_EBU (0xBE105300)
617 /***********************************************************************/
619 /***EBU Clock Control Register***/
620 #define DANUBE_EBU_CLC ((volatile u32*)(DANUBE_EBU+ 0x0000))
621 #define DANUBE_EBU_CLC_DISS (1 << 1)
622 #define DANUBE_EBU_CLC_DISR (1 << 0)
624 /***EBU Global Control Register***/
625 #define DANUBE_EBU_CON ((volatile u32*)(DANUBE_EBU+ 0x0010))
626 #define DANUBE_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20)
627 #define DANUBE_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16)
628 #define DANUBE_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8)
629 #define DANUBE_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6)
630 #define DANUBE_EBU_CON_ARBSYNC (1 << 5)
631 #define DANUBE_EBU_CON_1 (1 << 3)
633 /***EBU Address Select Register 0***/
634 #define DANUBE_EBU_ADDSEL0 ((volatile u32*)(DANUBE_EBU+ 0x0020))
635 #define DANUBE_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
636 #define DANUBE_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
637 #define DANUBE_EBU_ADDSEL0_MIRRORE (1 << 1)
638 #define DANUBE_EBU_ADDSEL0_REGEN (1 << 0)
640 /***EBU Address Select Register 1***/
641 #define DANUBE_EBU_ADDSEL1 ((volatile u32*)(DANUBE_EBU+ 0x0024))
642 #define DANUBE_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
643 #define DANUBE_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
644 #define DANUBE_EBU_ADDSEL1_MIRRORE (1 << 1)
645 #define DANUBE_EBU_ADDSEL1_REGEN (1 << 0)
647 /***EBU Address Select Register 2***/
648 #define DANUBE_EBU_ADDSEL2 ((volatile u32*)(DANUBE_EBU+ 0x0028))
649 #define DANUBE_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
650 #define DANUBE_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
651 #define DANUBE_EBU_ADDSEL2_MIRRORE (1 << 1)
652 #define DANUBE_EBU_ADDSEL2_REGEN (1 << 0)
654 /***EBU Address Select Register 3***/
655 #define DANUBE_EBU_ADDSEL3 ((volatile u32*)(DANUBE_EBU+ 0x0028))
656 #define DANUBE_EBU_ADDSEL3_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
657 #define DANUBE_EBU_ADDSEL3_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
658 #define DANUBE_EBU_ADDSEL3_MIRRORE (1 << 1)
659 #define DANUBE_EBU_ADDSEL3_REGEN (1 << 0)
661 /***EBU Bus Configuration Register 0***/
662 #define DANUBE_EBU_BUSCON0 ((volatile u32*)(DANUBE_EBU+ 0x0060))
663 #define DANUBE_EBU_BUSCON0_WRDIS (1 << 31)
664 #define DANUBE_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
665 #define DANUBE_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
666 #define DANUBE_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
667 #define DANUBE_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
668 #define DANUBE_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
669 #define DANUBE_EBU_BUSCON0_WAITINV (1 << 19)
670 #define DANUBE_EBU_BUSCON0_SETUP (1 << 18)
671 #define DANUBE_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
672 #define DANUBE_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
673 #define DANUBE_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
674 #define DANUBE_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
675 #define DANUBE_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
676 #define DANUBE_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
678 /***EBU Bus Configuration Register 1***/
679 #define DANUBE_EBU_BUSCON1 ((volatile u32*)(DANUBE_EBU+ 0x0064))
680 #define DANUBE_EBU_BUSCON1_WRDIS (1 << 31)
681 #define DANUBE_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
682 #define DANUBE_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
683 #define DANUBE_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
684 #define DANUBE_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
685 #define DANUBE_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
686 #define DANUBE_EBU_BUSCON1_WAITINV (1 << 19)
687 #define DANUBE_EBU_BUSCON1_SETUP (1 << 18)
688 #define DANUBE_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
689 #define DANUBE_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
690 #define DANUBE_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
691 #define DANUBE_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
692 #define DANUBE_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
693 #define DANUBE_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
695 /***EBU Bus Configuration Register 2***/
696 #define DANUBE_EBU_BUSCON2 ((volatile u32*)(DANUBE_EBU+ 0x0068))
697 #define DANUBE_EBU_BUSCON2_WRDIS (1 << 31)
698 #define DANUBE_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
699 #define DANUBE_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
700 #define DANUBE_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
701 #define DANUBE_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
702 #define DANUBE_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
703 #define DANUBE_EBU_BUSCON2_WAITINV (1 << 19)
704 #define DANUBE_EBU_BUSCON2_SETUP (1 << 18)
705 #define DANUBE_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
706 #define DANUBE_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
707 #define DANUBE_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
708 #define DANUBE_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
709 #define DANUBE_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
710 #define DANUBE_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
712 #define DANUBE_EBU_PCC_CON ((volatile u32*)(DANUBE_EBU+ 0x0090))
713 #define DANUBE_EBU_PCC_STAT ((volatile u32*)(DANUBE_EBU+ 0x0094))
714 #define DANUBE_EBU_PCC_ISTAT ((volatile u32*)(DANUBE_EBU+ 0x00A0))
715 #define DANUBE_EBU_PCC_IEN ((volatile u32*)(DANUBE_EBU+ 0x00A4))
716 /***********************************************************************/
717 /* Module : SDRAM register address and bits */
718 /***********************************************************************/
720 #define DANUBE_SDRAM (0xBF800000)
721 /***********************************************************************/
723 /***MC Access Error Cause Register***/
724 #define DANUBE_SDRAM_MC_ERRCAUSE ((volatile u32*)(DANUBE_SDRAM+ 0x0100))
725 #define DANUBE_SDRAM_MC_ERRCAUSE_ERR (1 << 31)
726 #define DANUBE_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
727 #define DANUBE_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
728 #define DANUBE_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN)
730 /***MC Access Error Address Register***/
731 #define DANUBE_SDRAM_MC_ERRADDR ((volatile u32*)(DANUBE_SDRAM+ 0x0108))
732 #define DANUBE_SDRAM_MC_ERRADDR_ADDR
734 /***MC I/O General Purpose Register***/
735 #define DANUBE_SDRAM_MC_IOGP ((volatile u32*)(DANUBE_SDRAM+ 0x0800))
736 #define DANUBE_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28)
737 #define DANUBE_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24)
738 #define DANUBE_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20)
739 #define DANUBE_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16)
740 #define DANUBE_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12)
741 #define DANUBE_SDRAM_MC_IOGP_CPS (1 << 11)
742 #define DANUBE_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8)
743 #define DANUBE_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4)
744 #define DANUBE_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0)
746 /***MC Self Refresh Register***/
747 #define DANUBE_SDRAM_MC_SELFRFSH ((volatile u32*)(DANUBE_SDRAM+ 0x0A00))
748 #define DANUBE_SDRAM_MC_SELFRFSH_PWDS (1 << 1)
749 #define DANUBE_SDRAM_MC_SELFRFSH_PWD (1 << 0)
750 #define DANUBE_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2)
752 /***MC Enable Register***/
753 #define DANUBE_SDRAM_MC_CTRLENA ((volatile u32*)(DANUBE_SDRAM+ 0x1000))
754 #define DANUBE_SDRAM_MC_CTRLENA_ENA (1 << 0)
755 #define DANUBE_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1)
757 /***MC Mode Register Setup Code***/
758 #define DANUBE_SDRAM_MC_MRSCODE ((volatile u32*)(DANUBE_SDRAM+ 0x1008))
759 #define DANUBE_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7)
760 #define DANUBE_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4)
761 #define DANUBE_SDRAM_MC_MRSCODE_WT (1 << 3)
762 #define DANUBE_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0)
764 /***MC Configuration Data-word Width Register***/
765 #define DANUBE_SDRAM_MC_CFGDW ((volatile u32*)(DANUBE_SDRAM+ 0x1010))
766 #define DANUBE_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0)
767 #define DANUBE_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4)
769 /***MC Configuration Physical Bank 0 Register***/
770 #define DANUBE_SDRAM_MC_CFGPB0 ((volatile u32*)(DANUBE_SDRAM+ 0x1018))
771 #define DANUBE_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12)
772 #define DANUBE_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8)
773 #define DANUBE_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4)
774 #define DANUBE_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0)
775 #define DANUBE_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16)
777 /***MC Latency Register***/
778 #define DANUBE_SDRAM_MC_LATENCY ((volatile u32*)(DANUBE_SDRAM+ 0x1038))
779 #define DANUBE_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16)
780 #define DANUBE_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12)
781 #define DANUBE_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8)
782 #define DANUBE_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4)
783 #define DANUBE_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0)
784 #define DANUBE_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20)
786 /***MC Refresh Cycle Time Register***/
787 #define DANUBE_SDRAM_MC_TREFRESH ((volatile u32*)(DANUBE_SDRAM+ 0x1040))
788 #define DANUBE_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0)
789 #define DANUBE_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13)
791 /***********************************************************************/
792 /* Module : GPTC register address and bits */
793 /***********************************************************************/
795 #define DANUBE_GPTC (KSEG1 + 0x1E100A00)
796 #define DANUBE_GPTC_CLC ((volatile u32*) (DANUBE_GPTC + 0x0000))
797 #define DANUBE_GPTC_ID ((volatile u32*) (DANUBE_GPTC + 0x0008))
798 #define DANUBE_GPTC_IRNEN ((volatile u32*) (DANUBE_GPTC + 0x00F4))
799 #define DANUBE_GPTC_IRNICR ((volatile u32*) (DANUBE_GPTC + 0x00F8)
800 #define DANUBE_GPTC_IRNCR ((volatile u32*) (DANUBE_GPTC + 0x00FC))
802 #define DANUBE_GPTC_CON_1A ((volatile u32*) (DANUBE_GPTC + 0x0010))
803 #define DANUBE_GPTC_RUN_1A ((volatile u32*) (DANUBE_GPTC + 0x0018))
804 #define DANUBE_GPTC_RELOAD_1A ((volatile u32*) (DANUBE_GPTC + 0x0020))
805 #define DANUBE_GPTC_COUNT_1A ((volatile u32*) (DANUBE_GPTC + 0x0028))
807 #define DANUBE_GPTC_CON_1B ((volatile u32*) (DANUBE_GPTC + 0x0014))
808 #define DANUBE_GPTC_RUN_1B ((volatile u32*) (DANUBE_GPTC + 0x001C))
809 #define DANUBE_GPTC_RELOAD_1B ((volatile u32*) (DANUBE_GPTC + 0x0024))
810 #define DANUBE_GPTC_COUNT_1B ((volatile u32*) (DANUBE_GPTC + 0x002C))
812 #define DANUBE_GPTC_CON_2A ((volatile u32*) (DANUBE_GPTC + 0x0030))
813 #define DANUBE_GPTC_RUN_2A ((volatile u32*) (DANUBE_GPTC + 0x0038))
814 #define DANUBE_GPTC_RELOAD_2A ((volatile u32*) (DANUBE_GPTC + 0x0040))
815 #define DANUBE_GPTC_COUNT_2A ((volatile u32*) (DANUBE_GPTC + 0x0048))
817 #define DANUBE_GPTC_CON_2B ((volatile u32*) (DANUBE_GPTC + 0x0034))
818 #define DANUBE_GPTC_RUN_2B ((volatile u32*) (DANUBE_GPTC + 0x003C))
819 #define DANUBE_GPTC_RELOAD_2B ((volatile u32*) (DANUBE_GPTC + 0x0044))
820 #define DANUBE_GPTC_COUNT_2B ((volatile u32*) (DANUBE_GPTC + 0x004C))
822 /***********************************************************************/
823 /* Module : GPTU register address and bits */
824 /***********************************************************************/
826 #define DANUBE_GPTU (0xB8000300)
827 /***********************************************************************/
829 /***GPT Clock Control Register***/
830 #define DANUBE_GPTU_GPT_CLC ((volatile u32*)(DANUBE_GPTU+ 0x0000))
831 #define DANUBE_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)
832 #define DANUBE_GPTU_GPT_CLC_DISS (1 << 1)
833 #define DANUBE_GPTU_GPT_CLC_DISR (1 << 0)
835 /***GPT Timer 3 Control Register***/
836 #define DANUBE_GPTU_GPT_T3CON ((volatile u32*)(DANUBE_GPTU+ 0x0014))
837 #define DANUBE_GPTU_GPT_T3CON_T3RDIR (1 << 15)
838 #define DANUBE_GPTU_GPT_T3CON_T3CHDIR (1 << 14)
839 #define DANUBE_GPTU_GPT_T3CON_T3EDGE (1 << 13)
840 #define DANUBE_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11)
841 #define DANUBE_GPTU_GPT_T3CON_T3OTL (1 << 10)
842 #define DANUBE_GPTU_GPT_T3CON_T3UD (1 << 7)
843 #define DANUBE_GPTU_GPT_T3CON_T3R (1 << 6)
844 #define DANUBE_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3)
845 #define DANUBE_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0)
847 /***GPT Write Hardware Modified Timer 3 Control Register
848 If set and clear bit are written concurrently with 1, the associated bit is not changed.***/
849 #define DANUBE_GPTU_GPT_WHBT3CON ((volatile u32*)(DANUBE_GPTU+ 0x004C))
850 #define DANUBE_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15)
851 #define DANUBE_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14)
852 #define DANUBE_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13)
853 #define DANUBE_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12)
854 #define DANUBE_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11)
855 #define DANUBE_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10)
857 /***GPT Timer 2 Control Register***/
858 #define DANUBE_GPTU_GPT_T2CON ((volatile u32*)(DANUBE_GPTU+ 0x0010))
859 #define DANUBE_GPTU_GPT_T2CON_TxRDIR (1 << 15)
860 #define DANUBE_GPTU_GPT_T2CON_TxCHDIR (1 << 14)
861 #define DANUBE_GPTU_GPT_T2CON_TxEDGE (1 << 13)
862 #define DANUBE_GPTU_GPT_T2CON_TxIRDIS (1 << 12)
863 #define DANUBE_GPTU_GPT_T2CON_TxRC (1 << 9)
864 #define DANUBE_GPTU_GPT_T2CON_TxUD (1 << 7)
865 #define DANUBE_GPTU_GPT_T2CON_TxR (1 << 6)
866 #define DANUBE_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3)
867 #define DANUBE_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0)
869 /***GPT Timer 4 Control Register***/
870 #define DANUBE_GPTU_GPT_T4CON ((volatile u32*)(DANUBE_GPTU+ 0x0018))
871 #define DANUBE_GPTU_GPT_T4CON_TxRDIR (1 << 15)
872 #define DANUBE_GPTU_GPT_T4CON_TxCHDIR (1 << 14)
873 #define DANUBE_GPTU_GPT_T4CON_TxEDGE (1 << 13)
874 #define DANUBE_GPTU_GPT_T4CON_TxIRDIS (1 << 12)
875 #define DANUBE_GPTU_GPT_T4CON_TxRC (1 << 9)
876 #define DANUBE_GPTU_GPT_T4CON_TxUD (1 << 7)
877 #define DANUBE_GPTU_GPT_T4CON_TxR (1 << 6)
878 #define DANUBE_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3)
879 #define DANUBE_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0)
881 /***GPT Write HW Modified Timer 2 Control Register If set
882 and clear bit are written concurrently with 1, the associated bit is not changed.***/
883 #define DANUBE_GPTU_GPT_WHBT2CON ((volatile u32*)(DANUBE_GPTU+ 0x0048))
884 #define DANUBE_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15)
885 #define DANUBE_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14)
886 #define DANUBE_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13)
887 #define DANUBE_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12)
889 /***GPT Write HW Modified Timer 4 Control Register If set
890 and clear bit are written concurrently with 1, the associated bit is not changed.***/
891 #define DANUBE_GPTU_GPT_WHBT4CON ((volatile u32*)(DANUBE_GPTU+ 0x0050))
892 #define DANUBE_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15)
893 #define DANUBE_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14)
894 #define DANUBE_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13)
895 #define DANUBE_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12)
897 /***GPT Capture Reload Register***/
898 #define DANUBE_GPTU_GPT_CAPREL ((volatile u32*)(DANUBE_GPTU+ 0x0030))
899 #define DANUBE_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0)
901 /***GPT Timer 2 Register***/
902 #define DANUBE_GPTU_GPT_T2 ((volatile u32*)(DANUBE_GPTU+ 0x0034))
903 #define DANUBE_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
905 /***GPT Timer 3 Register***/
906 #define DANUBE_GPTU_GPT_T3 ((volatile u32*)(DANUBE_GPTU+ 0x0038))
907 #define DANUBE_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
909 /***GPT Timer 4 Register***/
910 #define DANUBE_GPTU_GPT_T4 ((volatile u32*)(DANUBE_GPTU+ 0x003C))
911 #define DANUBE_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
913 /***GPT Timer 5 Register***/
914 #define DANUBE_GPTU_GPT_T5 ((volatile u32*)(DANUBE_GPTU+ 0x0040))
915 #define DANUBE_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
917 /***GPT Timer 6 Register***/
918 #define DANUBE_GPTU_GPT_T6 ((volatile u32*)(DANUBE_GPTU+ 0x0044))
919 #define DANUBE_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
921 /***GPT Timer 6 Control Register***/
922 #define DANUBE_GPTU_GPT_T6CON ((volatile u32*)(DANUBE_GPTU+ 0x0020))
923 #define DANUBE_GPTU_GPT_T6CON_T6SR (1 << 15)
924 #define DANUBE_GPTU_GPT_T6CON_T6CLR (1 << 14)
925 #define DANUBE_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11)
926 #define DANUBE_GPTU_GPT_T6CON_T6OTL (1 << 10)
927 #define DANUBE_GPTU_GPT_T6CON_T6UD (1 << 7)
928 #define DANUBE_GPTU_GPT_T6CON_T6R (1 << 6)
929 #define DANUBE_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3)
930 #define DANUBE_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0)
932 /***GPT Write HW Modified Timer 6 Control Register If set
933 and clear bit are written concurrently with 1, the associated bit is not changed.***/
934 #define DANUBE_GPTU_GPT_WHBT6CON ((volatile u32*)(DANUBE_GPTU+ 0x0054))
935 #define DANUBE_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11)
936 #define DANUBE_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10)
938 /***GPT Timer 5 Control Register***/
939 #define DANUBE_GPTU_GPT_T5CON ((volatile u32*)(DANUBE_GPTU+ 0x001C))
940 #define DANUBE_GPTU_GPT_T5CON_T5SC (1 << 15)
941 #define DANUBE_GPTU_GPT_T5CON_T5CLR (1 << 14)
942 #define DANUBE_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12)
943 #define DANUBE_GPTU_GPT_T5CON_T5CC (1 << 11)
944 #define DANUBE_GPTU_GPT_T5CON_CT3 (1 << 10)
945 #define DANUBE_GPTU_GPT_T5CON_T5RC (1 << 9)
946 #define DANUBE_GPTU_GPT_T5CON_T5UDE (1 << 8)
947 #define DANUBE_GPTU_GPT_T5CON_T5UD (1 << 7)
948 #define DANUBE_GPTU_GPT_T5CON_T5R (1 << 6)
949 #define DANUBE_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3)
950 #define DANUBE_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0)
952 /***********************************************************************/
953 /* Module : IOM register address and bits */
954 /***********************************************************************/
956 #define DANUBE_IOM (0xBF105000)
957 /***********************************************************************/
960 #define DANUBE_IOM_RFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000))
961 #define DANUBE_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0)
963 /***Transmit FIFO***/
964 #define DANUBE_IOM_XFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000))
965 #define DANUBE_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0)
967 /***Interrupt Status Register HDLC***/
968 #define DANUBE_IOM_ISTAH ((volatile u32*)(DANUBE_IOM+ 0x0080))
969 #define DANUBE_IOM_ISTAH_RME (1 << 7)
970 #define DANUBE_IOM_ISTAH_RPF (1 << 6)
971 #define DANUBE_IOM_ISTAH_RFO (1 << 5)
972 #define DANUBE_IOM_ISTAH_XPR (1 << 4)
973 #define DANUBE_IOM_ISTAH_XMR (1 << 3)
974 #define DANUBE_IOM_ISTAH_XDU (1 << 2)
976 /***Interrupt Mask Register HDLC***/
977 #define DANUBE_IOM_MASKH ((volatile u32*)(DANUBE_IOM+ 0x0080))
978 #define DANUBE_IOM_MASKH_RME (1 << 7)
979 #define DANUBE_IOM_MASKH_RPF (1 << 6)
980 #define DANUBE_IOM_MASKH_RFO (1 << 5)
981 #define DANUBE_IOM_MASKH_XPR (1 << 4)
982 #define DANUBE_IOM_MASKH_XMR (1 << 3)
983 #define DANUBE_IOM_MASKH_XDU (1 << 2)
985 /***Status Register***/
986 #define DANUBE_IOM_STAR ((volatile u32*)(DANUBE_IOM+ 0x0084))
987 #define DANUBE_IOM_STAR_XDOV (1 << 7)
988 #define DANUBE_IOM_STAR_XFW (1 << 6)
989 #define DANUBE_IOM_STAR_RACI (1 << 3)
990 #define DANUBE_IOM_STAR_XACI (1 << 1)
992 /***Command Register***/
993 #define DANUBE_IOM_CMDR ((volatile u32*)(DANUBE_IOM+ 0x0084))
994 #define DANUBE_IOM_CMDR_RMC (1 << 7)
995 #define DANUBE_IOM_CMDR_RRES (1 << 6)
996 #define DANUBE_IOM_CMDR_XTF (1 << 3)
997 #define DANUBE_IOM_CMDR_XME (1 << 1)
998 #define DANUBE_IOM_CMDR_XRES (1 << 0)
1000 /***Mode Register***/
1001 #define DANUBE_IOM_MODEH ((volatile u32*)(DANUBE_IOM+ 0x0088))
1002 #define DANUBE_IOM_MODEH_MDS2 (1 << 7)
1003 #define DANUBE_IOM_MODEH_MDS1 (1 << 6)
1004 #define DANUBE_IOM_MODEH_MDS0 (1 << 5)
1005 #define DANUBE_IOM_MODEH_RAC (1 << 3)
1006 #define DANUBE_IOM_MODEH_DIM2 (1 << 2)
1007 #define DANUBE_IOM_MODEH_DIM1 (1 << 1)
1008 #define DANUBE_IOM_MODEH_DIM0 (1 << 0)
1010 /***Extended Mode Register***/
1011 #define DANUBE_IOM_EXMR ((volatile u32*)(DANUBE_IOM+ 0x008C))
1012 #define DANUBE_IOM_EXMR_XFBS (1 << 7)
1013 #define DANUBE_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5)
1014 #define DANUBE_IOM_EXMR_SRA (1 << 4)
1015 #define DANUBE_IOM_EXMR_XCRC (1 << 3)
1016 #define DANUBE_IOM_EXMR_RCRC (1 << 2)
1017 #define DANUBE_IOM_EXMR_ITF (1 << 0)
1019 /***SAPI1 Register***/
1020 #define DANUBE_IOM_SAP1 ((volatile u32*)(DANUBE_IOM+ 0x0094))
1021 #define DANUBE_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2)
1022 #define DANUBE_IOM_SAP1_MHA (1 << 0)
1024 /***Receive Frame Byte Count Low***/
1025 #define DANUBE_IOM_RBCL ((volatile u32*)(DANUBE_IOM+ 0x0098))
1026 #define DANUBE_IOM_RBCL_RBC(value) (1 << value)
1028 /***SAPI2 Register***/
1029 #define DANUBE_IOM_SAP2 ((volatile u32*)(DANUBE_IOM+ 0x0098))
1030 #define DANUBE_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2)
1031 #define DANUBE_IOM_SAP2_MLA (1 << 0)
1033 /***Receive Frame Byte Count High***/
1034 #define DANUBE_IOM_RBCH ((volatile u32*)(DANUBE_IOM+ 0x009C))
1035 #define DANUBE_IOM_RBCH_OV (1 << 4)
1036 #define DANUBE_IOM_RBCH_RBC11 (1 << 3)
1037 #define DANUBE_IOM_RBCH_RBC10 (1 << 2)
1038 #define DANUBE_IOM_RBCH_RBC9 (1 << 1)
1039 #define DANUBE_IOM_RBCH_RBC8 (1 << 0)
1041 /***TEI1 Register 1***/
1042 #define DANUBE_IOM_TEI1 ((volatile u32*)(DANUBE_IOM+ 0x009C))
1043 #define DANUBE_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1)
1044 #define DANUBE_IOM_TEI1_EA (1 << 0)
1046 /***Receive Status Register***/
1047 #define DANUBE_IOM_RSTA ((volatile u32*)(DANUBE_IOM+ 0x00A0))
1048 #define DANUBE_IOM_RSTA_VFR (1 << 7)
1049 #define DANUBE_IOM_RSTA_RDO (1 << 6)
1050 #define DANUBE_IOM_RSTA_CRC (1 << 5)
1051 #define DANUBE_IOM_RSTA_RAB (1 << 4)
1052 #define DANUBE_IOM_RSTA_SA1 (1 << 3)
1053 #define DANUBE_IOM_RSTA_SA0 (1 << 2)
1054 #define DANUBE_IOM_RSTA_TA (1 << 0)
1055 #define DANUBE_IOM_RSTA_CR (1 << 1)
1057 /***TEI2 Register***/
1058 #define DANUBE_IOM_TEI2 ((volatile u32*)(DANUBE_IOM+ 0x00A0))
1059 #define DANUBE_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1)
1060 #define DANUBE_IOM_TEI2_EA (1 << 0)
1062 /***Test Mode Register HDLC***/
1063 #define DANUBE_IOM_TMH ((volatile u32*)(DANUBE_IOM+ 0x00A4))
1064 #define DANUBE_IOM_TMH_TLP (1 << 0)
1066 /***Command/Indication Receive 0***/
1067 #define DANUBE_IOM_CIR0 ((volatile u32*)(DANUBE_IOM+ 0x00B8))
1068 #define DANUBE_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4)
1069 #define DANUBE_IOM_CIR0_CIC0 (1 << 3)
1070 #define DANUBE_IOM_CIR0_CIC1 (1 << 2)
1071 #define DANUBE_IOM_CIR0_SG (1 << 1)
1072 #define DANUBE_IOM_CIR0_BAS (1 << 0)
1074 /***Command/Indication Transmit 0***/
1075 #define DANUBE_IOM_CIX0 ((volatile u32*)(DANUBE_IOM+ 0x00B8))
1076 #define DANUBE_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4)
1077 #define DANUBE_IOM_CIX0_TBA2 (1 << 3)
1078 #define DANUBE_IOM_CIX0_TBA1 (1 << 2)
1079 #define DANUBE_IOM_CIX0_TBA0 (1 << 1)
1080 #define DANUBE_IOM_CIX0_BAC (1 << 0)
1082 /***Command/Indication Receive 1***/
1083 #define DANUBE_IOM_CIR1 ((volatile u32*)(DANUBE_IOM+ 0x00BC))
1084 #define DANUBE_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2)
1086 /***Command/Indication Transmit 1***/
1087 #define DANUBE_IOM_CIX1 ((volatile u32*)(DANUBE_IOM+ 0x00BC))
1088 #define DANUBE_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2)
1089 #define DANUBE_IOM_CIX1_CICW (1 << 1)
1090 #define DANUBE_IOM_CIX1_CI1E (1 << 0)
1092 /***Controller Data Access Reg. (CH10)***/
1093 #define DANUBE_IOM_CDA10 ((volatile u32*)(DANUBE_IOM+ 0x0100))
1094 #define DANUBE_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
1096 /***Controller Data Access Reg. (CH11)***/
1097 #define DANUBE_IOM_CDA11 ((volatile u32*)(DANUBE_IOM+ 0x0104))
1098 #define DANUBE_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
1100 /***Controller Data Access Reg. (CH20)***/
1101 #define DANUBE_IOM_CDA20 ((volatile u32*)(DANUBE_IOM+ 0x0108))
1102 #define DANUBE_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
1104 /***Controller Data Access Reg. (CH21)***/
1105 #define DANUBE_IOM_CDA21 ((volatile u32*)(DANUBE_IOM+ 0x010C))
1106 #define DANUBE_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
1108 /***Time Slot and Data Port Sel. (CH10)***/
1109 #define DANUBE_IOM_CDA_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0110))
1110 #define DANUBE_IOM_CDA_TSDP10_DPS (1 << 7)
1111 #define DANUBE_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1113 /***Time Slot and Data Port Sel. (CH11)***/
1114 #define DANUBE_IOM_CDA_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0114))
1115 #define DANUBE_IOM_CDA_TSDP11_DPS (1 << 7)
1116 #define DANUBE_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1118 /***Time Slot and Data Port Sel. (CH20)***/
1119 #define DANUBE_IOM_CDA_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0118))
1120 #define DANUBE_IOM_CDA_TSDP20_DPS (1 << 7)
1121 #define DANUBE_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1123 /***Time Slot and Data Port Sel. (CH21)***/
1124 #define DANUBE_IOM_CDA_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x011C))
1125 #define DANUBE_IOM_CDA_TSDP21_DPS (1 << 7)
1126 #define DANUBE_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1128 /***Time Slot and Data Port Sel. (CH10)***/
1129 #define DANUBE_IOM_CO_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0120))
1130 #define DANUBE_IOM_CO_TSDP10_DPS (1 << 7)
1131 #define DANUBE_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1133 /***Time Slot and Data Port Sel. (CH11)***/
1134 #define DANUBE_IOM_CO_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0124))
1135 #define DANUBE_IOM_CO_TSDP11_DPS (1 << 7)
1136 #define DANUBE_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1138 /***Time Slot and Data Port Sel. (CH20)***/
1139 #define DANUBE_IOM_CO_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0128))
1140 #define DANUBE_IOM_CO_TSDP20_DPS (1 << 7)
1141 #define DANUBE_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1143 /***Time Slot and Data Port Sel. (CH21)***/
1144 #define DANUBE_IOM_CO_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x012C))
1145 #define DANUBE_IOM_CO_TSDP21_DPS (1 << 7)
1146 #define DANUBE_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1148 /***Ctrl. Reg. Contr. Data Access CH1x***/
1149 #define DANUBE_IOM_CDA1_CR ((volatile u32*)(DANUBE_IOM+ 0x0138))
1150 #define DANUBE_IOM_CDA1_CR_EN_TBM (1 << 5)
1151 #define DANUBE_IOM_CDA1_CR_EN_I1 (1 << 4)
1152 #define DANUBE_IOM_CDA1_CR_EN_I0 (1 << 3)
1153 #define DANUBE_IOM_CDA1_CR_EN_O1 (1 << 2)
1154 #define DANUBE_IOM_CDA1_CR_EN_O0 (1 << 1)
1155 #define DANUBE_IOM_CDA1_CR_SWAP (1 << 0)
1157 /***Ctrl. Reg. Contr. Data Access CH1x***/
1158 #define DANUBE_IOM_CDA2_CR ((volatile u32*)(DANUBE_IOM+ 0x013C))
1159 #define DANUBE_IOM_CDA2_CR_EN_TBM (1 << 5)
1160 #define DANUBE_IOM_CDA2_CR_EN_I1 (1 << 4)
1161 #define DANUBE_IOM_CDA2_CR_EN_I0 (1 << 3)
1162 #define DANUBE_IOM_CDA2_CR_EN_O1 (1 << 2)
1163 #define DANUBE_IOM_CDA2_CR_EN_O0 (1 << 1)
1164 #define DANUBE_IOM_CDA2_CR_SWAP (1 << 0)
1166 /***Control Register B-Channel Data***/
1167 #define DANUBE_IOM_BCHA_CR ((volatile u32*)(DANUBE_IOM+ 0x0144))
1168 #define DANUBE_IOM_BCHA_CR_EN_BC2 (1 << 4)
1169 #define DANUBE_IOM_BCHA_CR_EN_BC1 (1 << 3)
1171 /***Control Register B-Channel Data***/
1172 #define DANUBE_IOM_BCHB_CR ((volatile u32*)(DANUBE_IOM+ 0x0148))
1173 #define DANUBE_IOM_BCHB_CR_EN_BC2 (1 << 4)
1174 #define DANUBE_IOM_BCHB_CR_EN_BC1 (1 << 3)
1176 /***Control Reg. for HDLC and CI1 Data***/
1177 #define DANUBE_IOM_DCI_CR ((volatile u32*)(DANUBE_IOM+ 0x014C))
1178 #define DANUBE_IOM_DCI_CR_DPS_CI1 (1 << 7)
1179 #define DANUBE_IOM_DCI_CR_EN_CI1 (1 << 6)
1180 #define DANUBE_IOM_DCI_CR_EN_D (1 << 5)
1182 /***Control Reg. for HDLC and CI1 Data***/
1183 #define DANUBE_IOM_DCIC_CR ((volatile u32*)(DANUBE_IOM+ 0x014C))
1184 #define DANUBE_IOM_DCIC_CR_DPS_CI0 (1 << 7)
1185 #define DANUBE_IOM_DCIC_CR_EN_CI0 (1 << 6)
1186 #define DANUBE_IOM_DCIC_CR_DPS_D (1 << 5)
1188 /***Control Reg. Serial Data Strobe x***/
1189 #define DANUBE_IOM_SDS_CR ((volatile u32*)(DANUBE_IOM+ 0x0154))
1190 #define DANUBE_IOM_SDS_CR_ENS_TSS (1 << 7)
1191 #define DANUBE_IOM_SDS_CR_ENS_TSS_1 (1 << 6)
1192 #define DANUBE_IOM_SDS_CR_ENS_TSS_3 (1 << 5)
1193 #define DANUBE_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
1195 /***Control Register IOM Data***/
1196 #define DANUBE_IOM_IOM_CR ((volatile u32*)(DANUBE_IOM+ 0x015C))
1197 #define DANUBE_IOM_IOM_CR_SPU (1 << 7)
1198 #define DANUBE_IOM_IOM_CR_CI_CS (1 << 5)
1199 #define DANUBE_IOM_IOM_CR_TIC_DIS (1 << 4)
1200 #define DANUBE_IOM_IOM_CR_EN_BCL (1 << 3)
1201 #define DANUBE_IOM_IOM_CR_CLKM (1 << 2)
1202 #define DANUBE_IOM_IOM_CR_Res (1 << 1)
1203 #define DANUBE_IOM_IOM_CR_DIS_IOM (1 << 0)
1205 /***Synchronous Transfer Interrupt***/
1206 #define DANUBE_IOM_STI ((volatile u32*)(DANUBE_IOM+ 0x0160))
1207 #define DANUBE_IOM_STI_STOV21 (1 << 7)
1208 #define DANUBE_IOM_STI_STOV20 (1 << 6)
1209 #define DANUBE_IOM_STI_STOV11 (1 << 5)
1210 #define DANUBE_IOM_STI_STOV10 (1 << 4)
1211 #define DANUBE_IOM_STI_STI21 (1 << 3)
1212 #define DANUBE_IOM_STI_STI20 (1 << 2)
1213 #define DANUBE_IOM_STI_STI11 (1 << 1)
1214 #define DANUBE_IOM_STI_STI10 (1 << 0)
1216 /***Acknowledge Synchronous Transfer Interrupt***/
1217 #define DANUBE_IOM_ASTI ((volatile u32*)(DANUBE_IOM+ 0x0160))
1218 #define DANUBE_IOM_ASTI_ACK21 (1 << 3)
1219 #define DANUBE_IOM_ASTI_ACK20 (1 << 2)
1220 #define DANUBE_IOM_ASTI_ACK11 (1 << 1)
1221 #define DANUBE_IOM_ASTI_ACK10 (1 << 0)
1223 /***Mask Synchronous Transfer Interrupt***/
1224 #define DANUBE_IOM_MSTI ((volatile u32*)(DANUBE_IOM+ 0x0164))
1225 #define DANUBE_IOM_MSTI_STOV21 (1 << 7)
1226 #define DANUBE_IOM_MSTI_STOV20 (1 << 6)
1227 #define DANUBE_IOM_MSTI_STOV11 (1 << 5)
1228 #define DANUBE_IOM_MSTI_STOV10 (1 << 4)
1229 #define DANUBE_IOM_MSTI_STI21 (1 << 3)
1230 #define DANUBE_IOM_MSTI_STI20 (1 << 2)
1231 #define DANUBE_IOM_MSTI_STI11 (1 << 1)
1232 #define DANUBE_IOM_MSTI_STI10 (1 << 0)
1234 /***Configuration Register for Serial Data Strobes***/
1235 #define DANUBE_IOM_SDS_CONF ((volatile u32*)(DANUBE_IOM+ 0x0168))
1236 #define DANUBE_IOM_SDS_CONF_SDS_BCL (1 << 0)
1238 /***Monitoring CDA Bits***/
1239 #define DANUBE_IOM_MCDA ((volatile u32*)(DANUBE_IOM+ 0x016C))
1240 #define DANUBE_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6)
1241 #define DANUBE_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4)
1242 #define DANUBE_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2)
1243 #define DANUBE_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0)
1245 /***********************************************************************/
1246 /* Module : ASC0 register address and bits */
1247 /***********************************************************************/
1248 #define DANUBE_ASC0 (KSEG1+0x1E100400)
1249 /***********************************************************************/
1250 #define DANUBE_ASC0_TBUF ((volatile u32*)(DANUBE_ASC0 + 0x0020))
1251 #define DANUBE_ASC0_RBUF ((volatile u32*)(DANUBE_ASC0 + 0x0024))
1252 #define DANUBE_ASC0_FSTAT ((volatile u32*)(DANUBE_ASC0 + 0x0048))
1253 #define DANUBE_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1))
1254 #define DANUBE_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24)
1255 #define DANUBE_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1))
1256 #define DANUBE_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16)
1257 #define DANUBE_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1))
1258 #define DANUBE_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8)
1259 #define DANUBE_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1))
1260 #define DANUBE_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0)
1262 /***********************************************************************/
1263 /* Module : ASC1 register address and bits */
1264 /***********************************************************************/
1266 #define DANUBE_ASC1 (KSEG1+0x1E100C00)
1267 /***********************************************************************/
1268 /***ASC Clock Control Register***/
1269 #define DANUBE_ASC1_CLC ((volatile u32*)(DANUBE_ASC1+ 0x0000))
1270 #define DANUBE_ASC1_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8)
1271 #define DANUBE_ASC1_CLC_DISS (1 << 1)
1272 #define DANUBE_ASC1_CLC_DISR (1 << 0)
1274 /***ASC Port Input Select Register***/
1275 #define DANUBE_ASC1_PISEL ((volatile u32*)(DANUBE_ASC1+ 0x0004))
1276 #define DANUBE_ASC1_PISEL ((volatile u32*)(DANUBE_ASC1+ 0x0004))
1277 #define DANUBE_ASC1_PISEL_RIS (1 << 0)
1279 /***ASC Control Register***/
1280 #define DANUBE_ASC1_CON ((volatile u32*)(DANUBE_ASC1+ 0x0010))
1281 #define DANUBE_ASC1_CON_BEN (1 << 20)
1282 #define DANUBE_ASC1_CON_TOEN (1 << 20)
1283 #define DANUBE_ASC1_CON_ROEN (1 << 19)
1284 #define DANUBE_ASC1_CON_RUEN (1 << 18)
1285 #define DANUBE_ASC1_CON_FEN (1 << 17)
1286 #define DANUBE_ASC1_CON_PAL (1 << 16)
1287 #define DANUBE_ASC1_CON_R (1 << 15)
1288 #define DANUBE_ASC1_CON_ACO (1 << 14)
1289 #define DANUBE_ASC1_CON_LB (1 << 13)
1290 #define DANUBE_ASC1_CON_ERCLK (1 << 10)
1291 #define DANUBE_ASC1_CON_FDE (1 << 9)
1292 #define DANUBE_ASC1_CON_BRS (1 << 8)
1293 #define DANUBE_ASC1_CON_STP (1 << 7)
1294 #define DANUBE_ASC1_CON_SP (1 << 6)
1295 #define DANUBE_ASC1_CON_ODD (1 << 5)
1296 #define DANUBE_ASC1_CON_PEN (1 << 4)
1297 #define DANUBE_ASC1_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0)
1299 /***ASC Staus Register***/
1300 #define DANUBE_ASC1_STATE ((volatile u32*)(DANUBE_ASC1+ 0x0014))
1301 /***ASC Write Hardware Modified Control Register***/
1302 #define DANUBE_ASC1_WHBSTATE ((volatile u32*)(DANUBE_ASC1+ 0x0018))
1303 #define DANUBE_ASC1_WHBSTATE_SETBE (1 << 113)
1304 #define DANUBE_ASC1_WHBSTATE_SETTOE (1 << 12)
1305 #define DANUBE_ASC1_WHBSTATE_SETROE (1 << 11)
1306 #define DANUBE_ASC1_WHBSTATE_SETRUE (1 << 10)
1307 #define DANUBE_ASC1_WHBSTATE_SETFE (1 << 19)
1308 #define DANUBE_ASC1_WHBSTATE_SETPE (1 << 18)
1309 #define DANUBE_ASC1_WHBSTATE_CLRBE (1 << 17)
1310 #define DANUBE_ASC1_WHBSTATE_CLRTOE (1 << 6)
1311 #define DANUBE_ASC1_WHBSTATE_CLRROE (1 << 5)
1312 #define DANUBE_ASC1_WHBSTATE_CLRRUE (1 << 4)
1313 #define DANUBE_ASC1_WHBSTATE_CLRFE (1 << 3)
1314 #define DANUBE_ASC1_WHBSTATE_CLRPE (1 << 2)
1315 #define DANUBE_ASC1_WHBSTATE_SETREN (1 << 1)
1316 #define DANUBE_ASC1_WHBSTATE_CLRREN (1 << 0)
1318 /***ASC Baudrate Timer/Reload Register***/
1319 #define DANUBE_ASC1_BG ((volatile u32*)(DANUBE_ASC1+ 0x0050))
1320 #define DANUBE_ASC1_BG_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0)
1322 /***ASC Fractional Divider Register***/
1323 #define DANUBE_ASC1_FDV ((volatile u32*)(DANUBE_ASC1+ 0x0018))
1324 #define DANUBE_ASC1_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0)
1326 /***ASC Transmit Buffer Register***/
1327 #define DANUBE_ASC1_TBUF ((volatile u32*)(DANUBE_ASC1+ 0x0020))
1328 #define DANUBE_ASC1_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0)
1330 /***ASC Receive Buffer Register***/
1331 #define DANUBE_ASC1_RBUF ((volatile u32*)(DANUBE_ASC1+ 0x0024))
1332 #define DANUBE_ASC1_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0)
1334 /***ASC Autobaud Control Register***/
1335 #define DANUBE_ASC1_ABCON ((volatile u32*)(DANUBE_ASC1+ 0x0030))
1336 #define DANUBE_ASC1_ABCON_RXINV (1 << 11)
1337 #define DANUBE_ASC1_ABCON_TXINV (1 << 10)
1338 #define DANUBE_ASC1_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8)
1339 #define DANUBE_ASC1_ABCON_FCDETEN (1 << 4)
1340 #define DANUBE_ASC1_ABCON_ABDETEN (1 << 3)
1341 #define DANUBE_ASC1_ABCON_ABSTEN (1 << 2)
1342 #define DANUBE_ASC1_ABCON_AUREN (1 << 1)
1343 #define DANUBE_ASC1_ABCON_ABEN (1 << 0)
1345 /***Receive FIFO Control Register***/
1346 #define DANUBE_ASC1_RXFCON ((volatile u32*)(DANUBE_ASC1+ 0x0040))
1347 #define DANUBE_ASC1_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
1348 #define DANUBE_ASC1_RXFCON_RXFFLU (1 << 1)
1349 #define DANUBE_ASC1_RXFCON_RXFEN (1 << 0)
1351 /***Transmit FIFO Control Register***/
1352 #define DANUBE_ASC1_TXFCON ((volatile u32*)(DANUBE_ASC1+ 0x0044))
1353 #define DANUBE_ASC1_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
1354 #define DANUBE_ASC1_TXFCON_TXFFLU (1 << 1)
1355 #define DANUBE_ASC1_TXFCON_TXFEN (1 << 0)
1357 /***FIFO Status Register***/
1358 #define DANUBE_ASC1_FSTAT ((volatile u32*)(DANUBE_ASC1+ 0x0048))
1359 #define DANUBE_ASC1_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8)
1360 #define DANUBE_ASC1_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0)
1361 #define DANUBE_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1))
1362 #define DANUBE_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24)
1363 #define DANUBE_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1))
1364 #define DANUBE_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16)
1365 #define DANUBE_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1))
1366 #define DANUBE_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8)
1367 #define DANUBE_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1))
1368 #define DANUBE_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0)
1370 /***ASC Autobaud Status Register***/
1371 #define DANUBE_ASC1_ABSTAT ((volatile u32*)(DANUBE_ASC1+ 0x0034))
1372 #define DANUBE_ASC1_ABSTAT_DETWAIT (1 << 4)
1373 #define DANUBE_ASC1_ABSTAT_SCCDET (1 << 3)
1374 #define DANUBE_ASC1_ABSTAT_SCSDET (1 << 2)
1375 #define DANUBE_ASC1_ABSTAT_FCCDET (1 << 1)
1376 #define DANUBE_ASC1_ABSTAT_FCSDET (1 << 0)
1378 /***ASC Write HW Modified Autobaud Status Register***/
1379 #define DANUBE_ASC1_WHBABSTAT ((volatile u32*)(DANUBE_ASC1+ 0x003C))
1380 #define DANUBE_ASC1_WHBABSTAT_SETDETWAIT (1 << 9)
1381 #define DANUBE_ASC1_WHBABSTAT_CLRDETWAIT (1 << 8)
1382 #define DANUBE_ASC1_WHBABSTAT_SETSCCDET (1 << 7)
1383 #define DANUBE_ASC1_WHBABSTAT_CLRSCCDET (1 << 6)
1384 #define DANUBE_ASC1_WHBABSTAT_SETSCSDET (1 << 5)
1385 #define DANUBE_ASC1_WHBABSTAT_CLRSCSDET (1 << 4)
1386 #define DANUBE_ASC1_WHBABSTAT_SETFCCDET (1 << 3)
1387 #define DANUBE_ASC1_WHBABSTAT_CLRFCCDET (1 << 2)
1388 #define DANUBE_ASC1_WHBABSTAT_SETFCSDET (1 << 1)
1389 #define DANUBE_ASC1_WHBABSTAT_CLRFCSDET (1 << 0)
1392 #define DANUBE_ASC1_IRNREN ((volatile u32*)(DANUBE_ASC1+ 0x00F4))
1393 #define DANUBE_ASC1_IRNICR ((volatile u32*)(DANUBE_ASC1+ 0x00FC))
1395 #define DANUBE_ASC1_IRNCR ((volatile u32*)(DANUBE_ASC1+ 0x00F8))
1396 #define ASC_IRNCR_TIR 0x4
1397 #define ASC_IRNCR_RIR 0x2
1398 #define ASC_IRNCR_EIR 0x4
1400 /***********************************************************************/
1401 /* Module : DMA register address and bits */
1402 /***********************************************************************/
1404 #define DANUBE_DMA (0xBE104100)
1405 /***********************************************************************/
1407 #define DANUBE_DMA_BASE DANUBE_DMA
1408 #define DANUBE_DMA_CLC (volatile u32*)DANUBE_DMA_BASE
1409 #define DANUBE_DMA_ID (volatile u32*)(DANUBE_DMA_BASE+0x08)
1410 #define DANUBE_DMA_CTRL (volatile u32*)(DANUBE_DMA_BASE+0x10)
1411 #define DANUBE_DMA_CPOLL (volatile u32*)(DANUBE_DMA_BASE+0x14)
1412 #define DANUBE_DMA_CS (volatile u32*)(DANUBE_DMA_BASE+0x18)
1413 #define DANUBE_DMA_CCTRL (volatile u32*)(DANUBE_DMA_BASE+0x1C)
1414 #define DANUBE_DMA_CDBA (volatile u32*)(DANUBE_DMA_BASE+0x20)
1415 #define DANUBE_DMA_CDLEN (volatile u32*)(DANUBE_DMA_BASE+0x24)
1416 #define DANUBE_DMA_CIS (volatile u32*)(DANUBE_DMA_BASE+0x28)
1417 #define DANUBE_DMA_CIE (volatile u32*)(DANUBE_DMA_BASE+0x2C)
1419 #define DANUBE_DMA_PS (volatile u32*)(DANUBE_DMA_BASE+0x40)
1420 #define DANUBE_DMA_PCTRL (volatile u32*)(DANUBE_DMA_BASE+0x44)
1422 #define DANUBE_DMA_IRNEN (volatile u32*)(DANUBE_DMA_BASE+0xf4)
1423 #define DANUBE_DMA_IRNCR (volatile u32*)(DANUBE_DMA_BASE+0xf8)
1424 #define DANUBE_DMA_IRNICR (volatile u32*)(DANUBE_DMA_BASE+0xfc)
1425 /***********************************************************************/
1426 /* Module : Debug register address and bits */
1427 /***********************************************************************/
1429 #define DANUBE_Debug (0xBF106000)
1430 /***********************************************************************/
1432 /***MCD Break Bus Switch Register***/
1433 #define DANUBE_Debug_MCD_BBS ((volatile u32*)(DANUBE_Debug+ 0x0000))
1434 #define DANUBE_Debug_MCD_BBS_BTP1 (1 << 19)
1435 #define DANUBE_Debug_MCD_BBS_BTP0 (1 << 18)
1436 #define DANUBE_Debug_MCD_BBS_BSP1 (1 << 17)
1437 #define DANUBE_Debug_MCD_BBS_BSP0 (1 << 16)
1438 #define DANUBE_Debug_MCD_BBS_BT5EN (1 << 15)
1439 #define DANUBE_Debug_MCD_BBS_BT4EN (1 << 14)
1440 #define DANUBE_Debug_MCD_BBS_BT5 (1 << 13)
1441 #define DANUBE_Debug_MCD_BBS_BT4 (1 << 12)
1442 #define DANUBE_Debug_MCD_BBS_BS5EN (1 << 7)
1443 #define DANUBE_Debug_MCD_BBS_BS4EN (1 << 6)
1444 #define DANUBE_Debug_MCD_BBS_BS5 (1 << 5)
1445 #define DANUBE_Debug_MCD_BBS_BS4 (1 << 4)
1447 /***MCD Multiplexer Control Register***/
1448 #define DANUBE_Debug_MCD_MCR ((volatile u32*)(DANUBE_Debug+ 0x0008))
1449 #define DANUBE_Debug_MCD_MCR_MUX5 (1 << 4)
1450 #define DANUBE_Debug_MCD_MCR_MUX4 (1 << 3)
1451 #define DANUBE_Debug_MCD_MCR_MUX1 (1 << 0)
1453 /***********************************************************************/
1454 /* Module : SRAM register address and bits */
1455 /***********************************************************************/
1457 #define DANUBE_SRAM (0xBF980000)
1458 /***********************************************************************/
1460 /***SRAM Size Register***/
1461 #define DANUBE_SRAM_SRAM_SIZE ((volatile u32*)(DANUBE_SRAM+ 0x0800))
1462 #define DANUBE_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0)
1464 /***********************************************************************/
1465 /* Module : BIU register address and bits */
1466 /***********************************************************************/
1468 #define DANUBE_BIU (0xBFA80000)
1469 /***********************************************************************/
1471 /***BIU Identification Register***/
1472 #define DANUBE_BIU_BIU_ID ((volatile u32*)(DANUBE_BIU+ 0x0000))
1473 #define DANUBE_BIU_BIU_ID_ARCH (1 << 16)
1474 #define DANUBE_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8)
1475 #define DANUBE_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0)
1477 /***BIU Access Error Cause Register***/
1478 #define DANUBE_BIU_BIU_ERRCAUSE ((volatile u32*)(DANUBE_BIU+ 0x0100))
1479 #define DANUBE_BIU_BIU_ERRCAUSE_ERR (1 << 31)
1480 #define DANUBE_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
1481 #define DANUBE_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
1483 /***BIU Access Error Address Register***/
1484 #define DANUBE_BIU_BIU_ERRADDR ((volatile u32*)(DANUBE_BIU+ 0x0108))
1485 #define DANUBE_BIU_BIU_ERRADDR_ADDR
1487 /***********************************************************************/
1488 /* Module : ICU register address and bits */
1489 /***********************************************************************/
1491 #define DANUBE_ICU (0xBF880200)
1492 /***********************************************************************/
1493 #define DANUBE_ICU_IM0_ISR ((volatile u32*)(DANUBE_ICU + 0x0000))
1494 #define DANUBE_ICU_IM0_IER ((volatile u32*)(DANUBE_ICU + 0x0008))
1495 #define DANUBE_ICU_IM0_IOSR ((volatile u32*)(DANUBE_ICU + 0x0010))
1496 #define DANUBE_ICU_IM0_IRSR ((volatile u32*)(DANUBE_ICU + 0x0018))
1497 #define DANUBE_ICU_IM0_IMR ((volatile u32*)(DANUBE_ICU + 0x0020))
1498 #define DANUBE_ICU_IM0_IMR_IID (1 << 31)
1499 #define DANUBE_ICU_IM0_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
1500 #define DANUBE_ICU_IM0_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
1501 #define DANUBE_ICU_IM0_IR(value) (1 << (value))
1503 #define DANUBE_ICU_IM1_ISR ((volatile u32*)(DANUBE_ICU + 0x0028))
1504 #define DANUBE_ICU_IM1_IER ((volatile u32*)(DANUBE_ICU + 0x0030))
1505 #define DANUBE_ICU_IM1_IOSR ((volatile u32*)(DANUBE_ICU + 0x0038))
1506 #define DANUBE_ICU_IM1_IRSR ((volatile u32*)(DANUBE_ICU + 0x0040))
1507 #define DANUBE_ICU_IM1_IMR ((volatile u32*)(DANUBE_ICU + 0x0048))
1508 #define DANUBE_ICU_IM1_IMR_IID (1 << 31)
1509 #define DANUBE_ICU_IM1_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
1510 #define DANUBE_ICU_IM1_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
1511 #define DANUBE_ICU_IM1_IR(value) (1 << (value))
1513 #define DANUBE_ICU_IM2_ISR ((volatile u32*)(DANUBE_ICU + 0x0050))
1514 #define DANUBE_ICU_IM2_IER ((volatile u32*)(DANUBE_ICU + 0x0058))
1515 #define DANUBE_ICU_IM2_IOSR ((volatile u32*)(DANUBE_ICU + 0x0060))
1516 #define DANUBE_ICU_IM2_IRSR ((volatile u32*)(DANUBE_ICU + 0x0068))
1517 #define DANUBE_ICU_IM2_IMR ((volatile u32*)(DANUBE_ICU + 0x0070))
1518 #define DANUBE_ICU_IM2_IMR_IID (1 << 31)
1519 #define DANUBE_ICU_IM2_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
1520 #define DANUBE_ICU_IM2_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
1521 #define DANUBE_ICU_IM2_IR(value) (1 << (value))
1523 #define DANUBE_ICU_IM3_ISR ((volatile u32*)(DANUBE_ICU + 0x0078))
1524 #define DANUBE_ICU_IM3_IER ((volatile u32*)(DANUBE_ICU + 0x0080))
1525 #define DANUBE_ICU_IM3_IOSR ((volatile u32*)(DANUBE_ICU + 0x0088))
1526 #define DANUBE_ICU_IM3_IRSR ((volatile u32*)(DANUBE_ICU + 0x0090))
1527 #define DANUBE_ICU_IM3_IMR ((volatile u32*)(DANUBE_ICU + 0x0098))
1528 #define DANUBE_ICU_IM3_IMR_IID (1 << 31)
1529 #define DANUBE_ICU_IM3_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
1530 #define DANUBE_ICU_IM3_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
1531 #define DANUBE_ICU_IM3_IR(value) (1 << (value))
1533 #define DANUBE_ICU_IM4_ISR ((volatile u32*)(DANUBE_ICU + 0x00A0))
1534 #define DANUBE_ICU_IM4_IER ((volatile u32*)(DANUBE_ICU + 0x00A8))
1535 #define DANUBE_ICU_IM4_IOSR ((volatile u32*)(DANUBE_ICU + 0x00B0))
1536 #define DANUBE_ICU_IM4_IRSR ((volatile u32*)(DANUBE_ICU + 0x00B8))
1537 #define DANUBE_ICU_IM4_IMR ((volatile u32*)(DANUBE_ICU + 0x00C0))
1538 #define DANUBE_ICU_IM4_IMR_IID (1 << 31)
1539 #define DANUBE_ICU_IM4_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
1540 #define DANUBE_ICU_IM4_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
1541 #define DANUBE_ICU_IM4_IR(value) (1 << (value))
1543 #define DANUBE_ICU_IM5_ISR ((volatile u32*)(DANUBE_ICU + 0x00C8))
1544 #define DANUBE_ICU_IM5_IER ((volatile u32*)(DANUBE_ICU + 0x00D0))
1545 #define DANUBE_ICU_IM5_IOSR ((volatile u32*)(DANUBE_ICU + 0x00D8))
1546 #define DANUBE_ICU_IM5_IRSR ((volatile u32*)(DANUBE_ICU + 0x00E0))
1547 #define DANUBE_ICU_IM5_IMR ((volatile u32*)(DANUBE_ICU + 0x00E8))
1548 #define DANUBE_ICU_IM5_IMR_IID (1 << 31)
1549 #define DANUBE_ICU_IM5_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
1550 #define DANUBE_ICU_IM5_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
1551 #define DANUBE_ICU_IM5_IR(value) (1 << (value))
1553 /***Interrupt Vector Value Register***/
1554 //#define DANUBE_ICU_IM_VEC ((volatile u32*)(DANUBE_ICU+ 0x00f0))
1555 #define DANUBE_ICU_IM_VEC ((volatile u32*)(DANUBE_ICU+ 0x00EC))
1557 /***Interrupt Vector Value Mask***/
1558 #define DANUBE_ICU_IM0_VEC_MASK 0x0000001f
1559 #define DANUBE_ICU_IM1_VEC_MASK 0x000003e0
1560 #define DANUBE_ICU_IM2_VEC_MASK 0x00007c00
1561 #define DANUBE_ICU_IM3_VEC_MASK 0x000f8000
1562 #define DANUBE_ICU_IM4_VEC_MASK 0x01f00000
1564 #define DANUBE_ICU_IM0_ISR_IR(value) (1<<(value))
1565 #define DANUBE_ICU_IM0_IER_IR(value) (1<<(value))
1566 #define DANUBE_ICU_IM1_ISR_IR(value) (1<<(value))
1567 #define DANUBE_ICU_IM1_IER_IR(value) (1<<(value))
1568 #define DANUBE_ICU_IM2_ISR_IR(value) (1<<(value))
1569 #define DANUBE_ICU_IM2_IER_IR(value) (1<<(value))
1570 #define DANUBE_ICU_IM3_ISR_IR(value) (1<<(value))
1571 #define DANUBE_ICU_IM3_IER_IR(value) (1<<(value))
1572 #define DANUBE_ICU_IM4_ISR_IR(value) (1<<(value))
1573 #define DANUBE_ICU_IM4_IER_IR(value) (1<<(value))
1574 #define DANUBE_ICU_IM5_ISR_IR(value) (1<<(value))
1575 #define DANUBE_ICU_IM5_IER_IR(value) (1<<(value))
1577 /***DMA Interrupt Mask Value***/
1578 #define DANUBE_DMA_H_MASK 0x00000fff
1580 /***External Interrupt Control Register***/
1581 #define DANUBE_ICU_EIU (KSEG1+0x1f101000)
1582 #define DANUBE_ICU_EIU_EXIN_C ((volatile u32*)(DANUBE_ICU_EIU+ 0x0000))
1583 #define DANUBE_ICU_EIU_INIC ((volatile u32*)(DANUBE_ICU_EIU+ 0x0004))
1584 #define DANUBE_ICU_EIU_INC ((volatile u32*)(DANUBE_ICU_EIU+ 0x0008))
1585 #define DANUBE_ICU_EIU_INEN ((volatile u32*)(DANUBE_ICU_EIU+ 0x000c))
1587 /***********************************************************************/
1588 /* Module : MPS register address and bits */
1589 /***********************************************************************/
1591 #define DANUBE_MPS (KSEG1+0x1F107000)
1592 /***********************************************************************/
1594 #define DANUBE_MPS_CHIPID ((volatile u32*)(DANUBE_MPS + 0x0344))
1595 #define DANUBE_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
1596 #define DANUBE_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
1597 #define DANUBE_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
1598 #define DANUBE_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
1599 #define DANUBE_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
1600 #define DANUBE_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1)
1602 /* voice channel 0 ... 3 interrupt enable register */
1603 #define DANUBE_MPS_VC0ENR ((volatile u32*)(DANUBE_MPS + 0x0000))
1604 #define DANUBE_MPS_VC1ENR ((volatile u32*)(DANUBE_MPS + 0x0004))
1605 #define DANUBE_MPS_VC2ENR ((volatile u32*)(DANUBE_MPS + 0x0008))
1606 #define DANUBE_MPS_VC3ENR ((volatile u32*)(DANUBE_MPS + 0x000C))
1607 /* voice channel 0 ... 3 interrupt status read register */
1608 #define DANUBE_MPS_RVC0SR ((volatile u32*)(DANUBE_MPS + 0x0010))
1609 #define DANUBE_MPS_RVC1SR ((volatile u32*)(DANUBE_MPS + 0x0014))
1610 #define DANUBE_MPS_RVC2SR ((volatile u32*)(DANUBE_MPS + 0x0018))
1611 #define DANUBE_MPS_RVC3SR ((volatile u32*)(DANUBE_MPS + 0x001C))
1612 /* voice channel 0 ... 3 interrupt status set register */
1613 #define DANUBE_MPS_SVC0SR ((volatile u32*)(DANUBE_MPS + 0x0020))
1614 #define DANUBE_MPS_SVC1SR ((volatile u32*)(DANUBE_MPS + 0x0024))
1615 #define DANUBE_MPS_SVC2SR ((volatile u32*)(DANUBE_MPS + 0x0028))
1616 #define DANUBE_MPS_SVC3SR ((volatile u32*)(DANUBE_MPS + 0x002C))
1617 /* voice channel 0 ... 3 interrupt status clear register */
1618 #define DANUBE_MPS_CVC0SR ((volatile u32*)(DANUBE_MPS + 0x0030))
1619 #define DANUBE_MPS_CVC1SR ((volatile u32*)(DANUBE_MPS + 0x0034))
1620 #define DANUBE_MPS_CVC2SR ((volatile u32*)(DANUBE_MPS + 0x0038))
1621 #define DANUBE_MPS_CVC3SR ((volatile u32*)(DANUBE_MPS + 0x003C))
1622 /* common status 0 and 1 read register */
1623 #define DANUBE_MPS_RAD0SR ((volatile u32*)(DANUBE_MPS + 0x0040))
1624 #define DANUBE_MPS_RAD1SR ((volatile u32*)(DANUBE_MPS + 0x0044))
1625 /* common status 0 and 1 set register */
1626 #define DANUBE_MPS_SAD0SR ((volatile u32*)(DANUBE_MPS + 0x0048))
1627 #define DANUBE_MPS_SAD1SR ((volatile u32*)(DANUBE_MPS + 0x004C))
1628 /* common status 0 and 1 clear register */
1629 #define DANUBE_MPS_CAD0SR ((volatile u32*)(DANUBE_MPS + 0x0050))
1630 #define DANUBE_MPS_CAD1SR ((volatile u32*)(DANUBE_MPS + 0x0054))
1631 /* common status 0 and 1 enable register */
1632 #define DANUBE_MPS_AD0ENR ((volatile u32*)(DANUBE_MPS + 0x0058))
1633 #define DANUBE_MPS_AD1ENR ((volatile u32*)(DANUBE_MPS + 0x005C))
1634 /* notification enable register */
1635 #define DANUBE_MPS_CPU0_NFER ((volatile u32*)(DANUBE_MPS + 0x0060))
1636 #define DANUBE_MPS_CPU1_NFER ((volatile u32*)(DANUBE_MPS + 0x0064))
1637 /* CPU to CPU interrup request register */
1638 #define DANUBE_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(DANUBE_MPS + 0x0070))
1639 #define DANUBE_MPS_CPU0_2_CPU1_IER ((volatile u32*)(DANUBE_MPS + 0x0074))
1640 /* Global interrupt request and request enable register */
1641 #define DANUBE_MPS_GIRR ((volatile u32*)(DANUBE_MPS + 0x0078))
1642 #define DANUBE_MPS_GIER ((volatile u32*)(DANUBE_MPS + 0x007C))
1644 #define DANUBE_MPS_SRAM ((volatile u32*)(KSEG1 + 0x1F200000))
1646 #define DANUBE_MPS_VCPU_FW_AD ((volatile u32*)(KSEG1 + 0x1F2001E0))
1648 #define DANUBE_FUSE_BASE_ADDR (KSEG1+0x1F107354)
1650 /************************************************************************/
1651 /* Module : DEU register address and bits */
1652 /************************************************************************/
1653 //#define DANUBE_DEU_BASE_ADDR (0xBE102000)
1654 #define DANUBE_DEU_BASE_ADDR (KSEG1 + 0x1E103100)
1655 /* DEU Control Register */
1656 #define DANUBE_DEU_CLK ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0000))
1657 #define DANUBE_DEU_ID ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0008))
1659 /* DEU control register */
1660 #define DANUBE_DES_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0010))
1661 #define DANUBE_DES_IHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0014))
1662 #define DANUBE_DES_ILR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0018))
1663 #define DANUBE_DES_K1HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x001C))
1664 #define DANUBE_DES_K1LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0020))
1665 #define DANUBE_DES_K3HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0024))
1666 #define DANUBE_DES_K3LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0028))
1667 #define DANUBE_DES_IVHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x002C))
1668 #define DANUBE_DES_IVLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0030))
1669 #define DANUBE_DES_OHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0040))
1670 #define DANUBE_DES_OLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050))
1672 /* AES DEU register */
1673 #define DANUBE_AES_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050))
1674 #define DANUBE_AES_ID3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0054))
1675 #define DANUBE_AES_ID2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0058))
1676 #define DANUBE_AES_ID1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x005C))
1677 #define DANUBE_AES_ID0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0060))
1679 /* AES Key register */
1680 #define DANUBE_AES_K7R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0064))
1681 #define DANUBE_AES_K6R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0068))
1682 #define DANUBE_AES_K5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x006C))
1683 #define DANUBE_AES_K4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0070))
1684 #define DANUBE_AES_K3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0074))
1685 #define DANUBE_AES_K2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0078))
1686 #define DANUBE_AES_K1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x007C))
1687 #define DANUBE_AES_K0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0080))
1689 /* AES vector register */
1690 #define DANUBE_AES_IV3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0084))
1691 #define DANUBE_AES_IV2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0088))
1692 #define DANUBE_AES_IV1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x008C))
1693 #define DANUBE_AES_IV0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0090))
1694 #define DANUBE_AES_0D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0094))
1695 #define DANUBE_AES_0D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0098))
1696 #define DANUBE_AES_OD1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x009C))
1697 #define DANUBE_AES_OD0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00A0))
1699 /* hash control registe */
1700 #define DANUBE_HASH_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B0))
1701 #define DANUBE_HASH_MR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B4))
1702 #define DANUBE_HASH_D1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B8 ))
1703 #define DANUBE_HASH_D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00BC ))
1704 #define DANUBE_HASH_D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C0 ))
1705 #define DANUBE_HASH_D4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C4))
1706 #define DANUBE_HASH_D5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C8))
1708 #define DANUBE_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00EC))
1710 #define DANUBE_DEU_IRNEN ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00F4))
1711 #define DANUBE_DEU_IRNCR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00F8))
1712 #define DANUBE_DEU_IRNICR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00FC))
1714 /************************************************************************/
1715 /* Module : PPE register address and bits */
1716 /************************************************************************/
1717 #define DANUBE_PPE32_BASE 0xBE180000
1718 #define DANUBE_PPE32_DEBUG_BREAK_TRACE_REG (DANUBE_PPE32_BASE + (0x0000 * 4))
1719 #define DANUBE_PPE32_INT_MASK_STATUS_REG (DANUBE_PPE32_BASE + (0x0030 * 4))
1720 #define DANUBE_PPE32_INT_RESOURCE_REG (DANUBE_PPE32_BASE + (0x0040 * 4))
1721 #define DANUBE_PPE32_CDM_CODE_MEM_B0 (DANUBE_PPE32_BASE + (0x1000 * 4))
1722 #define DANUBE_PPE32_CDM_CODE_MEM_B1 (DANUBE_PPE32_BASE + (0x2000 * 4))
1723 #define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4))
1725 #define DANUBE_PPE32_SRST (DANUBE_PPE32_BASE + 0x10080)
1728 * ETOP MDIO Registers
1730 #define DANUBE_PPE32_ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
1731 #define DANUBE_PPE32_ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
1732 #define DANUBE_PPE32_ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
1733 #define DANUBE_PPE32_ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
1734 #define DANUBE_PPE32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
1735 #define DANUBE_PPE32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
1736 #define DANUBE_PPE32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
1737 #define DANUBE_PPE32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
1738 #define DANUBE_PPE32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
1739 #define DANUBE_PPE32_ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
1740 #define DANUBE_PPE32_ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
1741 #define DANUBE_PPE32_ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
1744 #define DANUBE_PPE32_ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
1745 #define DANUBE_PPE32_ENET_IG_PKTDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
1746 #define DANUBE_PPE32_ENET_CoS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
1748 /* Sharebuff SB RAM2 control data */
1750 #define DANUBE_PPE32_SB2_DATABASE ((DANUBE_PPE32_BASE + (0x8C00 * 4)))
1751 #define DANUBE_PPE32_SB2_CTRLBASE ((DANUBE_PPE32_BASE + (0x92E0 * 4)))
1752 /************************************************************************/
1753 /* Module : PPE register address and bits */
1754 /************************************************************************/
1755 #define DANUBE_PPE32_BASE 0xBE180000
1756 #define DANUBE_PPE32_DEBUG_BREAK_TRACE_REG (DANUBE_PPE32_BASE + (0x0000 * 4))
1757 #define DANUBE_PPE32_INT_MASK_STATUS_REG (DANUBE_PPE32_BASE + (0x0030 * 4))
1758 #define DANUBE_PPE32_INT_RESOURCE_REG (DANUBE_PPE32_BASE + (0x0040 * 4))
1759 #define DANUBE_PPE32_CDM_CODE_MEM_B0 (DANUBE_PPE32_BASE + (0x1000 * 4))
1760 #define DANUBE_PPE32_CDM_CODE_MEM_B1 (DANUBE_PPE32_BASE + (0x2000 * 4))
1761 #define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4))
1764 * ETOP MDIO Registers
1766 #define ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
1767 #define ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
1768 #define ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
1769 #define ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
1770 #define ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
1771 #define ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
1772 #define ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
1773 #define ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
1774 #define ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
1775 #define ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
1776 #define ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
1777 #define ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
1778 #define ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
1779 #define ENETS_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4)))
1780 #define ENETS_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4)))
1781 #define ENETS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4)))
1782 #define ENETS_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4)))
1783 #define ENETS_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4)))
1784 #define ENETS_BUF_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4)))
1785 #define ENETS_COS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
1786 #define ENETS_IGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
1787 #define ENETS_IGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4)))
1788 #define ENET_MAC_DA0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4)))
1789 #define ENET_MAC_DA1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4)))
1791 #define ENETF_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4)))
1792 #define ENETF_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4)))
1793 #define ENETF_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4)))
1794 #define ENETF_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4)))
1795 #define ENETF_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4)))
1796 #define ENETF_HFCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4)))
1797 #define ENETF_TXCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4)))
1799 #define ENETF_VLCOS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4)))
1800 #define ENETF_VLCOS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4)))
1801 #define ENETF_VLCOS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4)))
1802 #define ENETF_VLCOS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4)))
1803 #define ENETF_EGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4)))
1804 #define ENETF_EGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4)))
1807 #define DANUBE_PPE32_ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
1808 #define DANUBE_PPE32_ENET_IG_PKTDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
1809 #define DANUBE_PPE32_ENET_CoS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
1811 /* Sharebuff SB RAM2 control data */
1813 #define DANUBE_PPE32_SB2_DATABASE ((DANUBE_PPE32_BASE + (0x8C00 * 4)))
1814 #define DANUBE_PPE32_SB2_CTRLBASE ((DANUBE_PPE32_BASE + (0x92E0 * 4)))
1816 /***********************************************************************/
1817 /* Module : PCI register address and bits */
1818 /***********************************************************************/
1819 #define PCI_CR_PR_OFFSET (KSEG1+0x1E105400)
1820 #define PCI_CFG_BASE (KSEG1+0x17000000)
1821 #define PCI_MEM_BASE (KSEG1+0x18000000)
1822 #define PCI_CS_PR_OFFSET (KSEG1+0x17000000)
1824 /* PCI CONTROLLER REGISTER ADDRESS MAP */
1825 #define PCI_CR_CLK_CTRL_REG (PCI_CR_PR_OFFSET + 0x0000)
1826 #define PCI_CR_PCI_ID_REG (PCI_CR_PR_OFFSET + 0x0004)
1827 #define PCI_CR_SFT_RST_REG (PCI_CR_PR_OFFSET + 0x0010)
1828 #define PCI_CR_PCI_FPI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0014)
1829 #define PCI_CR_FCI_PCI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0018)
1830 #define PCI_CR_FPI_ERR_TAG_REG (PCI_CR_PR_OFFSET + 0x001C)
1831 #define PCI_CR_PCI_IRR_REG (PCI_CR_PR_OFFSET + 0x0020)
1832 #define PCI_CR_PCI_IRA_REG (PCI_CR_PR_OFFSET + 0x0024)
1833 #define PCI_CR_PCI_IRM_REG (PCI_CR_PR_OFFSET + 0x0028)
1834 #define PCI_CR_PCI_EOI_REG (PCI_CR_PR_OFFSET + 0x002C)
1835 #define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
1836 #define PCI_CR_DV_ID_REG (PCI_CR_PR_OFFSET + 0x0034)
1837 #define PCI_CR_SUBSYS_ID_REG (PCI_CR_PR_OFFSET + 0x0038)
1838 #define PCI_CR_PCI_PM_REG (PCI_CR_PR_OFFSET + 0x003C)
1839 #define PCI_CR_CLASS_CODE1_REG (PCI_CR_PR_OFFSET + 0x0040)
1840 #define PCI_CR_BAR11MASK_REG (PCI_CR_PR_OFFSET + 0x0044)
1841 #define PCI_CR_BAR12MASK_REG (PCI_CR_PR_OFFSET + 0x0048)
1842 #define PCI_CR_BAR13MASK_REG (PCI_CR_PR_OFFSET + 0x004C)
1843 #define PCI_CR_BAR14MASK_REG (PCI_CR_PR_OFFSET + 0x0050)
1844 #define PCI_CR_BAR15MASK_REG (PCI_CR_PR_OFFSET + 0x0054)
1845 #define PCI_CR_BAR16MASK_REG (PCI_CR_PR_OFFSET + 0x0058)
1846 #define PCI_CR_CIS_PT1_REG (PCI_CR_PR_OFFSET + 0x005C)
1847 #define PCI_CR_SUBSYS_ID1_REG (PCI_CR_PR_OFFSET + 0x0060)
1848 #define PCI_CR_PCI_ADDR_MAP11_REG (PCI_CR_PR_OFFSET + 0x0064)
1849 #define PCI_CR_PCI_ADDR_MAP12_REG (PCI_CR_PR_OFFSET + 0x0068)
1850 #define PCI_CR_PCI_ADDR_MAP13_REG (PCI_CR_PR_OFFSET + 0x006C)
1851 #define PCI_CR_PCI_ADDR_MAP14_REG (PCI_CR_PR_OFFSET + 0x0070)
1852 #define PCI_CR_PCI_ADDR_MAP15_REG (PCI_CR_PR_OFFSET + 0x0074)
1853 #define PCI_CR_PCI_ADDR_MAP16_REG (PCI_CR_PR_OFFSET + 0x0078)
1854 #define PCI_CR_FPI_SEG_EN_REG (PCI_CR_PR_OFFSET + 0x007C)
1855 #define PCI_CR_PC_ARB_REG (PCI_CR_PR_OFFSET + 0x0080)
1856 #define PCI_CR_BAR21MASK_REG (PCI_CR_PR_OFFSET + 0x0084)
1857 #define PCI_CR_BAR22MASK_REG (PCI_CR_PR_OFFSET + 0x0088)
1858 #define PCI_CR_BAR23MASK_REG (PCI_CR_PR_OFFSET + 0x008C)
1859 #define PCI_CR_BAR24MASK_REG (PCI_CR_PR_OFFSET + 0x0090)
1860 #define PCI_CR_BAR25MASK_REG (PCI_CR_PR_OFFSET + 0x0094)
1861 #define PCI_CR_BAR26MASK_REG (PCI_CR_PR_OFFSET + 0x0098)
1862 #define PCI_CR_CIS_PT2_REG (PCI_CR_PR_OFFSET + 0x009C)
1863 #define PCI_CR_SUBSYS_ID2_REG (PCI_CR_PR_OFFSET + 0x00A0)
1864 #define PCI_CR_PCI_ADDR_MAP21_REG (PCI_CR_PR_OFFSET + 0x00A4)
1865 #define PCI_CR_PCI_ADDR_MAP22_REG (PCI_CR_PR_OFFSET + 0x00A8)
1866 #define PCI_CR_PCI_ADDR_MAP23_REG (PCI_CR_PR_OFFSET + 0x00AC)
1867 #define PCI_CR_PCI_ADDR_MAP24_REG (PCI_CR_PR_OFFSET + 0x00B0)
1868 #define PCI_CR_PCI_ADDR_MAP25_REG (PCI_CR_PR_OFFSET + 0x00B4)
1869 #define PCI_CR_PCI_ADDR_MAP26_REG (PCI_CR_PR_OFFSET + 0x00B8)
1870 #define PCI_CR_FPI_ADDR_MASK_REG (PCI_CR_PR_OFFSET + 0x00BC)
1871 #define PCI_CR_FCI_ADDR_MAP0_REG (PCI_CR_PR_OFFSET + 0x00C0)
1872 #define PCI_CR_FCI_ADDR_MAP1_REG (PCI_CR_PR_OFFSET + 0x00C4)
1873 #define PCI_CR_FCI_ADDR_MAP2_REG (PCI_CR_PR_OFFSET + 0x00C8)
1874 #define PCI_CR_FCI_ADDR_MAP3_REG (PCI_CR_PR_OFFSET + 0x00CC)
1875 #define PCI_CR_FCI_ADDR_MAP4_REG (PCI_CR_PR_OFFSET + 0x00D0)
1876 #define PCI_CR_FCI_ADDR_MAP5_REG (PCI_CR_PR_OFFSET + 0x00D4)
1877 #define PCI_CR_FCI_ADDR_MAP6_REG (PCI_CR_PR_OFFSET + 0x00D8)
1878 #define PCI_CR_FCI_ADDR_MAP7_REG (PCI_CR_PR_OFFSET + 0x00DC)
1879 #define PCI_CR_FCI_ADDR_MAP11lo_REG (PCI_CR_PR_OFFSET + 0x00E0)
1880 #define PCI_CR_FCI_ADDR_MAP11hg_REG (PCI_CR_PR_OFFSET + 0x00E4)
1881 #define PCI_CR_FCI_BURST_LENGTH_REG (PCI_CR_PR_OFFSET + 0x00E8)
1882 #define PCI_CR_PCI_SET_SERR_REG (PCI_CR_PR_OFFSET + 0x00EC)
1883 #define PCI_CR_DMA_FPI_ST_ADDR_REG (PCI_CR_PR_OFFSET + 0x00F0)
1884 #define PCI_CR_DMA_PCI_ST_ADDR_REG (PCI_CR_PR_OFFSET + 0x00F4)
1885 #define PCI_CR_DMA_TRAN_CNT_REG (PCI_CR_PR_OFFSET + 0x00F8)
1886 #define PCI_CR_DMA_TRAN_CTL_REG (PCI_CR_PR_OFFSET + 0x00FC)
1888 /* PCI CONFIGURATION SPACE REGISTER Base Address */
1889 #define EXT_PCI1_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x0800
1890 #define EXT_PCI2_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x1000
1891 #define EXT_PCI3_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x1800
1892 #define EXT_PCI4_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x2000
1893 #define EXT_PCI5_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x2800
1894 #define EXT_PCI6_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x3000
1895 #define EXT_PCI7_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x3800
1896 #define EXT_PCI8_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x4000
1897 #define EXT_PCI9_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x4800
1898 #define EXT_PCI10_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x5000
1899 #define EXT_PCI11_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x5800
1900 #define EXT_PCI12_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x6000
1901 #define EXT_PCI13_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x6800
1902 #define EXT_PCI14_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x7000
1903 #define EXT_PCI15_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0x7800
1904 #define EXT_CARDBUS_CONFIG_SPACE_BASE_ADDR PCI_CFG_BASE + 0XF000
1906 /* PCI CONFIGURATION SPACE REGISTER ADDRESS MAP */
1907 #define PCI_CS_DEV_VEN_ID_REG (PCI_CS_PR_OFFSET + 0x0000)
1908 #define PCI_CS_STS_CMD_REG (PCI_CS_PR_OFFSET + 0x0004)
1909 #define PCI_CS_CL_CODE_REVIDG (PCI_CS_PR_OFFSET + 0x0008)
1910 #define PCI_CS_BST_HT_LT_CLS_REG (PCI_CS_PR_OFFSET + 0x000C)
1911 #define PCI_CS_BASE_ADDR1_REG (PCI_CS_PR_OFFSET + 0x0010)
1912 #define PCI_CS_BASE_ADDR2_REG (PCI_CS_PR_OFFSET + 0x0014)
1913 #define PCI_CS_BASE_ADDR3_REG (PCI_CS_PR_OFFSET + 0x0018)
1914 #define PCI_CS_BASE_ADDR4_REG (PCI_CS_PR_OFFSET + 0x001C)
1915 #define PCI_CS_BASE_ADDR5_REG (PCI_CS_PR_OFFSET + 0x0020)
1916 #define PCI_CS_BASE_ADDR6_REG (PCI_CS_PR_OFFSET + 0x0024)
1917 #define PCI_CS_CARDBUS_CIS_PT_REG (PCI_CS_PR_OFFSET + 0x0028)
1918 #define PCI_CS_SUBSYS_VEN_ID_REG (PCI_CS_PR_OFFSET + 0x002C)
1919 #define PCI_CS_EXROM_BAS_ADDR_REG (PCI_CS_PR_OFFSET + 0x0030)
1920 #define PCI_CS_RES1_REG (PCI_CS_PR_OFFSET + 0x0034)
1921 #define PCI_CS_RES2_REG (PCI_CS_PR_OFFSET + 0x0038)
1922 #define PCI_CS_LAT_GNT_INTR_REG (PCI_CS_PR_OFFSET + 0x003C)
1923 #define PCI_CS_PM_PT_CPID_REG (PCI_CS_PR_OFFSET + 0x0040)
1924 #define PCI_CS_DAT_PMCSR_PM_REG (PCI_CS_PR_OFFSET + 0x0044)
1925 #define PCI_CS_RES3_REG (PCI_CS_PR_OFFSET + 0x0048)
1926 #define PCI_CS_RES4_REG (PCI_CS_PR_OFFSET + 0x004C)
1927 #define PCI_CS_ERR_ADDR_PCI_FPI_REG (PCI_CS_PR_OFFSET + 0x0050)
1928 #define PCI_CS_ERR_ADDR_FPI_PCI_REG (PCI_CS_PR_OFFSET + 0x0054)
1929 #define PCI_CS_ERR_TAG_FPI_PCI_REG (PCI_CS_PR_OFFSET + 0x0058)
1930 #define PCI_CS_PC_ARB_REG (PCI_CS_PR_OFFSET + 0x005C)
1931 #define PCI_CS_FPI_PCI_INT_STS_REG (PCI_CS_PR_OFFSET + 0x0060)
1932 #define PCI_CS_FPI_PCI_INT_ACK_REG (PCI_CS_PR_OFFSET + 0x0064)
1933 #define PCI_CS_FPI_PCI_INT_MASK_REG (PCI_CS_PR_OFFSET + 0x0068)
1934 #define PCI_CS_CARDBUS_CTL_STS_REG (PCI_CS_PR_OFFSET + 0x006C)
1936 // PCI CONTROLLER ADDRESS SPACE
1937 #define PCI_CA_PR_OFFSET 0xB8000000
1938 #define PCI_CA_PR_END 0xBBFFFFFF
1940 // PCI CONTROLLER REGISTER ADDRESS MASK
1941 #define PCI_CR_CLK_CTRL_MSK 0x82000000
1942 #define PCI_CR_PCI_ID_MSK 0x00000000
1943 #define PCI_CR_SFT_RST_MSK 0x00000002
1944 #define PCI_CR_PCI_FPI_ERR_ADDR_MSK 0x00000000
1945 #define PCI_CR_FCI_PCI_ERR_ADDR_MSK 0x00000000
1946 #define PCI_CR_FPI_ERR_TAG_MSK 0x00000000
1947 #define PCI_CR_PCI_IRR_MSK 0x07013B2F
1948 #define PCI_CR_PCI_IRA_MSK 0x07013B2F
1949 #define PCI_CR_PCI_IRM_MSK 0x07013B2F
1950 #define PCI_CR_PCI_EOI_MSK 0x07013B2F
1951 #define PCI_CR_PCI_MOD_MSK 0x1107070F
1952 #define PCI_CR_DV_ID_MSK 0x00000000
1953 #define PCI_CR_SUBSYS_ID_MSK 0x00000000
1954 #define PCI_CR_PCI_PM_MSK 0x0000001F
1955 #define PCI_CR_CLASS_CODE1_MSK 0x00000000
1956 #define PCI_CR_BAR11MASK_MSK 0x8FFFFFF8
1957 #define PCI_CR_BAR12MASK_MSK 0x80001F08
1958 #define PCI_CR_BAR13MASK_MSK 0x8FF00008
1959 #define PCI_CR_BAR14MASK_MSK 0x8FFFFF08
1960 #define PCI_CR_BAR15MASK_MSK 0x8FFFFF08
1961 #define PCI_CR_BAR16MASK_MSK 0x8FFFFFF9
1962 #define PCI_CR_CIS_PT1_MSK 0x03FFFFFF
1963 #define PCI_CR_SUBSYS_ID1_MSK 0x00000000
1964 #define PCI_CR_PCI_ADDR_MAP11_MSK 0x7FFF0001
1965 #define PCI_CR_PCI_ADDR_MAP12_MSK 0x7FFFFF01
1966 #define PCI_CR_PCI_ADDR_MAP13_MSK 0x7FF00001
1967 #define PCI_CR_PCI_ADDR_MAP14_MSK 0x7FFFFF01
1968 #define PCI_CR_PCI_ADDR_MAP15_MSK 0x7FF00001
1969 #define PCI_CR_PCI_ADDR_MAP16_MSK 0x7FF00001
1970 #define PCI_CR_FPI_SEG_EN_MSK 0x000003FF
1971 #define PCI_CR_CLASS_CODE2_MSK 0x00000000
1972 #define PCI_CR_BAR21MASK_MSK 0x800F0008
1973 #define PCI_CR_BAR22MASK_MSK 0x807F0008
1974 #define PCI_CR_BAR23MASK_MSK 0x8FF00008
1975 #define PCI_CR_BAR24MASK_MSK 0x8FFFFF08
1976 #define PCI_CR_BAR25MASK_MSK 0x8FFFFF08
1977 #define PCI_CR_BAR26MASK_MSK 0x8FFFFFF9
1978 #define PCI_CR_CIS_PT2_MSK 0x03FFFFFF
1979 #define PCI_CR_SUBSYS_ID2_MSK 0x00000000
1980 #define PCI_CR_PCI_ADDR_MAP21_MSK 0x7FFE0001
1981 #define PCI_CR_PCI_ADDR_MAP22_MSK 0x7FFF0001
1982 #define PCI_CR_PCI_ADDR_MAP23_MSK 0x7FF00001
1983 #define PCI_CR_PCI_ADDR_MAP24_MSK 0x7FFFFF01
1984 #define PCI_CR_PCI_ADDR_MAP25_MSK 0x7FFFFF01
1985 #define PCI_CR_PCI_ADDR_MAP26_MSK 0x7FF00001
1986 #define PCI_CR_FPI_ADDR_MASK_MSK 0x00070000
1987 #define PCI_CR_FCI_ADDR_MAP0_MSK 0xFFF00000
1988 #define PCI_CR_FCI_ADDR_MAP1_MSK 0xFFF00000
1989 #define PCI_CR_FCI_ADDR_MAP2_MSK 0xFFF00000
1990 #define PCI_CR_FCI_ADDR_MAP3_MSK 0xFFF00000
1991 #define PCI_CR_FCI_ADDR_MAP4_MSK 0xFFF00000
1992 #define PCI_CR_FCI_ADDR_MAP5_MSK 0xFFF00000
1993 #define PCI_CR_FCI_ADDR_MAP6_MSK 0xFFF00000
1994 #define PCI_CR_FCI_ADDR_MAP7_MSK 0xFFF00000
1995 #define PCI_CR_FCI_ADDR_MAP11lo_MSK 0xFFFF0000
1996 #define PCI_CR_FCI_ADDR_MAP11hg_MSK 0xFFF00000
1997 #define PCI_CR_FCI_BURST_LENGTH_MSK 0x00000303
1998 #define PCI_CR_PCI_SET_SERR_MSK 0x00000001
1999 #define PCI_CR_DMA_FPI_ST_ADDR_MSK 0xFFFFFFFF
2000 #define PCI_CR_DMA_PCI_ST_ADDR_MSK 0xFFFFFFFF
2001 #define PCI_CR_DMA_TRAN_CNT_MSK 0x000003FF
2002 #define PCI_CR_DMA_TRAN_CTL_MSK 0x00000003
2004 #define INTERNAL_ARB_ENABLE_BIT 0
2005 #define ARB_SCHEME_BIT 1
2006 #define PCI_MASTER0_PRIOR_2BITS 2
2007 #define PCI_MASTER1_PRIOR_2BITS 4
2008 #define PCI_MASTER2_PRIOR_2BITS 6
2009 #define PCI_MASTER0_REQ_MASK_2BITS 8
2010 #define PCI_MASTER1_REQ_MASK_2BITS 10
2011 #define PCI_MASTER2_REQ_MASK_2BITS 12
2013 #define IOPORT_RESOURCE_START 0x10000000
2014 #define IOPORT_RESOURCE_END 0xffffffff
2015 #define IOMEM_RESOURCE_START 0x10000000
2016 #define IOMEM_RESOURCE_END 0xffffffff
2018 /***********************************************************************/
2019 #define DANUBE_REG32(addr) *((volatile u32 *)(addr))
2020 /***********************************************************************/
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