target/linux/ipq806x/patches/0021-ARM-dts-qcom-Add-nodes-necessary-for-SMP-boot.patch

   1 From 5a054211d9380cef5a09da7c5e815c827f330a96 Mon Sep 17 00:00:00 2001
   2 From: Rohit Vaswani <rvaswani@codeaurora.org>
   3 Date: Fri, 1 Nov 2013 10:10:40 -0700
   4 Subject: [PATCH 021/182] ARM: dts: qcom: Add nodes necessary for SMP boot
   5
   6 Add the necessary nodes to support SMP on MSM8660, MSM8960, and
   7 MSM8974/APQ8074. While we're here also add in the error
   8 interrupts for the Krait cache error detection.
   9
  10 Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
  11 [sboyd: Split into separate patch, add error interrupts]
  12 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  13 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  14 ---
  15  arch/arm/boot/dts/qcom-msm8660.dtsi |   24 ++++++++++++
  16  arch/arm/boot/dts/qcom-msm8960.dtsi |   52 ++++++++++++++++++++++++++
  17  arch/arm/boot/dts/qcom-msm8974.dtsi |   69 +++++++++++++++++++++++++++++++++++
  18  3 files changed, 145 insertions(+)
  19
  20 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi
  21 +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
  22 @@ -9,6 +9,30 @@
  23         compatible = "qcom,msm8660";
  24         interrupt-parent = <&intc>;
  25
  26 +       cpus {
  27 +               #address-cells = <1>;
  28 +               #size-cells = <0>;
  29 +               compatible = "qcom,scorpion";
  30 +               enable-method = "qcom,gcc-msm8660";
  31 +
  32 +               cpu@0 {
  33 +                       device_type = "cpu";
  34 +                       reg = <0>;
  35 +                       next-level-cache = <&L2>;
  36 +               };
  37 +
  38 +               cpu@1 {
  39 +                       device_type = "cpu";
  40 +                       reg = <1>;
  41 +                       next-level-cache = <&L2>;
  42 +               };
  43 +
  44 +               L2: l2-cache {
  45 +                       compatible = "cache";
  46 +                       cache-level = <2>;
  47 +               };
  48 +       };
  49 +
  50         intc: interrupt-controller@2080000 {
  51                 compatible = "qcom,msm-8660-qgic";
  52                 interrupt-controller;
  53 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi
  54 +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
  55 @@ -9,6 +9,36 @@
  56         compatible = "qcom,msm8960";
  57         interrupt-parent = <&intc>;
  58
  59 +       cpus {
  60 +               #address-cells = <1>;
  61 +               #size-cells = <0>;
  62 +               interrupts = <1 14 0x304>;
  63 +               compatible = "qcom,krait";
  64 +               enable-method = "qcom,kpss-acc-v1";
  65 +
  66 +               cpu@0 {
  67 +                       device_type = "cpu";
  68 +                       reg = <0>;
  69 +                       next-level-cache = <&L2>;
  70 +                       qcom,acc = <&acc0>;
  71 +                       qcom,saw = <&saw0>;
  72 +               };
  73 +
  74 +               cpu@1 {
  75 +                       device_type = "cpu";
  76 +                       reg = <1>;
  77 +                       next-level-cache = <&L2>;
  78 +                       qcom,acc = <&acc1>;
  79 +                       qcom,saw = <&saw1>;
  80 +               };
  81 +
  82 +               L2: l2-cache {
  83 +                       compatible = "cache";
  84 +                       cache-level = <2>;
  85 +                       interrupts = <0 2 0x4>;
  86 +               };
  87 +       };
  88 +
  89         intc: interrupt-controller@2000000 {
  90                 compatible = "qcom,msm-qgic2";
  91                 interrupt-controller;
  92 @@ -53,6 +83,28 @@
  93                 #reset-cells = <1>;
  94         };
  95
  96 +       acc0: clock-controller@2088000 {
  97 +               compatible = "qcom,kpss-acc-v1";
  98 +               reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
  99 +       };
 100 +
 101 +       acc1: clock-controller@2098000 {
 102 +               compatible = "qcom,kpss-acc-v1";
 103 +               reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 104 +       };
 105 +
 106 +       saw0: regulator@2089000 {
 107 +               compatible = "qcom,saw2";
 108 +               reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 109 +               regulator;
 110 +       };
 111 +
 112 +       saw1: regulator@2099000 {
 113 +               compatible = "qcom,saw2";
 114 +               reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 115 +               regulator;
 116 +       };
 117 +
 118         serial@16440000 {
 119                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 120                 reg = <0x16440000 0x1000>,
 121 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
 122 +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
 123 @@ -9,6 +9,49 @@
 124         compatible = "qcom,msm8974";
 125         interrupt-parent = <&intc>;
 126
 127 +       cpus {
 128 +               #address-cells = <1>;
 129 +               #size-cells = <0>;
 130 +               interrupts = <1 9 0xf04>;
 131 +               compatible = "qcom,krait";
 132 +               enable-method = "qcom,kpss-acc-v2";
 133 +
 134 +               cpu@0 {
 135 +                       device_type = "cpu";
 136 +                       reg = <0>;
 137 +                       next-level-cache = <&L2>;
 138 +                       qcom,acc = <&acc0>;
 139 +               };
 140 +
 141 +               cpu@1 {
 142 +                       device_type = "cpu";
 143 +                       reg = <1>;
 144 +                       next-level-cache = <&L2>;
 145 +                       qcom,acc = <&acc1>;
 146 +               };
 147 +
 148 +               cpu@2 {
 149 +                       device_type = "cpu";
 150 +                       reg = <2>;
 151 +                       next-level-cache = <&L2>;
 152 +                       qcom,acc = <&acc2>;
 153 +               };
 154 +
 155 +               cpu@3 {
 156 +                       device_type = "cpu";
 157 +                       reg = <3>;
 158 +                       next-level-cache = <&L2>;
 159 +                       qcom,acc = <&acc3>;
 160 +               };
 161 +
 162 +               L2: l2-cache {
 163 +                       compatible = "cache";
 164 +                       cache-level = <2>;
 165 +                       interrupts = <0 2 0x4>;
 166 +                       qcom,saw = <&saw_l2>;
 167 +               };
 168 +       };
 169 +
 170         soc: soc {
 171                 #address-cells = <1>;
 172                 #size-cells = <1>;
 173 @@ -91,6 +134,32 @@
 174                         };
 175                 };
 176
 177 +               saw_l2: regulator@f9012000 {
 178 +                       compatible = "qcom,saw2";
 179 +                       reg = <0xf9012000 0x1000>;
 180 +                       regulator;
 181 +               };
 182 +
 183 +               acc0: clock-controller@f9088000 {
 184 +                       compatible = "qcom,kpss-acc-v2";
 185 +                       reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 186 +               };
 187 +
 188 +               acc1: clock-controller@f9098000 {
 189 +                       compatible = "qcom,kpss-acc-v2";
 190 +                       reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 191 +               };
 192 +
 193 +               acc2: clock-controller@f90a8000 {
 194 +                       compatible = "qcom,kpss-acc-v2";
 195 +                       reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 196 +               };
 197 +
 198 +               acc3: clock-controller@f90b8000 {
 199 +                       compatible = "qcom,kpss-acc-v2";
 200 +                       reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 201 +               };
 202 +
 203                 restart@fc4ab000 {
 204                         compatible = "qcom,pshold";
 205                         reg = <0xfc4ab000 0x4>;