target/linux/ipq806x/patches/0156-usb-dwc3-Add-Qualcomm-DWC3-glue-layer-driver.patch

   1 From 364532aeb9024d0ff7b88121f9a953f559b1c136 Mon Sep 17 00:00:00 2001
   2 From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
   3 Date: Mon, 7 Oct 2013 10:44:57 +0300
   4 Subject: [PATCH 156/182] usb: dwc3: Add Qualcomm DWC3 glue layer driver
   5
   6 DWC3 glue layer is hardware layer around Synopsys DesignWare
   7 USB3 core. Its purpose is to supply Synopsys IP with required
   8 clocks, voltages and interface it with the rest of the SoC.
   9
  10 Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
  11 ---
  12  drivers/usb/dwc3/Kconfig     |    8 +++
  13  drivers/usb/dwc3/Makefile    |    1 +
  14  drivers/usb/dwc3/dwc3-qcom.c |  156 ++++++++++++++++++++++++++++++++++++++++++
  15  3 files changed, 165 insertions(+)
  16  create mode 100644 drivers/usb/dwc3/dwc3-qcom.c
  17
  18 --- a/drivers/usb/dwc3/Kconfig
  19 +++ b/drivers/usb/dwc3/Kconfig
  20 @@ -59,6 +59,14 @@ config USB_DWC3_EXYNOS
  21           Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside,
  22           say 'Y' or 'M' if you have one such device.
  23
  24 +config USB_DWC3_QCOM
  25 +       tristate "Qualcomm Platforms"
  26 +       default USB_DWC3
  27 +       select USB_QCOM_DWC3_PHYS
  28 +       help
  29 +         Recent Qualcomm SoCs ship with one DesignWare Core USB3 IP inside,
  30 +         say 'Y' or 'M' if you have one such device.
  31 +
  32  config USB_DWC3_PCI
  33         tristate "PCIe-based Platforms"
  34         depends on PCI
  35 --- a/drivers/usb/dwc3/Makefile
  36 +++ b/drivers/usb/dwc3/Makefile
  37 @@ -31,5 +31,6 @@ endif
  38
  39  obj-$(CONFIG_USB_DWC3_OMAP)            += dwc3-omap.o
  40  obj-$(CONFIG_USB_DWC3_EXYNOS)          += dwc3-exynos.o
  41 +obj-$(CONFIG_USB_DWC3_QCOM)            += dwc3-qcom.o
  42  obj-$(CONFIG_USB_DWC3_PCI)             += dwc3-pci.o
  43  obj-$(CONFIG_USB_DWC3_KEYSTONE)                += dwc3-keystone.o
  44 --- /dev/null
  45 +++ b/drivers/usb/dwc3/dwc3-qcom.c
  46 @@ -0,0 +1,156 @@
  47 +/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
  48 + *
  49 + * This program is free software; you can redistribute it and/or modify
  50 + * it under the terms of the GNU General Public License version 2 and
  51 + * only version 2 as published by the Free Software Foundation.
  52 + *
  53 + * This program is distributed in the hope that it will be useful,
  54 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  55 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  56 + * GNU General Public License for more details.
  57 + */
  58 +
  59 +#include <linux/clk.h>
  60 +#include <linux/err.h>
  61 +#include <linux/io.h>
  62 +#include <linux/module.h>
  63 +#include <linux/of.h>
  64 +#include <linux/of_platform.h>
  65 +#include <linux/platform_device.h>
  66 +#include <linux/regulator/consumer.h>
  67 +#include <linux/usb/phy.h>
  68 +
  69 +#include "core.h"
  70 +
  71 +
  72 +struct dwc3_qcom {
  73 +       struct device           *dev;
  74 +
  75 +       struct clk              *core_clk;
  76 +       struct clk              *iface_clk;
  77 +       struct clk              *sleep_clk;
  78 +
  79 +       struct regulator        *gdsc;
  80 +};
  81 +
  82 +static int dwc3_qcom_probe(struct platform_device *pdev)
  83 +{
  84 +       struct device_node *node = pdev->dev.of_node;
  85 +       struct dwc3_qcom *mdwc;
  86 +       int ret = 0;
  87 +
  88 +       mdwc = devm_kzalloc(&pdev->dev, sizeof(*mdwc), GFP_KERNEL);
  89 +       if (!mdwc)
  90 +               return -ENOMEM;
  91 +
  92 +       platform_set_drvdata(pdev, mdwc);
  93 +
  94 +       mdwc->dev = &pdev->dev;
  95 +
  96 +       mdwc->gdsc = devm_regulator_get(mdwc->dev, "gdsc");
  97 +
  98 +       mdwc->core_clk = devm_clk_get(mdwc->dev, "core");
  99 +       if (IS_ERR(mdwc->core_clk)) {
 100 +               dev_dbg(mdwc->dev, "failed to get core clock\n");
 101 +               return PTR_ERR(mdwc->core_clk);
 102 +       }
 103 +
 104 +       mdwc->iface_clk = devm_clk_get(mdwc->dev, "iface");
 105 +       if (IS_ERR(mdwc->iface_clk)) {
 106 +               dev_dbg(mdwc->dev, "failed to get iface clock, skipping\n");
 107 +               mdwc->iface_clk = NULL;
 108 +       }
 109 +
 110 +       mdwc->sleep_clk = devm_clk_get(mdwc->dev, "sleep");
 111 +       if (IS_ERR(mdwc->sleep_clk)) {
 112 +               dev_dbg(mdwc->dev, "failed to get sleep clock, skipping\n");
 113 +               mdwc->sleep_clk = NULL;
 114 +       }
 115 +
 116 +       if (!IS_ERR(mdwc->gdsc)) {
 117 +               ret = regulator_enable(mdwc->gdsc);
 118 +               if (ret)
 119 +                       dev_err(mdwc->dev, "cannot enable gdsc\n");
 120 +       }
 121 +
 122 +       clk_prepare_enable(mdwc->core_clk);
 123 +
 124 +       if (mdwc->iface_clk)
 125 +               clk_prepare_enable(mdwc->iface_clk);
 126 +
 127 +       if (mdwc->sleep_clk)
 128 +               clk_prepare_enable(mdwc->sleep_clk);
 129 +
 130 +       ret = of_platform_populate(node, NULL, NULL, mdwc->dev);
 131 +       if (ret) {
 132 +               dev_err(mdwc->dev, "failed to register core - %d\n", ret);
 133 +               dev_dbg(mdwc->dev, "failed to add create dwc3 core\n");
 134 +               goto dis_clks;
 135 +       }
 136 +
 137 +       return 0;
 138 +
 139 +dis_clks:
 140 +
 141 +       dev_err(mdwc->dev, "disabling clocks\n");
 142 +
 143 +       if (mdwc->sleep_clk)
 144 +               clk_disable_unprepare(mdwc->sleep_clk);
 145 +
 146 +       if (mdwc->iface_clk)
 147 +               clk_disable_unprepare(mdwc->iface_clk);
 148 +
 149 +       clk_disable_unprepare(mdwc->core_clk);
 150 +
 151 +       if (!IS_ERR(mdwc->gdsc)) {
 152 +               ret = regulator_disable(mdwc->gdsc);
 153 +               if (ret)
 154 +                       dev_dbg(mdwc->dev, "cannot disable gdsc\n");
 155 +       }
 156 +
 157 +       return ret;
 158 +}
 159 +
 160 +static int dwc3_qcom_remove(struct platform_device *pdev)
 161 +{
 162 +       int ret = 0;
 163 +
 164 +       struct dwc3_qcom *mdwc = platform_get_drvdata(pdev);
 165 +
 166 +       if (mdwc->sleep_clk)
 167 +               clk_disable_unprepare(mdwc->sleep_clk);
 168 +
 169 +       if (mdwc->iface_clk)
 170 +               clk_disable_unprepare(mdwc->iface_clk);
 171 +
 172 +       clk_disable_unprepare(mdwc->core_clk);
 173 +
 174 +       if (!IS_ERR(mdwc->gdsc)) {
 175 +               ret = regulator_disable(mdwc->gdsc);
 176 +               if (ret)
 177 +                       dev_dbg(mdwc->dev, "cannot disable gdsc\n");
 178 +       }
 179 +       return ret;
 180 +}
 181 +
 182 +static const struct of_device_id of_dwc3_match[] = {
 183 +       { .compatible = "qcom,dwc3" },
 184 +       { /* Sentinel */ }
 185 +};
 186 +MODULE_DEVICE_TABLE(of, of_dwc3_match);
 187 +
 188 +static struct platform_driver dwc3_qcom_driver = {
 189 +       .probe          = dwc3_qcom_probe,
 190 +       .remove         = dwc3_qcom_remove,
 191 +       .driver         = {
 192 +               .name   = "qcom-dwc3",
 193 +               .owner  = THIS_MODULE,
 194 +               .of_match_table = of_dwc3_match,
 195 +       },
 196 +};
 197 +
 198 +module_platform_driver(dwc3_qcom_driver);
 199 +
 200 +MODULE_ALIAS("platform:qcom-dwc3");
 201 +MODULE_LICENSE("GPL v2");
 202 +MODULE_DESCRIPTION("DesignWare USB3 QCOM Glue Layer");