target/linux/lantiq/files-3.3/arch/mips/lantiq/xway/pci-ath-fixup.c

   1 /*
   2  *  Atheros AP94 reference board PCI initialization
   3  *
   4  *  Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License version 2 as published
   8  *  by the Free Software Foundation.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/init.h>
  13 #include <linux/delay.h>
  14 #include <lantiq_soc.h>
  15
  16 #define LTQ_PCI_MEM_BASE                0x18000000
  17
  18 struct ath_fixup {
  19         u16             *cal_data;
  20         unsigned        slot;
  21 };
  22
  23 static int ath_num_fixups;
  24 static struct ath_fixup ath_fixups[2];
  25
  26 static void ath_pci_fixup(struct pci_dev *dev)
  27 {
  28         void __iomem *mem;
  29         u16 *cal_data = NULL;
  30         u16 cmd;
  31         u32 bar0;
  32         u32 val;
  33         unsigned i;
  34
  35         for (i = 0; i < ath_num_fixups; i++) {
  36                 if (ath_fixups[i].cal_data == NULL)
  37                         continue;
  38
  39                 if (ath_fixups[i].slot != PCI_SLOT(dev->devfn))
  40                         continue;
  41
  42                 cal_data = ath_fixups[i].cal_data;
  43                 break;
  44         }
  45
  46         if (cal_data == NULL)
  47                 return;
  48
  49         if (*cal_data != 0xa55a) {
  50                 pr_err("pci %s: invalid calibration data\n", pci_name(dev));
  51                 return;
  52         }
  53
  54         pr_info("pci %s: fixup device configuration\n", pci_name(dev));
  55
  56         mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000);
  57         if (!mem) {
  58                 pr_err("pci %s: ioremap error\n", pci_name(dev));
  59                 return;
  60         }
  61
  62         pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
  63         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE);
  64         pci_read_config_word(dev, PCI_COMMAND, &cmd);
  65         cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  66         pci_write_config_word(dev, PCI_COMMAND, cmd);
  67
  68         /* set pointer to first reg address */
  69         cal_data += 3;
  70         while (*cal_data != 0xffff) {
  71                 u32 reg;
  72                 reg = *cal_data++;
  73                 val = *cal_data++;
  74                 val |= (*cal_data++) << 16;
  75
  76                 ltq_w32(swab32(val), mem + reg);
  77                 udelay(100);
  78         }
  79
  80         pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
  81         dev->vendor = val & 0xffff;
  82         dev->device = (val >> 16) & 0xffff;
  83
  84         pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
  85         dev->revision = val & 0xff;
  86         dev->class = val >> 8; /* upper 3 bytes */
  87
  88         pr_info("pci %s: fixup info: [%04x:%04x] revision %02x class %#08x\n",
  89                 pci_name(dev), dev->vendor, dev->device, dev->revision, dev->class);
  90
  91         pci_read_config_word(dev, PCI_COMMAND, &cmd);
  92         cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
  93         pci_write_config_word(dev, PCI_COMMAND, cmd);
  94
  95         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
  96
  97         iounmap(mem);
  98 }
  99 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath_pci_fixup);
 100
 101 void __init ltq_pci_ath_fixup(unsigned slot, u16 *cal_data)
 102 {
 103         if (ath_num_fixups >= ARRAY_SIZE(ath_fixups))
 104                 return;
 105
 106         ath_fixups[ath_num_fixups].slot = slot;
 107         ath_fixups[ath_num_fixups].cal_data = cal_data;
 108         ath_num_fixups++;
 109 }