target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h

   1 /************************************************************************
   2  *
   3  * Copyright (c) 2007
   4  * Infineon Technologies AG
   5  * St. Martin Strasse 53; 81669 Muenchen; Germany
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version
  10  * 2 of the License, or (at your option) any later version.
  11  *
  12  ************************************************************************/
  13
  14 #ifndef __SVIP_DMA_H
  15 #define __SVIP_DMA_H
  16
  17 #define LTQ_DMA_CH_ON  1
  18 #define LTQ_DMA_CH_OFF 0
  19 #define LTQ_DMA_CH_DEFAULT_WEIGHT 100;
  20
  21 #define DMA_OWN   1
  22 #define CPU_OWN   0
  23 #define DMA_MAJOR 250
  24
  25 /* Descriptors */
  26 #define DMA_DESC_OWN_CPU                0x0
  27 #define DMA_DESC_OWN_DMA                0x80000000
  28 #define DMA_DESC_CPT_SET                0x40000000
  29 #define DMA_DESC_SOP_SET                0x20000000
  30 #define DMA_DESC_EOP_SET                0x10000000
  31
  32 struct rx_desc {
  33         union {
  34                 struct {
  35 #ifdef CONFIG_CPU_LITTLE_ENDIAN
  36                         volatile u32 data_length:16;
  37                         volatile u32 reserve2:7;
  38                         volatile u32 byte_offset:2;
  39                         volatile u32 reserve1:3;
  40                         volatile u32 eop:1;
  41                         volatile u32 sop:1;
  42                         volatile u32 c:1;
  43                         volatile u32 own:1;
  44 #else
  45                         volatile u32 own:1;
  46                         volatile u32 c:1;
  47                         volatile u32 sop:1;
  48                         volatile u32 eop:1;
  49                         volatile u32 reserve1:3;
  50                         volatile u32 byte_offset:2;
  51                         volatile u32 reserve2:7;
  52                         volatile u32 data_length:16;
  53 #endif
  54                 } field;
  55
  56                 volatile u32 word;
  57         } status;
  58
  59         volatile u32 data_pointer;
  60 };
  61
  62 struct tx_desc {
  63         union {
  64                 struct {
  65 #ifdef CONFIG_CPU_LITTLE_ENDIAN
  66                         volatile u32 data_length:16;
  67                         volatile u32 reserved:7;
  68                         volatile u32 byte_offset:5;
  69                         volatile u32 eop:1;
  70                         volatile u32 sop:1;
  71                         volatile u32 c:1;
  72                         volatile u32 own:1;
  73 #else
  74                         volatile u32 own:1;
  75                         volatile u32 c:1;
  76                         volatile u32 sop:1;
  77                         volatile u32 eop:1;
  78                         volatile u32 byte_offset:5;
  79                         volatile u32 reserved:7;
  80                         volatile u32 data_length:16;
  81 #endif
  82                 } field;
  83
  84                 volatile u32 word;
  85         } status;
  86
  87         volatile u32 data_pointer;
  88 };
  89
  90 /* DMA pseudo interrupts notified to switch driver */
  91 #define RCV_INT          0x01
  92 #define TX_BUF_FULL_INT  0x02
  93 #define TRANSMIT_CPT_INT 0x04
  94 #define CHANNEL_CLOSED   0x10
  95
  96 /* Parameters for switch DMA device */
  97 #define DEFAULT_SW_CHANNEL_WEIGHT 3
  98 #define DEFAULT_SW_PORT_WEIGHT    7
  99
 100 #define DEFAULT_SW_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
 101 #define DEFAULT_SW_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
 102
 103 #define DEFAULT_SW_TX_CHANNEL_NUM 4
 104 #define DEFAULT_SW_RX_CHANNEL_NUM 4
 105
 106 #define DEFAULT_SW_TX_CHANNEL_DESCR_NUM 20
 107 #define DEFAULT_SW_RX_CHANNEL_DESCR_NUM 20
 108
 109 /* Parameters for SSC DMA device */
 110 #define DEFAULT_SSC_CHANNEL_WEIGHT 3
 111 #define DEFAULT_SSC_PORT_WEIGHT    7
 112
 113 #define DEFAULT_SSC_TX_CHANNEL_CLASS 3
 114 #define DEFAULT_SSC_RX_CHANNEL_CLASS 0
 115
 116 #define DEFAULT_SSC_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
 117 #define DEFAULT_SSC_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
 118
 119 #define DEFAULT_SSC0_TX_CHANNEL_NUM 1
 120 #define DEFAULT_SSC0_RX_CHANNEL_NUM 1
 121 #define DEFAULT_SSC1_TX_CHANNEL_NUM 1
 122 #define DEFAULT_SSC1_RX_CHANNEL_NUM 1
 123
 124 #define DEFAULT_SSC_TX_CHANNEL_DESCR_NUM 10
 125 #define DEFAULT_SSC_RX_CHANNEL_DESCR_NUM 10
 126
 127 /* Parameters for memory DMA device */
 128 #define DEFAULT_MEM_CHANNEL_WEIGHT 3
 129 #define DEFAULT_MEM_PORT_WEIGHT    7
 130
 131 #define DEFAULT_MEM_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
 132 #define DEFAULT_MEM_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
 133
 134 #define DEFAULT_MEM_TX_CHANNEL_NUM 1
 135 #define DEFAULT_MEM_RX_CHANNEL_NUM 1
 136
 137 #define DEFAULT_MEM_TX_CHANNEL_DESCR_NUM 2
 138 #define DEFAULT_MEM_RX_CHANNEL_DESCR_NUM 2
 139
 140 /* Parameters for DEU DMA device */
 141 #define DEFAULT_DEU_CHANNEL_WEIGHT 1
 142 #define DEFAULT_DEU_PORT_WEIGHT    1
 143
 144 #define DEFAULT_DEU_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
 145 #define DEFAULT_DEU_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
 146
 147 #define DEFAULT_DEU_TX_CHANNEL_DESCR_NUM 20
 148 #define DEFAULT_DEU_RX_CHANNEL_DESCR_NUM 20
 149
 150 #define DMA_DESCR_NUM     30 /* number of descriptors per channel */
 151
 152 enum dma_dir_t {
 153         DIR_RX = 0,
 154         DIR_TX = 1,
 155 };
 156
 157 struct dma_device_info;
 158
 159 struct dma_channel_info {
 160         /*Pointer to the peripheral device who is using this channel*/
 161         /*const*/ struct dma_device_info *dma_dev;
 162         /*direction*/
 163         const enum dma_dir_t dir; /*RX or TX*/
 164         /*class for this channel for QoS*/
 165         int pri;
 166         /*irq number*/
 167         const int irq;
 168         /*relative channel number*/
 169         const int rel_chan_no;
 170         /*absolute channel number*/
 171         int abs_chan_no;
 172
 173         /*specify byte_offset*/
 174         int byte_offset;
 175         int tx_weight;
 176
 177         /*descriptor parameter*/
 178         int desc_base;
 179         int desc_len;
 180         int curr_desc;
 181         int prev_desc;/*only used if it is a tx channel*/
 182
 183         /*weight setting for WFQ algorithm*/
 184         int weight;
 185         int default_weight;
 186
 187         int packet_size;
 188
 189         /*status of this channel*/
 190         int control; /*on or off*/
 191         int xfer_cnt;
 192         int dur; /*descriptor underrun*/
 193
 194         /**optional information for the upper layer devices*/
 195         void *opt[DMA_DESCR_NUM];
 196
 197         /*channel operations*/
 198         int (*open)(struct dma_channel_info *ch);
 199         int (*close)(struct dma_channel_info *ch);
 200         int (*reset)(struct dma_channel_info *ch);
 201         void (*enable_irq)(struct dma_channel_info *ch);
 202         void (*disable_irq)(struct dma_channel_info *ch);
 203 };
 204
 205
 206 struct dma_device_info {
 207         /*device name of this peripheral*/
 208         const char device_name[16];
 209         const int  max_rx_chan_num;
 210         const int  max_tx_chan_num;
 211         int drop_enable;
 212
 213         int reserved;
 214
 215         int tx_burst_len;
 216         int rx_burst_len;
 217         int tx_weight;
 218
 219         int  current_tx_chan;
 220         int  current_rx_chan;
 221         int  num_tx_chan;
 222         int  num_rx_chan;
 223         int  tx_endianness_mode;
 224         int  rx_endianness_mode;
 225         struct dma_channel_info *tx_chan[4];
 226         struct dma_channel_info *rx_chan[4];
 227
 228         /*functions, optional*/
 229         u8 *(*buffer_alloc)(int len,int *offset, void **opt);
 230         void (*buffer_free)(u8 *dataptr, void *opt);
 231         int (*intr_handler)(struct dma_device_info *dma_dev, int status);
 232
 233         /* used by peripheral driver only */
 234         void *priv;
 235 };
 236
 237 struct dma_device_info *dma_device_reserve(char *dev_name);
 238 int dma_device_release(struct dma_device_info *dma_dev);
 239 int dma_device_register(struct dma_device_info *dma_dev);
 240 int dma_device_unregister(struct dma_device_info *dma_dev);
 241 int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt);
 242 int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr,
 243                      int len, void *opt);
 244
 245 #endif