target/linux/lantiq/files/arch/mips/lantiq/falcon/gpio.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  *  Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
   7  *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
   8  */
   9
  10 #include <linux/gpio.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/slab.h>
  13 #include <linux/export.h>
  14 #include <linux/err.h>
  15 #include <linux/platform_device.h>
  16
  17 #include <lantiq_soc.h>
  18
  19 /* Multiplexer Control Register */
  20 #define LTQ_PADC_MUX(x)         (x * 0x4)
  21 /* Pad Control Availability Register */
  22 #define LTQ_PADC_AVAIL          0x000000F0
  23
  24 /* Data Output Register */
  25 #define LTQ_GPIO_OUT            0x00000000
  26 /* Data Input Register */
  27 #define LTQ_GPIO_IN             0x00000004
  28 /* Direction Register */
  29 #define LTQ_GPIO_DIR            0x00000008
  30 /* External Interrupt Control Register 0 */
  31 #define LTQ_GPIO_EXINTCR0       0x00000018
  32 /* External Interrupt Control Register 1 */
  33 #define LTQ_GPIO_EXINTCR1       0x0000001C
  34 /* IRN Capture Register */
  35 #define LTQ_GPIO_IRNCR          0x00000020
  36 /* IRN Interrupt Configuration Register */
  37 #define LTQ_GPIO_IRNCFG         0x0000002C
  38 /* IRN Interrupt Enable Set Register */
  39 #define LTQ_GPIO_IRNRNSET       0x00000030
  40 /* IRN Interrupt Enable Clear Register */
  41 #define LTQ_GPIO_IRNENCLR       0x00000034
  42 /* Output Set Register */
  43 #define LTQ_GPIO_OUTSET         0x00000040
  44 /* Output Cler Register */
  45 #define LTQ_GPIO_OUTCLR         0x00000044
  46 /* Direction Clear Register */
  47 #define LTQ_GPIO_DIRSET         0x00000048
  48 /* Direction Set Register */
  49 #define LTQ_GPIO_DIRCLR         0x0000004C
  50
  51 /* turn a gpio_chip into a falcon_gpio_port */
  52 #define ctop(c)         container_of(c, struct falcon_gpio_port, gpio_chip)
  53 /* turn a irq_data into a falcon_gpio_port */
  54 #define itop(i)         ((struct falcon_gpio_port *) irq_get_chip_data(i->irq))
  55
  56 #define ltq_pad_r32(p, reg)             ltq_r32(p->pad + reg)
  57 #define ltq_pad_w32(p, val, reg)        ltq_w32(val, p->pad + reg)
  58 #define ltq_pad_w32_mask(c, clear, set, reg) \
  59                 ltq_pad_w32(c, (ltq_pad_r32(c, reg) & ~(clear)) | (set), reg)
  60
  61 #define ltq_port_r32(p, reg)            ltq_r32(p->port + reg)
  62 #define ltq_port_w32(p, val, reg)       ltq_w32(val, p->port + reg)
  63 #define ltq_port_w32_mask(p, clear, set, reg) \
  64                 ltq_port_w32(p, (ltq_port_r32(p, reg) & ~(clear)) | (set), reg)
  65
  66 #define MAX_PORTS               5
  67 #define PINS_PER_PORT           32
  68
  69 struct falcon_gpio_port {
  70         struct gpio_chip gpio_chip;
  71         void __iomem *pad;
  72         void __iomem *port;
  73         unsigned int irq_base;
  74         unsigned int chained_irq;
  75         struct clk *clk;
  76 };
  77
  78 static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS];
  79
  80 int gpio_to_irq(unsigned int gpio)
  81 {
  82         return __gpio_to_irq(gpio);
  83 }
  84 EXPORT_SYMBOL(gpio_to_irq);
  85
  86 int ltq_gpio_mux_set(unsigned int pin, unsigned int mux)
  87 {
  88         int port = pin / 100;
  89         int offset = pin % 100;
  90         struct falcon_gpio_port *gpio_port;
  91
  92         if ((offset >= PINS_PER_PORT) || (port >= MAX_PORTS))
  93                 return -EINVAL;
  94
  95         gpio_port = &ltq_gpio_port[port];
  96         ltq_pad_w32(gpio_port, mux & 0x3, LTQ_PADC_MUX(offset));
  97
  98         return 0;
  99 }
 100 EXPORT_SYMBOL(ltq_gpio_mux_set);
 101
 102 int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux,
 103                         unsigned int dir, const char *name)
 104 {
 105         int port = pin / 100;
 106         int offset = pin % 100;
 107
 108         if (offset >= PINS_PER_PORT || port >= MAX_PORTS)
 109                 return -EINVAL;
 110
 111         if (devm_gpio_request(dev, pin, name)) {
 112                 pr_err("failed to setup lantiq gpio: %s\n", name);
 113                 return -EBUSY;
 114         }
 115
 116         if (dir)
 117                 gpio_direction_output(pin, 1);
 118         else
 119                 gpio_direction_input(pin);
 120
 121         return ltq_gpio_mux_set(pin, mux);
 122 }
 123 EXPORT_SYMBOL(ltq_gpio_request);
 124
 125 static int
 126 falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 127 {
 128         ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRCLR);
 129
 130         return 0;
 131 }
 132
 133 static void
 134 falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
 135 {
 136         if (value)
 137                 ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTSET);
 138         else
 139                 ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTCLR);
 140 }
 141
 142 static int
 143 falcon_gpio_direction_output(struct gpio_chip *chip,
 144                         unsigned int offset, int value)
 145 {
 146         falcon_gpio_set(chip, offset, value);
 147         ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRSET);
 148
 149         return 0;
 150 }
 151
 152 static int
 153 falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
 154 {
 155         if ((ltq_port_r32(ctop(chip), LTQ_GPIO_DIR) >> offset) & 1)
 156                 return (ltq_port_r32(ctop(chip), LTQ_GPIO_OUT) >> offset) & 1;
 157         else
 158                 return (ltq_port_r32(ctop(chip), LTQ_GPIO_IN) >> offset) & 1;
 159 }
 160
 161 static int
 162 falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
 163 {
 164         if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) {
 165                 if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1)
 166                         return -EBUSY;
 167                 /* switch on gpio function */
 168                 ltq_pad_w32(ctop(chip), 1, LTQ_PADC_MUX(offset));
 169                 return 0;
 170         }
 171
 172         return -ENODEV;
 173 }
 174
 175 static void
 176 falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
 177 {
 178         if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) {
 179                 if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1)
 180                         return;
 181                 /* switch off gpio function */
 182                 ltq_pad_w32(ctop(chip), 0, LTQ_PADC_MUX(offset));
 183         }
 184 }
 185
 186 static int
 187 falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 188 {
 189         return ctop(chip)->irq_base + offset;
 190 }
 191
 192 static void
 193 falcon_gpio_disable_irq(struct irq_data *d)
 194 {
 195         unsigned int offset = d->irq - itop(d)->irq_base;
 196
 197         ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR);
 198 }
 199
 200 static void
 201 falcon_gpio_enable_irq(struct irq_data *d)
 202 {
 203         unsigned int offset = d->irq - itop(d)->irq_base;
 204
 205         if (!ltq_pad_r32(itop(d), LTQ_PADC_MUX(offset)) < 1)
 206                 /* switch on gpio function */
 207                 ltq_pad_w32(itop(d), 1, LTQ_PADC_MUX(offset));
 208
 209         ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNRNSET);
 210 }
 211
 212 static void
 213 falcon_gpio_ack_irq(struct irq_data *d)
 214 {
 215         unsigned int offset = d->irq - itop(d)->irq_base;
 216
 217         ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR);
 218 }
 219
 220 static void
 221 falcon_gpio_mask_and_ack_irq(struct irq_data *d)
 222 {
 223         unsigned int offset = d->irq - itop(d)->irq_base;
 224
 225         ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR);
 226         ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR);
 227 }
 228
 229 static struct irq_chip falcon_gpio_irq_chip;
 230 static int
 231 falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
 232 {
 233         unsigned int offset = d->irq - itop(d)->irq_base;
 234         unsigned int mask = 1 << offset;
 235
 236         if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
 237                 return 0;
 238
 239         if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
 240                 /* level triggered */
 241                 ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_IRNCFG);
 242                 irq_set_chip_and_handler_name(d->irq,
 243                                 &falcon_gpio_irq_chip, handle_level_irq, "mux");
 244         } else {
 245                 /* edge triggered */
 246                 ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_IRNCFG);
 247                 irq_set_chip_and_handler_name(d->irq,
 248                         &falcon_gpio_irq_chip, handle_simple_irq, "mux");
 249         }
 250
 251         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
 252                 ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0);
 253                 ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR1);
 254         } else {
 255                 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0)
 256                         /* positive logic: rising edge, high level */
 257                         ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0);
 258                 else
 259                         /* negative logic: falling edge, low level */
 260                         ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR0);
 261                 ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR1);
 262         }
 263
 264         return gpio_direction_input(itop(d)->gpio_chip.base + offset);
 265 }
 266
 267 static void
 268 falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 269 {
 270         struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
 271         unsigned long irncr;
 272         int offset;
 273
 274         /* acknowledge interrupt */
 275         irncr = ltq_port_r32(gpio_port, LTQ_GPIO_IRNCR);
 276         ltq_port_w32(gpio_port, irncr, LTQ_GPIO_IRNCR);
 277
 278         desc->irq_data.chip->irq_ack(&desc->irq_data);
 279
 280         for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
 281                 generic_handle_irq(gpio_port->irq_base + offset);
 282 }
 283
 284 static struct irq_chip falcon_gpio_irq_chip = {
 285         .name = "gpio_irq_mux",
 286         .irq_mask = falcon_gpio_disable_irq,
 287         .irq_unmask = falcon_gpio_enable_irq,
 288         .irq_ack = falcon_gpio_ack_irq,
 289         .irq_mask_ack = falcon_gpio_mask_and_ack_irq,
 290         .irq_set_type = falcon_gpio_irq_type,
 291 };
 292
 293 static struct irqaction gpio_cascade = {
 294         .handler = no_action,
 295         .flags = IRQF_DISABLED,
 296         .name = "gpio_cascade",
 297 };
 298
 299 static int
 300 falcon_gpio_probe(struct platform_device *pdev)
 301 {
 302         struct falcon_gpio_port *gpio_port;
 303         int ret, i;
 304         struct resource *gpiores, *padres;
 305         int irq;
 306
 307         if (pdev->id >= MAX_PORTS)
 308                 return -ENODEV;
 309
 310         gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 311         padres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 312         irq = platform_get_irq(pdev, 0);
 313         if (!gpiores || !padres)
 314                 return -ENODEV;
 315
 316         gpio_port = &ltq_gpio_port[pdev->id];
 317         gpio_port->gpio_chip.label = "falcon-gpio";
 318         gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
 319         gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
 320         gpio_port->gpio_chip.get = falcon_gpio_get;
 321         gpio_port->gpio_chip.set = falcon_gpio_set;
 322         gpio_port->gpio_chip.request = falcon_gpio_request;
 323         gpio_port->gpio_chip.free = falcon_gpio_free;
 324         gpio_port->gpio_chip.base = 100 * pdev->id;
 325         gpio_port->gpio_chip.ngpio = 32;
 326         gpio_port->gpio_chip.dev = &pdev->dev;
 327
 328         gpio_port->port = ltq_remap_resource(gpiores);
 329         gpio_port->pad = ltq_remap_resource(padres);
 330
 331         if (!gpio_port->port || !gpio_port->pad) {
 332                 dev_err(&pdev->dev, "Could not map io ranges\n");
 333                 ret = -ENOMEM;
 334                 goto err;
 335         }
 336
 337         gpio_port->clk = clk_get(&pdev->dev, NULL);
 338         if (IS_ERR(gpio_port->clk)) {
 339                 dev_err(&pdev->dev, "Could not get clock\n");
 340                 ret = PTR_ERR(gpio_port->clk);;
 341                 goto err;
 342         }
 343         clk_enable(gpio_port->clk);
 344
 345         if (irq > 0) {
 346                 /* irq_chip support */
 347                 gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
 348                 gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * pdev->id);
 349
 350                 for (i = 0; i < 32; i++) {
 351                         irq_set_chip_and_handler_name(gpio_port->irq_base + i,
 352                                 &falcon_gpio_irq_chip, handle_simple_irq,
 353                                 "mux");
 354                         irq_set_chip_data(gpio_port->irq_base + i, gpio_port);
 355                         /* set to negative logic (falling edge, low level) */
 356                         ltq_port_w32_mask(gpio_port, 0, 1 << i,
 357                                 LTQ_GPIO_EXINTCR0);
 358                 }
 359
 360                 gpio_port->chained_irq = irq;
 361                 setup_irq(irq, &gpio_cascade);
 362                 irq_set_handler_data(irq, gpio_port);
 363                 irq_set_chained_handler(irq, falcon_gpio_irq_handler);
 364         }
 365
 366         ret = gpiochip_add(&gpio_port->gpio_chip);
 367         if (ret < 0) {
 368                 dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n",
 369                         pdev->id, ret);
 370                 goto err;
 371         }
 372         platform_set_drvdata(pdev, gpio_port);
 373         return ret;
 374
 375 err:
 376         dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret);
 377         if (gpiores)
 378                 release_resource(gpiores);
 379         if (padres)
 380                 release_resource(padres);
 381
 382         if (gpio_port->port)
 383                 iounmap(gpio_port->port);
 384         if (gpio_port->pad)
 385                 iounmap(gpio_port->pad);
 386         return ret;
 387 }
 388
 389 static struct platform_driver falcon_gpio_driver = {
 390         .probe = falcon_gpio_probe,
 391         .driver = {
 392                 .name = "falcon_gpio",
 393                 .owner = THIS_MODULE,
 394         },
 395 };
 396
 397 int __init
 398 falcon_gpio_init(void)
 399 {
 400         int ret;
 401
 402         pr_info("FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n");
 403         ret = platform_driver_register(&falcon_gpio_driver);
 404         if (ret)
 405                 pr_err("falcon_gpio: Error registering platform driver!");
 406         return ret;
 407 }
 408
 409 postcore_initcall(falcon_gpio_init);