target/linux/lantiq/patches-3.14/0029-GPIO-MIPS-lantiq-add-gpio-driver-for-falcon-SoC.patch

   1 From 7e178ce2e5f3aef38d4bdd2c0e02eae6100d5af4 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 7 Aug 2014 18:22:19 +0200
   4 Subject: [PATCH 29/36] GPIO: MIPS: lantiq: add gpio driver for falcon SoC
   5
   6 Add driver for GPIO blocks found on Lantiq FALCON SoC. The SoC has 5 banks of
   7 up to 32 pads. The GPIO blocks have a per pin IRQs.
   8
   9 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
  10 Acked-by: John Crispin <blogic@openwrt.org>
  11 Cc: linux-mips@linux-mips.org
  12 Cc: linux-gpio@vger.kernel.org
  13 ---
  14  drivers/gpio/Kconfig       |    5 +
  15  drivers/gpio/Makefile      |    1 +
  16  drivers/gpio/gpio-falcon.c |  348 ++++++++++++++++++++++++++++++++++++++++++++
  17  3 files changed, 354 insertions(+)
  18  create mode 100644 drivers/gpio/gpio-falcon.c
  19
  20 --- a/drivers/gpio/Kconfig
  21 +++ b/drivers/gpio/Kconfig
  22 @@ -145,6 +145,11 @@ config GPIO_EP93XX
  23         depends on ARCH_EP93XX
  24         select GPIO_GENERIC
  25
  26 +config GPIO_FALCON
  27 +       def_bool y
  28 +       depends on MIPS && SOC_FALCON
  29 +       select GPIO_GENERIC
  30 +
  31  config GPIO_MM_LANTIQ
  32         bool "Lantiq Memory mapped GPIOs"
  33         depends on LANTIQ && SOC_XWAY
  34 --- a/drivers/gpio/Makefile
  35 +++ b/drivers/gpio/Makefile
  36 @@ -26,6 +26,7 @@ obj-$(CONFIG_GPIO_DAVINCI)    += gpio-davin
  37  obj-$(CONFIG_GPIO_EM)          += gpio-em.o
  38  obj-$(CONFIG_GPIO_EP93XX)      += gpio-ep93xx.o
  39  obj-$(CONFIG_GPIO_F7188X)      += gpio-f7188x.o
  40 +obj-$(CONFIG_GPIO_FALCON)      += gpio-falcon.o
  41  obj-$(CONFIG_GPIO_GE_FPGA)     += gpio-ge.o
  42  obj-$(CONFIG_GPIO_GRGPIO)      += gpio-grgpio.o
  43  obj-$(CONFIG_GPIO_ICH)         += gpio-ich.o
  44 --- /dev/null
  45 +++ b/drivers/gpio/gpio-falcon.c
  46 @@ -0,0 +1,348 @@
  47 +/*
  48 + *  This program is free software; you can redistribute it and/or modify it
  49 + *  under the terms of the GNU General Public License version 2 as published
  50 + *  by the Free Software Foundation.
  51 + *
  52 + *  Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
  53 + *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
  54 + */
  55 +
  56 +#include <linux/gpio.h>
  57 +#include <linux/interrupt.h>
  58 +#include <linux/slab.h>
  59 +#include <linux/export.h>
  60 +#include <linux/err.h>
  61 +#include <linux/module.h>
  62 +#include <linux/of.h>
  63 +#include <linux/of_irq.h>
  64 +#include <linux/pinctrl/pinctrl.h>
  65 +#include <linux/pinctrl/consumer.h>
  66 +#include <linux/platform_device.h>
  67 +
  68 +#include <lantiq_soc.h>
  69 +
  70 +/* Data Output Register */
  71 +#define GPIO_OUT            0x00000000
  72 +/* Data Input Register */
  73 +#define GPIO_IN             0x00000004
  74 +/* Direction Register */
  75 +#define GPIO_DIR            0x00000008
  76 +/* External Interrupt Control Register 0 */
  77 +#define GPIO_EXINTCR0       0x00000018
  78 +/* External Interrupt Control Register 1 */
  79 +#define GPIO_EXINTCR1       0x0000001C
  80 +/* IRN Capture Register */
  81 +#define GPIO_IRNCR          0x00000020
  82 +/* IRN Interrupt Configuration Register */
  83 +#define GPIO_IRNCFG            0x0000002C
  84 +/* IRN Interrupt Enable Set Register */
  85 +#define GPIO_IRNRNSET       0x00000030
  86 +/* IRN Interrupt Enable Clear Register */
  87 +#define GPIO_IRNENCLR       0x00000034
  88 +/* Output Set Register */
  89 +#define GPIO_OUTSET         0x00000040
  90 +/* Output Cler Register */
  91 +#define GPIO_OUTCLR         0x00000044
  92 +/* Direction Clear Register */
  93 +#define GPIO_DIRSET         0x00000048
  94 +/* Direction Set Register */
  95 +#define GPIO_DIRCLR         0x0000004C
  96 +
  97 +/* turn a gpio_chip into a falcon_gpio_port */
  98 +#define ctop(c)                container_of(c, struct falcon_gpio_port, gpio_chip)
  99 +/* turn a irq_data into a falcon_gpio_port */
 100 +#define itop(i)                ((struct falcon_gpio_port *) irq_get_chip_data(i->irq))
 101 +
 102 +#define port_r32(p, reg)       ltq_r32(p->port + reg)
 103 +#define port_w32(p, val, reg)  ltq_w32(val, p->port + reg)
 104 +#define port_w32_mask(p, clear, set, reg) \
 105 +               port_w32(p, (port_r32(p, reg) & ~(clear)) | (set), reg)
 106 +
 107 +#define MAX_BANKS              5
 108 +#define PINS_PER_PORT          32
 109 +
 110 +struct falcon_gpio_port {
 111 +       struct gpio_chip gpio_chip;
 112 +       void __iomem *port;
 113 +       unsigned int irq_base;
 114 +       unsigned int chained_irq;
 115 +       struct clk *clk;
 116 +       char name[6];
 117 +};
 118 +
 119 +static struct irq_chip falcon_gpio_irq_chip;
 120 +
 121 +static int falcon_gpio_direction_input(struct gpio_chip *chip,
 122 +                                       unsigned int offset)
 123 +{
 124 +       port_w32(ctop(chip), 1 << offset, GPIO_DIRCLR);
 125 +
 126 +       return 0;
 127 +}
 128 +
 129 +static void falcon_gpio_set(struct gpio_chip *chip, unsigned int offset,
 130 +                                       int value)
 131 +{
 132 +       if (value)
 133 +               port_w32(ctop(chip), 1 << offset, GPIO_OUTSET);
 134 +       else
 135 +               port_w32(ctop(chip), 1 << offset, GPIO_OUTCLR);
 136 +}
 137 +
 138 +static int falcon_gpio_direction_output(struct gpio_chip *chip,
 139 +                                       unsigned int offset, int value)
 140 +{
 141 +       falcon_gpio_set(chip, offset, value);
 142 +       port_w32(ctop(chip), 1 << offset, GPIO_DIRSET);
 143 +
 144 +       return 0;
 145 +}
 146 +
 147 +static int falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
 148 +{
 149 +       if ((port_r32(ctop(chip), GPIO_DIR) >> offset) & 1)
 150 +               return (port_r32(ctop(chip), GPIO_OUT) >> offset) & 1;
 151 +       else
 152 +               return (port_r32(ctop(chip), GPIO_IN) >> offset) & 1;
 153 +}
 154 +
 155 +static int falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
 156 +{
 157 +       int gpio = chip->base + offset;
 158 +
 159 +       return pinctrl_request_gpio(gpio);
 160 +}
 161 +
 162 +static void falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
 163 +{
 164 +       int gpio = chip->base + offset;
 165 +
 166 +       pinctrl_free_gpio(gpio);
 167 +}
 168 +
 169 +static int falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 170 +{
 171 +       return ctop(chip)->irq_base + offset;
 172 +}
 173 +
 174 +static void falcon_gpio_disable_irq(struct irq_data *d)
 175 +{
 176 +       unsigned int offset = d->irq - itop(d)->irq_base;
 177 +
 178 +       port_w32(itop(d), 1 << offset, GPIO_IRNENCLR);
 179 +}
 180 +
 181 +static void falcon_gpio_enable_irq(struct irq_data *d)
 182 +{
 183 +       unsigned int offset = d->irq - itop(d)->irq_base;
 184 +
 185 +       port_w32(itop(d), 1 << offset, GPIO_IRNRNSET);
 186 +}
 187 +
 188 +static void falcon_gpio_ack_irq(struct irq_data *d)
 189 +{
 190 +       unsigned int offset = d->irq - itop(d)->irq_base;
 191 +
 192 +       port_w32(itop(d), 1 << offset, GPIO_IRNCR);
 193 +}
 194 +
 195 +static void falcon_gpio_mask_and_ack_irq(struct irq_data *d)
 196 +{
 197 +       unsigned int offset = d->irq - itop(d)->irq_base;
 198 +
 199 +       port_w32(itop(d), 1 << offset, GPIO_IRNENCLR);
 200 +       port_w32(itop(d), 1 << offset, GPIO_IRNCR);
 201 +}
 202 +
 203 +static int falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
 204 +{
 205 +       unsigned int offset = d->irq - itop(d)->irq_base;
 206 +       unsigned int mask = 1 << offset;
 207 +
 208 +       if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
 209 +               return 0;
 210 +
 211 +       if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
 212 +               /* level triggered */
 213 +               port_w32_mask(itop(d), 0, mask, GPIO_IRNCFG);
 214 +               irq_set_chip_and_handler_name(d->irq,
 215 +                       &falcon_gpio_irq_chip, handle_level_irq, "mux");
 216 +       } else {
 217 +               /* edge triggered */
 218 +               port_w32_mask(itop(d), mask, 0, GPIO_IRNCFG);
 219 +               irq_set_chip_and_handler_name(d->irq,
 220 +                       &falcon_gpio_irq_chip, handle_simple_irq, "mux");
 221 +       }
 222 +
 223 +       if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
 224 +               port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR0);
 225 +               port_w32_mask(itop(d), 0, mask, GPIO_EXINTCR1);
 226 +       } else {
 227 +               if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0)
 228 +                       /* positive logic: rising edge, high level */
 229 +                       port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR0);
 230 +               else
 231 +                       /* negative logic: falling edge, low level */
 232 +                       port_w32_mask(itop(d), 0, mask, GPIO_EXINTCR0);
 233 +               port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR1);
 234 +       }
 235 +
 236 +       return gpio_direction_input(itop(d)->gpio_chip.base + offset);
 237 +}
 238 +
 239 +static void falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 240 +{
 241 +       struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
 242 +       unsigned long irncr;
 243 +       int offset;
 244 +
 245 +       /* acknowledge interrupt */
 246 +       irncr = port_r32(gpio_port, GPIO_IRNCR);
 247 +       port_w32(gpio_port, irncr, GPIO_IRNCR);
 248 +
 249 +       desc->irq_data.chip->irq_ack(&desc->irq_data);
 250 +
 251 +       for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
 252 +               generic_handle_irq(gpio_port->irq_base + offset);
 253 +}
 254 +
 255 +static int falcon_gpio_irq_map(struct irq_domain *d, unsigned int irq,
 256 +                               irq_hw_number_t hw)
 257 +{
 258 +       struct falcon_gpio_port *port = d->host_data;
 259 +
 260 +       irq_set_chip_and_handler_name(irq, &falcon_gpio_irq_chip,
 261 +                       handle_simple_irq, "mux");
 262 +       irq_set_chip_data(irq, port);
 263 +
 264 +       /* set to negative logic (falling edge, low level) */
 265 +       port_w32_mask(port, 0, 1 << hw, GPIO_EXINTCR0);
 266 +       return 0;
 267 +}
 268 +
 269 +static struct irq_chip falcon_gpio_irq_chip = {
 270 +       .name = "gpio_irq_mux",
 271 +       .irq_mask = falcon_gpio_disable_irq,
 272 +       .irq_unmask = falcon_gpio_enable_irq,
 273 +       .irq_ack = falcon_gpio_ack_irq,
 274 +       .irq_mask_ack = falcon_gpio_mask_and_ack_irq,
 275 +       .irq_set_type = falcon_gpio_irq_type,
 276 +};
 277 +
 278 +static const struct irq_domain_ops irq_domain_ops = {
 279 +       .xlate = irq_domain_xlate_onetwocell,
 280 +       .map = falcon_gpio_irq_map,
 281 +};
 282 +
 283 +static struct irqaction gpio_cascade = {
 284 +       .handler = no_action,
 285 +       .flags = IRQF_DISABLED,
 286 +       .name = "gpio_cascade",
 287 +};
 288 +
 289 +static int falcon_gpio_probe(struct platform_device *pdev)
 290 +{
 291 +       struct pinctrl_gpio_range *gpio_range;
 292 +       struct device_node *node = pdev->dev.of_node;
 293 +       const __be32 *bank = of_get_property(node, "lantiq,bank", NULL);
 294 +       struct falcon_gpio_port *gpio_port;
 295 +       struct resource *gpiores, irqres;
 296 +       int ret, size;
 297 +
 298 +       if (!bank || *bank >= MAX_BANKS)
 299 +               return -ENODEV;
 300 +
 301 +       size = pinctrl_falcon_get_range_size(*bank);
 302 +       if (size < 1) {
 303 +               dev_err(&pdev->dev, "pad not loaded for bank %d\n", *bank);
 304 +               return size;
 305 +       }
 306 +
 307 +       gpio_range = devm_kzalloc(&pdev->dev, sizeof(struct pinctrl_gpio_range),
 308 +                               GFP_KERNEL);
 309 +       if (!gpio_range)
 310 +               return -ENOMEM;
 311 +
 312 +       gpio_port = devm_kzalloc(&pdev->dev, sizeof(struct falcon_gpio_port),
 313 +                               GFP_KERNEL);
 314 +       if (!gpio_port)
 315 +               return -ENOMEM;
 316 +
 317 +       snprintf(gpio_port->name, 6, "gpio%d", *bank);
 318 +       gpio_port->gpio_chip.label = gpio_port->name;
 319 +       gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
 320 +       gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
 321 +       gpio_port->gpio_chip.get = falcon_gpio_get;
 322 +       gpio_port->gpio_chip.set = falcon_gpio_set;
 323 +       gpio_port->gpio_chip.request = falcon_gpio_request;
 324 +       gpio_port->gpio_chip.free = falcon_gpio_free;
 325 +       gpio_port->gpio_chip.base = *bank * PINS_PER_PORT;
 326 +       gpio_port->gpio_chip.ngpio = size;
 327 +       gpio_port->gpio_chip.dev = &pdev->dev;
 328 +
 329 +       gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 330 +       gpio_port->port = devm_request_and_ioremap(&pdev->dev, gpiores);
 331 +       if (IS_ERR(gpio_port->port))
 332 +               return PTR_ERR(gpio_port->port);
 333 +
 334 +       gpio_port->clk = devm_clk_get(&pdev->dev, NULL);
 335 +       if (IS_ERR(gpio_port->clk))
 336 +               return PTR_ERR(gpio_port->clk);
 337 +       clk_activate(gpio_port->clk);
 338 +
 339 +       if (of_irq_to_resource_table(node, &irqres, 1) == 1) {
 340 +               gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * *bank);
 341 +               gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
 342 +               gpio_port->chained_irq = irqres.start;
 343 +               irq_domain_add_legacy(node, size, gpio_port->irq_base, 0,
 344 +                                       &irq_domain_ops, gpio_port);
 345 +               setup_irq(irqres.start, &gpio_cascade);
 346 +               irq_set_handler_data(irqres.start, gpio_port);
 347 +               irq_set_chained_handler(irqres.start, falcon_gpio_irq_handler);
 348 +       }
 349 +
 350 +       ret = gpiochip_add(&gpio_port->gpio_chip);
 351 +       if (ret)
 352 +               return ret;
 353 +
 354 +       platform_set_drvdata(pdev, gpio_port);
 355 +
 356 +       gpio_range->name = "FALCON GPIO";
 357 +       gpio_range->id = *bank;
 358 +       gpio_range->base = gpio_port->gpio_chip.base;
 359 +       gpio_range->pin_base = gpio_port->gpio_chip.base;
 360 +       gpio_range->npins = gpio_port->gpio_chip.ngpio;
 361 +       gpio_range->gc = &gpio_port->gpio_chip;
 362 +
 363 +       pinctrl_falcon_add_gpio_range(gpio_range);
 364 +
 365 +       return 0;
 366 +}
 367 +
 368 +static const struct of_device_id falcon_gpio_match[] = {
 369 +       { .compatible = "lantiq,falcon-gpio" },
 370 +       {},
 371 +};
 372 +MODULE_DEVICE_TABLE(of, falcon_gpio_match);
 373 +
 374 +static struct platform_driver falcon_gpio_driver = {
 375 +       .probe = falcon_gpio_probe,
 376 +       .driver = {
 377 +               .name = "gpio-falcon",
 378 +               .owner = THIS_MODULE,
 379 +               .of_match_table = falcon_gpio_match,
 380 +       },
 381 +};
 382 +
 383 +int __init falcon_gpio_init(void)
 384 +{
 385 +       int ret;
 386 +
 387 +       pr_info("FALC(tm) ON GPIO Driver, (C) 2012 Lantiq Deutschland Gmbh\n");
 388 +       ret = platform_driver_register(&falcon_gpio_driver);
 389 +       if (ret)
 390 +               pr_err("falcon_gpio: Error registering platform driver!");
 391 +       return ret;
 392 +}
 393 +
 394 +subsys_initcall(falcon_gpio_init);