target/linux/lantiq/patches-3.3/0067-MIPS-lantiq-fix-dwc_otg-usb-for-ase.patch

   1 From 6f421cda8e6e43f74b8f8a7f63db67c6d3ac9ba3 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 11 Apr 2012 18:43:50 +0200
   4 Subject: [PATCH 67/70] MIPS: lantiq: fix dwc_otg usb for ase
   5
   6 changed irq number and pmu settings. little bit of fiddling to get the now variable
   7 irq into resources.
   8
   9 Signed-off-by: Conor O'Gorman <i@conorogorman.net>
  10 ---
  11  .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h |    1 +
  12  drivers/usb/dwc_otg/dwc_otg_driver.c               |    3 +++
  13  drivers/usb/dwc_otg/dwc_otg_ifx.c                  |    5 ++++-
  14  3 files changed, 8 insertions(+), 1 deletions(-)
  15
  16 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
  17 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
  18 @@ -36,6 +36,7 @@
  19
  20  #define LTQ_TIMER6_INT         (INT_NUM_IM1_IRL0 + 23)
  21  #define LTQ_USB_INT            (INT_NUM_IM1_IRL0 + 22)
  22 +#define LTQ_USB_ASE_INT                (INT_NUM_IM0_IRL0 + 31)
  23  #define LTQ_USB_OC_INT         (INT_NUM_IM4_IRL0 + 23)
  24
  25  #define MIPS_CPU_TIMER_IRQ             7
  26 --- a/drivers/usb/dwc_otg/dwc_otg_driver.c
  27 +++ b/drivers/usb/dwc_otg/dwc_otg_driver.c
  28 @@ -860,6 +860,9 @@ static int __init dwc_otg_init(void)
  29
  30      printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION);
  31
  32 +    if (ltq_is_ase())
  33 +        dwc_irq = LTQ_USB_ASE_INT;
  34 +
  35         // ifxmips setup
  36      retval = ifx_usb_hc_init(dwc_iomem_base, dwc_irq);
  37      if (retval < 0)
  38 --- a/drivers/usb/dwc_otg/dwc_otg_ifx.c
  39 +++ b/drivers/usb/dwc_otg/dwc_otg_ifx.c
  40 @@ -61,7 +61,10 @@ void dwc_otg_power_on (void)
  41         // clear power
  42         writel(readl(DANUBE_PMU_PWDCR) | 0x41, DANUBE_PMU_PWDCR);
  43         // set clock gating
  44 -       writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR);
  45 +       if (ltq_is_ase())
  46 +               writel(readl(DANUBE_CGU_IFCCR) & ~0x20, DANUBE_CGU_IFCCR);
  47 +       else
  48 +               writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR);
  49         // set power
  50         writel(readl(DANUBE_PMU_PWDCR) & ~0x1, DANUBE_PMU_PWDCR);
  51         writel(readl(DANUBE_PMU_PWDCR) & ~0x40, DANUBE_PMU_PWDCR);