target/linux/lantiq/patches-3.8/0017-MIPS-lantiq-adds-static-clock-for-PP32.patch

   1 From 46a704b1b093f4053eceaf8e5f0ab54949afa532 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 19 Jan 2013 08:54:24 +0000
   4 Subject: [PATCH 17/40] MIPS: lantiq: adds static clock for PP32
   5
   6 The Lantiq DSL SoCs have an internal networking processor. Add code to read
   7 the static clock rate.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 Patchwork: http://patchwork.linux-mips.org/patch/4815/
  11 ---
  12  arch/mips/include/asm/mach-lantiq/lantiq.h |    1 +
  13  arch/mips/lantiq/clk.c                     |   12 ++++++--
  14  arch/mips/lantiq/clk.h                     |    7 ++++-
  15  arch/mips/lantiq/falcon/sysctrl.c          |    4 +--
  16  arch/mips/lantiq/xway/clk.c                |   43 ++++++++++++++++++++++++++++
  17  arch/mips/lantiq/xway/sysctrl.c            |   12 ++++----
  18  6 files changed, 69 insertions(+), 10 deletions(-)
  19
  20 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h
  21 +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
  22 @@ -41,6 +41,7 @@ extern void clk_deactivate(struct clk *c
  23  extern struct clk *clk_get_cpu(void);
  24  extern struct clk *clk_get_fpi(void);
  25  extern struct clk *clk_get_io(void);
  26 +extern struct clk *clk_get_ppe(void);
  27
  28  /* find out what bootsource we have */
  29  extern unsigned char ltq_boot_select(void);
  30 --- a/arch/mips/lantiq/clk.c
  31 +++ b/arch/mips/lantiq/clk.c
  32 @@ -26,13 +26,15 @@
  33  #include "prom.h"
  34
  35  /* lantiq socs have 3 static clocks */
  36 -static struct clk cpu_clk_generic[3];
  37 +static struct clk cpu_clk_generic[4];
  38
  39 -void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io)
  40 +void clkdev_add_static(unsigned long cpu, unsigned long fpi,
  41 +                       unsigned long io, unsigned long ppe)
  42  {
  43         cpu_clk_generic[0].rate = cpu;
  44         cpu_clk_generic[1].rate = fpi;
  45         cpu_clk_generic[2].rate = io;
  46 +       cpu_clk_generic[3].rate = ppe;
  47  }
  48
  49  struct clk *clk_get_cpu(void)
  50 @@ -51,6 +53,12 @@ struct clk *clk_get_io(void)
  51         return &cpu_clk_generic[2];
  52  }
  53
  54 +struct clk *clk_get_ppe(void)
  55 +{
  56 +       return &cpu_clk_generic[3];
  57 +}
  58 +EXPORT_SYMBOL_GPL(clk_get_ppe);
  59 +
  60  static inline int clk_good(struct clk *clk)
  61  {
  62         return clk && !IS_ERR(clk);
  63 --- a/arch/mips/lantiq/clk.h
  64 +++ b/arch/mips/lantiq/clk.h
  65 @@ -27,12 +27,15 @@
  66  #define CLOCK_167M     166666667
  67  #define CLOCK_196_608M 196608000
  68  #define CLOCK_200M     200000000
  69 +#define CLOCK_222M     222000000
  70 +#define CLOCK_240M     240000000
  71  #define CLOCK_250M     250000000
  72  #define CLOCK_266M     266666666
  73  #define CLOCK_300M     300000000
  74  #define CLOCK_333M     333333333
  75  #define CLOCK_393M     393215332
  76  #define CLOCK_400M     400000000
  77 +#define CLOCK_450M     450000000
  78  #define CLOCK_500M     500000000
  79  #define CLOCK_600M     600000000
  80
  81 @@ -64,15 +67,17 @@ struct clk {
  82  };
  83
  84  extern void clkdev_add_static(unsigned long cpu, unsigned long fpi,
  85 -                               unsigned long io);
  86 +                               unsigned long io, unsigned long ppe);
  87
  88  extern unsigned long ltq_danube_cpu_hz(void);
  89  extern unsigned long ltq_danube_fpi_hz(void);
  90 +extern unsigned long ltq_danube_pp32_hz(void);
  91
  92  extern unsigned long ltq_ar9_cpu_hz(void);
  93  extern unsigned long ltq_ar9_fpi_hz(void);
  94
  95  extern unsigned long ltq_vr9_cpu_hz(void);
  96  extern unsigned long ltq_vr9_fpi_hz(void);
  97 +extern unsigned long ltq_vr9_pp32_hz(void);
  98
  99  #endif
 100 --- a/arch/mips/lantiq/falcon/sysctrl.c
 101 +++ b/arch/mips/lantiq/falcon/sysctrl.c
 102 @@ -241,9 +241,9 @@ void __init ltq_soc_init(void)
 103
 104         /* get our 3 static rates for cpu, fpi and io clocks */
 105         if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV)
 106 -               clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M);
 107 +               clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M, 0);
 108         else
 109 -               clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M);
 110 +               clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M, 0);
 111
 112         /* add our clock domains */
 113         clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0);
 114 --- a/arch/mips/lantiq/xway/clk.c
 115 +++ b/arch/mips/lantiq/xway/clk.c
 116 @@ -53,6 +53,29 @@ unsigned long ltq_danube_cpu_hz(void)
 117         }
 118  }
 119
 120 +unsigned long ltq_danube_pp32_hz(void)
 121 +{
 122 +       unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3;
 123 +       unsigned long clk;
 124 +
 125 +       switch (clksys) {
 126 +       case 1:
 127 +               clk = CLOCK_240M;
 128 +               break;
 129 +       case 2:
 130 +               clk = CLOCK_222M;
 131 +               break;
 132 +       case 3:
 133 +               clk = CLOCK_133M;
 134 +               break;
 135 +       default:
 136 +               clk = CLOCK_266M;
 137 +               break;
 138 +       }
 139 +
 140 +       return clk;
 141 +}
 142 +
 143  unsigned long ltq_ar9_sys_hz(void)
 144  {
 145         if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
 146 @@ -147,5 +170,25 @@ unsigned long ltq_vr9_fpi_hz(void)
 147                 break;
 148         }
 149
 150 +       return clk;
 151 +}
 152 +
 153 +unsigned long ltq_vr9_pp32_hz(void)
 154 +{
 155 +       unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 3;
 156 +       unsigned long clk;
 157 +
 158 +       switch (clksys) {
 159 +       case 1:
 160 +               clk = CLOCK_450M;
 161 +               break;
 162 +       case 2:
 163 +               clk = CLOCK_300M;
 164 +               break;
 165 +       default:
 166 +               clk = CLOCK_500M;
 167 +               break;
 168 +       }
 169 +
 170         return clk;
 171  }
 172 --- a/arch/mips/lantiq/xway/sysctrl.c
 173 +++ b/arch/mips/lantiq/xway/sysctrl.c
 174 @@ -356,14 +356,16 @@ void __init ltq_soc_init(void)
 175
 176         if (of_machine_is_compatible("lantiq,ase")) {
 177                 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
 178 -                       clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
 179 +                       clkdev_add_static(CLOCK_266M, CLOCK_133M,
 180 +                                               CLOCK_133M, CLOCK_266M);
 181                 else
 182 -                       clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
 183 +                       clkdev_add_static(CLOCK_133M, CLOCK_133M,
 184 +                                               CLOCK_133M, CLOCK_133M);
 185                 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),
 186                 clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY);
 187         } else if (of_machine_is_compatible("lantiq,vr9")) {
 188                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
 189 -                               ltq_vr9_fpi_hz());
 190 +                               ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
 191                 clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY);
 192                 clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK);
 193                 clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI);
 194 @@ -376,10 +378,10 @@ void __init ltq_soc_init(void)
 195                                 PMU_PPE_QSB | PMU_PPE_TOP);
 196         } else if (of_machine_is_compatible("lantiq,ar9")) {
 197                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
 198 -                               ltq_ar9_fpi_hz());
 199 +                               ltq_ar9_fpi_hz(), CLOCK_250M);
 200                 clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH);
 201         } else {
 202                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 203 -                               ltq_danube_fpi_hz());
 204 +                               ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
 205         }
 206  }