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[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.8 / 0040-owrt-lantiq-add-atm-hack.patch
1 From ae15f50544e6012c998ef59f6c12e334da3c9bff Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 3 Aug 2012 10:27:25 +0200
4 Subject: [PATCH 40/40] owrt: lantiq: add atm hack
5
6 ---
7 arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++
8 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++
9 arch/mips/lantiq/irq.c | 2 +
10 arch/mips/mm/cache.c | 2 +
11 include/uapi/linux/atm.h | 6 +
12 net/atm/common.c | 6 +
13 net/atm/proc.c | 2 +-
14 7 files changed, 416 insertions(+), 1 deletion(-)
15 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h
16 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
17
18 --- /dev/null
19 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
20 @@ -0,0 +1,196 @@
21 +/******************************************************************************
22 +**
23 +** FILE NAME : ifx_atm.h
24 +** PROJECT : UEIP
25 +** MODULES : ATM
26 +**
27 +** DATE : 17 Jun 2009
28 +** AUTHOR : Xu Liang
29 +** DESCRIPTION : Global ATM driver header file
30 +** COPYRIGHT : Copyright (c) 2006
31 +** Infineon Technologies AG
32 +** Am Campeon 1-12, 85579 Neubiberg, Germany
33 +**
34 +** This program is free software; you can redistribute it and/or modify
35 +** it under the terms of the GNU General Public License as published by
36 +** the Free Software Foundation; either version 2 of the License, or
37 +** (at your option) any later version.
38 +**
39 +** HISTORY
40 +** $Date $Author $Comment
41 +** 07 JUL 2009 Xu Liang Init Version
42 +*******************************************************************************/
43 +
44 +#ifndef IFX_ATM_H
45 +#define IFX_ATM_H
46 +
47 +
48 +
49 +/*!
50 + \defgroup IFX_ATM UEIP Project - ATM driver module
51 + \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
52 + */
53 +
54 +/*!
55 + \defgroup IFX_ATM_IOCTL IOCTL Commands
56 + \ingroup IFX_ATM
57 + \brief IOCTL Commands used by user application.
58 + */
59 +
60 +/*!
61 + \defgroup IFX_ATM_STRUCT Structures
62 + \ingroup IFX_ATM
63 + \brief Structures used by user application.
64 + */
65 +
66 +/*!
67 + \file ifx_atm.h
68 + \ingroup IFX_ATM
69 + \brief ATM driver header file
70 + */
71 +
72 +
73 +
74 +/*
75 + * ####################################
76 + * Definition
77 + * ####################################
78 + */
79 +
80 +/*!
81 + \addtogroup IFX_ATM_STRUCT
82 + */
83 +/*@{*/
84 +
85 +/*
86 + * ATM MIB
87 + */
88 +
89 +/*!
90 + \struct atm_cell_ifEntry_t
91 + \brief Structure used for Cell Level MIB Counters.
92 +
93 + User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
94 + */
95 +typedef struct {
96 + __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
97 + __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
98 + __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
99 + __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
100 + __u32 ifInErrors; /*!< counter of error ingress cells */
101 + __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
102 + __u32 ifOutErrors; /*!< counter of error egress cells */
103 +} atm_cell_ifEntry_t;
104 +
105 +/*!
106 + \struct atm_aal5_ifEntry_t
107 + \brief Structure used for AAL5 Frame Level MIB Counters.
108 +
109 + User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
110 + */
111 +typedef struct {
112 + __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
113 + __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
114 + __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
115 + __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
116 + __u32 ifInUcastPkts; /*!< counter of ingress packets */
117 + __u32 ifOutUcastPkts; /*!< counter of egress packets */
118 + __u32 ifInErrors; /*!< counter of error ingress packets */
119 + __u32 ifInDiscards; /*!< counter of dropped ingress packets */
120 + __u32 ifOutErros; /*!< counter of error egress packets */
121 + __u32 ifOutDiscards; /*!< counter of dropped egress packets */
122 +} atm_aal5_ifEntry_t;
123 +
124 +/*!
125 + \struct atm_aal5_vcc_t
126 + \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
127 +
128 + This structure is a part of structure "atm_aal5_vcc_x_t".
129 + */
130 +typedef struct {
131 + __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
132 + __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
133 + __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
134 +} atm_aal5_vcc_t;
135 +
136 +/*!
137 + \struct atm_aal5_vcc_x_t
138 + \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
139 +
140 + User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
141 + */
142 +typedef struct {
143 + int vpi; /*!< VPI of the VCC to get MIB counters */
144 + int vci; /*!< VCI of the VCC to get MIB counters */
145 + atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
146 +} atm_aal5_vcc_x_t;
147 +
148 +/*@}*/
149 +
150 +
151 +
152 +/*
153 + * ####################################
154 + * IOCTL
155 + * ####################################
156 + */
157 +
158 +/*!
159 + \addtogroup IFX_ATM_IOCTL
160 + */
161 +/*@{*/
162 +
163 +/*
164 + * ioctl Command
165 + */
166 +/*!
167 + \brief ATM IOCTL Magic Number
168 + */
169 +#define PPE_ATM_IOC_MAGIC 'o'
170 +/*!
171 + \brief ATM IOCTL Command - Get Cell Level MIB Counters
172 +
173 + This command is obsolete. User can get cell level MIB from DSL API.
174 + This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
175 + */
176 +#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
177 +/*!
178 + \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
179 +
180 + Get AAL5 packet counters.
181 + This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
182 + */
183 +#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
184 +/*!
185 + \brief ATM IOCTL Command - Get Per PVC MIB Counters
186 +
187 + Get AAL5 packet counters for each PVC.
188 + This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
189 + */
190 +#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
191 +/*!
192 + \brief Total Number of ATM IOCTL Commands
193 + */
194 +#define PPE_ATM_IOC_MAXNR 3
195 +
196 +/*@}*/
197 +
198 +
199 +
200 +/*
201 + * ####################################
202 + * API
203 + * ####################################
204 + */
205 +
206 +#ifdef __KERNEL__
207 +struct port_cell_info {
208 + unsigned int port_num;
209 + unsigned int tx_link_rate[2];
210 +};
211 +#endif
212 +
213 +
214 +
215 +#endif // IFX_ATM_H
216 +
217 --- /dev/null
218 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
219 @@ -0,0 +1,203 @@
220 +/******************************************************************************
221 +**
222 +** FILE NAME : ifx_ptm.h
223 +** PROJECT : UEIP
224 +** MODULES : PTM
225 +**
226 +** DATE : 17 Jun 2009
227 +** AUTHOR : Xu Liang
228 +** DESCRIPTION : Global PTM driver header file
229 +** COPYRIGHT : Copyright (c) 2006
230 +** Infineon Technologies AG
231 +** Am Campeon 1-12, 85579 Neubiberg, Germany
232 +**
233 +** This program is free software; you can redistribute it and/or modify
234 +** it under the terms of the GNU General Public License as published by
235 +** the Free Software Foundation; either version 2 of the License, or
236 +** (at your option) any later version.
237 +**
238 +** HISTORY
239 +** $Date $Author $Comment
240 +** 07 JUL 2009 Xu Liang Init Version
241 +*******************************************************************************/
242 +
243 +#ifndef IFX_PTM_H
244 +#define IFX_PTM_H
245 +
246 +
247 +
248 +/*!
249 + \defgroup IFX_PTM UEIP Project - PTM driver module
250 + \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
251 + */
252 +
253 +/*!
254 + \defgroup IFX_PTM_IOCTL IOCTL Commands
255 + \ingroup IFX_PTM
256 + \brief IOCTL Commands used by user application.
257 + */
258 +
259 +/*!
260 + \defgroup IFX_PTM_STRUCT Structures
261 + \ingroup IFX_PTM
262 + \brief Structures used by user application.
263 + */
264 +
265 +/*!
266 + \file ifx_ptm.h
267 + \ingroup IFX_PTM
268 + \brief PTM driver header file
269 + */
270 +
271 +
272 +
273 +/*
274 + * ####################################
275 + * Definition
276 + * ####################################
277 + */
278 +
279 +
280 +
281 +/*
282 + * ####################################
283 + * IOCTL
284 + * ####################################
285 + */
286 +
287 +/*!
288 + \addtogroup IFX_PTM_IOCTL
289 + */
290 +/*@{*/
291 +
292 +/*
293 + * ioctl Command
294 + */
295 +/*!
296 + \brief PTM IOCTL Command - Get codeword MIB counters.
297 +
298 + This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
299 + */
300 +#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1
301 +/*!
302 + \brief PTM IOCTL Command - Get packet MIB counters.
303 +
304 + This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
305 + */
306 +#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2
307 +/*!
308 + \brief PTM IOCTL Command - Get firmware configuration (CRC).
309 +
310 + This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
311 + */
312 +#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3
313 +/*!
314 + \brief PTM IOCTL Command - Set firmware configuration (CRC).
315 +
316 + This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
317 + */
318 +#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4
319 +/*!
320 + \brief PTM IOCTL Command - Program priority value to TX queue mapping.
321 +
322 + This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
323 + */
324 +#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14
325 +
326 +/*@}*/
327 +
328 +
329 +/*!
330 + \addtogroup IFX_PTM_STRUCT
331 + */
332 +/*@{*/
333 +
334 +/*
335 + * ioctl Data Type
336 + */
337 +
338 +/*!
339 + \typedef PTM_CW_IF_ENTRY_T
340 + \brief Wrapping of structure "ptm_cw_ifEntry_t".
341 + */
342 +/*!
343 + \struct ptm_cw_ifEntry_t
344 + \brief Structure used for CodeWord level MIB counters.
345 + */
346 +typedef struct ptm_cw_ifEntry_t {
347 + uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */
348 + uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */
349 + uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */
350 + uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */
351 + uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */
352 +} PTM_CW_IF_ENTRY_T;
353 +
354 +/*!
355 + \typedef PTM_FRAME_MIB_T
356 + \brief Wrapping of structure "ptm_frame_mib_t".
357 + */
358 +/*!
359 + \struct ptm_frame_mib_t
360 + \brief Structure used for packet level MIB counters.
361 + */
362 +typedef struct ptm_frame_mib_t {
363 + uint32_t RxCorrect; /*!< output, number of ingress packet */
364 + uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */
365 + uint32_t RxDropped; /*!< output, number of dropped ingress packet */
366 + uint32_t TxSend; /*!< output, number of egress packet */
367 +} PTM_FRAME_MIB_T;
368 +
369 +/*!
370 + \typedef IFX_PTM_CFG_T
371 + \brief Wrapping of structure "ptm_cfg_t".
372 + */
373 +/*!
374 + \struct ptm_cfg_t
375 + \brief Structure used for ETH/TC CRC configuration.
376 + */
377 +typedef struct ptm_cfg_t {
378 + uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */
379 + uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */
380 + uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */
381 + uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */
382 + uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */
383 + uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */
384 + uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */
385 +} IFX_PTM_CFG_T;
386 +
387 +/*!
388 + \typedef IFX_PTM_PRIO_Q_MAP_T
389 + \brief Wrapping of structure "ppe_prio_q_map".
390 + */
391 +/*!
392 + \struct ppe_prio_q_map
393 + \brief Structure used for Priority Value to TX Queue mapping.
394 + */
395 +typedef struct ppe_prio_q_map {
396 + int pkt_prio;
397 + int qid;
398 + int vpi; // ignored in eth interface
399 + int vci; // ignored in eth interface
400 +} IFX_PTM_PRIO_Q_MAP_T;
401 +
402 +/*@}*/
403 +
404 +
405 +
406 +/*
407 + * ####################################
408 + * API
409 + * ####################################
410 + */
411 +
412 +#ifdef __KERNEL__
413 +struct port_cell_info {
414 + unsigned int port_num;
415 + unsigned int tx_link_rate[2];
416 +};
417 +#endif
418 +
419 +
420 +
421 +#endif // IFX_PTM_H
422 +
423 --- a/arch/mips/lantiq/irq.c
424 +++ b/arch/mips/lantiq/irq.c
425 @@ -14,6 +14,7 @@
426 #include <linux/of_platform.h>
427 #include <linux/of_address.h>
428 #include <linux/of_irq.h>
429 +#include <linux/module.h>
430
431 #include <asm/bootinfo.h>
432 #include <asm/irq_cpu.h>
433 @@ -99,6 +100,7 @@ void ltq_mask_and_ack_irq(struct irq_dat
434 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
435 ltq_icu_w32(im, BIT(offset), isr);
436 }
437 +EXPORT_SYMBOL(ltq_mask_and_ack_irq);
438
439 static void ltq_ack_irq(struct irq_data *d)
440 {
441 --- a/arch/mips/mm/cache.c
442 +++ b/arch/mips/mm/cache.c
443 @@ -58,6 +58,8 @@ void (*_dma_cache_wback)(unsigned long s
444 void (*_dma_cache_inv)(unsigned long start, unsigned long size);
445
446 EXPORT_SYMBOL(_dma_cache_wback_inv);
447 +EXPORT_SYMBOL(_dma_cache_wback);
448 +EXPORT_SYMBOL(_dma_cache_inv);
449
450 #endif /* CONFIG_DMA_NONCOHERENT */
451
452 --- a/include/uapi/linux/atm.h
453 +++ b/include/uapi/linux/atm.h
454 @@ -130,8 +130,14 @@
455 #define ATM_ABR 4
456 #define ATM_ANYCLASS 5 /* compatible with everything */
457
458 +#define ATM_VBR_NRT ATM_VBR
459 +#define ATM_VBR_RT 6
460 +#define ATM_UBR_PLUS 7
461 +#define ATM_GFR 8
462 +
463 #define ATM_MAX_PCR -1 /* maximum available PCR */
464
465 +
466 struct atm_trafprm {
467 unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */
468 int max_pcr; /* maximum PCR in cells per second */
469 --- a/net/atm/common.c
470 +++ b/net/atm/common.c
471 @@ -62,11 +62,17 @@ static void vcc_remove_socket(struct soc
472 write_unlock_irq(&vcc_sklist_lock);
473 }
474
475 +struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
476 +EXPORT_SYMBOL(ifx_atm_alloc_tx);
477 +
478 static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
479 {
480 struct sk_buff *skb;
481 struct sock *sk = sk_atm(vcc);
482
483 + if (ifx_atm_alloc_tx != NULL)
484 + return ifx_atm_alloc_tx(vcc, size);
485 +
486 if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) {
487 pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n",
488 sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);
489 --- a/net/atm/proc.c
490 +++ b/net/atm/proc.c
491 @@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_fil
492 static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
493 {
494 static const char *const class_name[] = {
495 - "off", "UBR", "CBR", "VBR", "ABR"};
496 + "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
497 static const char *const aal_name[] = {
498 "---", "1", "2", "3/4", /* 0- 3 */
499 "???", "5", "???", "???", /* 4- 7 */
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