target/linux/lantiq/patches-3.9/0010-NET-MIPS-lantiq-update-etop-driver-for-devicetree.patch

   1 From fd69e82feee0966fd61374ea76d6ff36ce42e51c Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 29 Jun 2013 19:42:16 +0200
   4 Subject: [PATCH 10/22] NET: MIPS: lantiq: update etop driver for devicetree
   5
   6 ---
   7  drivers/net/ethernet/lantiq_etop.c |  500 +++++++++++++++++++++++++-----------
   8  1 file changed, 354 insertions(+), 146 deletions(-)
   9
  10 diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
  11 index bfdb0686..c711787 100644
  12 --- a/drivers/net/ethernet/lantiq_etop.c
  13 +++ b/drivers/net/ethernet/lantiq_etop.c
  14 @@ -12,7 +12,7 @@
  15   *   along with this program; if not, write to the Free Software
  16   *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  17   *
  18 - *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
  19 + *   Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
  20   */
  21
  22  #include <linux/kernel.h>
  23 @@ -36,6 +36,10 @@
  24  #include <linux/io.h>
  25  #include <linux/dma-mapping.h>
  26  #include <linux/module.h>
  27 +#include <linux/clk.h>
  28 +#include <linux/of_net.h>
  29 +#include <linux/of_irq.h>
  30 +#include <linux/of_platform.h>
  31
  32  #include <asm/checksum.h>
  33
  34 @@ -71,25 +75,61 @@
  35  #define ETOP_MII_REVERSE       0xe
  36  #define ETOP_PLEN_UNDER                0x40
  37  #define ETOP_CGEN              0x800
  38 -
  39 -/* use 2 static channels for TX/RX */
  40 -#define LTQ_ETOP_TX_CHANNEL    1
  41 -#define LTQ_ETOP_RX_CHANNEL    6
  42 -#define IS_TX(x)               (x == LTQ_ETOP_TX_CHANNEL)
  43 -#define IS_RX(x)               (x == LTQ_ETOP_RX_CHANNEL)
  44 -
  45 +#define ETOP_CFG_MII0          0x01
  46 +
  47 +#define LTQ_GBIT_MDIO_CTL      0xCC
  48 +#define LTQ_GBIT_MDIO_DATA     0xd0
  49 +#define LTQ_GBIT_GCTL0         0x68
  50 +#define LTQ_GBIT_PMAC_HD_CTL   0x8c
  51 +#define LTQ_GBIT_P0_CTL                0x4
  52 +#define LTQ_GBIT_PMAC_RX_IPG   0xa8
  53 +#define LTQ_GBIT_RGMII_CTL     0x78
  54 +
  55 +#define PMAC_HD_CTL_AS         (1 << 19)
  56 +#define PMAC_HD_CTL_RXSH       (1 << 22)
  57 +
  58 +/* Switch Enable (0=disable, 1=enable) */
  59 +#define GCTL0_SE               0x80000000
  60 +/* Disable MDIO auto polling (0=disable, 1=enable) */
  61 +#define PX_CTL_DMDIO           0x00400000
  62 +
  63 +/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
  64 +#define MDC_CLOCK_MASK         0xff000000
  65 +#define MDC_CLOCK_OFFSET       24
  66 +
  67 +/* register information for the gbit's MDIO bus */
  68 +#define MDIO_XR9_REQUEST       0x00008000
  69 +#define MDIO_XR9_READ          0x00000800
  70 +#define MDIO_XR9_WRITE         0x00000400
  71 +#define MDIO_XR9_REG_MASK      0x1f
  72 +#define MDIO_XR9_ADDR_MASK     0x1f
  73 +#define MDIO_XR9_RD_MASK       0xffff
  74 +#define MDIO_XR9_REG_OFFSET    0
  75 +#define MDIO_XR9_ADDR_OFFSET   5
  76 +#define MDIO_XR9_WR_OFFSET     16
  77 +
  78 +#define LTQ_DMA_ETOP   ((of_machine_is_compatible("lantiq,ase")) ? \
  79 +                       (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
  80 +
  81 +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
  82  #define ltq_etop_r32(x)                ltq_r32(ltq_etop_membase + (x))
  83  #define ltq_etop_w32(x, y)     ltq_w32(x, ltq_etop_membase + (y))
  84  #define ltq_etop_w32_mask(x, y, z)     \
  85                 ltq_w32_mask(x, y, ltq_etop_membase + (z))
  86
  87 -#define DRV_VERSION    "1.0"
  88 +#define ltq_gbit_r32(x)                ltq_r32(ltq_gbit_membase + (x))
  89 +#define ltq_gbit_w32(x, y)     ltq_w32(x, ltq_gbit_membase + (y))
  90 +#define ltq_gbit_w32_mask(x, y, z)     \
  91 +               ltq_w32_mask(x, y, ltq_gbit_membase + (z))
  92 +
  93 +#define DRV_VERSION    "1.2"
  94
  95  static void __iomem *ltq_etop_membase;
  96 +static void __iomem *ltq_gbit_membase;
  97
  98  struct ltq_etop_chan {
  99 -       int idx;
 100         int tx_free;
 101 +       int irq;
 102         struct net_device *netdev;
 103         struct napi_struct napi;
 104         struct ltq_dma_channel dma;
 105 @@ -99,22 +139,35 @@ struct ltq_etop_chan {
 106  struct ltq_etop_priv {
 107         struct net_device *netdev;
 108         struct platform_device *pdev;
 109 -       struct ltq_eth_data *pldata;
 110         struct resource *res;
 111
 112         struct mii_bus *mii_bus;
 113         struct phy_device *phydev;
 114
 115 -       struct ltq_etop_chan ch[MAX_DMA_CHAN];
 116 -       int tx_free[MAX_DMA_CHAN >> 1];
 117 +       struct ltq_etop_chan txch;
 118 +       struct ltq_etop_chan rxch;
 119 +
 120 +       int tx_irq;
 121 +       int rx_irq;
 122 +
 123 +       const void *mac;
 124 +       int mii_mode;
 125
 126         spinlock_t lock;
 127 +
 128 +       struct clk *clk_ppe;
 129 +       struct clk *clk_switch;
 130 +       struct clk *clk_ephy;
 131 +       struct clk *clk_ephycgu;
 132  };
 133
 134 +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
 135 +                               int phy_reg, u16 phy_data);
 136 +
 137  static int
 138  ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
 139  {
 140 -       ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
 141 +       ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
 142         if (!ch->skb[ch->dma.desc])
 143                 return -ENOMEM;
 144         ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
 145 @@ -149,8 +202,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan *ch)
 146         spin_unlock_irqrestore(&priv->lock, flags);
 147
 148         skb_put(skb, len);
 149 +       skb->dev = ch->netdev;
 150         skb->protocol = eth_type_trans(skb, ch->netdev);
 151         netif_receive_skb(skb);
 152 +       ch->netdev->stats.rx_packets++;
 153 +       ch->netdev->stats.rx_bytes += len;
 154  }
 155
 156  static int
 157 @@ -158,8 +214,10 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
 158  {
 159         struct ltq_etop_chan *ch = container_of(napi,
 160                                 struct ltq_etop_chan, napi);
 161 +       struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 162         int rx = 0;
 163         int complete = 0;
 164 +       unsigned long flags;
 165
 166         while ((rx < budget) && !complete) {
 167                 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 168 @@ -173,7 +231,9 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
 169         }
 170         if (complete || !rx) {
 171                 napi_complete(&ch->napi);
 172 +               spin_lock_irqsave(&priv->lock, flags);
 173                 ltq_dma_ack_irq(&ch->dma);
 174 +               spin_unlock_irqrestore(&priv->lock, flags);
 175         }
 176         return rx;
 177  }
 178 @@ -185,12 +245,14 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
 179                 container_of(napi, struct ltq_etop_chan, napi);
 180         struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 181         struct netdev_queue *txq =
 182 -               netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
 183 +               netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
 184         unsigned long flags;
 185
 186         spin_lock_irqsave(&priv->lock, flags);
 187         while ((ch->dma.desc_base[ch->tx_free].ctl &
 188                         (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
 189 +               ch->netdev->stats.tx_packets++;
 190 +               ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
 191                 dev_kfree_skb_any(ch->skb[ch->tx_free]);
 192                 ch->skb[ch->tx_free] = NULL;
 193                 memset(&ch->dma.desc_base[ch->tx_free], 0,
 194 @@ -203,7 +265,9 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
 195         if (netif_tx_queue_stopped(txq))
 196                 netif_tx_start_queue(txq);
 197         napi_complete(&ch->napi);
 198 +       spin_lock_irqsave(&priv->lock, flags);
 199         ltq_dma_ack_irq(&ch->dma);
 200 +       spin_unlock_irqrestore(&priv->lock, flags);
 201         return 1;
 202  }
 203
 204 @@ -211,9 +275,10 @@ static irqreturn_t
 205  ltq_etop_dma_irq(int irq, void *_priv)
 206  {
 207         struct ltq_etop_priv *priv = _priv;
 208 -       int ch = irq - LTQ_DMA_CH0_INT;
 209 -
 210 -       napi_schedule(&priv->ch[ch].napi);
 211 +       if (irq == priv->txch.dma.irq)
 212 +               napi_schedule(&priv->txch.napi);
 213 +       else
 214 +               napi_schedule(&priv->rxch.napi);
 215         return IRQ_HANDLED;
 216  }
 217
 218 @@ -225,7 +290,7 @@ ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
 219         ltq_dma_free(&ch->dma);
 220         if (ch->dma.irq)
 221                 free_irq(ch->dma.irq, priv);
 222 -       if (IS_RX(ch->idx)) {
 223 +       if (ch == &priv->txch) {
 224                 int desc;
 225                 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
 226                         dev_kfree_skb_any(ch->skb[ch->dma.desc]);
 227 @@ -236,23 +301,59 @@ static void
 228  ltq_etop_hw_exit(struct net_device *dev)
 229  {
 230         struct ltq_etop_priv *priv = netdev_priv(dev);
 231 -       int i;
 232
 233 -       ltq_pmu_disable(PMU_PPE);
 234 -       for (i = 0; i < MAX_DMA_CHAN; i++)
 235 -               if (IS_TX(i) || IS_RX(i))
 236 -                       ltq_etop_free_channel(dev, &priv->ch[i]);
 237 +       clk_disable(priv->clk_ppe);
 238 +
 239 +       if (of_machine_is_compatible("lantiq,ar9"))
 240 +               clk_disable(priv->clk_switch);
 241 +
 242 +       if (of_machine_is_compatible("lantiq,ase")) {
 243 +               clk_disable(priv->clk_ephy);
 244 +               clk_disable(priv->clk_ephycgu);
 245 +       }
 246 +
 247 +       ltq_etop_free_channel(dev, &priv->txch);
 248 +       ltq_etop_free_channel(dev, &priv->rxch);
 249 +}
 250 +
 251 +static void
 252 +ltq_etop_gbit_init(struct net_device *dev)
 253 +{
 254 +       struct ltq_etop_priv *priv = netdev_priv(dev);
 255 +
 256 +       clk_enable(priv->clk_switch);
 257 +
 258 +       ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
 259 +       /** Disable MDIO auto polling mode */
 260 +       ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
 261 +       /* set 1522 packet size */
 262 +       ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
 263 +       /* disable pmac & dmac headers */
 264 +       ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
 265 +               LTQ_GBIT_PMAC_HD_CTL);
 266 +       /* Due to traffic halt when burst length 8,
 267 +               replace default IPG value with 0x3B */
 268 +       ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
 269 +       /* set mdc clock to 2.5 MHz */
 270 +       ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
 271 +               LTQ_GBIT_RGMII_CTL);
 272  }
 273
 274  static int
 275  ltq_etop_hw_init(struct net_device *dev)
 276  {
 277         struct ltq_etop_priv *priv = netdev_priv(dev);
 278 -       int i;
 279 +       int mii_mode = priv->mii_mode;
 280 +
 281 +       clk_enable(priv->clk_ppe);
 282
 283 -       ltq_pmu_enable(PMU_PPE);
 284 +       if (of_machine_is_compatible("lantiq,ar9")) {
 285 +               ltq_etop_gbit_init(dev);
 286 +               /* force the etops link to the gbit to MII */
 287 +               mii_mode = PHY_INTERFACE_MODE_MII;
 288 +       }
 289
 290 -       switch (priv->pldata->mii_mode) {
 291 +       switch (mii_mode) {
 292         case PHY_INTERFACE_MODE_RMII:
 293                 ltq_etop_w32_mask(ETOP_MII_MASK,
 294                         ETOP_MII_REVERSE, LTQ_ETOP_CFG);
 295 @@ -264,39 +365,68 @@ ltq_etop_hw_init(struct net_device *dev)
 296                 break;
 297
 298         default:
 299 +               if (of_machine_is_compatible("lantiq,ase")) {
 300 +                       clk_enable(priv->clk_ephy);
 301 +                       /* disable external MII */
 302 +                       ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
 303 +                       /* enable clock for internal PHY */
 304 +                       clk_enable(priv->clk_ephycgu);
 305 +                       /* we need to write this magic to the internal phy to
 306 +                          make it work */
 307 +                       ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
 308 +                       pr_info("Selected EPHY mode\n");
 309 +                       break;
 310 +               }
 311                 netdev_err(dev, "unknown mii mode %d\n",
 312 -                       priv->pldata->mii_mode);
 313 +                       mii_mode);
 314                 return -ENOTSUPP;
 315         }
 316
 317         /* enable crc generation */
 318         ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
 319
 320 +       return 0;
 321 +}
 322 +
 323 +static int
 324 +ltq_etop_dma_init(struct net_device *dev)
 325 +{
 326 +       struct ltq_etop_priv *priv = netdev_priv(dev);
 327 +       int tx = priv->tx_irq - LTQ_DMA_ETOP;
 328 +       int rx = priv->rx_irq - LTQ_DMA_ETOP;
 329 +       int err;
 330 +
 331         ltq_dma_init_port(DMA_PORT_ETOP);
 332
 333 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 334 -               int irq = LTQ_DMA_CH0_INT + i;
 335 -               struct ltq_etop_chan *ch = &priv->ch[i];
 336 -
 337 -               ch->idx = ch->dma.nr = i;
 338 -
 339 -               if (IS_TX(i)) {
 340 -                       ltq_dma_alloc_tx(&ch->dma);
 341 -                       request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
 342 -                               "etop_tx", priv);
 343 -               } else if (IS_RX(i)) {
 344 -                       ltq_dma_alloc_rx(&ch->dma);
 345 -                       for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
 346 -                                       ch->dma.desc++)
 347 -                               if (ltq_etop_alloc_skb(ch))
 348 -                                       return -ENOMEM;
 349 -                       ch->dma.desc = 0;
 350 -                       request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
 351 -                               "etop_rx", priv);
 352 +       priv->txch.dma.nr = tx;
 353 +       ltq_dma_alloc_tx(&priv->txch.dma);
 354 +       err = request_irq(priv->tx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
 355 +               "eth_tx", priv);
 356 +       if (err) {
 357 +               netdev_err(dev, "failed to allocate tx irq\n");
 358 +               goto err_out;
 359 +       }
 360 +       priv->txch.dma.irq = priv->tx_irq;
 361 +
 362 +       priv->rxch.dma.nr = rx;
 363 +       ltq_dma_alloc_rx(&priv->rxch.dma);
 364 +       for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
 365 +                       priv->rxch.dma.desc++) {
 366 +               if (ltq_etop_alloc_skb(&priv->rxch)) {
 367 +                       netdev_err(dev, "failed to allocate skbs\n");
 368 +                       err = -ENOMEM;
 369 +                       goto err_out;
 370                 }
 371 -               ch->dma.irq = irq;
 372         }
 373 -       return 0;
 374 +       priv->rxch.dma.desc = 0;
 375 +       err = request_irq(priv->rx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
 376 +               "eth_rx", priv);
 377 +       if (err)
 378 +               netdev_err(dev, "failed to allocate rx irq\n");
 379 +       else
 380 +               priv->rxch.dma.irq = priv->rx_irq;
 381 +err_out:
 382 +       return err;
 383  }
 384
 385  static void
 386 @@ -312,7 +442,10 @@ ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 387  {
 388         struct ltq_etop_priv *priv = netdev_priv(dev);
 389
 390 -       return phy_ethtool_gset(priv->phydev, cmd);
 391 +       if (priv->phydev)
 392 +               return phy_ethtool_gset(priv->phydev, cmd);
 393 +       else
 394 +               return 0;
 395  }
 396
 397  static int
 398 @@ -320,7 +453,10 @@ ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 399  {
 400         struct ltq_etop_priv *priv = netdev_priv(dev);
 401
 402 -       return phy_ethtool_sset(priv->phydev, cmd);
 403 +       if (priv->phydev)
 404 +               return phy_ethtool_sset(priv->phydev, cmd);
 405 +       else
 406 +               return 0;
 407  }
 408
 409  static int
 410 @@ -328,7 +464,10 @@ ltq_etop_nway_reset(struct net_device *dev)
 411  {
 412         struct ltq_etop_priv *priv = netdev_priv(dev);
 413
 414 -       return phy_start_aneg(priv->phydev);
 415 +       if (priv->phydev)
 416 +               return phy_start_aneg(priv->phydev);
 417 +       else
 418 +               return 0;
 419  }
 420
 421  static const struct ethtool_ops ltq_etop_ethtool_ops = {
 422 @@ -339,6 +478,39 @@ static const struct ethtool_ops ltq_etop_ethtool_ops = {
 423  };
 424
 425  static int
 426 +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
 427 +               int phy_reg, u16 phy_data)
 428 +{
 429 +       u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
 430 +               (phy_data << MDIO_XR9_WR_OFFSET) |
 431 +               ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
 432 +               ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
 433 +
 434 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 435 +               ;
 436 +       ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
 437 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 438 +               ;
 439 +       return 0;
 440 +}
 441 +
 442 +static int
 443 +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
 444 +{
 445 +       u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
 446 +               ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
 447 +               ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
 448 +
 449 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 450 +               ;
 451 +       ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
 452 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 453 +               ;
 454 +       val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
 455 +       return val;
 456 +}
 457 +
 458 +static int
 459  ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
 460  {
 461         u32 val = MDIO_REQUEST |
 462 @@ -379,14 +551,18 @@ ltq_etop_mdio_probe(struct net_device *dev)
 463  {
 464         struct ltq_etop_priv *priv = netdev_priv(dev);
 465         struct phy_device *phydev = NULL;
 466 -       int phy_addr;
 467 -
 468 -       for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
 469 -               if (priv->mii_bus->phy_map[phy_addr]) {
 470 -                       phydev = priv->mii_bus->phy_map[phy_addr];
 471 -                       break;
 472 -               }
 473 -       }
 474 +       u32 phy_supported =  (SUPPORTED_10baseT_Half
 475 +                       | SUPPORTED_10baseT_Full
 476 +                       | SUPPORTED_100baseT_Half
 477 +                       | SUPPORTED_100baseT_Full
 478 +                       | SUPPORTED_Autoneg
 479 +                       | SUPPORTED_MII
 480 +                       | SUPPORTED_TP);
 481 +
 482 +       if (of_machine_is_compatible("lantiq,ase"))
 483 +               phydev = priv->mii_bus->phy_map[8];
 484 +       else
 485 +               phydev = priv->mii_bus->phy_map[0];
 486
 487         if (!phydev) {
 488                 netdev_err(dev, "no PHY found\n");
 489 @@ -394,21 +570,18 @@ ltq_etop_mdio_probe(struct net_device *dev)
 490         }
 491
 492         phydev = phy_connect(dev, dev_name(&phydev->dev),
 493 -                            &ltq_etop_mdio_link, priv->pldata->mii_mode);
 494 +                       &ltq_etop_mdio_link, priv->mii_mode);
 495
 496         if (IS_ERR(phydev)) {
 497                 netdev_err(dev, "Could not attach to PHY\n");
 498                 return PTR_ERR(phydev);
 499         }
 500
 501 -       phydev->supported &= (SUPPORTED_10baseT_Half
 502 -                             | SUPPORTED_10baseT_Full
 503 -                             | SUPPORTED_100baseT_Half
 504 -                             | SUPPORTED_100baseT_Full
 505 -                             | SUPPORTED_Autoneg
 506 -                             | SUPPORTED_MII
 507 -                             | SUPPORTED_TP);
 508 +       if (of_machine_is_compatible("lantiq,ar9"))
 509 +               phy_supported |= SUPPORTED_1000baseT_Half
 510 +                       | SUPPORTED_1000baseT_Full;
 511
 512 +       phydev->supported &= phy_supported;
 513         phydev->advertising = phydev->supported;
 514         priv->phydev = phydev;
 515         pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
 516 @@ -433,8 +606,13 @@ ltq_etop_mdio_init(struct net_device *dev)
 517         }
 518
 519         priv->mii_bus->priv = dev;
 520 -       priv->mii_bus->read = ltq_etop_mdio_rd;
 521 -       priv->mii_bus->write = ltq_etop_mdio_wr;
 522 +       if (of_machine_is_compatible("lantiq,ar9")) {
 523 +               priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
 524 +               priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
 525 +       } else {
 526 +               priv->mii_bus->read = ltq_etop_mdio_rd;
 527 +               priv->mii_bus->write = ltq_etop_mdio_wr;
 528 +       }
 529         priv->mii_bus->name = "ltq_mii";
 530         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
 531                 priv->pdev->name, priv->pdev->id);
 532 @@ -483,17 +661,19 @@ static int
 533  ltq_etop_open(struct net_device *dev)
 534  {
 535         struct ltq_etop_priv *priv = netdev_priv(dev);
 536 -       int i;
 537 +       unsigned long flags;
 538
 539 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 540 -               struct ltq_etop_chan *ch = &priv->ch[i];
 541 +       napi_enable(&priv->txch.napi);
 542 +       napi_enable(&priv->rxch.napi);
 543 +
 544 +       spin_lock_irqsave(&priv->lock, flags);
 545 +       ltq_dma_open(&priv->txch.dma);
 546 +       ltq_dma_open(&priv->rxch.dma);
 547 +       spin_unlock_irqrestore(&priv->lock, flags);
 548 +
 549 +       if (priv->phydev)
 550 +               phy_start(priv->phydev);
 551
 552 -               if (!IS_TX(i) && (!IS_RX(i)))
 553 -                       continue;
 554 -               ltq_dma_open(&ch->dma);
 555 -               napi_enable(&ch->napi);
 556 -       }
 557 -       phy_start(priv->phydev);
 558         netif_tx_start_all_queues(dev);
 559         return 0;
 560  }
 561 @@ -502,18 +682,19 @@ static int
 562  ltq_etop_stop(struct net_device *dev)
 563  {
 564         struct ltq_etop_priv *priv = netdev_priv(dev);
 565 -       int i;
 566 +       unsigned long flags;
 567
 568         netif_tx_stop_all_queues(dev);
 569 -       phy_stop(priv->phydev);
 570 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 571 -               struct ltq_etop_chan *ch = &priv->ch[i];
 572 +       if (priv->phydev)
 573 +               phy_stop(priv->phydev);
 574 +       napi_disable(&priv->txch.napi);
 575 +       napi_disable(&priv->rxch.napi);
 576 +
 577 +       spin_lock_irqsave(&priv->lock, flags);
 578 +       ltq_dma_close(&priv->txch.dma);
 579 +       ltq_dma_close(&priv->rxch.dma);
 580 +       spin_unlock_irqrestore(&priv->lock, flags);
 581
 582 -               if (!IS_RX(i) && !IS_TX(i))
 583 -                       continue;
 584 -               napi_disable(&ch->napi);
 585 -               ltq_dma_close(&ch->dma);
 586 -       }
 587         return 0;
 588  }
 589
 590 @@ -523,16 +704,16 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
 591         int queue = skb_get_queue_mapping(skb);
 592         struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
 593         struct ltq_etop_priv *priv = netdev_priv(dev);
 594 -       struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
 595 -       struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 596 -       int len;
 597 +       struct ltq_dma_desc *desc =
 598 +               &priv->txch.dma.desc_base[priv->txch.dma.desc];
 599         unsigned long flags;
 600         u32 byte_offset;
 601 +       int len;
 602
 603         len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
 604
 605 -       if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
 606 -               dev_kfree_skb_any(skb);
 607 +       if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
 608 +                       priv->txch.skb[priv->txch.dma.desc]) {
 609                 netdev_err(dev, "tx ring full\n");
 610                 netif_tx_stop_queue(txq);
 611                 return NETDEV_TX_BUSY;
 612 @@ -540,7 +721,7 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
 613
 614         /* dma needs to start on a 16 byte aligned address */
 615         byte_offset = CPHYSADDR(skb->data) % 16;
 616 -       ch->skb[ch->dma.desc] = skb;
 617 +       priv->txch.skb[priv->txch.dma.desc] = skb;
 618
 619         dev->trans_start = jiffies;
 620
 621 @@ -550,11 +731,11 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
 622         wmb();
 623         desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
 624                 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
 625 -       ch->dma.desc++;
 626 -       ch->dma.desc %= LTQ_DESC_NUM;
 627 +       priv->txch.dma.desc++;
 628 +       priv->txch.dma.desc %= LTQ_DESC_NUM;
 629         spin_unlock_irqrestore(&priv->lock, flags);
 630
 631 -       if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
 632 +       if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
 633                 netif_tx_stop_queue(txq);
 634
 635         return NETDEV_TX_OK;
 636 @@ -633,34 +814,33 @@ ltq_etop_init(struct net_device *dev)
 637         struct ltq_etop_priv *priv = netdev_priv(dev);
 638         struct sockaddr mac;
 639         int err;
 640 -       bool random_mac = false;
 641
 642         ether_setup(dev);
 643         dev->watchdog_timeo = 10 * HZ;
 644         err = ltq_etop_hw_init(dev);
 645         if (err)
 646                 goto err_hw;
 647 +       err = ltq_etop_dma_init(dev);
 648 +       if (err)
 649 +               goto err_hw;
 650 +
 651         ltq_etop_change_mtu(dev, 1500);
 652
 653 -       memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
 654 +       if (priv->mac)
 655 +               memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
 656         if (!is_valid_ether_addr(mac.sa_data)) {
 657                 pr_warn("etop: invalid MAC, using random\n");
 658 -               eth_random_addr(mac.sa_data);
 659 -               random_mac = true;
 660 +               random_ether_addr(mac.sa_data);
 661         }
 662
 663         err = ltq_etop_set_mac_address(dev, &mac);
 664         if (err)
 665                 goto err_netdev;
 666 -
 667 -       /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
 668 -       if (random_mac)
 669 -               dev->addr_assign_type = NET_ADDR_RANDOM;
 670 -
 671         ltq_etop_set_multicast_list(dev);
 672 -       err = ltq_etop_mdio_init(dev);
 673 -       if (err)
 674 -               goto err_netdev;
 675 +       if (!ltq_etop_mdio_init(dev))
 676 +               dev->ethtool_ops = &ltq_etop_ethtool_ops;
 677 +       else
 678 +               pr_warn("etop: mdio probe failed\n");;
 679         return 0;
 680
 681  err_netdev:
 682 @@ -680,6 +860,9 @@ ltq_etop_tx_timeout(struct net_device *dev)
 683         err = ltq_etop_hw_init(dev);
 684         if (err)
 685                 goto err_hw;
 686 +       err = ltq_etop_dma_init(dev);
 687 +       if (err)
 688 +               goto err_hw;
 689         dev->trans_start = jiffies;
 690         netif_wake_queue(dev);
 691         return;
 692 @@ -703,14 +886,18 @@ static const struct net_device_ops ltq_eth_netdev_ops = {
 693         .ndo_tx_timeout = ltq_etop_tx_timeout,
 694  };
 695
 696 -static int __init
 697 -ltq_etop_probe(struct platform_device *pdev)
 698 +static int ltq_etop_probe(struct platform_device *pdev)
 699  {
 700         struct net_device *dev;
 701         struct ltq_etop_priv *priv;
 702 -       struct resource *res;
 703 +       struct resource *res, *gbit_res, irqres[2];
 704         int err;
 705 -       int i;
 706 +
 707 +       err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
 708 +       if (err != 2) {
 709 +               dev_err(&pdev->dev, "failed to get etop irqs\n");
 710 +               return -EINVAL;
 711 +       }
 712
 713         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 714         if (!res) {
 715 @@ -736,30 +923,60 @@ ltq_etop_probe(struct platform_device *pdev)
 716                 goto err_out;
 717         }
 718
 719 -       dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
 720 -       if (!dev) {
 721 -               err = -ENOMEM;
 722 -               goto err_out;
 723 +       if (of_machine_is_compatible("lantiq,ar9")) {
 724 +               gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 725 +               if (!gbit_res) {
 726 +                       dev_err(&pdev->dev, "failed to get gbit resource\n");
 727 +                       err = -ENOENT;
 728 +                       goto err_out;
 729 +               }
 730 +               ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
 731 +                       gbit_res->start, resource_size(gbit_res));
 732 +               if (!ltq_gbit_membase) {
 733 +                       dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
 734 +                               pdev->id);
 735 +                       err = -ENOMEM;
 736 +                       goto err_out;
 737 +               }
 738         }
 739 +
 740 +       dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
 741         strcpy(dev->name, "eth%d");
 742         dev->netdev_ops = &ltq_eth_netdev_ops;
 743 -       dev->ethtool_ops = &ltq_etop_ethtool_ops;
 744         priv = netdev_priv(dev);
 745         priv->res = res;
 746         priv->pdev = pdev;
 747 -       priv->pldata = dev_get_platdata(&pdev->dev);
 748         priv->netdev = dev;
 749 +       priv->tx_irq = irqres[0].start;
 750 +       priv->rx_irq = irqres[1].start;
 751 +       priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
 752 +       priv->mac = ltq_get_eth_mac();
 753 +       if (!priv->mac)
 754 +               priv->mac = of_get_mac_address(pdev->dev.of_node);
 755 +
 756 +       priv->clk_ppe = clk_get(&pdev->dev, NULL);
 757 +       if (IS_ERR(priv->clk_ppe))
 758 +               return PTR_ERR(priv->clk_ppe);
 759 +       if (of_machine_is_compatible("lantiq,ar9")) {
 760 +               priv->clk_switch = clk_get(&pdev->dev, "switch");
 761 +               if (IS_ERR(priv->clk_switch))
 762 +                       return PTR_ERR(priv->clk_switch);
 763 +       }
 764 +       if (of_machine_is_compatible("lantiq,ase")) {
 765 +               priv->clk_ephy = clk_get(&pdev->dev, "ephy");
 766 +               if (IS_ERR(priv->clk_ephy))
 767 +                       return PTR_ERR(priv->clk_ephy);
 768 +               priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
 769 +               if (IS_ERR(priv->clk_ephycgu))
 770 +                       return PTR_ERR(priv->clk_ephycgu);
 771 +       }
 772 +
 773         spin_lock_init(&priv->lock);
 774
 775 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 776 -               if (IS_TX(i))
 777 -                       netif_napi_add(dev, &priv->ch[i].napi,
 778 -                               ltq_etop_poll_tx, 8);
 779 -               else if (IS_RX(i))
 780 -                       netif_napi_add(dev, &priv->ch[i].napi,
 781 -                               ltq_etop_poll_rx, 32);
 782 -               priv->ch[i].netdev = dev;
 783 -       }
 784 +       netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
 785 +       netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
 786 +       priv->txch.netdev = dev;
 787 +       priv->rxch.netdev = dev;
 788
 789         err = register_netdev(dev);
 790         if (err)
 791 @@ -788,32 +1005,23 @@ ltq_etop_remove(struct platform_device *pdev)
 792         return 0;
 793  }
 794
 795 +static const struct of_device_id ltq_etop_match[] = {
 796 +       { .compatible = "lantiq,etop-xway" },
 797 +       {},
 798 +};
 799 +MODULE_DEVICE_TABLE(of, ltq_etop_match);
 800 +
 801  static struct platform_driver ltq_mii_driver = {
 802 +       .probe = ltq_etop_probe,
 803         .remove = ltq_etop_remove,
 804         .driver = {
 805                 .name = "ltq_etop",
 806                 .owner = THIS_MODULE,
 807 +               .of_match_table = ltq_etop_match,
 808         },
 809  };
 810
 811 -int __init
 812 -init_ltq_etop(void)
 813 -{
 814 -       int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
 815 -
 816 -       if (ret)
 817 -               pr_err("ltq_etop: Error registering platform driver!");
 818 -       return ret;
 819 -}
 820 -
 821 -static void __exit
 822 -exit_ltq_etop(void)
 823 -{
 824 -       platform_driver_unregister(&ltq_mii_driver);
 825 -}
 826 -
 827 -module_init(init_ltq_etop);
 828 -module_exit(exit_ltq_etop);
 829 +module_platform_driver(ltq_mii_driver);
 830
 831  MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 832  MODULE_DESCRIPTION("Lantiq SoC ETOP");
 833 --
 834 1.7.10.4
 835