target/linux/magicbox-2.6/files/arch/ppc/platforms/4xx/magicbox.c

   1 /*
   2  * Support for IBM PPC 405EP-based MagicBox board
   3  * Copyright (C) 2006  Karol Lewandowski
   4  *
   5  * Heavily based on bubinga.c
   6  *
   7  * Author: SAW (IBM), derived from walnut.c.
   8  *         Maintained by MontaVista Software <source@mvista.com>
   9  *
  10  * 2003 (c) MontaVista Softare Inc.  This file is licensed under the
  11  * terms of the GNU General Public License version 2. This program is
  12  * licensed "as is" without any warranty of any kind, whether express
  13  * or implied.
  14  */
  15
  16 #include <linux/autoconf.h>
  17 #include <linux/init.h>
  18 #include <linux/smp.h>
  19 #include <linux/threads.h>
  20 #include <linux/param.h>
  21 #include <linux/string.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/pci.h>
  24 #include <linux/tty.h>
  25 #include <linux/serial.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/mtd/partitions.h>
  29 #include <linux/mtd/physmap.h>
  30
  31 #include <asm/system.h>
  32 #include <asm/pci-bridge.h>
  33 #include <asm/processor.h>
  34 #include <asm/machdep.h>
  35 #include <asm/page.h>
  36 #include <asm/time.h>
  37 #include <asm/io.h>
  38 #include <asm/kgdb.h>
  39 #include <asm/ocp.h>
  40 #include <asm/ibm_ocp_pci.h>
  41
  42 #include <platforms/4xx/ibm405ep.h>
  43
  44 #undef DEBUG
  45
  46 #ifdef DEBUG
  47 #define DBG(x...) printk(x)
  48 #else
  49 #define DBG(x...)
  50 #endif
  51
  52 extern bd_t __res;
  53
  54 /* Some IRQs unique to board
  55  * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
  56  */
  57 int __init
  58 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  59 {
  60         static char pci_irq_table[][4] =
  61             /*
  62              *      PCI IDSEL/INTPIN->INTLINE
  63              *      A       B       C       D
  64              */
  65         {
  66                 {28, 28, 28, 28},       /* IDSEL 1 - PCI slot 1 */
  67                 {29, 29, 29, 29},       /* IDSEL 2 - PCI slot 2 */
  68                 {30, 30, 30, 30},       /* IDSEL 3 - PCI slot 3 */
  69                 {31, 31, 31, 31},       /* IDSEL 4 - PCI slot 4 */
  70         };
  71
  72         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
  73         return PCI_IRQ_TABLE_LOOKUP;
  74 };
  75
  76
  77 /* The serial clock for the chip is an internal clock determined by
  78  * different clock speeds/dividers.
  79  * Calculate the proper input baud rate and setup the serial driver.
  80  */
  81 static void __init
  82 magicbox_early_serial_map(void)
  83 {
  84         u32 uart_div;
  85         int uart_clock;
  86         struct uart_port port;
  87
  88          /* Calculate the serial clock input frequency
  89           *
  90           * The base baud is the PLL OUTA (provided in the board info
  91           * structure) divided by the external UART Divisor, divided
  92           * by 16.
  93           */
  94         uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
  95         uart_clock = __res.bi_procfreq / uart_div;
  96
  97         /* Setup serial port access */
  98         memset(&port, 0, sizeof(port));
  99         port.membase = (void*)ACTING_UART0_IO_BASE;
 100         port.irq = ACTING_UART0_INT;
 101         port.uartclk = uart_clock;
 102         port.regshift = 0;
 103         port.iotype = SERIAL_IO_MEM;
 104         port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
 105         port.line = 0;
 106
 107         if (early_serial_setup(&port) != 0) {
 108                 printk("Early serial init of port 0 failed\n");
 109         }
 110
 111         port.membase = (void*)ACTING_UART1_IO_BASE;
 112         port.irq = ACTING_UART1_INT;
 113         port.line = 1;
 114
 115         if (early_serial_setup(&port) != 0) {
 116                 printk("Early serial init of port 1 failed\n");
 117         }
 118 }
 119
 120 void __init
 121 bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
 122 {
 123         unsigned int bar_response, bar;
 124         /*
 125          * Expected PCI mapping:
 126          *
 127          *  PLB addr             PCI memory addr
 128          *  ---------------------       ---------------------
 129          *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
 130          *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
 131          *
 132          *  PLB addr             PCI io addr
 133          *  ---------------------       ---------------------
 134          *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
 135          *
 136          * The following code is simplified by assuming that the bootrom
 137          * has been well behaved in following this mapping.
 138          */
 139
 140 #ifdef DEBUG
 141         int i;
 142
 143         printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
 144         printk("PCI bridge regs before fixup \n");
 145         for (i = 0; i <= 3; i++) {
 146                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 147                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 148                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
 149                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
 150         }
 151         printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 152         printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 153         printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 154         printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 155
 156 #endif
 157
 158         /* added for IBM boot rom version 1.15 bios bar changes  -AK */
 159
 160         /* Disable region first */
 161         out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
 162         /* PLB starting addr, PCI: 0x80000000 */
 163         out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
 164         /* PCI start addr, 0x80000000 */
 165         out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
 166         /* 512MB range of PLB to PCI */
 167         out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
 168         /* Enable no pre-fetch, enable region */
 169         out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
 170                                                 (PPC405_PCI_UPPER_MEM -
 171                                                  PPC405_PCI_MEM_BASE)) | 0x01));
 172
 173         /* Disable region one */
 174         out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 175         out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
 176         out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
 177         out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
 178         out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 179         out_le32((void *) &(pcip->ptm1ms), 0x00000001);
 180
 181         /* Disable region two */
 182         out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 183         out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
 184         out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
 185         out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
 186         out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 187         out_le32((void *) &(pcip->ptm2ms), 0x00000000);
 188         out_le32((void *) &(pcip->ptm2la), 0x00000000);
 189
 190         /* Zero config bars */
 191         for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 192                 early_write_config_dword(hose, hose->first_busno,
 193                                          PCI_FUNC(hose->first_busno), bar,
 194                                          0x00000000);
 195                 early_read_config_dword(hose, hose->first_busno,
 196                                         PCI_FUNC(hose->first_busno), bar,
 197                                         &bar_response);
 198                 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
 199                     hose->first_busno, PCI_SLOT(hose->first_busno),
 200                     PCI_FUNC(hose->first_busno), bar, bar_response);
 201         }
 202         /* end work arround */
 203
 204 #ifdef DEBUG
 205         printk("PCI bridge regs after fixup \n");
 206         for (i = 0; i <= 3; i++) {
 207                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 208                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 209                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
 210                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
 211         }
 212         printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 213         printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 214         printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 215         printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 216
 217 #endif /* DEBUG */
 218 }
 219
 220 static struct resource magicbox_flash_resource = {
 221         .start = 0xffc00000,
 222         .end   = 0xffffffffULL,
 223         .flags = IORESOURCE_MEM,
 224 };
 225
 226 static struct mtd_partition magicbox_flash_parts[] = {
 227         {
 228                 .name = "linux",
 229                 .offset = 0x0,
 230                 .size = 0x3c0000,
 231         },
 232         {
 233                 .name = "rootfs",
 234                 .offset = 0x100000,
 235                 .size = 0x2c0000,
 236         }
 237 };
 238
 239 static struct physmap_flash_data magicbox_flash_data = {
 240         .width          = 2,
 241         .parts          = magicbox_flash_parts,
 242         .nr_parts       = ARRAY_SIZE(magicbox_flash_parts),
 243 };
 244
 245 static struct platform_device magicbox_flash_device = {
 246         .name           = "physmap-flash",
 247         .id             = 0,
 248         .dev = {
 249                         .platform_data = &magicbox_flash_data,
 250                 },
 251         .num_resources  = 1,
 252         .resource       = &magicbox_flash_resource,
 253 };
 254
 255 static int magicbox_setup_flash(void)
 256 {
 257         platform_device_register(&magicbox_flash_device);
 258
 259         return 0;
 260 };
 261
 262 arch_initcall (magicbox_setup_flash);
 263
 264 void __init
 265 magicbox_setup_arch(void)
 266 {
 267         ppc4xx_setup_arch();
 268
 269         ibm_ocp_set_emac(0, 1);
 270
 271         magicbox_early_serial_map();
 272
 273         /* Identify the system */
 274         printk("MagicBox port (C) 2005 Karol Lewandowski <kl@jasmine.eu.org>\n");
 275 }
 276
 277 void __init
 278 magicbox_map_io(void)
 279 {
 280         ppc4xx_map_io();
 281 }
 282
 283 void __init
 284 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 285               unsigned long r6, unsigned long r7)
 286 {
 287         ppc4xx_init(r3, r4, r5, r6, r7);
 288
 289         ppc_md.setup_arch = magicbox_setup_arch;
 290         ppc_md.setup_io_mappings = magicbox_map_io;
 291
 292 #ifdef CONFIG_KGDB
 293         ppc_md.early_serial_map = bubinga_early_serial_map;
 294 #endif
 295
 296 }